tjh.dev / kernel
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Merge tag 'drm-fixes-for-4.8-rc3-2' of git://people.freedesktop.org/~airlied/linux

Pull more drm fixes from Dave Airlie:
"Daniel pointed out I'd missed some i915 fixes, and I also found a
single etnaviv fix I missed.

So here they are"

* tag 'drm-fixes-for-4.8-rc3-2' of git://people.freedesktop.org/~airlied/linux:
drm/etnaviv: take GPU lock later in the submit process
drm/i915: Fix modeset handling during gpu reset, v5.
drm/i915: fix aliasing_ppgtt leak
drm/i915: fix WaInsertDummyPushConstPs
drm/i915: Fix iboost setting for SKL Y/U DP DDI buffer translation entry 2
drm/i915/gen9: Give one extra block per line for SKL plane WM calculations
drm/i915: Acquire audio powerwell for HD-Audio registers
drm/i915: Add missing rpm wakelock to GGTT pread
drm/i915/fbc: FBC causes display flicker when VT-d is enabled on Skylake
drm/i915: Clean up the extra RPM ref on CHV with i915.enable_rc6=0
drm/i915: Program iboost settings for HDMI/DVI on SKL
drm/i915: Fix iboost setting for DDI with 4 lanes on SKL
drm/i915: Handle ENOSPC after failing to insert a mappable node
drm/i915: Flush GT idle status upon reset

Linus Torvalds 952b159f d8298d26

+228 -104
+5 -5
drivers/gpu/drm/etnaviv/etnaviv_gpu.c
··· 1333 1333 if (ret < 0) 1334 1334 return ret; 1335 1335 1336 - mutex_lock(&gpu->lock); 1337 - 1338 1336 /* 1339 1337 * TODO 1340 1338 * ··· 1346 1348 if (unlikely(event == ~0U)) { 1347 1349 DRM_ERROR("no free event\n"); 1348 1350 ret = -EBUSY; 1349 - goto out_unlock; 1351 + goto out_pm_put; 1350 1352 } 1351 1353 1352 1354 fence = etnaviv_gpu_fence_alloc(gpu); 1353 1355 if (!fence) { 1354 1356 event_free(gpu, event); 1355 1357 ret = -ENOMEM; 1356 - goto out_unlock; 1358 + goto out_pm_put; 1357 1359 } 1360 + 1361 + mutex_lock(&gpu->lock); 1358 1362 1359 1363 gpu->event[event].fence = fence; 1360 1364 submit->fence = fence->seqno; ··· 1395 1395 hangcheck_timer_reset(gpu); 1396 1396 ret = 0; 1397 1397 1398 - out_unlock: 1399 1398 mutex_unlock(&gpu->lock); 1400 1399 1400 + out_pm_put: 1401 1401 etnaviv_gpu_pm_put(gpu); 1402 1402 1403 1403 return ret;
+1
drivers/gpu/drm/i915/i915_drv.h
··· 1854 1854 enum modeset_restore modeset_restore; 1855 1855 struct mutex modeset_restore_lock; 1856 1856 struct drm_atomic_state *modeset_restore_state; 1857 + struct drm_modeset_acquire_ctx reset_ctx; 1857 1858 1858 1859 struct list_head vm_list; /* Global list of all address spaces */ 1859 1860 struct i915_ggtt ggtt; /* VM representing the global address space */
+8 -2
drivers/gpu/drm/i915/i915_gem.c
··· 879 879 ret = i915_gem_shmem_pread(dev, obj, args, file); 880 880 881 881 /* pread for non shmem backed objects */ 882 - if (ret == -EFAULT || ret == -ENODEV) 882 + if (ret == -EFAULT || ret == -ENODEV) { 883 + intel_runtime_pm_get(to_i915(dev)); 883 884 ret = i915_gem_gtt_pread(dev, obj, args->size, 884 885 args->offset, args->data_ptr); 886 + intel_runtime_pm_put(to_i915(dev)); 887 + } 885 888 886 889 out: 887 890 drm_gem_object_unreference(&obj->base); ··· 1309 1306 * textures). Fallback to the shmem path in that case. */ 1310 1307 } 1311 1308 1312 - if (ret == -EFAULT) { 1309 + if (ret == -EFAULT || ret == -ENOSPC) { 1313 1310 if (obj->phys_handle) 1314 1311 ret = i915_gem_phys_pwrite(obj, args, file); 1315 1312 else if (i915_gem_object_has_struct_page(obj)) ··· 3172 3169 } 3173 3170 3174 3171 intel_ring_init_seqno(engine, engine->last_submitted_seqno); 3172 + 3173 + engine->i915->gt.active_engines &= ~intel_engine_flag(engine); 3175 3174 } 3176 3175 3177 3176 void i915_gem_reset(struct drm_device *dev) ··· 3191 3186 3192 3187 for_each_engine(engine, dev_priv) 3193 3188 i915_gem_reset_engine_cleanup(engine); 3189 + mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); 3194 3190 3195 3191 i915_gem_context_reset(dev); 3196 3192
+1
drivers/gpu/drm/i915/i915_gem_gtt.c
··· 2873 2873 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2874 2874 2875 2875 ppgtt->base.cleanup(&ppgtt->base); 2876 + kfree(ppgtt); 2876 2877 } 2877 2878 2878 2879 i915_gem_cleanup_stolen(dev);
+1
drivers/gpu/drm/i915/i915_reg.h
··· 1536 1536 #define BALANCE_LEG_MASK(port) (7<<(8+3*(port))) 1537 1537 /* Balance leg disable bits */ 1538 1538 #define BALANCE_LEG_DISABLE_SHIFT 23 1539 + #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 1539 1540 1540 1541 /* 1541 1542 * Fence registers
+6
drivers/gpu/drm/i915/intel_audio.c
··· 600 600 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) 601 601 return; 602 602 603 + i915_audio_component_get_power(dev); 604 + 603 605 /* 604 606 * Enable/disable generating the codec wake signal, overriding the 605 607 * internal logic to generate the codec wake to controller. ··· 617 615 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 618 616 usleep_range(1000, 1500); 619 617 } 618 + 619 + i915_audio_component_put_power(dev); 620 620 } 621 621 622 622 /* Get CDCLK in kHz */ ··· 652 648 !IS_HASWELL(dev_priv)) 653 649 return 0; 654 650 651 + i915_audio_component_get_power(dev); 655 652 mutex_lock(&dev_priv->av_mutex); 656 653 /* 1. get the pipe */ 657 654 intel_encoder = dev_priv->dig_port_map[port]; ··· 703 698 704 699 unlock: 705 700 mutex_unlock(&dev_priv->av_mutex); 701 + i915_audio_component_put_power(dev); 706 702 return err; 707 703 } 708 704
+65 -26
drivers/gpu/drm/i915/intel_ddi.c
··· 145 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 146 146 { 0x0000201B, 0x000000A2, 0x0 }, 147 147 { 0x00005012, 0x00000088, 0x0 }, 148 - { 0x80007011, 0x000000CD, 0x0 }, 148 + { 0x80007011, 0x000000CD, 0x1 }, 149 149 { 0x80009010, 0x000000C0, 0x1 }, 150 150 { 0x0000201B, 0x0000009D, 0x0 }, 151 151 { 0x80005012, 0x000000C0, 0x1 }, ··· 158 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 159 159 { 0x00000018, 0x000000A2, 0x0 }, 160 160 { 0x00005012, 0x00000088, 0x0 }, 161 - { 0x80007011, 0x000000CD, 0x0 }, 161 + { 0x80007011, 0x000000CD, 0x3 }, 162 162 { 0x80009010, 0x000000C0, 0x3 }, 163 163 { 0x00000018, 0x0000009D, 0x0 }, 164 164 { 0x80005012, 0x000000C0, 0x3 }, ··· 388 388 } 389 389 } 390 390 391 + static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) 392 + { 393 + int n_hdmi_entries; 394 + int hdmi_level; 395 + int hdmi_default_entry; 396 + 397 + hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 398 + 399 + if (IS_BROXTON(dev_priv)) 400 + return hdmi_level; 401 + 402 + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 403 + skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 404 + hdmi_default_entry = 8; 405 + } else if (IS_BROADWELL(dev_priv)) { 406 + n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 407 + hdmi_default_entry = 7; 408 + } else if (IS_HASWELL(dev_priv)) { 409 + n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 410 + hdmi_default_entry = 6; 411 + } else { 412 + WARN(1, "ddi translation table missing\n"); 413 + n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 414 + hdmi_default_entry = 7; 415 + } 416 + 417 + /* Choose a good default if VBT is badly populated */ 418 + if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 419 + hdmi_level >= n_hdmi_entries) 420 + hdmi_level = hdmi_default_entry; 421 + 422 + return hdmi_level; 423 + } 424 + 391 425 /* 392 426 * Starting with Haswell, DDI port buffers must be programmed with correct 393 427 * values in advance. The buffer values are different for FDI and DP modes, ··· 433 399 { 434 400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 435 401 u32 iboost_bit = 0; 436 - int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 402 + int i, n_hdmi_entries, n_dp_entries, n_edp_entries, 437 403 size; 438 404 int hdmi_level; 439 405 enum port port; ··· 444 410 const struct ddi_buf_trans *ddi_translations; 445 411 446 412 port = intel_ddi_get_encoder_port(encoder); 447 - hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 413 + hdmi_level = intel_ddi_hdmi_level(dev_priv, port); 448 414 449 415 if (IS_BROXTON(dev_priv)) { 450 416 if (encoder->type != INTEL_OUTPUT_HDMI) ··· 464 430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries); 465 431 ddi_translations_hdmi = 466 432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); 467 - hdmi_default_entry = 8; 468 433 /* If we're boosting the current, set bit 31 of trans1 */ 469 434 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 470 435 dev_priv->vbt.ddi_port_info[port].dp_boost_level) ··· 489 456 490 457 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 491 458 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 492 - hdmi_default_entry = 7; 493 459 } else if (IS_HASWELL(dev_priv)) { 494 460 ddi_translations_fdi = hsw_ddi_translations_fdi; 495 461 ddi_translations_dp = hsw_ddi_translations_dp; ··· 496 464 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 497 465 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 498 466 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 499 - hdmi_default_entry = 6; 500 467 } else { 501 468 WARN(1, "ddi translation table missing\n"); 502 469 ddi_translations_edp = bdw_ddi_translations_dp; ··· 505 474 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 506 475 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 507 476 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 508 - hdmi_default_entry = 7; 509 477 } 510 478 511 479 switch (encoder->type) { ··· 534 504 535 505 if (encoder->type != INTEL_OUTPUT_HDMI) 536 506 return; 537 - 538 - /* Choose a good default if VBT is badly populated */ 539 - if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 540 - hdmi_level >= n_hdmi_entries) 541 - hdmi_level = hdmi_default_entry; 542 507 543 508 /* Entry 9 is for HDMI: */ 544 509 I915_WRITE(DDI_BUF_TRANS_LO(port, i), ··· 1404 1379 TRANS_CLK_SEL_DISABLED); 1405 1380 } 1406 1381 1407 - static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1408 - u32 level, enum port port, int type) 1382 + static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1383 + enum port port, uint8_t iboost) 1409 1384 { 1385 + u32 tmp; 1386 + 1387 + tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); 1388 + tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1389 + if (iboost) 1390 + tmp |= iboost << BALANCE_LEG_SHIFT(port); 1391 + else 1392 + tmp |= BALANCE_LEG_DISABLE(port); 1393 + I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); 1394 + } 1395 + 1396 + static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) 1397 + { 1398 + struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); 1399 + struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 1400 + enum port port = intel_dig_port->port; 1401 + int type = encoder->type; 1410 1402 const struct ddi_buf_trans *ddi_translations; 1411 1403 uint8_t iboost; 1412 1404 uint8_t dp_iboost, hdmi_iboost; 1413 1405 int n_entries; 1414 - u32 reg; 1415 1406 1416 1407 /* VBT may override standard boost values */ 1417 1408 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; ··· 1469 1428 return; 1470 1429 } 1471 1430 1472 - reg = I915_READ(DISPIO_CR_TX_BMU_CR0); 1473 - reg &= ~BALANCE_LEG_MASK(port); 1474 - reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); 1431 + _skl_ddi_set_iboost(dev_priv, port, iboost); 1475 1432 1476 - if (iboost) 1477 - reg |= iboost << BALANCE_LEG_SHIFT(port); 1478 - else 1479 - reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); 1480 - 1481 - I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); 1433 + if (port == PORT_A && intel_dig_port->max_lanes == 4) 1434 + _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1482 1435 } 1483 1436 1484 1437 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, ··· 1603 1568 level = translate_signal_level(signal_levels); 1604 1569 1605 1570 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 1606 - skl_ddi_set_iboost(dev_priv, level, port, encoder->type); 1571 + skl_ddi_set_iboost(encoder, level); 1607 1572 else if (IS_BROXTON(dev_priv)) 1608 1573 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); 1609 1574 ··· 1672 1637 intel_dp_stop_link_train(intel_dp); 1673 1638 } else if (type == INTEL_OUTPUT_HDMI) { 1674 1639 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1640 + int level = intel_ddi_hdmi_level(dev_priv, port); 1641 + 1642 + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 1643 + skl_ddi_set_iboost(intel_encoder, level); 1675 1644 1676 1645 intel_hdmi->set_infoframes(encoder, 1677 1646 crtc->config->has_hdmi_sink,
+114 -64
drivers/gpu/drm/i915/intel_display.c
··· 3093 3093 3094 3094 for_each_crtc(dev, crtc) { 3095 3095 struct intel_plane *plane = to_intel_plane(crtc->primary); 3096 - struct intel_plane_state *plane_state; 3097 - 3098 - drm_modeset_lock_crtc(crtc, &plane->base); 3099 - plane_state = to_intel_plane_state(plane->base.state); 3096 + struct intel_plane_state *plane_state = 3097 + to_intel_plane_state(plane->base.state); 3100 3098 3101 3099 if (plane_state->visible) 3102 3100 plane->update_plane(&plane->base, 3103 3101 to_intel_crtc_state(crtc->state), 3104 3102 plane_state); 3105 - 3106 - drm_modeset_unlock_crtc(crtc); 3107 3103 } 3104 + } 3105 + 3106 + static int 3107 + __intel_display_resume(struct drm_device *dev, 3108 + struct drm_atomic_state *state) 3109 + { 3110 + struct drm_crtc_state *crtc_state; 3111 + struct drm_crtc *crtc; 3112 + int i, ret; 3113 + 3114 + intel_modeset_setup_hw_state(dev); 3115 + i915_redisable_vga(dev); 3116 + 3117 + if (!state) 3118 + return 0; 3119 + 3120 + for_each_crtc_in_state(state, crtc, crtc_state, i) { 3121 + /* 3122 + * Force recalculation even if we restore 3123 + * current state. With fast modeset this may not result 3124 + * in a modeset when the state is compatible. 3125 + */ 3126 + crtc_state->mode_changed = true; 3127 + } 3128 + 3129 + /* ignore any reset values/BIOS leftovers in the WM registers */ 3130 + to_intel_atomic_state(state)->skip_intermediate_wm = true; 3131 + 3132 + ret = drm_atomic_commit(state); 3133 + 3134 + WARN_ON(ret == -EDEADLK); 3135 + return ret; 3108 3136 } 3109 3137 3110 3138 void intel_prepare_reset(struct drm_i915_private *dev_priv) 3111 3139 { 3140 + struct drm_device *dev = &dev_priv->drm; 3141 + struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 3142 + struct drm_atomic_state *state; 3143 + int ret; 3144 + 3112 3145 /* no reset support for gen2 */ 3113 3146 if (IS_GEN2(dev_priv)) 3114 3147 return; 3115 3148 3116 - /* reset doesn't touch the display */ 3149 + /* 3150 + * Need mode_config.mutex so that we don't 3151 + * trample ongoing ->detect() and whatnot. 3152 + */ 3153 + mutex_lock(&dev->mode_config.mutex); 3154 + drm_modeset_acquire_init(ctx, 0); 3155 + while (1) { 3156 + ret = drm_modeset_lock_all_ctx(dev, ctx); 3157 + if (ret != -EDEADLK) 3158 + break; 3159 + 3160 + drm_modeset_backoff(ctx); 3161 + } 3162 + 3163 + /* reset doesn't touch the display, but flips might get nuked anyway, */ 3117 3164 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) 3118 3165 return; 3119 3166 3120 - drm_modeset_lock_all(&dev_priv->drm); 3121 3167 /* 3122 3168 * Disabling the crtcs gracefully seems nicer. Also the 3123 3169 * g33 docs say we should at least disable all the planes. 3124 3170 */ 3125 - intel_display_suspend(&dev_priv->drm); 3171 + state = drm_atomic_helper_duplicate_state(dev, ctx); 3172 + if (IS_ERR(state)) { 3173 + ret = PTR_ERR(state); 3174 + state = NULL; 3175 + DRM_ERROR("Duplicating state failed with %i\n", ret); 3176 + goto err; 3177 + } 3178 + 3179 + ret = drm_atomic_helper_disable_all(dev, ctx); 3180 + if (ret) { 3181 + DRM_ERROR("Suspending crtc's failed with %i\n", ret); 3182 + goto err; 3183 + } 3184 + 3185 + dev_priv->modeset_restore_state = state; 3186 + state->acquire_ctx = ctx; 3187 + return; 3188 + 3189 + err: 3190 + drm_atomic_state_free(state); 3126 3191 } 3127 3192 3128 3193 void intel_finish_reset(struct drm_i915_private *dev_priv) 3129 3194 { 3195 + struct drm_device *dev = &dev_priv->drm; 3196 + struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; 3197 + struct drm_atomic_state *state = dev_priv->modeset_restore_state; 3198 + int ret; 3199 + 3130 3200 /* 3131 3201 * Flips in the rings will be nuked by the reset, 3132 3202 * so complete all pending flips so that user space ··· 3207 3137 /* no reset support for gen2 */ 3208 3138 if (IS_GEN2(dev_priv)) 3209 3139 return; 3140 + 3141 + dev_priv->modeset_restore_state = NULL; 3210 3142 3211 3143 /* reset doesn't touch the display */ 3212 3144 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { ··· 3221 3149 * FIXME: Atomic will make this obsolete since we won't schedule 3222 3150 * CS-based flips (which might get lost in gpu resets) any more. 3223 3151 */ 3224 - intel_update_primary_planes(&dev_priv->drm); 3225 - return; 3152 + intel_update_primary_planes(dev); 3153 + } else { 3154 + /* 3155 + * The display has been reset as well, 3156 + * so need a full re-initialization. 3157 + */ 3158 + intel_runtime_pm_disable_interrupts(dev_priv); 3159 + intel_runtime_pm_enable_interrupts(dev_priv); 3160 + 3161 + intel_modeset_init_hw(dev); 3162 + 3163 + spin_lock_irq(&dev_priv->irq_lock); 3164 + if (dev_priv->display.hpd_irq_setup) 3165 + dev_priv->display.hpd_irq_setup(dev_priv); 3166 + spin_unlock_irq(&dev_priv->irq_lock); 3167 + 3168 + ret = __intel_display_resume(dev, state); 3169 + if (ret) 3170 + DRM_ERROR("Restoring old state failed with %i\n", ret); 3171 + 3172 + intel_hpd_init(dev_priv); 3226 3173 } 3227 3174 3228 - /* 3229 - * The display has been reset as well, 3230 - * so need a full re-initialization. 3231 - */ 3232 - intel_runtime_pm_disable_interrupts(dev_priv); 3233 - intel_runtime_pm_enable_interrupts(dev_priv); 3234 - 3235 - intel_modeset_init_hw(&dev_priv->drm); 3236 - 3237 - spin_lock_irq(&dev_priv->irq_lock); 3238 - if (dev_priv->display.hpd_irq_setup) 3239 - dev_priv->display.hpd_irq_setup(dev_priv); 3240 - spin_unlock_irq(&dev_priv->irq_lock); 3241 - 3242 - intel_display_resume(&dev_priv->drm); 3243 - 3244 - intel_hpd_init(dev_priv); 3245 - 3246 - drm_modeset_unlock_all(&dev_priv->drm); 3175 + drm_modeset_drop_locks(ctx); 3176 + drm_modeset_acquire_fini(ctx); 3177 + mutex_unlock(&dev->mode_config.mutex); 3247 3178 } 3248 3179 3249 3180 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) ··· 16231 16156 struct drm_atomic_state *state = dev_priv->modeset_restore_state; 16232 16157 struct drm_modeset_acquire_ctx ctx; 16233 16158 int ret; 16234 - bool setup = false; 16235 16159 16236 16160 dev_priv->modeset_restore_state = NULL; 16161 + if (state) 16162 + state->acquire_ctx = &ctx; 16237 16163 16238 16164 /* 16239 16165 * This is a cludge because with real atomic modeset mode_config.mutex ··· 16245 16169 mutex_lock(&dev->mode_config.mutex); 16246 16170 drm_modeset_acquire_init(&ctx, 0); 16247 16171 16248 - retry: 16249 - ret = drm_modeset_lock_all_ctx(dev, &ctx); 16172 + while (1) { 16173 + ret = drm_modeset_lock_all_ctx(dev, &ctx); 16174 + if (ret != -EDEADLK) 16175 + break; 16250 16176 16251 - if (ret == 0 && !setup) { 16252 - setup = true; 16253 - 16254 - intel_modeset_setup_hw_state(dev); 16255 - i915_redisable_vga(dev); 16256 - } 16257 - 16258 - if (ret == 0 && state) { 16259 - struct drm_crtc_state *crtc_state; 16260 - struct drm_crtc *crtc; 16261 - int i; 16262 - 16263 - state->acquire_ctx = &ctx; 16264 - 16265 - /* ignore any reset values/BIOS leftovers in the WM registers */ 16266 - to_intel_atomic_state(state)->skip_intermediate_wm = true; 16267 - 16268 - for_each_crtc_in_state(state, crtc, crtc_state, i) { 16269 - /* 16270 - * Force recalculation even if we restore 16271 - * current state. With fast modeset this may not result 16272 - * in a modeset when the state is compatible. 16273 - */ 16274 - crtc_state->mode_changed = true; 16275 - } 16276 - 16277 - ret = drm_atomic_commit(state); 16278 - } 16279 - 16280 - if (ret == -EDEADLK) { 16281 16177 drm_modeset_backoff(&ctx); 16282 - goto retry; 16283 16178 } 16179 + 16180 + if (!ret) 16181 + ret = __intel_display_resume(dev, state); 16284 16182 16285 16183 drm_modeset_drop_locks(&ctx); 16286 16184 drm_modeset_acquire_fini(&ctx);
+20
drivers/gpu/drm/i915/intel_fbc.c
··· 1230 1230 if (i915.enable_fbc >= 0) 1231 1231 return !!i915.enable_fbc; 1232 1232 1233 + if (!HAS_FBC(dev_priv)) 1234 + return 0; 1235 + 1233 1236 if (IS_BROADWELL(dev_priv)) 1234 1237 return 1; 1235 1238 1236 1239 return 0; 1240 + } 1241 + 1242 + static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) 1243 + { 1244 + #ifdef CONFIG_INTEL_IOMMU 1245 + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ 1246 + if (intel_iommu_gfx_mapped && 1247 + (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { 1248 + DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); 1249 + return true; 1250 + } 1251 + #endif 1252 + 1253 + return false; 1237 1254 } 1238 1255 1239 1256 /** ··· 1269 1252 fbc->enabled = false; 1270 1253 fbc->active = false; 1271 1254 fbc->work.scheduled = false; 1255 + 1256 + if (need_fbc_vtd_wa(dev_priv)) 1257 + mkwrite_device_info(dev_priv)->has_fbc = false; 1272 1258 1273 1259 i915.enable_fbc = intel_sanitize_fbc_option(dev_priv); 1274 1260 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
+3 -3
drivers/gpu/drm/i915/intel_pm.c
··· 3344 3344 plane_bytes_per_line *= 4; 3345 3345 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3346 3346 plane_blocks_per_line /= 4; 3347 + } else if (tiling == DRM_FORMAT_MOD_NONE) { 3348 + plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; 3347 3349 } else { 3348 3350 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3349 3351 } ··· 6576 6574 6577 6575 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) 6578 6576 { 6579 - if (IS_CHERRYVIEW(dev_priv)) 6580 - return; 6581 - else if (IS_VALLEYVIEW(dev_priv)) 6577 + if (IS_VALLEYVIEW(dev_priv)) 6582 6578 valleyview_cleanup_gt_powersave(dev_priv); 6583 6579 6584 6580 if (!i915.enable_rc6)
+4 -4
drivers/gpu/drm/i915/intel_ringbuffer.c
··· 1178 1178 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | 1179 1179 L3_HIGH_PRIO_CREDITS(2)); 1180 1180 1181 - /* WaInsertDummyPushConstPs:bxt */ 1182 - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) 1181 + /* WaToEnableHwFixForPushConstHWBug:bxt */ 1182 + if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) 1183 1183 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 1184 1184 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 1185 1185 ··· 1222 1222 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | 1223 1223 GEN8_LQSC_RO_PERF_DIS); 1224 1224 1225 - /* WaInsertDummyPushConstPs:kbl */ 1226 - if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) 1225 + /* WaToEnableHwFixForPushConstHWBug:kbl */ 1226 + if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) 1227 1227 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 1228 1228 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 1229 1229