Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sm8150: Retire DEFINE_QNODE
The struct definition macros are hard to read and compare, expand them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-7-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Konrad Dybcio
and committed by
Georgi Djakov
9533964b
5affec83
+1263
-138
+1263
-138
drivers/interconnect/qcom/sm8150.c
+1263
-138
drivers/interconnect/qcom/sm8150.c
···
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#include "icc-rpmh.h"
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#include "sm8150.h"
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DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
20
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DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
21
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DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
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DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
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DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
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DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
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DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
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DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
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DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
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DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
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DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
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DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
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DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
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DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
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DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
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DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
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DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
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DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
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DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
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DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
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DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
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DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
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DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
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DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
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DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
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DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
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DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
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DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
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DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
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DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
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DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
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DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
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DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
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DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
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DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
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DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
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DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
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DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
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DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
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DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
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DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
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DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
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DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
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DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
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DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
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DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
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DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
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DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
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DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
106
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DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
107
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DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
108
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DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
109
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DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
110
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DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
111
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DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
112
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DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
113
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DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
114
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DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
115
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DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
116
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DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
117
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DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
118
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DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
119
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DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
120
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DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
121
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DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
122
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DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
123
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DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
124
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DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
125
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DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
126
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DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
127
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DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
128
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DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
129
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DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
130
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DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
131
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DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
132
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DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
133
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DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
134
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DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
135
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DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
136
-
DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
137
-
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
138
-
DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
139
-
DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
140
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DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
141
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DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
142
-
DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
143
-
DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
144
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DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
145
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DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
146
-
DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
147
-
DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
148
-
DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
149
-
DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
150
-
DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
151
-
DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
152
-
DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
153
-
DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
154
-
DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
155
-
DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
156
-
DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
19
+
static struct qcom_icc_node qhm_a1noc_cfg = {
20
+
.name = "qhm_a1noc_cfg",
21
+
.id = SM8150_MASTER_A1NOC_CFG,
22
+
.channels = 1,
23
+
.buswidth = 4,
24
+
.num_links = 1,
25
+
.links = { SM8150_SLAVE_SERVICE_A1NOC },
26
+
};
27
+
28
+
static struct qcom_icc_node qhm_qup0 = {
29
+
.name = "qhm_qup0",
30
+
.id = SM8150_MASTER_QUP_0,
31
+
.channels = 1,
32
+
.buswidth = 4,
33
+
.num_links = 1,
34
+
.links = { SM8150_A1NOC_SNOC_SLV },
35
+
};
36
+
37
+
static struct qcom_icc_node xm_emac = {
38
+
.name = "xm_emac",
39
+
.id = SM8150_MASTER_EMAC,
40
+
.channels = 1,
41
+
.buswidth = 8,
42
+
.num_links = 1,
43
+
.links = { SM8150_A1NOC_SNOC_SLV },
44
+
};
45
+
46
+
static struct qcom_icc_node xm_ufs_mem = {
47
+
.name = "xm_ufs_mem",
48
+
.id = SM8150_MASTER_UFS_MEM,
49
+
.channels = 1,
50
+
.buswidth = 8,
51
+
.num_links = 1,
52
+
.links = { SM8150_A1NOC_SNOC_SLV },
53
+
};
54
+
55
+
static struct qcom_icc_node xm_usb3_0 = {
56
+
.name = "xm_usb3_0",
57
+
.id = SM8150_MASTER_USB3,
58
+
.channels = 1,
59
+
.buswidth = 8,
60
+
.num_links = 1,
61
+
.links = { SM8150_A1NOC_SNOC_SLV },
62
+
};
63
+
64
+
static struct qcom_icc_node xm_usb3_1 = {
65
+
.name = "xm_usb3_1",
66
+
.id = SM8150_MASTER_USB3_1,
67
+
.channels = 1,
68
+
.buswidth = 8,
69
+
.num_links = 1,
70
+
.links = { SM8150_A1NOC_SNOC_SLV },
71
+
};
72
+
73
+
static struct qcom_icc_node qhm_a2noc_cfg = {
74
+
.name = "qhm_a2noc_cfg",
75
+
.id = SM8150_MASTER_A2NOC_CFG,
76
+
.channels = 1,
77
+
.buswidth = 4,
78
+
.num_links = 1,
79
+
.links = { SM8150_SLAVE_SERVICE_A2NOC },
80
+
};
81
+
82
+
static struct qcom_icc_node qhm_qdss_bam = {
83
+
.name = "qhm_qdss_bam",
84
+
.id = SM8150_MASTER_QDSS_BAM,
85
+
.channels = 1,
86
+
.buswidth = 4,
87
+
.num_links = 1,
88
+
.links = { SM8150_A2NOC_SNOC_SLV },
89
+
};
90
+
91
+
static struct qcom_icc_node qhm_qspi = {
92
+
.name = "qhm_qspi",
93
+
.id = SM8150_MASTER_QSPI,
94
+
.channels = 1,
95
+
.buswidth = 4,
96
+
.num_links = 1,
97
+
.links = { SM8150_A2NOC_SNOC_SLV },
98
+
};
99
+
100
+
static struct qcom_icc_node qhm_qup1 = {
101
+
.name = "qhm_qup1",
102
+
.id = SM8150_MASTER_QUP_1,
103
+
.channels = 1,
104
+
.buswidth = 4,
105
+
.num_links = 1,
106
+
.links = { SM8150_A2NOC_SNOC_SLV },
107
+
};
108
+
109
+
static struct qcom_icc_node qhm_qup2 = {
110
+
.name = "qhm_qup2",
111
+
.id = SM8150_MASTER_QUP_2,
112
+
.channels = 1,
113
+
.buswidth = 4,
114
+
.num_links = 1,
115
+
.links = { SM8150_A2NOC_SNOC_SLV },
116
+
};
117
+
118
+
static struct qcom_icc_node qhm_sensorss_ahb = {
119
+
.name = "qhm_sensorss_ahb",
120
+
.id = SM8150_MASTER_SENSORS_AHB,
121
+
.channels = 1,
122
+
.buswidth = 4,
123
+
.num_links = 1,
124
+
.links = { SM8150_A2NOC_SNOC_SLV },
125
+
};
126
+
127
+
static struct qcom_icc_node qhm_tsif = {
128
+
.name = "qhm_tsif",
129
+
.id = SM8150_MASTER_TSIF,
130
+
.channels = 1,
131
+
.buswidth = 4,
132
+
.num_links = 1,
133
+
.links = { SM8150_A2NOC_SNOC_SLV },
134
+
};
135
+
136
+
static struct qcom_icc_node qnm_cnoc = {
137
+
.name = "qnm_cnoc",
138
+
.id = SM8150_MASTER_CNOC_A2NOC,
139
+
.channels = 1,
140
+
.buswidth = 8,
141
+
.num_links = 1,
142
+
.links = { SM8150_A2NOC_SNOC_SLV },
143
+
};
144
+
145
+
static struct qcom_icc_node qxm_crypto = {
146
+
.name = "qxm_crypto",
147
+
.id = SM8150_MASTER_CRYPTO_CORE_0,
148
+
.channels = 1,
149
+
.buswidth = 8,
150
+
.num_links = 1,
151
+
.links = { SM8150_A2NOC_SNOC_SLV },
152
+
};
153
+
154
+
static struct qcom_icc_node qxm_ipa = {
155
+
.name = "qxm_ipa",
156
+
.id = SM8150_MASTER_IPA,
157
+
.channels = 1,
158
+
.buswidth = 8,
159
+
.num_links = 1,
160
+
.links = { SM8150_A2NOC_SNOC_SLV },
161
+
};
162
+
163
+
static struct qcom_icc_node xm_pcie3_0 = {
164
+
.name = "xm_pcie3_0",
165
+
.id = SM8150_MASTER_PCIE,
166
+
.channels = 1,
167
+
.buswidth = 8,
168
+
.num_links = 1,
169
+
.links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC },
170
+
};
171
+
172
+
static struct qcom_icc_node xm_pcie3_1 = {
173
+
.name = "xm_pcie3_1",
174
+
.id = SM8150_MASTER_PCIE_1,
175
+
.channels = 1,
176
+
.buswidth = 8,
177
+
.num_links = 1,
178
+
.links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC },
179
+
};
180
+
181
+
static struct qcom_icc_node xm_qdss_etr = {
182
+
.name = "xm_qdss_etr",
183
+
.id = SM8150_MASTER_QDSS_ETR,
184
+
.channels = 1,
185
+
.buswidth = 8,
186
+
.num_links = 1,
187
+
.links = { SM8150_A2NOC_SNOC_SLV },
188
+
};
189
+
190
+
static struct qcom_icc_node xm_sdc2 = {
191
+
.name = "xm_sdc2",
192
+
.id = SM8150_MASTER_SDCC_2,
193
+
.channels = 1,
194
+
.buswidth = 8,
195
+
.num_links = 1,
196
+
.links = { SM8150_A2NOC_SNOC_SLV },
197
+
};
198
+
199
+
static struct qcom_icc_node xm_sdc4 = {
200
+
.name = "xm_sdc4",
201
+
.id = SM8150_MASTER_SDCC_4,
202
+
.channels = 1,
203
+
.buswidth = 8,
204
+
.num_links = 1,
205
+
.links = { SM8150_A2NOC_SNOC_SLV },
206
+
};
207
+
208
+
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
209
+
.name = "qxm_camnoc_hf0_uncomp",
210
+
.id = SM8150_MASTER_CAMNOC_HF0_UNCOMP,
211
+
.channels = 1,
212
+
.buswidth = 32,
213
+
.num_links = 1,
214
+
.links = { SM8150_SLAVE_CAMNOC_UNCOMP },
215
+
};
216
+
217
+
static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
218
+
.name = "qxm_camnoc_hf1_uncomp",
219
+
.id = SM8150_MASTER_CAMNOC_HF1_UNCOMP,
220
+
.channels = 1,
221
+
.buswidth = 32,
222
+
.num_links = 1,
223
+
.links = { SM8150_SLAVE_CAMNOC_UNCOMP },
224
+
};
225
+
226
+
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
227
+
.name = "qxm_camnoc_sf_uncomp",
228
+
.id = SM8150_MASTER_CAMNOC_SF_UNCOMP,
229
+
.channels = 1,
230
+
.buswidth = 32,
231
+
.num_links = 1,
232
+
.links = { SM8150_SLAVE_CAMNOC_UNCOMP },
233
+
};
234
+
235
+
static struct qcom_icc_node qnm_npu = {
236
+
.name = "qnm_npu",
237
+
.id = SM8150_MASTER_NPU,
238
+
.channels = 1,
239
+
.buswidth = 32,
240
+
.num_links = 1,
241
+
.links = { SM8150_SLAVE_CDSP_MEM_NOC },
242
+
};
243
+
244
+
static struct qcom_icc_node qhm_spdm = {
245
+
.name = "qhm_spdm",
246
+
.id = SM8150_MASTER_SPDM,
247
+
.channels = 1,
248
+
.buswidth = 4,
249
+
.num_links = 1,
250
+
.links = { SM8150_SLAVE_CNOC_A2NOC },
251
+
};
252
+
253
+
static struct qcom_icc_node qnm_snoc = {
254
+
.name = "qnm_snoc",
255
+
.id = SM8150_SNOC_CNOC_MAS,
256
+
.channels = 1,
257
+
.buswidth = 8,
258
+
.num_links = 50,
259
+
.links = { SM8150_SLAVE_TLMM_SOUTH,
260
+
SM8150_SLAVE_CDSP_CFG,
261
+
SM8150_SLAVE_SPSS_CFG,
262
+
SM8150_SLAVE_CAMERA_CFG,
263
+
SM8150_SLAVE_SDCC_4,
264
+
SM8150_SLAVE_SDCC_2,
265
+
SM8150_SLAVE_CNOC_MNOC_CFG,
266
+
SM8150_SLAVE_EMAC_CFG,
267
+
SM8150_SLAVE_UFS_MEM_CFG,
268
+
SM8150_SLAVE_TLMM_EAST,
269
+
SM8150_SLAVE_SSC_CFG,
270
+
SM8150_SLAVE_SNOC_CFG,
271
+
SM8150_SLAVE_NORTH_PHY_CFG,
272
+
SM8150_SLAVE_QUP_0,
273
+
SM8150_SLAVE_GLM,
274
+
SM8150_SLAVE_PCIE_1_CFG,
275
+
SM8150_SLAVE_A2NOC_CFG,
276
+
SM8150_SLAVE_QDSS_CFG,
277
+
SM8150_SLAVE_DISPLAY_CFG,
278
+
SM8150_SLAVE_TCSR,
279
+
SM8150_SLAVE_CNOC_DDRSS,
280
+
SM8150_SLAVE_RBCPR_MMCX_CFG,
281
+
SM8150_SLAVE_NPU_CFG,
282
+
SM8150_SLAVE_PCIE_0_CFG,
283
+
SM8150_SLAVE_GRAPHICS_3D_CFG,
284
+
SM8150_SLAVE_VENUS_CFG,
285
+
SM8150_SLAVE_TSIF,
286
+
SM8150_SLAVE_IPA_CFG,
287
+
SM8150_SLAVE_CLK_CTL,
288
+
SM8150_SLAVE_AOP,
289
+
SM8150_SLAVE_QUP_1,
290
+
SM8150_SLAVE_AHB2PHY_SOUTH,
291
+
SM8150_SLAVE_USB3_1,
292
+
SM8150_SLAVE_SERVICE_CNOC,
293
+
SM8150_SLAVE_UFS_CARD_CFG,
294
+
SM8150_SLAVE_QUP_2,
295
+
SM8150_SLAVE_RBCPR_CX_CFG,
296
+
SM8150_SLAVE_TLMM_WEST,
297
+
SM8150_SLAVE_A1NOC_CFG,
298
+
SM8150_SLAVE_AOSS,
299
+
SM8150_SLAVE_PRNG,
300
+
SM8150_SLAVE_VSENSE_CTRL_CFG,
301
+
SM8150_SLAVE_QSPI,
302
+
SM8150_SLAVE_USB3,
303
+
SM8150_SLAVE_SPDM_WRAPPER,
304
+
SM8150_SLAVE_CRYPTO_0_CFG,
305
+
SM8150_SLAVE_PIMEM_CFG,
306
+
SM8150_SLAVE_TLMM_NORTH,
307
+
SM8150_SLAVE_RBCPR_MX_CFG,
308
+
SM8150_SLAVE_IMEM_CFG
309
+
},
310
+
};
311
+
312
+
static struct qcom_icc_node xm_qdss_dap = {
313
+
.name = "xm_qdss_dap",
314
+
.id = SM8150_MASTER_QDSS_DAP,
315
+
.channels = 1,
316
+
.buswidth = 8,
317
+
.num_links = 51,
318
+
.links = { SM8150_SLAVE_TLMM_SOUTH,
319
+
SM8150_SLAVE_CDSP_CFG,
320
+
SM8150_SLAVE_SPSS_CFG,
321
+
SM8150_SLAVE_CAMERA_CFG,
322
+
SM8150_SLAVE_SDCC_4,
323
+
SM8150_SLAVE_SDCC_2,
324
+
SM8150_SLAVE_CNOC_MNOC_CFG,
325
+
SM8150_SLAVE_EMAC_CFG,
326
+
SM8150_SLAVE_UFS_MEM_CFG,
327
+
SM8150_SLAVE_TLMM_EAST,
328
+
SM8150_SLAVE_SSC_CFG,
329
+
SM8150_SLAVE_SNOC_CFG,
330
+
SM8150_SLAVE_NORTH_PHY_CFG,
331
+
SM8150_SLAVE_QUP_0,
332
+
SM8150_SLAVE_GLM,
333
+
SM8150_SLAVE_PCIE_1_CFG,
334
+
SM8150_SLAVE_A2NOC_CFG,
335
+
SM8150_SLAVE_QDSS_CFG,
336
+
SM8150_SLAVE_DISPLAY_CFG,
337
+
SM8150_SLAVE_TCSR,
338
+
SM8150_SLAVE_CNOC_DDRSS,
339
+
SM8150_SLAVE_CNOC_A2NOC,
340
+
SM8150_SLAVE_RBCPR_MMCX_CFG,
341
+
SM8150_SLAVE_NPU_CFG,
342
+
SM8150_SLAVE_PCIE_0_CFG,
343
+
SM8150_SLAVE_GRAPHICS_3D_CFG,
344
+
SM8150_SLAVE_VENUS_CFG,
345
+
SM8150_SLAVE_TSIF,
346
+
SM8150_SLAVE_IPA_CFG,
347
+
SM8150_SLAVE_CLK_CTL,
348
+
SM8150_SLAVE_AOP,
349
+
SM8150_SLAVE_QUP_1,
350
+
SM8150_SLAVE_AHB2PHY_SOUTH,
351
+
SM8150_SLAVE_USB3_1,
352
+
SM8150_SLAVE_SERVICE_CNOC,
353
+
SM8150_SLAVE_UFS_CARD_CFG,
354
+
SM8150_SLAVE_QUP_2,
355
+
SM8150_SLAVE_RBCPR_CX_CFG,
356
+
SM8150_SLAVE_TLMM_WEST,
357
+
SM8150_SLAVE_A1NOC_CFG,
358
+
SM8150_SLAVE_AOSS,
359
+
SM8150_SLAVE_PRNG,
360
+
SM8150_SLAVE_VSENSE_CTRL_CFG,
361
+
SM8150_SLAVE_QSPI,
362
+
SM8150_SLAVE_USB3,
363
+
SM8150_SLAVE_SPDM_WRAPPER,
364
+
SM8150_SLAVE_CRYPTO_0_CFG,
365
+
SM8150_SLAVE_PIMEM_CFG,
366
+
SM8150_SLAVE_TLMM_NORTH,
367
+
SM8150_SLAVE_RBCPR_MX_CFG,
368
+
SM8150_SLAVE_IMEM_CFG
369
+
},
370
+
};
371
+
372
+
static struct qcom_icc_node qhm_cnoc_dc_noc = {
373
+
.name = "qhm_cnoc_dc_noc",
374
+
.id = SM8150_MASTER_CNOC_DC_NOC,
375
+
.channels = 1,
376
+
.buswidth = 4,
377
+
.num_links = 2,
378
+
.links = { SM8150_SLAVE_GEM_NOC_CFG,
379
+
SM8150_SLAVE_LLCC_CFG
380
+
},
381
+
};
382
+
383
+
static struct qcom_icc_node acm_apps = {
384
+
.name = "acm_apps",
385
+
.id = SM8150_MASTER_AMPSS_M0,
386
+
.channels = 2,
387
+
.buswidth = 32,
388
+
.num_links = 3,
389
+
.links = { SM8150_SLAVE_ECC,
390
+
SM8150_SLAVE_LLCC,
391
+
SM8150_SLAVE_GEM_NOC_SNOC
392
+
},
393
+
};
394
+
395
+
static struct qcom_icc_node acm_gpu_tcu = {
396
+
.name = "acm_gpu_tcu",
397
+
.id = SM8150_MASTER_GPU_TCU,
398
+
.channels = 1,
399
+
.buswidth = 8,
400
+
.num_links = 2,
401
+
.links = { SM8150_SLAVE_LLCC,
402
+
SM8150_SLAVE_GEM_NOC_SNOC
403
+
},
404
+
};
405
+
406
+
static struct qcom_icc_node acm_sys_tcu = {
407
+
.name = "acm_sys_tcu",
408
+
.id = SM8150_MASTER_SYS_TCU,
409
+
.channels = 1,
410
+
.buswidth = 8,
411
+
.num_links = 2,
412
+
.links = { SM8150_SLAVE_LLCC,
413
+
SM8150_SLAVE_GEM_NOC_SNOC
414
+
},
415
+
};
416
+
417
+
static struct qcom_icc_node qhm_gemnoc_cfg = {
418
+
.name = "qhm_gemnoc_cfg",
419
+
.id = SM8150_MASTER_GEM_NOC_CFG,
420
+
.channels = 1,
421
+
.buswidth = 4,
422
+
.num_links = 2,
423
+
.links = { SM8150_SLAVE_SERVICE_GEM_NOC,
424
+
SM8150_SLAVE_MSS_PROC_MS_MPU_CFG
425
+
},
426
+
};
427
+
428
+
static struct qcom_icc_node qnm_cmpnoc = {
429
+
.name = "qnm_cmpnoc",
430
+
.id = SM8150_MASTER_COMPUTE_NOC,
431
+
.channels = 2,
432
+
.buswidth = 32,
433
+
.num_links = 3,
434
+
.links = { SM8150_SLAVE_ECC,
435
+
SM8150_SLAVE_LLCC,
436
+
SM8150_SLAVE_GEM_NOC_SNOC
437
+
},
438
+
};
439
+
440
+
static struct qcom_icc_node qnm_gpu = {
441
+
.name = "qnm_gpu",
442
+
.id = SM8150_MASTER_GRAPHICS_3D,
443
+
.channels = 2,
444
+
.buswidth = 32,
445
+
.num_links = 2,
446
+
.links = { SM8150_SLAVE_LLCC,
447
+
SM8150_SLAVE_GEM_NOC_SNOC
448
+
},
449
+
};
450
+
451
+
static struct qcom_icc_node qnm_mnoc_hf = {
452
+
.name = "qnm_mnoc_hf",
453
+
.id = SM8150_MASTER_MNOC_HF_MEM_NOC,
454
+
.channels = 2,
455
+
.buswidth = 32,
456
+
.num_links = 1,
457
+
.links = { SM8150_SLAVE_LLCC },
458
+
};
459
+
460
+
static struct qcom_icc_node qnm_mnoc_sf = {
461
+
.name = "qnm_mnoc_sf",
462
+
.id = SM8150_MASTER_MNOC_SF_MEM_NOC,
463
+
.channels = 1,
464
+
.buswidth = 32,
465
+
.num_links = 2,
466
+
.links = { SM8150_SLAVE_LLCC,
467
+
SM8150_SLAVE_GEM_NOC_SNOC
468
+
},
469
+
};
470
+
471
+
static struct qcom_icc_node qnm_pcie = {
472
+
.name = "qnm_pcie",
473
+
.id = SM8150_MASTER_GEM_NOC_PCIE_SNOC,
474
+
.channels = 1,
475
+
.buswidth = 16,
476
+
.num_links = 2,
477
+
.links = { SM8150_SLAVE_LLCC,
478
+
SM8150_SLAVE_GEM_NOC_SNOC
479
+
},
480
+
};
481
+
482
+
static struct qcom_icc_node qnm_snoc_gc = {
483
+
.name = "qnm_snoc_gc",
484
+
.id = SM8150_MASTER_SNOC_GC_MEM_NOC,
485
+
.channels = 1,
486
+
.buswidth = 8,
487
+
.num_links = 1,
488
+
.links = { SM8150_SLAVE_LLCC },
489
+
};
490
+
491
+
static struct qcom_icc_node qnm_snoc_sf = {
492
+
.name = "qnm_snoc_sf",
493
+
.id = SM8150_MASTER_SNOC_SF_MEM_NOC,
494
+
.channels = 1,
495
+
.buswidth = 16,
496
+
.num_links = 1,
497
+
.links = { SM8150_SLAVE_LLCC },
498
+
};
499
+
500
+
static struct qcom_icc_node qxm_ecc = {
501
+
.name = "qxm_ecc",
502
+
.id = SM8150_MASTER_ECC,
503
+
.channels = 2,
504
+
.buswidth = 32,
505
+
.num_links = 1,
506
+
.links = { SM8150_SLAVE_LLCC },
507
+
};
508
+
509
+
static struct qcom_icc_node llcc_mc = {
510
+
.name = "llcc_mc",
511
+
.id = SM8150_MASTER_LLCC,
512
+
.channels = 4,
513
+
.buswidth = 4,
514
+
.num_links = 1,
515
+
.links = { SM8150_SLAVE_EBI_CH0 },
516
+
};
517
+
518
+
static struct qcom_icc_node qhm_mnoc_cfg = {
519
+
.name = "qhm_mnoc_cfg",
520
+
.id = SM8150_MASTER_CNOC_MNOC_CFG,
521
+
.channels = 1,
522
+
.buswidth = 4,
523
+
.num_links = 1,
524
+
.links = { SM8150_SLAVE_SERVICE_MNOC },
525
+
};
526
+
527
+
static struct qcom_icc_node qxm_camnoc_hf0 = {
528
+
.name = "qxm_camnoc_hf0",
529
+
.id = SM8150_MASTER_CAMNOC_HF0,
530
+
.channels = 1,
531
+
.buswidth = 32,
532
+
.num_links = 1,
533
+
.links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
534
+
};
535
+
536
+
static struct qcom_icc_node qxm_camnoc_hf1 = {
537
+
.name = "qxm_camnoc_hf1",
538
+
.id = SM8150_MASTER_CAMNOC_HF1,
539
+
.channels = 1,
540
+
.buswidth = 32,
541
+
.num_links = 1,
542
+
.links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
543
+
};
544
+
545
+
static struct qcom_icc_node qxm_camnoc_sf = {
546
+
.name = "qxm_camnoc_sf",
547
+
.id = SM8150_MASTER_CAMNOC_SF,
548
+
.channels = 1,
549
+
.buswidth = 32,
550
+
.num_links = 1,
551
+
.links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
552
+
};
553
+
554
+
static struct qcom_icc_node qxm_mdp0 = {
555
+
.name = "qxm_mdp0",
556
+
.id = SM8150_MASTER_MDP_PORT0,
557
+
.channels = 1,
558
+
.buswidth = 32,
559
+
.num_links = 1,
560
+
.links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
561
+
};
562
+
563
+
static struct qcom_icc_node qxm_mdp1 = {
564
+
.name = "qxm_mdp1",
565
+
.id = SM8150_MASTER_MDP_PORT1,
566
+
.channels = 1,
567
+
.buswidth = 32,
568
+
.num_links = 1,
569
+
.links = { SM8150_SLAVE_MNOC_HF_MEM_NOC },
570
+
};
571
+
572
+
static struct qcom_icc_node qxm_rot = {
573
+
.name = "qxm_rot",
574
+
.id = SM8150_MASTER_ROTATOR,
575
+
.channels = 1,
576
+
.buswidth = 32,
577
+
.num_links = 1,
578
+
.links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
579
+
};
580
+
581
+
static struct qcom_icc_node qxm_venus0 = {
582
+
.name = "qxm_venus0",
583
+
.id = SM8150_MASTER_VIDEO_P0,
584
+
.channels = 1,
585
+
.buswidth = 32,
586
+
.num_links = 1,
587
+
.links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
588
+
};
589
+
590
+
static struct qcom_icc_node qxm_venus1 = {
591
+
.name = "qxm_venus1",
592
+
.id = SM8150_MASTER_VIDEO_P1,
593
+
.channels = 1,
594
+
.buswidth = 32,
595
+
.num_links = 1,
596
+
.links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
597
+
};
598
+
599
+
static struct qcom_icc_node qxm_venus_arm9 = {
600
+
.name = "qxm_venus_arm9",
601
+
.id = SM8150_MASTER_VIDEO_PROC,
602
+
.channels = 1,
603
+
.buswidth = 8,
604
+
.num_links = 1,
605
+
.links = { SM8150_SLAVE_MNOC_SF_MEM_NOC },
606
+
};
607
+
608
+
static struct qcom_icc_node qhm_snoc_cfg = {
609
+
.name = "qhm_snoc_cfg",
610
+
.id = SM8150_MASTER_SNOC_CFG,
611
+
.channels = 1,
612
+
.buswidth = 4,
613
+
.num_links = 1,
614
+
.links = { SM8150_SLAVE_SERVICE_SNOC },
615
+
};
616
+
617
+
static struct qcom_icc_node qnm_aggre1_noc = {
618
+
.name = "qnm_aggre1_noc",
619
+
.id = SM8150_A1NOC_SNOC_MAS,
620
+
.channels = 1,
621
+
.buswidth = 16,
622
+
.num_links = 6,
623
+
.links = { SM8150_SLAVE_SNOC_GEM_NOC_SF,
624
+
SM8150_SLAVE_PIMEM,
625
+
SM8150_SLAVE_OCIMEM,
626
+
SM8150_SLAVE_APPSS,
627
+
SM8150_SNOC_CNOC_SLV,
628
+
SM8150_SLAVE_QDSS_STM
629
+
},
630
+
};
631
+
632
+
static struct qcom_icc_node qnm_aggre2_noc = {
633
+
.name = "qnm_aggre2_noc",
634
+
.id = SM8150_A2NOC_SNOC_MAS,
635
+
.channels = 1,
636
+
.buswidth = 16,
637
+
.num_links = 9,
638
+
.links = { SM8150_SLAVE_SNOC_GEM_NOC_SF,
639
+
SM8150_SLAVE_PIMEM,
640
+
SM8150_SLAVE_OCIMEM,
641
+
SM8150_SLAVE_APPSS,
642
+
SM8150_SNOC_CNOC_SLV,
643
+
SM8150_SLAVE_PCIE_0,
644
+
SM8150_SLAVE_PCIE_1,
645
+
SM8150_SLAVE_TCU,
646
+
SM8150_SLAVE_QDSS_STM
647
+
},
648
+
};
649
+
650
+
static struct qcom_icc_node qnm_gemnoc = {
651
+
.name = "qnm_gemnoc",
652
+
.id = SM8150_MASTER_GEM_NOC_SNOC,
653
+
.channels = 1,
654
+
.buswidth = 8,
655
+
.num_links = 6,
656
+
.links = { SM8150_SLAVE_PIMEM,
657
+
SM8150_SLAVE_OCIMEM,
658
+
SM8150_SLAVE_APPSS,
659
+
SM8150_SNOC_CNOC_SLV,
660
+
SM8150_SLAVE_TCU,
661
+
SM8150_SLAVE_QDSS_STM
662
+
},
663
+
};
664
+
665
+
static struct qcom_icc_node qxm_pimem = {
666
+
.name = "qxm_pimem",
667
+
.id = SM8150_MASTER_PIMEM,
668
+
.channels = 1,
669
+
.buswidth = 8,
670
+
.num_links = 2,
671
+
.links = { SM8150_SLAVE_SNOC_GEM_NOC_GC,
672
+
SM8150_SLAVE_OCIMEM
673
+
},
674
+
};
675
+
676
+
static struct qcom_icc_node xm_gic = {
677
+
.name = "xm_gic",
678
+
.id = SM8150_MASTER_GIC,
679
+
.channels = 1,
680
+
.buswidth = 8,
681
+
.num_links = 2,
682
+
.links = { SM8150_SLAVE_SNOC_GEM_NOC_GC,
683
+
SM8150_SLAVE_OCIMEM
684
+
},
685
+
};
686
+
687
+
static struct qcom_icc_node qns_a1noc_snoc = {
688
+
.name = "qns_a1noc_snoc",
689
+
.id = SM8150_A1NOC_SNOC_SLV,
690
+
.channels = 1,
691
+
.buswidth = 16,
692
+
.num_links = 1,
693
+
.links = { SM8150_A1NOC_SNOC_MAS },
694
+
};
695
+
696
+
static struct qcom_icc_node srvc_aggre1_noc = {
697
+
.name = "srvc_aggre1_noc",
698
+
.id = SM8150_SLAVE_SERVICE_A1NOC,
699
+
.channels = 1,
700
+
.buswidth = 4,
701
+
};
702
+
703
+
static struct qcom_icc_node qns_a2noc_snoc = {
704
+
.name = "qns_a2noc_snoc",
705
+
.id = SM8150_A2NOC_SNOC_SLV,
706
+
.channels = 1,
707
+
.buswidth = 16,
708
+
.num_links = 1,
709
+
.links = { SM8150_A2NOC_SNOC_MAS },
710
+
};
711
+
712
+
static struct qcom_icc_node qns_pcie_mem_noc = {
713
+
.name = "qns_pcie_mem_noc",
714
+
.id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC,
715
+
.channels = 1,
716
+
.buswidth = 16,
717
+
.num_links = 1,
718
+
.links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC },
719
+
};
720
+
721
+
static struct qcom_icc_node srvc_aggre2_noc = {
722
+
.name = "srvc_aggre2_noc",
723
+
.id = SM8150_SLAVE_SERVICE_A2NOC,
724
+
.channels = 1,
725
+
.buswidth = 4,
726
+
};
727
+
728
+
static struct qcom_icc_node qns_camnoc_uncomp = {
729
+
.name = "qns_camnoc_uncomp",
730
+
.id = SM8150_SLAVE_CAMNOC_UNCOMP,
731
+
.channels = 1,
732
+
.buswidth = 32,
733
+
};
734
+
735
+
static struct qcom_icc_node qns_cdsp_mem_noc = {
736
+
.name = "qns_cdsp_mem_noc",
737
+
.id = SM8150_SLAVE_CDSP_MEM_NOC,
738
+
.channels = 2,
739
+
.buswidth = 32,
740
+
.num_links = 1,
741
+
.links = { SM8150_MASTER_COMPUTE_NOC },
742
+
};
743
+
744
+
static struct qcom_icc_node qhs_a1_noc_cfg = {
745
+
.name = "qhs_a1_noc_cfg",
746
+
.id = SM8150_SLAVE_A1NOC_CFG,
747
+
.channels = 1,
748
+
.buswidth = 4,
749
+
.num_links = 1,
750
+
.links = { SM8150_MASTER_A1NOC_CFG },
751
+
};
752
+
753
+
static struct qcom_icc_node qhs_a2_noc_cfg = {
754
+
.name = "qhs_a2_noc_cfg",
755
+
.id = SM8150_SLAVE_A2NOC_CFG,
756
+
.channels = 1,
757
+
.buswidth = 4,
758
+
.num_links = 1,
759
+
.links = { SM8150_MASTER_A2NOC_CFG },
760
+
};
761
+
762
+
static struct qcom_icc_node qhs_ahb2phy_south = {
763
+
.name = "qhs_ahb2phy_south",
764
+
.id = SM8150_SLAVE_AHB2PHY_SOUTH,
765
+
.channels = 1,
766
+
.buswidth = 4,
767
+
};
768
+
769
+
static struct qcom_icc_node qhs_aop = {
770
+
.name = "qhs_aop",
771
+
.id = SM8150_SLAVE_AOP,
772
+
.channels = 1,
773
+
.buswidth = 4,
774
+
};
775
+
776
+
static struct qcom_icc_node qhs_aoss = {
777
+
.name = "qhs_aoss",
778
+
.id = SM8150_SLAVE_AOSS,
779
+
.channels = 1,
780
+
.buswidth = 4,
781
+
};
782
+
783
+
static struct qcom_icc_node qhs_camera_cfg = {
784
+
.name = "qhs_camera_cfg",
785
+
.id = SM8150_SLAVE_CAMERA_CFG,
786
+
.channels = 1,
787
+
.buswidth = 4,
788
+
};
789
+
790
+
static struct qcom_icc_node qhs_clk_ctl = {
791
+
.name = "qhs_clk_ctl",
792
+
.id = SM8150_SLAVE_CLK_CTL,
793
+
.channels = 1,
794
+
.buswidth = 4,
795
+
};
796
+
797
+
static struct qcom_icc_node qhs_compute_dsp = {
798
+
.name = "qhs_compute_dsp",
799
+
.id = SM8150_SLAVE_CDSP_CFG,
800
+
.channels = 1,
801
+
.buswidth = 4,
802
+
};
803
+
804
+
static struct qcom_icc_node qhs_cpr_cx = {
805
+
.name = "qhs_cpr_cx",
806
+
.id = SM8150_SLAVE_RBCPR_CX_CFG,
807
+
.channels = 1,
808
+
.buswidth = 4,
809
+
};
810
+
811
+
static struct qcom_icc_node qhs_cpr_mmcx = {
812
+
.name = "qhs_cpr_mmcx",
813
+
.id = SM8150_SLAVE_RBCPR_MMCX_CFG,
814
+
.channels = 1,
815
+
.buswidth = 4,
816
+
};
817
+
818
+
static struct qcom_icc_node qhs_cpr_mx = {
819
+
.name = "qhs_cpr_mx",
820
+
.id = SM8150_SLAVE_RBCPR_MX_CFG,
821
+
.channels = 1,
822
+
.buswidth = 4,
823
+
};
824
+
825
+
static struct qcom_icc_node qhs_crypto0_cfg = {
826
+
.name = "qhs_crypto0_cfg",
827
+
.id = SM8150_SLAVE_CRYPTO_0_CFG,
828
+
.channels = 1,
829
+
.buswidth = 4,
830
+
};
831
+
832
+
static struct qcom_icc_node qhs_ddrss_cfg = {
833
+
.name = "qhs_ddrss_cfg",
834
+
.id = SM8150_SLAVE_CNOC_DDRSS,
835
+
.channels = 1,
836
+
.buswidth = 4,
837
+
.num_links = 1,
838
+
.links = { SM8150_MASTER_CNOC_DC_NOC },
839
+
};
840
+
841
+
static struct qcom_icc_node qhs_display_cfg = {
842
+
.name = "qhs_display_cfg",
843
+
.id = SM8150_SLAVE_DISPLAY_CFG,
844
+
.channels = 1,
845
+
.buswidth = 4,
846
+
};
847
+
848
+
static struct qcom_icc_node qhs_emac_cfg = {
849
+
.name = "qhs_emac_cfg",
850
+
.id = SM8150_SLAVE_EMAC_CFG,
851
+
.channels = 1,
852
+
.buswidth = 4,
853
+
};
854
+
855
+
static struct qcom_icc_node qhs_glm = {
856
+
.name = "qhs_glm",
857
+
.id = SM8150_SLAVE_GLM,
858
+
.channels = 1,
859
+
.buswidth = 4,
860
+
};
861
+
862
+
static struct qcom_icc_node qhs_gpuss_cfg = {
863
+
.name = "qhs_gpuss_cfg",
864
+
.id = SM8150_SLAVE_GRAPHICS_3D_CFG,
865
+
.channels = 1,
866
+
.buswidth = 8,
867
+
};
868
+
869
+
static struct qcom_icc_node qhs_imem_cfg = {
870
+
.name = "qhs_imem_cfg",
871
+
.id = SM8150_SLAVE_IMEM_CFG,
872
+
.channels = 1,
873
+
.buswidth = 4,
874
+
};
875
+
876
+
static struct qcom_icc_node qhs_ipa = {
877
+
.name = "qhs_ipa",
878
+
.id = SM8150_SLAVE_IPA_CFG,
879
+
.channels = 1,
880
+
.buswidth = 4,
881
+
};
882
+
883
+
static struct qcom_icc_node qhs_mnoc_cfg = {
884
+
.name = "qhs_mnoc_cfg",
885
+
.id = SM8150_SLAVE_CNOC_MNOC_CFG,
886
+
.channels = 1,
887
+
.buswidth = 4,
888
+
.num_links = 1,
889
+
.links = { SM8150_MASTER_CNOC_MNOC_CFG },
890
+
};
891
+
892
+
static struct qcom_icc_node qhs_npu_cfg = {
893
+
.name = "qhs_npu_cfg",
894
+
.id = SM8150_SLAVE_NPU_CFG,
895
+
.channels = 1,
896
+
.buswidth = 4,
897
+
};
898
+
899
+
static struct qcom_icc_node qhs_pcie0_cfg = {
900
+
.name = "qhs_pcie0_cfg",
901
+
.id = SM8150_SLAVE_PCIE_0_CFG,
902
+
.channels = 1,
903
+
.buswidth = 4,
904
+
};
905
+
906
+
static struct qcom_icc_node qhs_pcie1_cfg = {
907
+
.name = "qhs_pcie1_cfg",
908
+
.id = SM8150_SLAVE_PCIE_1_CFG,
909
+
.channels = 1,
910
+
.buswidth = 4,
911
+
};
912
+
913
+
static struct qcom_icc_node qhs_phy_refgen_north = {
914
+
.name = "qhs_phy_refgen_north",
915
+
.id = SM8150_SLAVE_NORTH_PHY_CFG,
916
+
.channels = 1,
917
+
.buswidth = 4,
918
+
};
919
+
920
+
static struct qcom_icc_node qhs_pimem_cfg = {
921
+
.name = "qhs_pimem_cfg",
922
+
.id = SM8150_SLAVE_PIMEM_CFG,
923
+
.channels = 1,
924
+
.buswidth = 4,
925
+
};
926
+
927
+
static struct qcom_icc_node qhs_prng = {
928
+
.name = "qhs_prng",
929
+
.id = SM8150_SLAVE_PRNG,
930
+
.channels = 1,
931
+
.buswidth = 4,
932
+
};
933
+
934
+
static struct qcom_icc_node qhs_qdss_cfg = {
935
+
.name = "qhs_qdss_cfg",
936
+
.id = SM8150_SLAVE_QDSS_CFG,
937
+
.channels = 1,
938
+
.buswidth = 4,
939
+
};
940
+
941
+
static struct qcom_icc_node qhs_qspi = {
942
+
.name = "qhs_qspi",
943
+
.id = SM8150_SLAVE_QSPI,
944
+
.channels = 1,
945
+
.buswidth = 4,
946
+
};
947
+
948
+
static struct qcom_icc_node qhs_qupv3_east = {
949
+
.name = "qhs_qupv3_east",
950
+
.id = SM8150_SLAVE_QUP_2,
951
+
.channels = 1,
952
+
.buswidth = 4,
953
+
};
954
+
955
+
static struct qcom_icc_node qhs_qupv3_north = {
956
+
.name = "qhs_qupv3_north",
957
+
.id = SM8150_SLAVE_QUP_1,
958
+
.channels = 1,
959
+
.buswidth = 4,
960
+
};
961
+
962
+
static struct qcom_icc_node qhs_qupv3_south = {
963
+
.name = "qhs_qupv3_south",
964
+
.id = SM8150_SLAVE_QUP_0,
965
+
.channels = 1,
966
+
.buswidth = 4,
967
+
};
968
+
969
+
static struct qcom_icc_node qhs_sdc2 = {
970
+
.name = "qhs_sdc2",
971
+
.id = SM8150_SLAVE_SDCC_2,
972
+
.channels = 1,
973
+
.buswidth = 4,
974
+
};
975
+
976
+
static struct qcom_icc_node qhs_sdc4 = {
977
+
.name = "qhs_sdc4",
978
+
.id = SM8150_SLAVE_SDCC_4,
979
+
.channels = 1,
980
+
.buswidth = 4,
981
+
};
982
+
983
+
static struct qcom_icc_node qhs_snoc_cfg = {
984
+
.name = "qhs_snoc_cfg",
985
+
.id = SM8150_SLAVE_SNOC_CFG,
986
+
.channels = 1,
987
+
.buswidth = 4,
988
+
.num_links = 1,
989
+
.links = { SM8150_MASTER_SNOC_CFG },
990
+
};
991
+
992
+
static struct qcom_icc_node qhs_spdm = {
993
+
.name = "qhs_spdm",
994
+
.id = SM8150_SLAVE_SPDM_WRAPPER,
995
+
.channels = 1,
996
+
.buswidth = 4,
997
+
};
998
+
999
+
static struct qcom_icc_node qhs_spss_cfg = {
1000
+
.name = "qhs_spss_cfg",
1001
+
.id = SM8150_SLAVE_SPSS_CFG,
1002
+
.channels = 1,
1003
+
.buswidth = 4,
1004
+
};
1005
+
1006
+
static struct qcom_icc_node qhs_ssc_cfg = {
1007
+
.name = "qhs_ssc_cfg",
1008
+
.id = SM8150_SLAVE_SSC_CFG,
1009
+
.channels = 1,
1010
+
.buswidth = 4,
1011
+
};
1012
+
1013
+
static struct qcom_icc_node qhs_tcsr = {
1014
+
.name = "qhs_tcsr",
1015
+
.id = SM8150_SLAVE_TCSR,
1016
+
.channels = 1,
1017
+
.buswidth = 4,
1018
+
};
1019
+
1020
+
static struct qcom_icc_node qhs_tlmm_east = {
1021
+
.name = "qhs_tlmm_east",
1022
+
.id = SM8150_SLAVE_TLMM_EAST,
1023
+
.channels = 1,
1024
+
.buswidth = 4,
1025
+
};
1026
+
1027
+
static struct qcom_icc_node qhs_tlmm_north = {
1028
+
.name = "qhs_tlmm_north",
1029
+
.id = SM8150_SLAVE_TLMM_NORTH,
1030
+
.channels = 1,
1031
+
.buswidth = 4,
1032
+
};
1033
+
1034
+
static struct qcom_icc_node qhs_tlmm_south = {
1035
+
.name = "qhs_tlmm_south",
1036
+
.id = SM8150_SLAVE_TLMM_SOUTH,
1037
+
.channels = 1,
1038
+
.buswidth = 4,
1039
+
};
1040
+
1041
+
static struct qcom_icc_node qhs_tlmm_west = {
1042
+
.name = "qhs_tlmm_west",
1043
+
.id = SM8150_SLAVE_TLMM_WEST,
1044
+
.channels = 1,
1045
+
.buswidth = 4,
1046
+
};
1047
+
1048
+
static struct qcom_icc_node qhs_tsif = {
1049
+
.name = "qhs_tsif",
1050
+
.id = SM8150_SLAVE_TSIF,
1051
+
.channels = 1,
1052
+
.buswidth = 4,
1053
+
};
1054
+
1055
+
static struct qcom_icc_node qhs_ufs_card_cfg = {
1056
+
.name = "qhs_ufs_card_cfg",
1057
+
.id = SM8150_SLAVE_UFS_CARD_CFG,
1058
+
.channels = 1,
1059
+
.buswidth = 4,
1060
+
};
1061
+
1062
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1063
+
.name = "qhs_ufs_mem_cfg",
1064
+
.id = SM8150_SLAVE_UFS_MEM_CFG,
1065
+
.channels = 1,
1066
+
.buswidth = 4,
1067
+
};
1068
+
1069
+
static struct qcom_icc_node qhs_usb3_0 = {
1070
+
.name = "qhs_usb3_0",
1071
+
.id = SM8150_SLAVE_USB3,
1072
+
.channels = 1,
1073
+
.buswidth = 4,
1074
+
};
1075
+
1076
+
static struct qcom_icc_node qhs_usb3_1 = {
1077
+
.name = "qhs_usb3_1",
1078
+
.id = SM8150_SLAVE_USB3_1,
1079
+
.channels = 1,
1080
+
.buswidth = 4,
1081
+
};
1082
+
1083
+
static struct qcom_icc_node qhs_venus_cfg = {
1084
+
.name = "qhs_venus_cfg",
1085
+
.id = SM8150_SLAVE_VENUS_CFG,
1086
+
.channels = 1,
1087
+
.buswidth = 4,
1088
+
};
1089
+
1090
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1091
+
.name = "qhs_vsense_ctrl_cfg",
1092
+
.id = SM8150_SLAVE_VSENSE_CTRL_CFG,
1093
+
.channels = 1,
1094
+
.buswidth = 4,
1095
+
};
1096
+
1097
+
static struct qcom_icc_node qns_cnoc_a2noc = {
1098
+
.name = "qns_cnoc_a2noc",
1099
+
.id = SM8150_SLAVE_CNOC_A2NOC,
1100
+
.channels = 1,
1101
+
.buswidth = 8,
1102
+
.num_links = 1,
1103
+
.links = { SM8150_MASTER_CNOC_A2NOC },
1104
+
};
1105
+
1106
+
static struct qcom_icc_node srvc_cnoc = {
1107
+
.name = "srvc_cnoc",
1108
+
.id = SM8150_SLAVE_SERVICE_CNOC,
1109
+
.channels = 1,
1110
+
.buswidth = 4,
1111
+
};
1112
+
1113
+
static struct qcom_icc_node qhs_llcc = {
1114
+
.name = "qhs_llcc",
1115
+
.id = SM8150_SLAVE_LLCC_CFG,
1116
+
.channels = 1,
1117
+
.buswidth = 4,
1118
+
};
1119
+
1120
+
static struct qcom_icc_node qhs_memnoc = {
1121
+
.name = "qhs_memnoc",
1122
+
.id = SM8150_SLAVE_GEM_NOC_CFG,
1123
+
.channels = 1,
1124
+
.buswidth = 4,
1125
+
.num_links = 1,
1126
+
.links = { SM8150_MASTER_GEM_NOC_CFG },
1127
+
};
1128
+
1129
+
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1130
+
.name = "qhs_mdsp_ms_mpu_cfg",
1131
+
.id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG,
1132
+
.channels = 1,
1133
+
.buswidth = 4,
1134
+
};
1135
+
1136
+
static struct qcom_icc_node qns_ecc = {
1137
+
.name = "qns_ecc",
1138
+
.id = SM8150_SLAVE_ECC,
1139
+
.channels = 1,
1140
+
.buswidth = 32,
1141
+
};
1142
+
1143
+
static struct qcom_icc_node qns_gem_noc_snoc = {
1144
+
.name = "qns_gem_noc_snoc",
1145
+
.id = SM8150_SLAVE_GEM_NOC_SNOC,
1146
+
.channels = 1,
1147
+
.buswidth = 8,
1148
+
.num_links = 1,
1149
+
.links = { SM8150_MASTER_GEM_NOC_SNOC },
1150
+
};
1151
+
1152
+
static struct qcom_icc_node qns_llcc = {
1153
+
.name = "qns_llcc",
1154
+
.id = SM8150_SLAVE_LLCC,
1155
+
.channels = 4,
1156
+
.buswidth = 16,
1157
+
.num_links = 1,
1158
+
.links = { SM8150_MASTER_LLCC },
1159
+
};
1160
+
1161
+
static struct qcom_icc_node srvc_gemnoc = {
1162
+
.name = "srvc_gemnoc",
1163
+
.id = SM8150_SLAVE_SERVICE_GEM_NOC,
1164
+
.channels = 1,
1165
+
.buswidth = 4,
1166
+
};
1167
+
1168
+
static struct qcom_icc_node ebi = {
1169
+
.name = "ebi",
1170
+
.id = SM8150_SLAVE_EBI_CH0,
1171
+
.channels = 4,
1172
+
.buswidth = 4,
1173
+
};
1174
+
1175
+
static struct qcom_icc_node qns2_mem_noc = {
1176
+
.name = "qns2_mem_noc",
1177
+
.id = SM8150_SLAVE_MNOC_SF_MEM_NOC,
1178
+
.channels = 1,
1179
+
.buswidth = 32,
1180
+
.num_links = 1,
1181
+
.links = { SM8150_MASTER_MNOC_SF_MEM_NOC },
1182
+
};
1183
+
1184
+
static struct qcom_icc_node qns_mem_noc_hf = {
1185
+
.name = "qns_mem_noc_hf",
1186
+
.id = SM8150_SLAVE_MNOC_HF_MEM_NOC,
1187
+
.channels = 2,
1188
+
.buswidth = 32,
1189
+
.num_links = 1,
1190
+
.links = { SM8150_MASTER_MNOC_HF_MEM_NOC },
1191
+
};
1192
+
1193
+
static struct qcom_icc_node srvc_mnoc = {
1194
+
.name = "srvc_mnoc",
1195
+
.id = SM8150_SLAVE_SERVICE_MNOC,
1196
+
.channels = 1,
1197
+
.buswidth = 4,
1198
+
};
1199
+
1200
+
static struct qcom_icc_node qhs_apss = {
1201
+
.name = "qhs_apss",
1202
+
.id = SM8150_SLAVE_APPSS,
1203
+
.channels = 1,
1204
+
.buswidth = 8,
1205
+
};
1206
+
1207
+
static struct qcom_icc_node qns_cnoc = {
1208
+
.name = "qns_cnoc",
1209
+
.id = SM8150_SNOC_CNOC_SLV,
1210
+
.channels = 1,
1211
+
.buswidth = 8,
1212
+
.num_links = 1,
1213
+
.links = { SM8150_SNOC_CNOC_MAS },
1214
+
};
1215
+
1216
+
static struct qcom_icc_node qns_gemnoc_gc = {
1217
+
.name = "qns_gemnoc_gc",
1218
+
.id = SM8150_SLAVE_SNOC_GEM_NOC_GC,
1219
+
.channels = 1,
1220
+
.buswidth = 8,
1221
+
.num_links = 1,
1222
+
.links = { SM8150_MASTER_SNOC_GC_MEM_NOC },
1223
+
};
1224
+
1225
+
static struct qcom_icc_node qns_gemnoc_sf = {
1226
+
.name = "qns_gemnoc_sf",
1227
+
.id = SM8150_SLAVE_SNOC_GEM_NOC_SF,
1228
+
.channels = 1,
1229
+
.buswidth = 16,
1230
+
.num_links = 1,
1231
+
.links = { SM8150_MASTER_SNOC_SF_MEM_NOC },
1232
+
};
1233
+
1234
+
static struct qcom_icc_node qxs_imem = {
1235
+
.name = "qxs_imem",
1236
+
.id = SM8150_SLAVE_OCIMEM,
1237
+
.channels = 1,
1238
+
.buswidth = 8,
1239
+
};
1240
+
1241
+
static struct qcom_icc_node qxs_pimem = {
1242
+
.name = "qxs_pimem",
1243
+
.id = SM8150_SLAVE_PIMEM,
1244
+
.channels = 1,
1245
+
.buswidth = 8,
1246
+
};
1247
+
1248
+
static struct qcom_icc_node srvc_snoc = {
1249
+
.name = "srvc_snoc",
1250
+
.id = SM8150_SLAVE_SERVICE_SNOC,
1251
+
.channels = 1,
1252
+
.buswidth = 4,
1253
+
};
1254
+
1255
+
static struct qcom_icc_node xs_pcie_0 = {
1256
+
.name = "xs_pcie_0",
1257
+
.id = SM8150_SLAVE_PCIE_0,
1258
+
.channels = 1,
1259
+
.buswidth = 8,
1260
+
};
1261
+
1262
+
static struct qcom_icc_node xs_pcie_1 = {
1263
+
.name = "xs_pcie_1",
1264
+
.id = SM8150_SLAVE_PCIE_1,
1265
+
.channels = 1,
1266
+
.buswidth = 8,
1267
+
};
1268
+
1269
+
static struct qcom_icc_node xs_qdss_stm = {
1270
+
.name = "xs_qdss_stm",
1271
+
.id = SM8150_SLAVE_QDSS_STM,
1272
+
.channels = 1,
1273
+
.buswidth = 4,
1274
+
};
1275
+
1276
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1277
+
.name = "xs_sys_tcu_cfg",
1278
+
.id = SM8150_SLAVE_TCU,
1279
+
.channels = 1,
1280
+
.buswidth = 8,
1281
+
};
157
1282
158
1283
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
159
1284
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);