Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: mchp-pci1xxxx: DMA support for copying data to and from SPI Buf
pci1xxxx_spi_transfer_with_dma adds DMA support to copy the data between
host cpu buffer and SPI IO Buffer.
On DMA Completion interrupt, the next SPI transaction is initiated in isr.
Helper functions pci1xxxx_spi_setup, pci1xxxx_spi_setup_dma_from_io,
pci1xxxx_spi_setup_dma_to_io and pci1xxxx_start_spi_xfer are added for
setting up spi, setting up dma operations, and to start spi transfer
respectively. In the existing implementation, codes are replaced with
helper functions wherever applicable.
Signed-off-by: Thangaraj Samynathan <thangaraj.s@microchip.com>
Link: https://lore.kernel.org/r/20240207080621.30742-3-thangaraj.s@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Thangaraj Samynathan
and committed by
Mark Brown
9538edeb
3e7cfd6a
+340
-29
+340
-29
drivers/spi/spi-pci1xxxx.c
+340
-29
drivers/spi/spi-pci1xxxx.c
···
5
5
// Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com>
6
6
7
7
8
+
#include <linux/bitfield.h>
8
9
#include <linux/dma-mapping.h>
9
10
#include <linux/iopoll.h>
10
11
#include <linux/irq.h>
···
13
12
#include <linux/msi.h>
14
13
#include <linux/pci_regs.h>
15
14
#include <linux/pci.h>
15
+
#include <linux/spinlock.h>
16
16
#include <linux/spi/spi.h>
17
17
#include <linux/delay.h>
18
18
···
39
37
#define SPI_MST_CTL_MODE_SEL (BIT(2))
40
38
#define SPI_MST_CTL_GO (BIT(0))
41
39
40
+
#define SPI_PERI_ADDR_BASE (0x160000)
42
41
#define SPI_SYSTEM_ADDR_BASE (0x2000)
43
42
#define SPI_MST1_ADDR_BASE (0x800)
44
43
···
51
48
#define DEV_REV_MASK (GENMASK(7, 0))
52
49
53
50
#define SPI_SYSLOCK BIT(4)
51
+
#define SPI0 (0)
52
+
#define SPI1 (1)
54
53
55
54
/* DMA Related Registers */
56
55
#define SPI_DMA_ADDR_BASE (0x1000)
57
56
#define SPI_DMA_GLOBAL_WR_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x0C)
57
+
#define SPI_DMA_WR_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x10)
58
58
#define SPI_DMA_GLOBAL_RD_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x2C)
59
+
#define SPI_DMA_RD_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x30)
60
+
#define SPI_DMA_INTR_WR_STS (SPI_DMA_ADDR_BASE + 0x4C)
61
+
#define SPI_DMA_WR_INT_MASK (SPI_DMA_ADDR_BASE + 0x54)
62
+
#define SPI_DMA_INTR_WR_CLR (SPI_DMA_ADDR_BASE + 0x58)
63
+
#define SPI_DMA_ERR_WR_STS (SPI_DMA_ADDR_BASE + 0x5C)
59
64
#define SPI_DMA_INTR_IMWR_WDONE_LOW (SPI_DMA_ADDR_BASE + 0x60)
60
65
#define SPI_DMA_INTR_IMWR_WDONE_HIGH (SPI_DMA_ADDR_BASE + 0x64)
61
66
#define SPI_DMA_INTR_IMWR_WABORT_LOW (SPI_DMA_ADDR_BASE + 0x68)
62
67
#define SPI_DMA_INTR_IMWR_WABORT_HIGH (SPI_DMA_ADDR_BASE + 0x6C)
63
68
#define SPI_DMA_INTR_WR_IMWR_DATA (SPI_DMA_ADDR_BASE + 0x70)
69
+
#define SPI_DMA_INTR_RD_STS (SPI_DMA_ADDR_BASE + 0xA0)
70
+
#define SPI_DMA_RD_INT_MASK (SPI_DMA_ADDR_BASE + 0xA8)
71
+
#define SPI_DMA_INTR_RD_CLR (SPI_DMA_ADDR_BASE + 0xAC)
72
+
#define SPI_DMA_ERR_RD_STS (SPI_DMA_ADDR_BASE + 0xB8)
64
73
#define SPI_DMA_INTR_IMWR_RDONE_LOW (SPI_DMA_ADDR_BASE + 0xCC)
65
74
#define SPI_DMA_INTR_IMWR_RDONE_HIGH (SPI_DMA_ADDR_BASE + 0xD0)
66
75
#define SPI_DMA_INTR_IMWR_RABORT_LOW (SPI_DMA_ADDR_BASE + 0xD4)
67
76
#define SPI_DMA_INTR_IMWR_RABORT_HIGH (SPI_DMA_ADDR_BASE + 0xD8)
68
77
#define SPI_DMA_INTR_RD_IMWR_DATA (SPI_DMA_ADDR_BASE + 0xDC)
78
+
79
+
#define SPI_DMA_CH0_WR_BASE (SPI_DMA_ADDR_BASE + 0x200)
80
+
#define SPI_DMA_CH0_RD_BASE (SPI_DMA_ADDR_BASE + 0x300)
81
+
#define SPI_DMA_CH1_WR_BASE (SPI_DMA_ADDR_BASE + 0x400)
82
+
#define SPI_DMA_CH1_RD_BASE (SPI_DMA_ADDR_BASE + 0x500)
83
+
84
+
#define SPI_DMA_CH_CTL1_OFFSET (0x00)
85
+
#define SPI_DMA_CH_XFER_LEN_OFFSET (0x08)
86
+
#define SPI_DMA_CH_SAR_LO_OFFSET (0x0C)
87
+
#define SPI_DMA_CH_SAR_HI_OFFSET (0x10)
88
+
#define SPI_DMA_CH_DAR_LO_OFFSET (0x14)
89
+
#define SPI_DMA_CH_DAR_HI_OFFSET (0x18)
90
+
91
+
#define SPI_DMA_CH0_DONE_INT BIT(0)
92
+
#define SPI_DMA_CH1_DONE_INT BIT(1)
93
+
#define SPI_DMA_CH0_ABORT_INT BIT(16)
94
+
#define SPI_DMA_CH1_ABORT_INT BIT(17)
95
+
#define SPI_DMA_DONE_INT_MASK (SPI_DMA_CH0_DONE_INT | SPI_DMA_CH1_DONE_INT)
96
+
#define SPI_DMA_ABORT_INT_MASK (SPI_DMA_CH0_ABORT_INT | SPI_DMA_CH1_ABORT_INT)
97
+
#define DMA_CH_CONTROL_LIE BIT(3)
98
+
#define DMA_CH_CONTROL_RIE BIT(4)
99
+
#define DMA_INTR_EN (DMA_CH_CONTROL_RIE | DMA_CH_CONTROL_LIE)
69
100
70
101
/* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
71
102
···
119
82
#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100))
120
83
#define SYSLOCK_RETRY_CNT (1000)
121
84
#define SPI_DMA_ENGINE_EN (0x1)
85
+
#define SPI_DMA_ENGINE_DIS (0x0)
122
86
123
87
#define SPI_INTR BIT(8)
124
88
#define SPI_FORCE_CE BIT(4)
···
132
94
133
95
struct pci1xxxx_spi_internal {
134
96
u8 hw_inst;
135
-
bool spi_xfer_in_progress;
97
+
u8 clkdiv;
136
98
int irq;
99
+
int mode;
100
+
bool spi_xfer_in_progress;
101
+
void *rx_buf;
102
+
bool dma_aborted_rd;
103
+
u32 bytes_recvd;
104
+
u32 tx_sgl_len;
105
+
u32 rx_sgl_len;
106
+
struct scatterlist *tx_sgl, *rx_sgl;
107
+
bool dma_aborted_wr;
137
108
struct completion spi_xfer_done;
138
109
struct spi_controller *spi_host;
139
110
struct pci1xxxx_spi *parent;
111
+
struct spi_transfer *xfer;
140
112
struct {
141
113
unsigned int dev_sel : 3;
142
114
unsigned int msi_vector_sel : 1;
···
159
111
u8 dev_rev;
160
112
void __iomem *reg_base;
161
113
void __iomem *dma_offset_bar;
114
+
/* lock to safely access the DMA registers in isr */
115
+
spinlock_t dma_reg_lock;
162
116
bool can_dma;
163
117
struct pci1xxxx_spi_internal *spi_int[] __counted_by(total_hw_instances);
164
118
};
···
280
230
if (ret)
281
231
return ret;
282
232
233
+
spin_lock_init(&spi_bus->dma_reg_lock);
283
234
get_cached_msi_msg(irq, &msi);
284
235
writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
285
236
writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
···
294
243
writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_LOW);
295
244
writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
296
245
writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
246
+
dma_set_max_seg_size(&spi_bus->dev->dev, PCI1XXXX_SPI_BUFFER_SIZE);
297
247
spi_bus->can_dma = true;
298
248
return 0;
299
249
}
···
339
287
return val;
340
288
}
341
289
342
-
static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
343
-
struct spi_device *spi, struct spi_transfer *xfer)
290
+
static void pci1xxxx_spi_setup_dma_to_io(struct pci1xxxx_spi_internal *p,
291
+
dma_addr_t dma_addr, u32 len)
292
+
{
293
+
void __iomem *base;
294
+
295
+
if (!p->hw_inst)
296
+
base = p->parent->dma_offset_bar + SPI_DMA_CH0_RD_BASE;
297
+
else
298
+
base = p->parent->dma_offset_bar + SPI_DMA_CH1_RD_BASE;
299
+
300
+
writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);
301
+
writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);
302
+
writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_SAR_LO_OFFSET);
303
+
writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_SAR_HI_OFFSET);
304
+
/* Updated SPI Command Registers */
305
+
writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),
306
+
base + SPI_DMA_CH_DAR_LO_OFFSET);
307
+
writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),
308
+
base + SPI_DMA_CH_DAR_HI_OFFSET);
309
+
}
310
+
311
+
static void pci1xxxx_spi_setup_dma_from_io(struct pci1xxxx_spi_internal *p,
312
+
dma_addr_t dma_addr, u32 len)
313
+
{
314
+
void *base;
315
+
316
+
if (!p->hw_inst)
317
+
base = p->parent->dma_offset_bar + SPI_DMA_CH0_WR_BASE;
318
+
else
319
+
base = p->parent->dma_offset_bar + SPI_DMA_CH1_WR_BASE;
320
+
321
+
writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);
322
+
writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);
323
+
writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_DAR_LO_OFFSET);
324
+
writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_DAR_HI_OFFSET);
325
+
writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),
326
+
base + SPI_DMA_CH_SAR_LO_OFFSET);
327
+
writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),
328
+
base + SPI_DMA_CH_SAR_HI_OFFSET);
329
+
}
330
+
331
+
static void pci1xxxx_spi_setup(struct pci1xxxx_spi *par, u8 hw_inst, u32 mode,
332
+
u8 clkdiv, u32 len)
333
+
{
334
+
u32 regval;
335
+
336
+
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
337
+
regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
338
+
SPI_MST_CTL_SPEED_MASK);
339
+
340
+
if (mode == SPI_MODE_3)
341
+
regval |= SPI_MST_CTL_MODE_SEL;
342
+
343
+
regval |= FIELD_PREP(SPI_MST_CTL_CMD_LEN_MASK, len);
344
+
regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv);
345
+
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
346
+
}
347
+
348
+
static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p, u8 hw_inst)
349
+
{
350
+
u32 regval;
351
+
352
+
regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
353
+
regval |= SPI_MST_CTL_GO;
354
+
writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
355
+
}
356
+
357
+
static int pci1xxxx_spi_transfer_with_io(struct spi_controller *spi_ctlr,
358
+
struct spi_device *spi, struct spi_transfer *xfer)
344
359
{
345
360
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
346
-
int mode, len, loop_iter, transfer_len;
347
361
struct pci1xxxx_spi *par = p->parent;
362
+
int len, loop_iter, transfer_len;
348
363
unsigned long bytes_transfered;
349
364
unsigned long bytes_recvd;
350
365
unsigned long loop_count;
···
421
302
u8 clkdiv;
422
303
423
304
p->spi_xfer_in_progress = true;
424
-
mode = spi->mode;
305
+
p->bytes_recvd = 0;
425
306
clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
426
307
tx_buf = xfer->tx_buf;
427
308
rx_buf = xfer->rx_buf;
···
446
327
memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst),
447
328
&tx_buf[bytes_transfered], len);
448
329
bytes_transfered += len;
449
-
regval = readl(par->reg_base +
450
-
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
451
-
regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
452
-
SPI_MST_CTL_SPEED_MASK);
453
-
454
-
if (mode == SPI_MODE_3)
455
-
regval |= SPI_MST_CTL_MODE_SEL;
456
-
else
457
-
regval &= ~SPI_MST_CTL_MODE_SEL;
458
-
459
-
regval |= (clkdiv << 5);
460
-
regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
461
-
regval |= (len << 8);
462
-
writel(regval, par->reg_base +
463
-
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
464
-
regval = readl(par->reg_base +
465
-
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
466
-
regval |= SPI_MST_CTL_GO;
467
-
writel(regval, par->reg_base +
468
-
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
330
+
pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len);
331
+
pci1xxxx_start_spi_xfer(p, p->hw_inst);
469
332
470
333
/* Wait for DMA_TERM interrupt */
471
334
result = wait_for_completion_timeout(&p->spi_xfer_done,
···
467
366
return 0;
468
367
}
469
368
470
-
static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
369
+
static int pci1xxxx_spi_transfer_with_dma(struct spi_controller *spi_ctlr,
370
+
struct spi_device *spi,
371
+
struct spi_transfer *xfer)
372
+
{
373
+
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
374
+
struct pci1xxxx_spi *par = p->parent;
375
+
dma_addr_t rx_dma_addr = 0;
376
+
dma_addr_t tx_dma_addr = 0;
377
+
int ret = 0;
378
+
u32 regval;
379
+
380
+
p->spi_xfer_in_progress = true;
381
+
p->tx_sgl = xfer->tx_sg.sgl;
382
+
p->rx_sgl = xfer->rx_sg.sgl;
383
+
p->rx_buf = xfer->rx_buf;
384
+
regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
385
+
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
386
+
387
+
if (!xfer->tx_buf || !p->tx_sgl) {
388
+
ret = -EINVAL;
389
+
goto error;
390
+
}
391
+
p->xfer = xfer;
392
+
p->mode = spi->mode;
393
+
p->clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
394
+
p->bytes_recvd = 0;
395
+
p->rx_buf = xfer->rx_buf;
396
+
regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
397
+
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
398
+
399
+
tx_dma_addr = sg_dma_address(p->tx_sgl);
400
+
rx_dma_addr = sg_dma_address(p->rx_sgl);
401
+
p->tx_sgl_len = sg_dma_len(p->tx_sgl);
402
+
p->rx_sgl_len = sg_dma_len(p->rx_sgl);
403
+
pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);
404
+
pci1xxxx_spi_setup_dma_to_io(p, (tx_dma_addr), p->tx_sgl_len);
405
+
if (rx_dma_addr)
406
+
pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
407
+
writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
408
+
409
+
reinit_completion(&p->spi_xfer_done);
410
+
/* Wait for DMA_TERM interrupt */
411
+
ret = wait_for_completion_timeout(&p->spi_xfer_done, PCI1XXXX_SPI_TIMEOUT);
412
+
if (!ret) {
413
+
ret = -ETIMEDOUT;
414
+
if (p->dma_aborted_rd) {
415
+
writel(SPI_DMA_ENGINE_DIS,
416
+
par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
417
+
/*
418
+
* DMA ENGINE reset takes time if any TLP
419
+
* completeion in progress, should wait
420
+
* till DMA Engine reset is completed.
421
+
*/
422
+
ret = readl_poll_timeout(par->dma_offset_bar +
423
+
SPI_DMA_GLOBAL_RD_ENGINE_EN, regval,
424
+
(regval == 0x0), 0, USEC_PER_MSEC);
425
+
if (ret) {
426
+
ret = -ECANCELED;
427
+
goto error;
428
+
}
429
+
writel(SPI_DMA_ENGINE_EN,
430
+
par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
431
+
p->dma_aborted_rd = false;
432
+
ret = -ECANCELED;
433
+
}
434
+
if (p->dma_aborted_wr) {
435
+
writel(SPI_DMA_ENGINE_DIS,
436
+
par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
437
+
438
+
/*
439
+
* DMA ENGINE reset takes time if any TLP
440
+
* completeion in progress, should wait
441
+
* till DMA Engine reset is completed.
442
+
*/
443
+
ret = readl_poll_timeout(par->dma_offset_bar +
444
+
SPI_DMA_GLOBAL_WR_ENGINE_EN, regval,
445
+
(regval == 0x0), 0, USEC_PER_MSEC);
446
+
if (ret) {
447
+
ret = -ECANCELED;
448
+
goto error;
449
+
}
450
+
451
+
writel(SPI_DMA_ENGINE_EN,
452
+
par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
453
+
p->dma_aborted_wr = false;
454
+
ret = -ECANCELED;
455
+
}
456
+
goto error;
457
+
}
458
+
ret = 0;
459
+
460
+
error:
461
+
p->spi_xfer_in_progress = false;
462
+
463
+
return ret;
464
+
}
465
+
466
+
static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
467
+
struct spi_device *spi, struct spi_transfer *xfer)
468
+
{
469
+
if (spi_ctlr->can_dma(spi_ctlr, spi, xfer) && spi_ctlr->cur_msg_mapped)
470
+
return pci1xxxx_spi_transfer_with_dma(spi_ctlr, spi, xfer);
471
+
else
472
+
return pci1xxxx_spi_transfer_with_io(spi_ctlr, spi, xfer);
473
+
}
474
+
475
+
static irqreturn_t pci1xxxx_spi_isr_io(int irq, void *dev)
471
476
{
472
477
struct pci1xxxx_spi_internal *p = dev;
473
478
irqreturn_t spi_int_fired = IRQ_NONE;
···
583
376
regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
584
377
if (regval & SPI_INTR) {
585
378
/* Clear xfer_done */
586
-
complete(&p->spi_xfer_done);
379
+
if (p->parent->can_dma && p->rx_buf)
380
+
writel(p->hw_inst, p->parent->dma_offset_bar +
381
+
SPI_DMA_WR_DOORBELL_REG);
382
+
else
383
+
complete(&p->parent->spi_int[p->hw_inst]->spi_xfer_done);
587
384
spi_int_fired = IRQ_HANDLED;
588
385
}
589
-
590
386
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
591
-
592
387
return spi_int_fired;
388
+
}
389
+
390
+
static void pci1xxxx_spi_setup_next_dma_transfer(struct pci1xxxx_spi_internal *p)
391
+
{
392
+
dma_addr_t tx_dma_addr = 0;
393
+
dma_addr_t rx_dma_addr = 0;
394
+
u32 prev_len;
395
+
396
+
p->tx_sgl = sg_next(p->tx_sgl);
397
+
if (p->rx_sgl)
398
+
p->rx_sgl = sg_next(p->rx_sgl);
399
+
if (!p->tx_sgl) {
400
+
/* Clear xfer_done */
401
+
complete(&p->spi_xfer_done);
402
+
} else {
403
+
tx_dma_addr = sg_dma_address(p->tx_sgl);
404
+
prev_len = p->tx_sgl_len;
405
+
p->tx_sgl_len = sg_dma_len(p->tx_sgl);
406
+
if (prev_len != p->tx_sgl_len)
407
+
pci1xxxx_spi_setup(p->parent,
408
+
p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);
409
+
pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len);
410
+
if (p->rx_sgl) {
411
+
rx_dma_addr = sg_dma_address(p->rx_sgl);
412
+
p->rx_sgl_len = sg_dma_len(p->rx_sgl);
413
+
pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);
414
+
}
415
+
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
416
+
}
417
+
}
418
+
419
+
static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev)
420
+
{
421
+
struct pci1xxxx_spi_internal *p = dev;
422
+
irqreturn_t spi_int_fired = IRQ_NONE;
423
+
unsigned long flags;
424
+
u32 regval;
425
+
426
+
spin_lock_irqsave(&p->parent->dma_reg_lock, flags);
427
+
/* Clear the DMA RD INT and start spi xfer*/
428
+
regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS);
429
+
if (regval & SPI_DMA_DONE_INT_MASK) {
430
+
if (regval & SPI_DMA_CH0_DONE_INT)
431
+
pci1xxxx_start_spi_xfer(p, SPI0);
432
+
if (regval & SPI_DMA_CH1_DONE_INT)
433
+
pci1xxxx_start_spi_xfer(p, SPI1);
434
+
spi_int_fired = IRQ_HANDLED;
435
+
}
436
+
if (regval & SPI_DMA_ABORT_INT_MASK) {
437
+
p->dma_aborted_rd = true;
438
+
spi_int_fired = IRQ_HANDLED;
439
+
}
440
+
writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR);
441
+
442
+
/* Clear the DMA WR INT */
443
+
regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS);
444
+
if (regval & SPI_DMA_DONE_INT_MASK) {
445
+
if (regval & SPI_DMA_CH0_DONE_INT)
446
+
pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI0]);
447
+
448
+
if (regval & SPI_DMA_CH1_DONE_INT)
449
+
pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI1]);
450
+
451
+
spi_int_fired = IRQ_HANDLED;
452
+
}
453
+
if (regval & SPI_DMA_ABORT_INT_MASK) {
454
+
p->dma_aborted_wr = true;
455
+
spi_int_fired = IRQ_HANDLED;
456
+
}
457
+
writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR);
458
+
spin_unlock_irqrestore(&p->parent->dma_reg_lock, flags);
459
+
460
+
/* Clear the SPI GO_BIT Interrupt */
461
+
regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
462
+
if (regval & SPI_INTR) {
463
+
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG);
464
+
spi_int_fired = IRQ_HANDLED;
465
+
}
466
+
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
467
+
return spi_int_fired;
468
+
}
469
+
470
+
static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
471
+
{
472
+
struct pci1xxxx_spi_internal *p = dev;
473
+
474
+
if (p->spi_host->can_dma(p->spi_host, NULL, p->xfer))
475
+
return pci1xxxx_spi_isr_dma(irq, dev);
476
+
else
477
+
return pci1xxxx_spi_isr_io(irq, dev);
478
+
}
479
+
480
+
static bool pci1xxxx_spi_can_dma(struct spi_controller *host,
481
+
struct spi_device *spi,
482
+
struct spi_transfer *xfer)
483
+
{
484
+
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(host);
485
+
struct pci1xxxx_spi *par = p->parent;
486
+
487
+
return par->can_dma;
593
488
}
594
489
595
490
static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
···
814
505
spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;
815
506
spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL |
816
507
SPI_TX_DUAL | SPI_LOOP;
508
+
spi_host->can_dma = pci1xxxx_spi_can_dma;
817
509
spi_host->transfer_one = pci1xxxx_spi_transfer_one;
510
+
818
511
spi_host->set_cs = pci1xxxx_spi_set_cs;
819
512
spi_host->bits_per_word_mask = SPI_BPW_MASK(8);
820
513
spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;