+5

arch/loongarch/Kconfig

reviewed

··· 115 115 select GPIOLIB 116 116 select HAS_IOPORT 117 117 select HAVE_ARCH_AUDITSYSCALL 118 118 + select HAVE_ARCH_BITREVERSE 118 119 select HAVE_ARCH_JUMP_LABEL 119 120 select HAVE_ARCH_JUMP_LABEL_RELATIVE 120 121 select HAVE_ARCH_KASAN ··· 567 566 on all LoongArch systems. But you can disable it manually if you want 568 567 to run kernel only on systems with h/w unaligned access support in 569 568 order to optimise for performance. 569 569 + 570 570 + config CPU_HAS_AMO 571 571 + bool 572 572 + default 64BIT 570 573 571 574 config CPU_HAS_FPU 572 575 bool

+6 -1

arch/loongarch/Makefile

reviewed

··· 5 5 6 6 boot := arch/loongarch/boot 7 7 8 8 - KBUILD_DEFCONFIG := loongson3_defconfig 8 8 + ifeq ($(shell uname -m),loongarch32) 9 9 + KBUILD_DEFCONFIG := loongson32_defconfig 10 10 + else 11 11 + KBUILD_DEFCONFIG := loongson64_defconfig 12 12 + endif 13 13 + 9 14 KBUILD_DTBS := dtbs 10 15 11 16 image-name-y := vmlinux

+15 -49

arch/loongarch/configs/loongson3_defconfig arch/loongarch/configs/loongson32_defconfig

reviewed

··· 5 5 CONFIG_NO_HZ=y 6 6 CONFIG_HIGH_RES_TIMERS=y 7 7 CONFIG_BPF_SYSCALL=y 8 8 - CONFIG_BPF_JIT=y 9 8 CONFIG_PREEMPT=y 10 9 CONFIG_PREEMPT_DYNAMIC=y 11 11 - CONFIG_SCHED_CORE=y 12 10 CONFIG_BSD_PROCESS_ACCT=y 13 11 CONFIG_BSD_PROCESS_ACCT_V3=y 14 12 CONFIG_TASKSTATS=y ··· 18 20 CONFIG_IKCONFIG_PROC=y 19 21 CONFIG_IKHEADERS=y 20 22 CONFIG_LOG_BUF_SHIFT=18 21 21 - CONFIG_NUMA_BALANCING=y 22 23 CONFIG_MEMCG=y 23 24 CONFIG_BLK_CGROUP=y 24 25 CONFIG_CFS_BANDWIDTH=y ··· 25 28 CONFIG_CGROUP_RDMA=y 26 29 CONFIG_CGROUP_DMEM=y 27 30 CONFIG_CGROUP_FREEZER=y 28 28 - CONFIG_CGROUP_HUGETLB=y 29 31 CONFIG_CPUSETS=y 30 32 CONFIG_CGROUP_DEVICE=y 31 33 CONFIG_CGROUP_CPUACCT=y ··· 41 45 CONFIG_KALLSYMS_ALL=y 42 46 CONFIG_PERF_EVENTS=y 43 47 CONFIG_KEXEC=y 44 44 - CONFIG_KEXEC_FILE=y 45 45 - CONFIG_CRASH_DUMP=y 46 48 CONFIG_LOONGARCH=y 47 47 - CONFIG_64BIT=y 48 48 - CONFIG_MACH_LOONGSON64=y 49 49 + CONFIG_32BIT=y 50 50 + CONFIG_32BIT_STANDARD=y 51 51 + CONFIG_MACH_LOONGSON32=y 49 52 CONFIG_PAGE_SIZE_16KB=y 50 53 CONFIG_HZ_250=y 51 54 CONFIG_DMI=y 52 55 CONFIG_EFI=y 53 53 - CONFIG_SMP=y 54 54 - CONFIG_HOTPLUG_CPU=y 55 55 - CONFIG_NR_CPUS=2048 56 56 - CONFIG_NUMA=y 57 57 - CONFIG_CPU_HAS_FPU=y 58 58 - CONFIG_CPU_HAS_LSX=y 59 59 - CONFIG_CPU_HAS_LASX=y 60 60 - CONFIG_RANDOMIZE_BASE=y 61 56 CONFIG_SUSPEND=y 62 57 CONFIG_HIBERNATION=y 63 58 CONFIG_ACPI=y ··· 66 79 CONFIG_CPU_FREQ_GOV_ONDEMAND=y 67 80 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y 68 81 CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y 69 69 - CONFIG_LOONGSON3_CPUFREQ=m 70 82 CONFIG_VIRTUALIZATION=y 71 71 - CONFIG_KVM=m 72 83 CONFIG_JUMP_LABEL=y 73 84 CONFIG_MODULES=y 74 85 CONFIG_MODULE_FORCE_LOAD=y ··· 103 118 # CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set 104 119 CONFIG_MEMORY_HOTREMOVE=y 105 120 CONFIG_KSM=y 106 106 - CONFIG_TRANSPARENT_HUGEPAGE=y 107 121 CONFIG_CMA=y 108 122 CONFIG_CMA_SYSFS=y 109 123 CONFIG_USERFAULTFD=y ··· 419 435 CONFIG_DEVTMPFS_MOUNT=y 420 436 CONFIG_FW_LOADER_COMPRESS=y 421 437 CONFIG_FW_LOADER_COMPRESS_ZSTD=y 422 422 - CONFIG_SYSFB_SIMPLEFB=y 423 438 CONFIG_EFI_ZBOOT=y 424 439 CONFIG_EFI_BOOTLOADER_CONTROL=m 425 440 CONFIG_EFI_CAPSULE_LOADER=m ··· 513 530 CONFIG_PATA_PCMCIA=m 514 531 CONFIG_MD=y 515 532 CONFIG_BLK_DEV_MD=m 533 533 + CONFIG_MD_LLBITMAP=y 516 534 CONFIG_MD_RAID0=m 517 535 CONFIG_MD_RAID1=m 518 536 CONFIG_MD_RAID10=m ··· 722 738 CONFIG_SERIAL_8250_MANY_PORTS=y 723 739 CONFIG_SERIAL_8250_SHARE_IRQ=y 724 740 CONFIG_SERIAL_8250_RSA=y 741 741 + CONFIG_SERIAL_8250_LOONGSON=y 725 742 CONFIG_SERIAL_OF_PLATFORM=y 726 743 CONFIG_SERIAL_NONSTANDARD=y 727 744 CONFIG_PRINTER=m 728 745 CONFIG_VIRTIO_CONSOLE=y 729 729 - CONFIG_IPMI_HANDLER=m 730 730 - CONFIG_IPMI_DEVICE_INTERFACE=m 731 731 - CONFIG_IPMI_SI=m 732 732 - CONFIG_IPMI_LS2K=y 733 746 CONFIG_HW_RANDOM=y 734 747 CONFIG_HW_RANDOM_VIRTIO=m 735 735 - CONFIG_TCG_TPM=m 736 736 - CONFIG_TCG_LOONGSON=m 737 748 CONFIG_I2C_CHARDEV=y 738 749 CONFIG_I2C_PIIX4=y 739 750 CONFIG_I2C_DESIGNWARE_CORE=y 740 751 CONFIG_I2C_DESIGNWARE_SLAVE=y 741 752 CONFIG_I2C_DESIGNWARE_PCI=y 742 753 CONFIG_I2C_GPIO=y 743 743 - CONFIG_I2C_LS2X=y 744 754 CONFIG_SPI=y 745 755 CONFIG_SPI_LOONGSON_PCI=m 746 756 CONFIG_SPI_LOONGSON_PLATFORM=m 747 757 CONFIG_PINCTRL=y 748 748 - CONFIG_PINCTRL_LOONGSON2=y 749 758 CONFIG_GPIO_SYSFS=y 750 750 - CONFIG_GPIO_LOONGSON=y 751 751 - CONFIG_GPIO_LOONGSON_64BIT=y 759 759 + CONFIG_GPIO_LOONGSON1=y 752 760 CONFIG_GPIO_PCA953X=m 753 761 CONFIG_GPIO_PCA953X_IRQ=y 754 762 CONFIG_GPIO_PCA9570=m ··· 754 778 CONFIG_SENSORS_LM93=m 755 779 CONFIG_SENSORS_W83795=m 756 780 CONFIG_SENSORS_W83627HF=m 757 757 - CONFIG_LOONGSON2_THERMAL=m 758 758 - CONFIG_MFD_LOONGSON_SE=m 781 781 + CONFIG_WATCHDOG=y 782 782 + CONFIG_LOONGSON1_WDT=m 759 783 CONFIG_RC_CORE=m 760 784 CONFIG_LIRC=y 761 785 CONFIG_RC_DECODERS=y ··· 777 801 CONFIG_DVB_BT8XX=m 778 802 CONFIG_DRM=y 779 803 CONFIG_DRM_LOAD_EDID_FIRMWARE=y 804 804 + CONFIG_DRM_EFIDRM=y 805 805 + CONFIG_DRM_SIMPLEDRM=y 780 806 CONFIG_DRM_RADEON=m 781 807 CONFIG_DRM_RADEON_USERPTR=y 782 782 - CONFIG_DRM_AMDGPU=m 783 783 - CONFIG_DRM_AMDGPU_SI=y 784 784 - CONFIG_DRM_AMDGPU_CIK=y 785 785 - CONFIG_DRM_AMDGPU_USERPTR=y 786 786 - CONFIG_DRM_AST=y 787 808 CONFIG_DRM_QXL=m 788 809 CONFIG_DRM_VIRTIO_GPU=m 789 810 CONFIG_DRM_LOONGSON=y 790 790 - CONFIG_DRM_SIMPLEDRM=y 791 811 CONFIG_FB=y 792 792 - CONFIG_FB_EFI=y 793 812 CONFIG_FB_RADEON=y 794 813 CONFIG_FIRMWARE_EDID=y 795 814 CONFIG_LCD_CLASS_DEVICE=y ··· 826 855 CONFIG_SND_USB_AUDIO_MIDI_V2=y 827 856 CONFIG_SND_SOC=m 828 857 CONFIG_SND_SOC_LOONGSON_CARD=m 858 858 + CONFIG_SND_LOONGSON1_AC97=m 829 859 CONFIG_SND_SOC_ES7134=m 830 860 CONFIG_SND_SOC_ES7241=m 831 861 CONFIG_SND_SOC_ES8311=m ··· 886 914 CONFIG_TYPEC_UCSI=m 887 915 CONFIG_UCSI_ACPI=m 888 916 CONFIG_MMC=y 889 889 - CONFIG_MMC_LOONGSON2=m 890 917 CONFIG_INFINIBAND=m 891 918 CONFIG_EDAC=y 919 919 + # CONFIG_EDAC_LEGACY_SYSFS is not set 892 920 CONFIG_EDAC_LOONGSON=y 893 921 CONFIG_RTC_CLASS=y 894 922 CONFIG_RTC_DRV_EFI=y 895 923 CONFIG_RTC_DRV_LOONGSON=y 896 924 CONFIG_DMADEVICES=y 897 897 - CONFIG_LOONGSON2_APB_DMA=y 925 925 + CONFIG_LOONGSON1_APB_DMA=y 898 926 CONFIG_UDMABUF=y 899 927 CONFIG_DMABUF_HEAPS=y 900 928 CONFIG_DMABUF_HEAPS_SYSTEM=y ··· 931 959 CONFIG_COMEDI_NI_PCIDIO=m 932 960 CONFIG_COMEDI_NI_PCIMIO=m 933 961 CONFIG_STAGING=y 934 934 - CONFIG_COMMON_CLK_LOONGSON2=y 935 935 - CONFIG_LOONGSON2_GUTS=y 936 936 - CONFIG_LOONGSON2_PM=y 962 962 + CONFIG_CLKSRC_LOONGSON1_PWM=y 963 963 + # CONFIG_IOMMU_SUPPORT is not set 937 964 CONFIG_PM_DEVFREQ=y 938 965 CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y 939 966 CONFIG_DEVFREQ_GOV_PERFORMANCE=y ··· 946 975 CONFIG_NTB_PERF=m 947 976 CONFIG_NTB_TRANSPORT=m 948 977 CONFIG_PWM=y 949 949 - CONFIG_PWM_LOONGSON=y 950 978 CONFIG_GENERIC_PHY=y 951 979 CONFIG_USB4=y 952 980 CONFIG_EXT2_FS=y ··· 1001 1031 CONFIG_FAT_DEFAULT_IOCHARSET="gb2312" 1002 1032 CONFIG_EXFAT_FS=m 1003 1033 CONFIG_NTFS3_FS=m 1004 1004 - CONFIG_NTFS3_64BIT_CLUSTER=y 1005 1034 CONFIG_NTFS3_LZX_XPRESS=y 1006 1035 CONFIG_PROC_KCORE=y 1007 1036 CONFIG_TMPFS=y 1008 1037 CONFIG_TMPFS_POSIX_ACL=y 1009 1009 - CONFIG_HUGETLBFS=y 1010 1038 CONFIG_CONFIGFS_FS=y 1011 1039 CONFIG_ORANGEFS_FS=m 1012 1040 CONFIG_ECRYPT_FS=m ··· 1094 1126 CONFIG_CRYPTO_DEV_VIRTIO=m 1095 1127 CONFIG_CRYPTO_DEV_LOONGSON_RNG=m 1096 1128 CONFIG_DMA_CMA=y 1097 1097 - CONFIG_DMA_NUMA_CMA=y 1098 1129 CONFIG_CMA_SIZE_MBYTES=0 1099 1130 CONFIG_PRINTK_TIME=y 1100 1131 CONFIG_STRIP_ASM_SYMS=y ··· 1103 1136 CONFIG_SCHEDSTATS=y 1104 1137 # CONFIG_DEBUG_PREEMPT is not set 1105 1138 # CONFIG_FTRACE is not set 1106 1106 - CONFIG_UNWINDER_ORC=y

+1140

arch/loongarch/configs/loongson64_defconfig

reviewed

··· 1 1 + # CONFIG_LOCALVERSION_AUTO is not set 2 2 + CONFIG_KERNEL_ZSTD=y 3 3 + CONFIG_SYSVIPC=y 4 4 + CONFIG_POSIX_MQUEUE=y 5 5 + CONFIG_NO_HZ=y 6 6 + CONFIG_HIGH_RES_TIMERS=y 7 7 + CONFIG_BPF_SYSCALL=y 8 8 + CONFIG_BPF_JIT=y 9 9 + CONFIG_PREEMPT=y 10 10 + CONFIG_PREEMPT_DYNAMIC=y 11 11 + CONFIG_SCHED_CORE=y 12 12 + CONFIG_BSD_PROCESS_ACCT=y 13 13 + CONFIG_BSD_PROCESS_ACCT_V3=y 14 14 + CONFIG_TASKSTATS=y 15 15 + CONFIG_TASK_DELAY_ACCT=y 16 16 + CONFIG_TASK_XACCT=y 17 17 + CONFIG_TASK_IO_ACCOUNTING=y 18 18 + CONFIG_PSI=y 19 19 + CONFIG_IKCONFIG=y 20 20 + CONFIG_IKCONFIG_PROC=y 21 21 + CONFIG_IKHEADERS=y 22 22 + CONFIG_LOG_BUF_SHIFT=18 23 23 + CONFIG_NUMA_BALANCING=y 24 24 + CONFIG_MEMCG=y 25 25 + CONFIG_BLK_CGROUP=y 26 26 + CONFIG_CFS_BANDWIDTH=y 27 27 + CONFIG_CGROUP_PIDS=y 28 28 + CONFIG_CGROUP_RDMA=y 29 29 + CONFIG_CGROUP_DMEM=y 30 30 + CONFIG_CGROUP_FREEZER=y 31 31 + CONFIG_CGROUP_HUGETLB=y 32 32 + CONFIG_CPUSETS=y 33 33 + CONFIG_CGROUP_DEVICE=y 34 34 + CONFIG_CGROUP_CPUACCT=y 35 35 + CONFIG_CGROUP_PERF=y 36 36 + CONFIG_CGROUP_BPF=y 37 37 + CONFIG_CGROUP_MISC=y 38 38 + CONFIG_NAMESPACES=y 39 39 + CONFIG_USER_NS=y 40 40 + CONFIG_CHECKPOINT_RESTORE=y 41 41 + CONFIG_SCHED_AUTOGROUP=y 42 42 + CONFIG_RELAY=y 43 43 + CONFIG_BLK_DEV_INITRD=y 44 44 + CONFIG_EXPERT=y 45 45 + CONFIG_KALLSYMS_ALL=y 46 46 + CONFIG_PERF_EVENTS=y 47 47 + CONFIG_KEXEC=y 48 48 + CONFIG_KEXEC_FILE=y 49 49 + CONFIG_CRASH_DUMP=y 50 50 + CONFIG_LOONGARCH=y 51 51 + CONFIG_64BIT=y 52 52 + CONFIG_MACH_LOONGSON64=y 53 53 + CONFIG_PAGE_SIZE_16KB=y 54 54 + CONFIG_HZ_250=y 55 55 + CONFIG_DMI=y 56 56 + CONFIG_EFI=y 57 57 + CONFIG_SMP=y 58 58 + CONFIG_HOTPLUG_CPU=y 59 59 + CONFIG_NR_CPUS=2048 60 60 + CONFIG_NUMA=y 61 61 + CONFIG_CPU_HAS_FPU=y 62 62 + CONFIG_CPU_HAS_LSX=y 63 63 + CONFIG_CPU_HAS_LASX=y 64 64 + CONFIG_RANDOMIZE_BASE=y 65 65 + CONFIG_SUSPEND=y 66 66 + CONFIG_HIBERNATION=y 67 67 + CONFIG_ACPI=y 68 68 + CONFIG_ACPI_SPCR_TABLE=y 69 69 + CONFIG_ACPI_TAD=y 70 70 + CONFIG_ACPI_DOCK=y 71 71 + CONFIG_ACPI_IPMI=m 72 72 + CONFIG_ACPI_HOTPLUG_CPU=y 73 73 + CONFIG_ACPI_PCI_SLOT=y 74 74 + CONFIG_ACPI_HOTPLUG_MEMORY=y 75 75 + CONFIG_ACPI_BGRT=y 76 76 + CONFIG_CPU_FREQ=y 77 77 + CONFIG_CPU_FREQ_GOV_POWERSAVE=y 78 78 + CONFIG_CPU_FREQ_GOV_USERSPACE=y 79 79 + CONFIG_CPU_FREQ_GOV_ONDEMAND=y 80 80 + CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y 81 81 + CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y 82 82 + CONFIG_LOONGSON3_CPUFREQ=m 83 83 + CONFIG_VIRTUALIZATION=y 84 84 + CONFIG_KVM=m 85 85 + CONFIG_JUMP_LABEL=y 86 86 + CONFIG_MODULES=y 87 87 + CONFIG_MODULE_FORCE_LOAD=y 88 88 + CONFIG_MODULE_UNLOAD=y 89 89 + CONFIG_MODULE_FORCE_UNLOAD=y 90 90 + CONFIG_MODVERSIONS=y 91 91 + CONFIG_MODULE_COMPRESS=y 92 92 + CONFIG_MODULE_COMPRESS_ZSTD=y 93 93 + CONFIG_MODULE_DECOMPRESS=y 94 94 + CONFIG_BLK_DEV_ZONED=y 95 95 + CONFIG_BLK_DEV_THROTTLING=y 96 96 + CONFIG_BLK_WBT=y 97 97 + CONFIG_BLK_CGROUP_IOLATENCY=y 98 98 + CONFIG_BLK_CGROUP_FC_APPID=y 99 99 + CONFIG_BLK_CGROUP_IOCOST=y 100 100 + CONFIG_BLK_CGROUP_IOPRIO=y 101 101 + CONFIG_BLK_INLINE_ENCRYPTION=y 102 102 + CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y 103 103 + CONFIG_PARTITION_ADVANCED=y 104 104 + CONFIG_BSD_DISKLABEL=y 105 105 + CONFIG_UNIXWARE_DISKLABEL=y 106 106 + CONFIG_CMDLINE_PARTITION=y 107 107 + CONFIG_IOSCHED_BFQ=y 108 108 + CONFIG_BFQ_GROUP_IOSCHED=y 109 109 + CONFIG_BINFMT_MISC=m 110 110 + CONFIG_ZSWAP=y 111 111 + CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y 112 112 + CONFIG_ZSMALLOC=y 113 113 + # CONFIG_COMPAT_BRK is not set 114 114 + CONFIG_MEMORY_HOTPLUG=y 115 115 + # CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE is not set 116 116 + CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y 117 117 + # CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_KERNEL is not set 118 118 + # CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_MOVABLE is not set 119 119 + CONFIG_MEMORY_HOTREMOVE=y 120 120 + CONFIG_KSM=y 121 121 + CONFIG_TRANSPARENT_HUGEPAGE=y 122 122 + CONFIG_CMA=y 123 123 + CONFIG_CMA_SYSFS=y 124 124 + CONFIG_USERFAULTFD=y 125 125 + CONFIG_NET=y 126 126 + CONFIG_PACKET=y 127 127 + CONFIG_UNIX=y 128 128 + CONFIG_TLS=m 129 129 + CONFIG_TLS_DEVICE=y 130 130 + CONFIG_XFRM_USER=y 131 131 + CONFIG_NET_KEY=y 132 132 + CONFIG_XDP_SOCKETS=y 133 133 + CONFIG_INET=y 134 134 + CONFIG_IP_MULTICAST=y 135 135 + CONFIG_IP_ADVANCED_ROUTER=y 136 136 + CONFIG_IP_MULTIPLE_TABLES=y 137 137 + CONFIG_IP_ROUTE_MULTIPATH=y 138 138 + CONFIG_IP_ROUTE_VERBOSE=y 139 139 + CONFIG_IP_PNP=y 140 140 + CONFIG_IP_PNP_DHCP=y 141 141 + CONFIG_IP_PNP_BOOTP=y 142 142 + CONFIG_IP_PNP_RARP=y 143 143 + CONFIG_NET_IPIP=m 144 144 + CONFIG_NET_IPGRE_DEMUX=m 145 145 + CONFIG_NET_IPGRE=m 146 146 + CONFIG_NET_IPGRE_BROADCAST=y 147 147 + CONFIG_IP_MROUTE=y 148 148 + CONFIG_IP_MROUTE_MULTIPLE_TABLES=y 149 149 + CONFIG_IP_PIMSM_V1=y 150 150 + CONFIG_IP_PIMSM_V2=y 151 151 + CONFIG_INET_AH=m 152 152 + CONFIG_INET_ESP=m 153 153 + CONFIG_INET_ESP_OFFLOAD=m 154 154 + CONFIG_INET_ESPINTCP=y 155 155 + CONFIG_INET_IPCOMP=m 156 156 + CONFIG_INET_UDP_DIAG=y 157 157 + CONFIG_TCP_CONG_ADVANCED=y 158 158 + CONFIG_TCP_CONG_BIC=y 159 159 + CONFIG_TCP_CONG_HSTCP=m 160 160 + CONFIG_TCP_CONG_HYBLA=m 161 161 + CONFIG_TCP_CONG_VEGAS=m 162 162 + CONFIG_TCP_CONG_NV=m 163 163 + CONFIG_TCP_CONG_SCALABLE=m 164 164 + CONFIG_TCP_CONG_VENO=m 165 165 + CONFIG_TCP_CONG_DCTCP=m 166 166 + CONFIG_TCP_CONG_CDG=m 167 167 + CONFIG_TCP_CONG_BBR=y 168 168 + CONFIG_IPV6_ROUTER_PREF=y 169 169 + CONFIG_IPV6_ROUTE_INFO=y 170 170 + CONFIG_INET6_AH=m 171 171 + CONFIG_INET6_ESP=m 172 172 + CONFIG_INET6_ESP_OFFLOAD=m 173 173 + CONFIG_INET6_ESPINTCP=y 174 174 + CONFIG_INET6_IPCOMP=m 175 175 + CONFIG_IPV6_MULTIPLE_TABLES=y 176 176 + CONFIG_IPV6_MROUTE=y 177 177 + CONFIG_MPTCP=y 178 178 + CONFIG_NETWORK_PHY_TIMESTAMPING=y 179 179 + CONFIG_NETFILTER=y 180 180 + CONFIG_BRIDGE_NETFILTER=m 181 181 + CONFIG_NETFILTER_NETLINK_LOG=m 182 182 + CONFIG_NF_CONNTRACK=m 183 183 + CONFIG_NF_CONNTRACK_AMANDA=m 184 184 + CONFIG_NF_CONNTRACK_FTP=m 185 185 + CONFIG_NF_CONNTRACK_NETBIOS_NS=m 186 186 + CONFIG_NF_CONNTRACK_SNMP=m 187 187 + CONFIG_NF_CONNTRACK_PPTP=m 188 188 + CONFIG_NF_CONNTRACK_TFTP=m 189 189 + CONFIG_NF_CT_NETLINK=m 190 190 + CONFIG_NF_TABLES=m 191 191 + CONFIG_NF_TABLES_INET=y 192 192 + CONFIG_NFT_CT=m 193 193 + CONFIG_NFT_CONNLIMIT=m 194 194 + CONFIG_NFT_LOG=m 195 195 + CONFIG_NFT_LIMIT=m 196 196 + CONFIG_NFT_MASQ=m 197 197 + CONFIG_NFT_REDIR=m 198 198 + CONFIG_NFT_NAT=m 199 199 + CONFIG_NFT_TUNNEL=m 200 200 + CONFIG_NFT_QUEUE=m 201 201 + CONFIG_NFT_QUOTA=m 202 202 + CONFIG_NFT_REJECT=m 203 203 + CONFIG_NFT_COMPAT=m 204 204 + CONFIG_NFT_HASH=m 205 205 + CONFIG_NFT_FIB_INET=m 206 206 + CONFIG_NFT_SOCKET=m 207 207 + CONFIG_NFT_OSF=m 208 208 + CONFIG_NFT_TPROXY=m 209 209 + CONFIG_NETFILTER_XT_SET=m 210 210 + CONFIG_NETFILTER_XT_TARGET_AUDIT=m 211 211 + CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m 212 212 + CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m 213 213 + CONFIG_NETFILTER_XT_TARGET_CONNMARK=m 214 214 + CONFIG_NETFILTER_XT_TARGET_CT=m 215 215 + CONFIG_NETFILTER_XT_TARGET_DSCP=m 216 216 + CONFIG_NETFILTER_XT_TARGET_HMARK=m 217 217 + CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m 218 218 + CONFIG_NETFILTER_XT_TARGET_LED=m 219 219 + CONFIG_NETFILTER_XT_TARGET_LOG=m 220 220 + CONFIG_NETFILTER_XT_TARGET_MARK=m 221 221 + CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 222 222 + CONFIG_NETFILTER_XT_TARGET_TRACE=m 223 223 + CONFIG_NETFILTER_XT_TARGET_SECMARK=m 224 224 + CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 225 225 + CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m 226 226 + CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m 227 227 + CONFIG_NETFILTER_XT_MATCH_BPF=m 228 228 + CONFIG_NETFILTER_XT_MATCH_CGROUP=m 229 229 + CONFIG_NETFILTER_XT_MATCH_CLUSTER=m 230 230 + CONFIG_NETFILTER_XT_MATCH_COMMENT=m 231 231 + CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m 232 232 + CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m 233 233 + CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m 234 234 + CONFIG_NETFILTER_XT_MATCH_CONNMARK=m 235 235 + CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m 236 236 + CONFIG_NETFILTER_XT_MATCH_CPU=m 237 237 + CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m 238 238 + CONFIG_NETFILTER_XT_MATCH_DSCP=m 239 239 + CONFIG_NETFILTER_XT_MATCH_ESP=m 240 240 + CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m 241 241 + CONFIG_NETFILTER_XT_MATCH_HELPER=m 242 242 + CONFIG_NETFILTER_XT_MATCH_IPCOMP=m 243 243 + CONFIG_NETFILTER_XT_MATCH_IPRANGE=m 244 244 + CONFIG_NETFILTER_XT_MATCH_IPVS=m 245 245 + CONFIG_NETFILTER_XT_MATCH_LENGTH=m 246 246 + CONFIG_NETFILTER_XT_MATCH_LIMIT=m 247 247 + CONFIG_NETFILTER_XT_MATCH_MAC=m 248 248 + CONFIG_NETFILTER_XT_MATCH_MARK=m 249 249 + CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m 250 250 + CONFIG_NETFILTER_XT_MATCH_NFACCT=m 251 251 + CONFIG_NETFILTER_XT_MATCH_OSF=m 252 252 + CONFIG_NETFILTER_XT_MATCH_OWNER=m 253 253 + CONFIG_NETFILTER_XT_MATCH_POLICY=m 254 254 + CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m 255 255 + CONFIG_NETFILTER_XT_MATCH_QUOTA=m 256 256 + CONFIG_NETFILTER_XT_MATCH_RATEEST=m 257 257 + CONFIG_NETFILTER_XT_MATCH_REALM=m 258 258 + CONFIG_NETFILTER_XT_MATCH_SOCKET=m 259 259 + CONFIG_NETFILTER_XT_MATCH_STATE=m 260 260 + CONFIG_NETFILTER_XT_MATCH_STATISTIC=m 261 261 + CONFIG_NETFILTER_XT_MATCH_STRING=m 262 262 + CONFIG_NETFILTER_XT_MATCH_TCPMSS=m 263 263 + CONFIG_NETFILTER_XT_MATCH_TIME=m 264 264 + CONFIG_NETFILTER_XT_MATCH_U32=m 265 265 + CONFIG_IP_SET=m 266 266 + CONFIG_IP_VS=m 267 267 + CONFIG_IP_VS_IPV6=y 268 268 + CONFIG_IP_VS_PROTO_TCP=y 269 269 + CONFIG_IP_VS_PROTO_UDP=y 270 270 + CONFIG_IP_VS_PROTO_ESP=y 271 271 + CONFIG_IP_VS_PROTO_AH=y 272 272 + CONFIG_IP_VS_PROTO_SCTP=y 273 273 + CONFIG_IP_VS_RR=m 274 274 + CONFIG_IP_VS_WRR=m 275 275 + CONFIG_IP_VS_NFCT=y 276 276 + CONFIG_NF_TABLES_IPV4=y 277 277 + CONFIG_NFT_DUP_IPV4=m 278 278 + CONFIG_NFT_FIB_IPV4=m 279 279 + CONFIG_NF_TABLES_ARP=y 280 280 + CONFIG_IP_NF_IPTABLES=m 281 281 + CONFIG_IP_NF_MATCH_AH=m 282 282 + CONFIG_IP_NF_MATCH_ECN=m 283 283 + CONFIG_IP_NF_MATCH_RPFILTER=m 284 284 + CONFIG_IP_NF_MATCH_TTL=m 285 285 + CONFIG_IP_NF_FILTER=m 286 286 + CONFIG_IP_NF_TARGET_REJECT=m 287 287 + CONFIG_IP_NF_TARGET_SYNPROXY=m 288 288 + CONFIG_IP_NF_NAT=m 289 289 + CONFIG_IP_NF_TARGET_MASQUERADE=m 290 290 + CONFIG_IP_NF_TARGET_NETMAP=m 291 291 + CONFIG_IP_NF_TARGET_REDIRECT=m 292 292 + CONFIG_IP_NF_MANGLE=m 293 293 + CONFIG_IP_NF_TARGET_ECN=m 294 294 + CONFIG_IP_NF_TARGET_TTL=m 295 295 + CONFIG_IP_NF_RAW=m 296 296 + CONFIG_IP_NF_SECURITY=m 297 297 + CONFIG_IP_NF_ARPTABLES=m 298 298 + CONFIG_IP_NF_ARPFILTER=m 299 299 + CONFIG_IP_NF_ARP_MANGLE=m 300 300 + CONFIG_NF_TABLES_IPV6=y 301 301 + CONFIG_NFT_FIB_IPV6=m 302 302 + CONFIG_IP6_NF_IPTABLES=y 303 303 + CONFIG_IP6_NF_MATCH_AH=m 304 304 + CONFIG_IP6_NF_MATCH_EUI64=m 305 305 + CONFIG_IP6_NF_MATCH_FRAG=m 306 306 + CONFIG_IP6_NF_MATCH_OPTS=m 307 307 + CONFIG_IP6_NF_MATCH_IPV6HEADER=m 308 308 + CONFIG_IP6_NF_MATCH_MH=m 309 309 + CONFIG_IP6_NF_MATCH_RPFILTER=m 310 310 + CONFIG_IP6_NF_MATCH_RT=m 311 311 + CONFIG_IP6_NF_MATCH_SRH=m 312 312 + CONFIG_IP6_NF_FILTER=y 313 313 + CONFIG_IP6_NF_TARGET_REJECT=m 314 314 + CONFIG_IP6_NF_TARGET_SYNPROXY=m 315 315 + CONFIG_IP6_NF_MANGLE=m 316 316 + CONFIG_IP6_NF_RAW=m 317 317 + CONFIG_IP6_NF_SECURITY=m 318 318 + CONFIG_IP6_NF_NAT=m 319 319 + CONFIG_IP6_NF_TARGET_MASQUERADE=m 320 320 + CONFIG_IP6_NF_TARGET_NPT=m 321 321 + CONFIG_NF_TABLES_BRIDGE=m 322 322 + CONFIG_NF_CONNTRACK_BRIDGE=m 323 323 + CONFIG_BRIDGE_NF_EBTABLES=m 324 324 + CONFIG_BRIDGE_EBT_BROUTE=m 325 325 + CONFIG_BRIDGE_EBT_T_FILTER=m 326 326 + CONFIG_BRIDGE_EBT_T_NAT=m 327 327 + CONFIG_BRIDGE_EBT_ARP=m 328 328 + CONFIG_BRIDGE_EBT_IP=m 329 329 + CONFIG_BRIDGE_EBT_IP6=m 330 330 + CONFIG_IP_SCTP=m 331 331 + CONFIG_RDS=y 332 332 + CONFIG_L2TP=m 333 333 + CONFIG_L2TP_V3=y 334 334 + CONFIG_L2TP_IP=m 335 335 + CONFIG_L2TP_ETH=m 336 336 + CONFIG_BRIDGE=m 337 337 + CONFIG_VLAN_8021Q=m 338 338 + CONFIG_VLAN_8021Q_GVRP=y 339 339 + CONFIG_VLAN_8021Q_MVRP=y 340 340 + CONFIG_LLC2=m 341 341 + CONFIG_NET_SCHED=y 342 342 + CONFIG_NET_SCH_HTB=m 343 343 + CONFIG_NET_SCH_PRIO=m 344 344 + CONFIG_NET_SCH_MULTIQ=m 345 345 + CONFIG_NET_SCH_RED=m 346 346 + CONFIG_NET_SCH_SFB=m 347 347 + CONFIG_NET_SCH_SFQ=m 348 348 + CONFIG_NET_SCH_TBF=m 349 349 + CONFIG_NET_SCH_CBS=m 350 350 + CONFIG_NET_SCH_GRED=m 351 351 + CONFIG_NET_SCH_NETEM=m 352 352 + CONFIG_NET_SCH_MQPRIO=m 353 353 + CONFIG_NET_SCH_SKBPRIO=m 354 354 + CONFIG_NET_SCH_QFQ=m 355 355 + CONFIG_NET_SCH_CODEL=m 356 356 + CONFIG_NET_SCH_FQ_CODEL=m 357 357 + CONFIG_NET_SCH_CAKE=m 358 358 + CONFIG_NET_SCH_FQ=m 359 359 + CONFIG_NET_SCH_PIE=m 360 360 + CONFIG_NET_SCH_FQ_PIE=m 361 361 + CONFIG_NET_SCH_INGRESS=m 362 362 + CONFIG_NET_SCH_DEFAULT=y 363 363 + CONFIG_NET_CLS_BASIC=m 364 364 + CONFIG_NET_CLS_FW=m 365 365 + CONFIG_NET_CLS_U32=m 366 366 + CONFIG_NET_CLS_FLOW=m 367 367 + CONFIG_NET_CLS_CGROUP=m 368 368 + CONFIG_NET_CLS_BPF=m 369 369 + CONFIG_NET_CLS_FLOWER=m 370 370 + CONFIG_NET_CLS_MATCHALL=m 371 371 + CONFIG_NET_CLS_ACT=y 372 372 + CONFIG_NET_ACT_POLICE=m 373 373 + CONFIG_NET_ACT_GACT=m 374 374 + CONFIG_NET_ACT_MIRRED=m 375 375 + CONFIG_NET_ACT_NAT=m 376 376 + CONFIG_NET_ACT_BPF=m 377 377 + CONFIG_OPENVSWITCH=m 378 378 + CONFIG_VSOCKETS=m 379 379 + CONFIG_VIRTIO_VSOCKETS=m 380 380 + CONFIG_NETLINK_DIAG=y 381 381 + CONFIG_CGROUP_NET_PRIO=y 382 382 + CONFIG_BPF_STREAM_PARSER=y 383 383 + CONFIG_BT=m 384 384 + CONFIG_BT_RFCOMM=m 385 385 + CONFIG_BT_RFCOMM_TTY=y 386 386 + CONFIG_BT_BNEP=m 387 387 + CONFIG_BT_BNEP_MC_FILTER=y 388 388 + CONFIG_BT_BNEP_PROTO_FILTER=y 389 389 + CONFIG_BT_HIDP=m 390 390 + CONFIG_BT_HS=y 391 391 + CONFIG_BT_HCIBTUSB=m 392 392 + CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y 393 393 + CONFIG_BT_HCIBTUSB_MTK=y 394 394 + CONFIG_BT_HCIUART=m 395 395 + CONFIG_BT_HCIUART_BCSP=y 396 396 + CONFIG_BT_HCIUART_ATH3K=y 397 397 + CONFIG_BT_HCIUART_INTEL=y 398 398 + CONFIG_BT_HCIUART_AG6XX=y 399 399 + CONFIG_BT_HCIBCM203X=m 400 400 + CONFIG_BT_HCIBPA10X=m 401 401 + CONFIG_BT_HCIBFUSB=m 402 402 + CONFIG_BT_HCIDTL1=m 403 403 + CONFIG_BT_HCIBT3C=m 404 404 + CONFIG_BT_HCIBLUECARD=m 405 405 + CONFIG_BT_HCIVHCI=m 406 406 + CONFIG_BT_MRVL=m 407 407 + CONFIG_BT_ATH3K=m 408 408 + CONFIG_BT_VIRTIO=m 409 409 + CONFIG_CFG80211=m 410 410 + CONFIG_CFG80211_WEXT=y 411 411 + CONFIG_MAC80211=m 412 412 + CONFIG_RFKILL=m 413 413 + CONFIG_RFKILL_INPUT=y 414 414 + CONFIG_NET_9P=y 415 415 + CONFIG_NET_9P_VIRTIO=y 416 416 + CONFIG_CEPH_LIB=m 417 417 + CONFIG_PCIEPORTBUS=y 418 418 + CONFIG_HOTPLUG_PCI_PCIE=y 419 419 + CONFIG_PCIEAER=y 420 420 + # CONFIG_PCIEASPM is not set 421 421 + CONFIG_PCI_IOV=y 422 422 + CONFIG_HOTPLUG_PCI=y 423 423 + CONFIG_HOTPLUG_PCI_SHPC=y 424 424 + CONFIG_PCI_HOST_GENERIC=y 425 425 + CONFIG_PCCARD=m 426 426 + CONFIG_YENTA=m 427 427 + CONFIG_RAPIDIO=y 428 428 + CONFIG_RAPIDIO_TSI721=y 429 429 + CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y 430 430 + CONFIG_RAPIDIO_ENUM_BASIC=m 431 431 + CONFIG_RAPIDIO_CHMAN=m 432 432 + CONFIG_RAPIDIO_MPORT_CDEV=m 433 433 + CONFIG_UEVENT_HELPER=y 434 434 + CONFIG_DEVTMPFS=y 435 435 + CONFIG_DEVTMPFS_MOUNT=y 436 436 + CONFIG_FW_LOADER_COMPRESS=y 437 437 + CONFIG_FW_LOADER_COMPRESS_ZSTD=y 438 438 + CONFIG_EFI_ZBOOT=y 439 439 + CONFIG_EFI_BOOTLOADER_CONTROL=m 440 440 + CONFIG_EFI_CAPSULE_LOADER=m 441 441 + CONFIG_EFI_TEST=m 442 442 + CONFIG_MTD=m 443 443 + CONFIG_MTD_BLOCK=m 444 444 + CONFIG_MTD_CFI=m 445 445 + CONFIG_MTD_JEDECPROBE=m 446 446 + CONFIG_MTD_CFI_INTELEXT=m 447 447 + CONFIG_MTD_CFI_AMDSTD=m 448 448 + CONFIG_MTD_CFI_STAA=m 449 449 + CONFIG_MTD_RAM=m 450 450 + CONFIG_MTD_ROM=m 451 451 + CONFIG_MTD_RAW_NAND=m 452 452 + CONFIG_MTD_NAND_PLATFORM=m 453 453 + CONFIG_MTD_NAND_LOONGSON=m 454 454 + CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y 455 455 + CONFIG_MTD_NAND_ECC_SW_BCH=y 456 456 + CONFIG_MTD_UBI=m 457 457 + CONFIG_MTD_UBI_BLOCK=y 458 458 + CONFIG_PARPORT=y 459 459 + CONFIG_PARPORT_PC=y 460 460 + CONFIG_PARPORT_SERIAL=y 461 461 + CONFIG_PARPORT_PC_FIFO=y 462 462 + CONFIG_ZRAM=m 463 463 + CONFIG_ZRAM_BACKEND_LZ4=y 464 464 + CONFIG_ZRAM_BACKEND_LZ4HC=y 465 465 + CONFIG_ZRAM_BACKEND_ZSTD=y 466 466 + CONFIG_ZRAM_BACKEND_DEFLATE=y 467 467 + CONFIG_ZRAM_BACKEND_842=y 468 468 + CONFIG_ZRAM_BACKEND_LZO=y 469 469 + CONFIG_ZRAM_DEF_COMP_ZSTD=y 470 470 + CONFIG_ZRAM_WRITEBACK=y 471 471 + CONFIG_ZRAM_MEMORY_TRACKING=y 472 472 + CONFIG_ZRAM_MULTI_COMP=y 473 473 + CONFIG_BLK_DEV_LOOP=y 474 474 + CONFIG_BLK_DEV_DRBD=m 475 475 + CONFIG_BLK_DEV_NBD=m 476 476 + CONFIG_BLK_DEV_RAM=y 477 477 + CONFIG_BLK_DEV_RAM_SIZE=8192 478 478 + CONFIG_VIRTIO_BLK=y 479 479 + CONFIG_BLK_DEV_RBD=m 480 480 + CONFIG_BLK_DEV_NVME=y 481 481 + CONFIG_NVME_MULTIPATH=y 482 482 + CONFIG_NVME_RDMA=m 483 483 + CONFIG_NVME_FC=m 484 484 + CONFIG_NVME_TCP=m 485 485 + CONFIG_NVME_TARGET=m 486 486 + CONFIG_NVME_TARGET_PASSTHRU=y 487 487 + CONFIG_NVME_TARGET_LOOP=m 488 488 + CONFIG_NVME_TARGET_RDMA=m 489 489 + CONFIG_NVME_TARGET_FC=m 490 490 + CONFIG_NVME_TARGET_TCP=m 491 491 + CONFIG_EEPROM_AT24=m 492 492 + CONFIG_PVPANIC=y 493 493 + CONFIG_PVPANIC_MMIO=m 494 494 + CONFIG_PVPANIC_PCI=m 495 495 + CONFIG_BLK_DEV_SD=y 496 496 + CONFIG_BLK_DEV_SR=y 497 497 + CONFIG_CHR_DEV_SG=y 498 498 + CONFIG_CHR_DEV_SCH=m 499 499 + CONFIG_SCSI_CONSTANTS=y 500 500 + CONFIG_SCSI_LOGGING=y 501 501 + CONFIG_SCSI_SPI_ATTRS=m 502 502 + CONFIG_SCSI_FC_ATTRS=m 503 503 + CONFIG_SCSI_SAS_ATA=y 504 504 + CONFIG_ISCSI_TCP=m 505 505 + CONFIG_SCSI_MVSAS=y 506 506 + # CONFIG_SCSI_MVSAS_DEBUG is not set 507 507 + CONFIG_SCSI_MVSAS_TASKLET=y 508 508 + CONFIG_SCSI_MVUMI=y 509 509 + CONFIG_MEGARAID_NEWGEN=y 510 510 + CONFIG_MEGARAID_MM=y 511 511 + CONFIG_MEGARAID_MAILBOX=y 512 512 + CONFIG_MEGARAID_LEGACY=y 513 513 + CONFIG_MEGARAID_SAS=y 514 514 + CONFIG_SCSI_MPT2SAS=y 515 515 + CONFIG_LIBFC=m 516 516 + CONFIG_LIBFCOE=m 517 517 + CONFIG_FCOE=m 518 518 + CONFIG_SCSI_QLOGIC_1280=m 519 519 + CONFIG_SCSI_QLA_FC=m 520 520 + CONFIG_TCM_QLA2XXX=m 521 521 + CONFIG_SCSI_QLA_ISCSI=m 522 522 + CONFIG_SCSI_LPFC=m 523 523 + CONFIG_SCSI_VIRTIO=m 524 524 + CONFIG_ATA=y 525 525 + CONFIG_SATA_AHCI=y 526 526 + CONFIG_SATA_AHCI_PLATFORM=y 527 527 + CONFIG_AHCI_DWC=y 528 528 + CONFIG_PATA_ATIIXP=y 529 529 + CONFIG_PATA_PCMCIA=m 530 530 + CONFIG_MD=y 531 531 + CONFIG_BLK_DEV_MD=m 532 532 + CONFIG_MD_LLBITMAP=y 533 533 + CONFIG_MD_RAID0=m 534 534 + CONFIG_MD_RAID1=m 535 535 + CONFIG_MD_RAID10=m 536 536 + CONFIG_MD_RAID456=m 537 537 + CONFIG_BCACHE=m 538 538 + CONFIG_BLK_DEV_DM=y 539 539 + CONFIG_DM_CRYPT=m 540 540 + CONFIG_DM_SNAPSHOT=m 541 541 + CONFIG_DM_THIN_PROVISIONING=m 542 542 + CONFIG_DM_CACHE=m 543 543 + CONFIG_DM_WRITECACHE=m 544 544 + CONFIG_DM_MIRROR=m 545 545 + CONFIG_DM_RAID=m 546 546 + CONFIG_DM_ZERO=m 547 547 + CONFIG_DM_MULTIPATH=m 548 548 + CONFIG_DM_MULTIPATH_QL=m 549 549 + CONFIG_DM_MULTIPATH_ST=m 550 550 + CONFIG_DM_MULTIPATH_HST=m 551 551 + CONFIG_DM_MULTIPATH_IOA=m 552 552 + CONFIG_DM_INIT=y 553 553 + CONFIG_DM_UEVENT=y 554 554 + CONFIG_DM_VERITY=m 555 555 + CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y 556 556 + CONFIG_DM_VERITY_FEC=y 557 557 + CONFIG_DM_INTEGRITY=m 558 558 + CONFIG_DM_ZONED=m 559 559 + CONFIG_DM_VDO=m 560 560 + CONFIG_TARGET_CORE=m 561 561 + CONFIG_TCM_IBLOCK=m 562 562 + CONFIG_TCM_FILEIO=m 563 563 + CONFIG_TCM_PSCSI=m 564 564 + CONFIG_TCM_USER2=m 565 565 + CONFIG_LOOPBACK_TARGET=m 566 566 + CONFIG_ISCSI_TARGET=m 567 567 + CONFIG_NETDEVICES=y 568 568 + CONFIG_BONDING=m 569 569 + CONFIG_DUMMY=y 570 570 + CONFIG_WIREGUARD=m 571 571 + CONFIG_IFB=m 572 572 + CONFIG_NET_TEAM=m 573 573 + CONFIG_NET_TEAM_MODE_BROADCAST=m 574 574 + CONFIG_NET_TEAM_MODE_ROUNDROBIN=m 575 575 + CONFIG_NET_TEAM_MODE_RANDOM=m 576 576 + CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m 577 577 + CONFIG_NET_TEAM_MODE_LOADBALANCE=m 578 578 + CONFIG_MACVLAN=m 579 579 + CONFIG_MACVTAP=m 580 580 + CONFIG_IPVLAN=m 581 581 + CONFIG_VXLAN=y 582 582 + CONFIG_RIONET=m 583 583 + CONFIG_TUN=m 584 584 + CONFIG_VETH=m 585 585 + CONFIG_VIRTIO_NET=m 586 586 + # CONFIG_NET_VENDOR_3COM is not set 587 587 + # CONFIG_NET_VENDOR_ADAPTEC is not set 588 588 + # CONFIG_NET_VENDOR_AGERE is not set 589 589 + # CONFIG_NET_VENDOR_ALACRITECH is not set 590 590 + # CONFIG_NET_VENDOR_ALTEON is not set 591 591 + # CONFIG_NET_VENDOR_AMAZON is not set 592 592 + # CONFIG_NET_VENDOR_AMD is not set 593 593 + # CONFIG_NET_VENDOR_AQUANTIA is not set 594 594 + # CONFIG_NET_VENDOR_ARC is not set 595 595 + # CONFIG_NET_VENDOR_ATHEROS is not set 596 596 + CONFIG_BNX2=y 597 597 + # CONFIG_NET_VENDOR_CAVIUM is not set 598 598 + CONFIG_CHELSIO_T1=m 599 599 + CONFIG_CHELSIO_T1_1G=y 600 600 + CONFIG_CHELSIO_T3=m 601 601 + CONFIG_CHELSIO_T4=m 602 602 + # CONFIG_NET_VENDOR_CISCO is not set 603 603 + # CONFIG_NET_VENDOR_DEC is not set 604 604 + # CONFIG_NET_VENDOR_DLINK is not set 605 605 + # CONFIG_NET_VENDOR_EMULEX is not set 606 606 + # CONFIG_NET_VENDOR_EZCHIP is not set 607 607 + # CONFIG_NET_VENDOR_I825XX is not set 608 608 + CONFIG_E1000=y 609 609 + CONFIG_E1000E=y 610 610 + CONFIG_IGB=y 611 611 + CONFIG_IXGBE=y 612 612 + CONFIG_I40E=y 613 613 + CONFIG_ICE=y 614 614 + CONFIG_FM10K=y 615 615 + CONFIG_IGC=y 616 616 + CONFIG_IDPF=y 617 617 + # CONFIG_NET_VENDOR_MARVELL is not set 618 618 + # CONFIG_NET_VENDOR_MELLANOX is not set 619 619 + # CONFIG_NET_VENDOR_MICREL is not set 620 620 + # CONFIG_NET_VENDOR_MYRI is not set 621 621 + # CONFIG_NET_VENDOR_NATSEMI is not set 622 622 + # CONFIG_NET_VENDOR_NETRONOME is not set 623 623 + # CONFIG_NET_VENDOR_NVIDIA is not set 624 624 + # CONFIG_NET_VENDOR_OKI is not set 625 625 + # CONFIG_NET_VENDOR_QLOGIC is not set 626 626 + # CONFIG_NET_VENDOR_BROCADE is not set 627 627 + # CONFIG_NET_VENDOR_QUALCOMM is not set 628 628 + # CONFIG_NET_VENDOR_RDC is not set 629 629 + CONFIG_8139CP=m 630 630 + CONFIG_8139TOO=m 631 631 + CONFIG_R8169=y 632 632 + # CONFIG_NET_VENDOR_RENESAS is not set 633 633 + # CONFIG_NET_VENDOR_ROCKER is not set 634 634 + # CONFIG_NET_VENDOR_SAMSUNG is not set 635 635 + # CONFIG_NET_VENDOR_SEEQ is not set 636 636 + # CONFIG_NET_VENDOR_SILAN is not set 637 637 + # CONFIG_NET_VENDOR_SIS is not set 638 638 + # CONFIG_NET_VENDOR_SOLARFLARE is not set 639 639 + # CONFIG_NET_VENDOR_SMSC is not set 640 640 + CONFIG_STMMAC_ETH=y 641 641 + # CONFIG_NET_VENDOR_SUN is not set 642 642 + # CONFIG_NET_VENDOR_TEHUTI is not set 643 643 + # CONFIG_NET_VENDOR_TI is not set 644 644 + # CONFIG_NET_VENDOR_VIA is not set 645 645 + CONFIG_NGBE=y 646 646 + CONFIG_TXGBE=y 647 647 + # CONFIG_NET_VENDOR_WIZNET is not set 648 648 + # CONFIG_NET_VENDOR_XILINX is not set 649 649 + CONFIG_MOTORCOMM_PHY=y 650 650 + CONFIG_PPP=m 651 651 + CONFIG_PPP_BSDCOMP=m 652 652 + CONFIG_PPP_DEFLATE=m 653 653 + CONFIG_PPP_FILTER=y 654 654 + CONFIG_PPP_MPPE=m 655 655 + CONFIG_PPP_MULTILINK=y 656 656 + CONFIG_PPPOE=m 657 657 + CONFIG_PPTP=m 658 658 + CONFIG_PPPOL2TP=m 659 659 + CONFIG_PPP_ASYNC=m 660 660 + CONFIG_PPP_SYNC_TTY=m 661 661 + CONFIG_USB_RTL8150=m 662 662 + CONFIG_USB_RTL8152=m 663 663 + CONFIG_USB_USBNET=m 664 664 + # CONFIG_USB_NET_AX8817X is not set 665 665 + # CONFIG_USB_NET_AX88179_178A is not set 666 666 + CONFIG_USB_NET_CDC_EEM=m 667 667 + CONFIG_USB_NET_HUAWEI_CDC_NCM=m 668 668 + CONFIG_USB_NET_CDC_MBIM=m 669 669 + # CONFIG_USB_NET_NET1080 is not set 670 670 + CONFIG_USB_NET_RNDIS_HOST=m 671 671 + # CONFIG_USB_BELKIN is not set 672 672 + # CONFIG_USB_ARMLINUX is not set 673 673 + # CONFIG_USB_NET_ZAURUS is not set 674 674 + CONFIG_ATH9K=m 675 675 + CONFIG_ATH9K_HTC=m 676 676 + CONFIG_IWLWIFI=m 677 677 + CONFIG_IWLDVM=m 678 678 + CONFIG_IWLMVM=m 679 679 + CONFIG_MT7601U=m 680 680 + CONFIG_RT2X00=m 681 681 + CONFIG_RT2800USB=m 682 682 + CONFIG_RTL8180=m 683 683 + CONFIG_RTL8187=m 684 684 + CONFIG_RTL8192CE=m 685 685 + CONFIG_RTL8192SE=m 686 686 + CONFIG_RTL8192DE=m 687 687 + CONFIG_RTL8723AE=m 688 688 + CONFIG_RTL8723BE=m 689 689 + CONFIG_RTL8188EE=m 690 690 + CONFIG_RTL8192EE=m 691 691 + CONFIG_RTL8821AE=m 692 692 + CONFIG_RTL8192CU=m 693 693 + CONFIG_RTL8192DU=m 694 694 + # CONFIG_RTLWIFI_DEBUG is not set 695 695 + CONFIG_RTL8XXXU=m 696 696 + CONFIG_RTW88=m 697 697 + CONFIG_RTW88_8822BE=m 698 698 + CONFIG_RTW88_8822BU=m 699 699 + CONFIG_RTW88_8822CE=m 700 700 + CONFIG_RTW88_8822CU=m 701 701 + CONFIG_RTW88_8723DE=m 702 702 + CONFIG_RTW88_8723DU=m 703 703 + CONFIG_RTW88_8821CE=m 704 704 + CONFIG_RTW88_8821CU=m 705 705 + CONFIG_RTW88_8821AU=m 706 706 + CONFIG_RTW88_8812AU=m 707 707 + CONFIG_RTW88_8814AE=m 708 708 + CONFIG_RTW88_8814AU=m 709 709 + CONFIG_RTW89=m 710 710 + CONFIG_RTW89_8851BE=m 711 711 + CONFIG_RTW89_8852AE=m 712 712 + CONFIG_RTW89_8852BE=m 713 713 + CONFIG_RTW89_8852BTE=m 714 714 + CONFIG_RTW89_8852CE=m 715 715 + CONFIG_RTW89_8922AE=m 716 716 + CONFIG_ZD1211RW=m 717 717 + CONFIG_USB4_NET=m 718 718 + CONFIG_INPUT_MOUSEDEV=y 719 719 + CONFIG_INPUT_MOUSEDEV_PSAUX=y 720 720 + CONFIG_INPUT_EVDEV=y 721 721 + CONFIG_KEYBOARD_GPIO=m 722 722 + CONFIG_KEYBOARD_GPIO_POLLED=m 723 723 + CONFIG_KEYBOARD_MATRIX=m 724 724 + CONFIG_KEYBOARD_XTKBD=m 725 725 + CONFIG_MOUSE_PS2_ELANTECH=y 726 726 + CONFIG_MOUSE_PS2_SENTELIC=y 727 727 + CONFIG_MOUSE_SERIAL=m 728 728 + CONFIG_INPUT_MISC=y 729 729 + CONFIG_INPUT_UINPUT=m 730 730 + CONFIG_SERIO_SERPORT=m 731 731 + CONFIG_SERIO_RAW=m 732 732 + CONFIG_LEGACY_PTY_COUNT=16 733 733 + CONFIG_SERIAL_8250=y 734 734 + CONFIG_SERIAL_8250_CONSOLE=y 735 735 + CONFIG_SERIAL_8250_NR_UARTS=16 736 736 + CONFIG_SERIAL_8250_RUNTIME_UARTS=16 737 737 + CONFIG_SERIAL_8250_EXTENDED=y 738 738 + CONFIG_SERIAL_8250_MANY_PORTS=y 739 739 + CONFIG_SERIAL_8250_SHARE_IRQ=y 740 740 + CONFIG_SERIAL_8250_RSA=y 741 741 + CONFIG_SERIAL_8250_LOONGSON=y 742 742 + CONFIG_SERIAL_OF_PLATFORM=y 743 743 + CONFIG_SERIAL_NONSTANDARD=y 744 744 + CONFIG_PRINTER=m 745 745 + CONFIG_VIRTIO_CONSOLE=y 746 746 + CONFIG_IPMI_HANDLER=m 747 747 + CONFIG_IPMI_DEVICE_INTERFACE=m 748 748 + CONFIG_IPMI_SI=m 749 749 + CONFIG_IPMI_LS2K=y 750 750 + CONFIG_HW_RANDOM=y 751 751 + CONFIG_HW_RANDOM_VIRTIO=m 752 752 + CONFIG_TCG_TPM=m 753 753 + CONFIG_TCG_LOONGSON=m 754 754 + CONFIG_I2C_CHARDEV=y 755 755 + CONFIG_I2C_PIIX4=y 756 756 + CONFIG_I2C_DESIGNWARE_CORE=y 757 757 + CONFIG_I2C_DESIGNWARE_SLAVE=y 758 758 + CONFIG_I2C_DESIGNWARE_PCI=y 759 759 + CONFIG_I2C_GPIO=y 760 760 + CONFIG_I2C_LS2X=y 761 761 + CONFIG_SPI=y 762 762 + CONFIG_SPI_LOONGSON_PCI=m 763 763 + CONFIG_SPI_LOONGSON_PLATFORM=m 764 764 + CONFIG_PINCTRL=y 765 765 + CONFIG_PINCTRL_LOONGSON2=y 766 766 + CONFIG_GPIO_SYSFS=y 767 767 + CONFIG_GPIO_LOONGSON=y 768 768 + CONFIG_GPIO_LOONGSON_64BIT=y 769 769 + CONFIG_GPIO_PCA953X=m 770 770 + CONFIG_GPIO_PCA953X_IRQ=y 771 771 + CONFIG_GPIO_PCA9570=m 772 772 + CONFIG_GPIO_PCF857X=m 773 773 + CONFIG_POWER_RESET=y 774 774 + CONFIG_POWER_RESET_RESTART=y 775 775 + CONFIG_POWER_RESET_SYSCON=y 776 776 + CONFIG_POWER_RESET_SYSCON_POWEROFF=y 777 777 + CONFIG_SYSCON_REBOOT_MODE=y 778 778 + CONFIG_SENSORS_LM75=m 779 779 + CONFIG_SENSORS_LM93=m 780 780 + CONFIG_SENSORS_W83795=m 781 781 + CONFIG_SENSORS_W83627HF=m 782 782 + CONFIG_LOONGSON2_THERMAL=m 783 783 + CONFIG_MFD_LOONGSON_SE=m 784 784 + CONFIG_RC_CORE=m 785 785 + CONFIG_LIRC=y 786 786 + CONFIG_RC_DECODERS=y 787 787 + CONFIG_IR_IMON_DECODER=m 788 788 + CONFIG_IR_JVC_DECODER=m 789 789 + CONFIG_IR_MCE_KBD_DECODER=m 790 790 + CONFIG_IR_NEC_DECODER=m 791 791 + CONFIG_IR_RC5_DECODER=m 792 792 + CONFIG_IR_RC6_DECODER=m 793 793 + CONFIG_IR_SANYO_DECODER=m 794 794 + CONFIG_IR_SHARP_DECODER=m 795 795 + CONFIG_IR_SONY_DECODER=m 796 796 + CONFIG_IR_XMP_DECODER=m 797 797 + CONFIG_MEDIA_SUPPORT=m 798 798 + CONFIG_MEDIA_USB_SUPPORT=y 799 799 + CONFIG_USB_VIDEO_CLASS=m 800 800 + CONFIG_MEDIA_PCI_SUPPORT=y 801 801 + CONFIG_VIDEO_BT848=m 802 802 + CONFIG_DVB_BT8XX=m 803 803 + CONFIG_DRM=y 804 804 + CONFIG_DRM_LOAD_EDID_FIRMWARE=y 805 805 + CONFIG_DRM_EFIDRM=y 806 806 + CONFIG_DRM_SIMPLEDRM=y 807 807 + CONFIG_DRM_RADEON=m 808 808 + CONFIG_DRM_RADEON_USERPTR=y 809 809 + CONFIG_DRM_AMDGPU=m 810 810 + CONFIG_DRM_AMDGPU_SI=y 811 811 + CONFIG_DRM_AMDGPU_CIK=y 812 812 + CONFIG_DRM_AMDGPU_USERPTR=y 813 813 + CONFIG_DRM_AST=y 814 814 + CONFIG_DRM_QXL=m 815 815 + CONFIG_DRM_VIRTIO_GPU=m 816 816 + CONFIG_DRM_LOONGSON=y 817 817 + CONFIG_FB=y 818 818 + CONFIG_FB_RADEON=y 819 819 + CONFIG_FIRMWARE_EDID=y 820 820 + CONFIG_LCD_CLASS_DEVICE=y 821 821 + CONFIG_LCD_PLATFORM=m 822 822 + # CONFIG_VGA_CONSOLE is not set 823 823 + CONFIG_FRAMEBUFFER_CONSOLE=y 824 824 + CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 825 825 + CONFIG_LOGO=y 826 826 + CONFIG_SOUND=y 827 827 + CONFIG_SND=y 828 828 + CONFIG_SND_SEQUENCER=m 829 829 + CONFIG_SND_SEQ_DUMMY=m 830 830 + CONFIG_SND_BT87X=m 831 831 + CONFIG_SND_BT87X_OVERCLOCK=y 832 832 + CONFIG_SND_HDA_INTEL=y 833 833 + CONFIG_SND_HDA_HWDEP=y 834 834 + CONFIG_SND_HDA_INPUT_BEEP=y 835 835 + CONFIG_SND_HDA_PATCH_LOADER=y 836 836 + CONFIG_SND_HDA_CODEC_REALTEK=y 837 837 + CONFIG_SND_HDA_CODEC_REALTEK_LIB=y 838 838 + CONFIG_SND_HDA_CODEC_ALC260=y 839 839 + CONFIG_SND_HDA_CODEC_ALC262=y 840 840 + CONFIG_SND_HDA_CODEC_ALC268=y 841 841 + CONFIG_SND_HDA_CODEC_ALC269=y 842 842 + CONFIG_SND_HDA_CODEC_ALC662=y 843 843 + CONFIG_SND_HDA_CODEC_ALC680=y 844 844 + CONFIG_SND_HDA_CODEC_ALC861=y 845 845 + CONFIG_SND_HDA_CODEC_ALC861VD=y 846 846 + CONFIG_SND_HDA_CODEC_ALC880=y 847 847 + CONFIG_SND_HDA_CODEC_ALC882=y 848 848 + CONFIG_SND_HDA_CODEC_SIGMATEL=y 849 849 + CONFIG_SND_HDA_CODEC_HDMI=y 850 850 + CONFIG_SND_HDA_CODEC_HDMI_GENERIC=y 851 851 + CONFIG_SND_HDA_CODEC_HDMI_INTEL=y 852 852 + CONFIG_SND_HDA_CODEC_HDMI_ATI=y 853 853 + CONFIG_SND_HDA_CODEC_HDMI_NVIDIA=y 854 854 + CONFIG_SND_HDA_CODEC_CONEXANT=y 855 855 + CONFIG_SND_USB_AUDIO=m 856 856 + CONFIG_SND_USB_AUDIO_MIDI_V2=y 857 857 + CONFIG_SND_SOC=m 858 858 + CONFIG_SND_SOC_LOONGSON_CARD=m 859 859 + CONFIG_SND_SOC_ES7134=m 860 860 + CONFIG_SND_SOC_ES7241=m 861 861 + CONFIG_SND_SOC_ES8311=m 862 862 + CONFIG_SND_SOC_ES8316=m 863 863 + CONFIG_SND_SOC_ES8323=m 864 864 + CONFIG_SND_SOC_ES8326=m 865 865 + CONFIG_SND_SOC_ES8328_I2C=m 866 866 + CONFIG_SND_SOC_ES8328_SPI=m 867 867 + CONFIG_SND_SOC_UDA1334=m 868 868 + CONFIG_SND_SOC_UDA1342=m 869 869 + CONFIG_SND_VIRTIO=m 870 870 + CONFIG_HIDRAW=y 871 871 + CONFIG_UHID=m 872 872 + CONFIG_HID_A4TECH=m 873 873 + CONFIG_HID_CHERRY=m 874 874 + CONFIG_HID_ELAN=m 875 875 + CONFIG_HID_LOGITECH=m 876 876 + CONFIG_HID_LOGITECH_DJ=m 877 877 + CONFIG_LOGITECH_FF=y 878 878 + CONFIG_LOGIRUMBLEPAD2_FF=y 879 879 + CONFIG_LOGIG940_FF=y 880 880 + CONFIG_HID_MICROSOFT=m 881 881 + CONFIG_HID_MULTITOUCH=m 882 882 + CONFIG_HID_SUNPLUS=m 883 883 + CONFIG_HID_WACOM=m 884 884 + CONFIG_USB_HIDDEV=y 885 885 + CONFIG_I2C_HID_ACPI=m 886 886 + CONFIG_I2C_HID_OF=m 887 887 + CONFIG_I2C_HID_OF_ELAN=m 888 888 + CONFIG_USB=y 889 889 + CONFIG_USB_OTG=y 890 890 + CONFIG_USB_MON=y 891 891 + CONFIG_USB_XHCI_HCD=y 892 892 + CONFIG_USB_EHCI_HCD=y 893 893 + CONFIG_USB_EHCI_ROOT_HUB_TT=y 894 894 + CONFIG_USB_EHCI_HCD_PLATFORM=y 895 895 + CONFIG_USB_OHCI_HCD=y 896 896 + CONFIG_USB_OHCI_HCD_PLATFORM=y 897 897 + CONFIG_USB_UHCI_HCD=m 898 898 + CONFIG_USB_ACM=m 899 899 + CONFIG_USB_PRINTER=m 900 900 + CONFIG_USB_STORAGE=m 901 901 + CONFIG_USB_STORAGE_REALTEK=m 902 902 + CONFIG_USB_UAS=m 903 903 + CONFIG_USB_DWC2=y 904 904 + CONFIG_USB_DWC2_HOST=y 905 905 + CONFIG_USB_SERIAL=m 906 906 + CONFIG_USB_SERIAL_CH341=m 907 907 + CONFIG_USB_SERIAL_CP210X=m 908 908 + CONFIG_USB_SERIAL_FTDI_SIO=m 909 909 + CONFIG_USB_SERIAL_PL2303=m 910 910 + CONFIG_USB_SERIAL_OPTION=m 911 911 + CONFIG_USB_GADGET=y 912 912 + CONFIG_TYPEC=m 913 913 + CONFIG_TYPEC_TCPM=m 914 914 + CONFIG_TYPEC_TCPCI=m 915 915 + CONFIG_TYPEC_UCSI=m 916 916 + CONFIG_UCSI_ACPI=m 917 917 + CONFIG_MMC=y 918 918 + CONFIG_MMC_LOONGSON2=m 919 919 + CONFIG_INFINIBAND=m 920 920 + CONFIG_EDAC=y 921 921 + CONFIG_EDAC_LOONGSON=y 922 922 + CONFIG_RTC_CLASS=y 923 923 + CONFIG_RTC_DRV_EFI=y 924 924 + CONFIG_RTC_DRV_LOONGSON=y 925 925 + CONFIG_DMADEVICES=y 926 926 + CONFIG_LOONGSON2_APB_DMA=y 927 927 + CONFIG_UDMABUF=y 928 928 + CONFIG_DMABUF_HEAPS=y 929 929 + CONFIG_DMABUF_HEAPS_SYSTEM=y 930 930 + CONFIG_DMABUF_HEAPS_CMA=y 931 931 + CONFIG_UIO=m 932 932 + CONFIG_UIO_PDRV_GENIRQ=m 933 933 + CONFIG_UIO_DMEM_GENIRQ=m 934 934 + CONFIG_UIO_PCI_GENERIC=m 935 935 + CONFIG_VFIO=m 936 936 + CONFIG_VFIO_PCI=m 937 937 + CONFIG_VIRTIO_PCI=y 938 938 + CONFIG_VIRTIO_BALLOON=m 939 939 + CONFIG_VIRTIO_INPUT=m 940 940 + CONFIG_VIRTIO_MMIO=m 941 941 + CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y 942 942 + CONFIG_VHOST_NET=m 943 943 + CONFIG_VHOST_SCSI=m 944 944 + CONFIG_VHOST_VSOCK=m 945 945 + CONFIG_COMEDI=m 946 946 + CONFIG_COMEDI_PCI_DRIVERS=m 947 947 + CONFIG_COMEDI_8255_PCI=m 948 948 + CONFIG_COMEDI_ADL_PCI6208=m 949 949 + CONFIG_COMEDI_ADL_PCI7X3X=m 950 950 + CONFIG_COMEDI_ADL_PCI8164=m 951 951 + CONFIG_COMEDI_ADL_PCI9111=m 952 952 + CONFIG_COMEDI_ADL_PCI9118=m 953 953 + CONFIG_COMEDI_ADV_PCI1710=m 954 954 + CONFIG_COMEDI_ADV_PCI1720=m 955 955 + CONFIG_COMEDI_ADV_PCI1723=m 956 956 + CONFIG_COMEDI_ADV_PCI1724=m 957 957 + CONFIG_COMEDI_ADV_PCI1760=m 958 958 + CONFIG_COMEDI_ADV_PCI_DIO=m 959 959 + CONFIG_COMEDI_NI_LABPC_PCI=m 960 960 + CONFIG_COMEDI_NI_PCIDIO=m 961 961 + CONFIG_COMEDI_NI_PCIMIO=m 962 962 + CONFIG_STAGING=y 963 963 + CONFIG_COMMON_CLK_LOONGSON2=y 964 964 + CONFIG_LOONGSON2_GUTS=y 965 965 + CONFIG_LOONGSON2_PM=y 966 966 + CONFIG_PM_DEVFREQ=y 967 967 + CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y 968 968 + CONFIG_DEVFREQ_GOV_PERFORMANCE=y 969 969 + CONFIG_DEVFREQ_GOV_POWERSAVE=y 970 970 + CONFIG_DEVFREQ_GOV_USERSPACE=y 971 971 + CONFIG_NTB=m 972 972 + CONFIG_NTB_MSI=y 973 973 + CONFIG_NTB_IDT=m 974 974 + CONFIG_NTB_EPF=m 975 975 + CONFIG_NTB_SWITCHTEC=m 976 976 + CONFIG_NTB_PERF=m 977 977 + CONFIG_NTB_TRANSPORT=m 978 978 + CONFIG_PWM=y 979 979 + CONFIG_PWM_LOONGSON=y 980 980 + CONFIG_GENERIC_PHY=y 981 981 + CONFIG_USB4=y 982 982 + CONFIG_EXT2_FS=y 983 983 + CONFIG_EXT2_FS_XATTR=y 984 984 + CONFIG_EXT2_FS_POSIX_ACL=y 985 985 + CONFIG_EXT2_FS_SECURITY=y 986 986 + CONFIG_EXT4_FS=y 987 987 + CONFIG_EXT4_FS_POSIX_ACL=y 988 988 + CONFIG_EXT4_FS_SECURITY=y 989 989 + CONFIG_JFS_FS=m 990 990 + CONFIG_JFS_POSIX_ACL=y 991 991 + CONFIG_JFS_SECURITY=y 992 992 + CONFIG_XFS_FS=y 993 993 + CONFIG_XFS_SUPPORT_V4=y 994 994 + CONFIG_XFS_SUPPORT_ASCII_CI=y 995 995 + CONFIG_XFS_QUOTA=y 996 996 + CONFIG_XFS_POSIX_ACL=y 997 997 + CONFIG_GFS2_FS=m 998 998 + CONFIG_GFS2_FS_LOCKING_DLM=y 999 999 + CONFIG_OCFS2_FS=m 1000 1000 + CONFIG_BTRFS_FS=y 1001 1001 + CONFIG_BTRFS_FS_POSIX_ACL=y 1002 1002 + CONFIG_F2FS_FS=m 1003 1003 + CONFIG_F2FS_FS_SECURITY=y 1004 1004 + CONFIG_F2FS_CHECK_FS=y 1005 1005 + CONFIG_F2FS_FS_COMPRESSION=y 1006 1006 + CONFIG_FS_ENCRYPTION=y 1007 1007 + CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y 1008 1008 + CONFIG_FS_VERITY=y 1009 1009 + CONFIG_FANOTIFY=y 1010 1010 + CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y 1011 1011 + CONFIG_QUOTA=y 1012 1012 + # CONFIG_PRINT_QUOTA_WARNING is not set 1013 1013 + CONFIG_QFMT_V1=m 1014 1014 + CONFIG_QFMT_V2=m 1015 1015 + CONFIG_AUTOFS_FS=y 1016 1016 + CONFIG_FUSE_FS=m 1017 1017 + CONFIG_CUSE=m 1018 1018 + CONFIG_VIRTIO_FS=m 1019 1019 + CONFIG_OVERLAY_FS=y 1020 1020 + CONFIG_OVERLAY_FS_INDEX=y 1021 1021 + CONFIG_OVERLAY_FS_XINO_AUTO=y 1022 1022 + CONFIG_OVERLAY_FS_METACOPY=y 1023 1023 + CONFIG_FSCACHE=y 1024 1024 + CONFIG_CACHEFILES=m 1025 1025 + CONFIG_ISO9660_FS=y 1026 1026 + CONFIG_JOLIET=y 1027 1027 + CONFIG_ZISOFS=y 1028 1028 + CONFIG_UDF_FS=y 1029 1029 + CONFIG_MSDOS_FS=m 1030 1030 + CONFIG_VFAT_FS=m 1031 1031 + CONFIG_FAT_DEFAULT_CODEPAGE=936 1032 1032 + CONFIG_FAT_DEFAULT_IOCHARSET="gb2312" 1033 1033 + CONFIG_EXFAT_FS=m 1034 1034 + CONFIG_NTFS3_FS=m 1035 1035 + CONFIG_NTFS3_64BIT_CLUSTER=y 1036 1036 + CONFIG_NTFS3_LZX_XPRESS=y 1037 1037 + CONFIG_PROC_KCORE=y 1038 1038 + CONFIG_TMPFS=y 1039 1039 + CONFIG_TMPFS_POSIX_ACL=y 1040 1040 + CONFIG_HUGETLBFS=y 1041 1041 + CONFIG_CONFIGFS_FS=y 1042 1042 + CONFIG_ORANGEFS_FS=m 1043 1043 + CONFIG_ECRYPT_FS=m 1044 1044 + CONFIG_ECRYPT_FS_MESSAGING=y 1045 1045 + CONFIG_HFS_FS=m 1046 1046 + CONFIG_HFSPLUS_FS=m 1047 1047 + CONFIG_UBIFS_FS=m 1048 1048 + CONFIG_UBIFS_FS_ADVANCED_COMPR=y 1049 1049 + CONFIG_CRAMFS=m 1050 1050 + CONFIG_SQUASHFS=y 1051 1051 + CONFIG_SQUASHFS_FILE_DIRECT=y 1052 1052 + CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y 1053 1053 + CONFIG_SQUASHFS_XATTR=y 1054 1054 + CONFIG_SQUASHFS_LZ4=y 1055 1055 + CONFIG_SQUASHFS_LZO=y 1056 1056 + CONFIG_SQUASHFS_XZ=y 1057 1057 + CONFIG_SQUASHFS_ZSTD=y 1058 1058 + CONFIG_MINIX_FS=m 1059 1059 + CONFIG_ROMFS_FS=m 1060 1060 + CONFIG_PSTORE=m 1061 1061 + CONFIG_PSTORE_COMPRESS=y 1062 1062 + CONFIG_UFS_FS=m 1063 1063 + CONFIG_EROFS_FS=m 1064 1064 + CONFIG_EROFS_FS_ZIP_LZMA=y 1065 1065 + CONFIG_EROFS_FS_ZIP_DEFLATE=y 1066 1066 + CONFIG_EROFS_FS_ZIP_ZSTD=y 1067 1067 + CONFIG_EROFS_FS_ONDEMAND=y 1068 1068 + CONFIG_EROFS_FS_PCPU_KTHREAD=y 1069 1069 + CONFIG_NFS_FS=y 1070 1070 + CONFIG_NFS_V3_ACL=y 1071 1071 + CONFIG_NFS_V4=y 1072 1072 + CONFIG_NFS_V4_1=y 1073 1073 + CONFIG_NFS_V4_2=y 1074 1074 + CONFIG_ROOT_NFS=y 1075 1075 + CONFIG_NFSD=y 1076 1076 + CONFIG_NFSD_V3_ACL=y 1077 1077 + CONFIG_NFSD_V4=y 1078 1078 + CONFIG_NFSD_BLOCKLAYOUT=y 1079 1079 + CONFIG_CEPH_FS=m 1080 1080 + CONFIG_CEPH_FSCACHE=y 1081 1081 + CONFIG_CEPH_FS_POSIX_ACL=y 1082 1082 + CONFIG_CEPH_FS_SECURITY_LABEL=y 1083 1083 + CONFIG_CIFS=m 1084 1084 + # CONFIG_CIFS_DEBUG is not set 1085 1085 + CONFIG_9P_FS=y 1086 1086 + CONFIG_NLS_DEFAULT="utf8" 1087 1087 + CONFIG_NLS_CODEPAGE_437=y 1088 1088 + CONFIG_NLS_CODEPAGE_936=y 1089 1089 + CONFIG_NLS_CODEPAGE_950=y 1090 1090 + CONFIG_NLS_ASCII=y 1091 1091 + CONFIG_NLS_ISO8859_1=y 1092 1092 + CONFIG_NLS_UTF8=y 1093 1093 + CONFIG_DLM=m 1094 1094 + CONFIG_KEY_DH_OPERATIONS=y 1095 1095 + CONFIG_SECURITY=y 1096 1096 + CONFIG_SECURITY_SELINUX=y 1097 1097 + CONFIG_SECURITY_SELINUX_BOOTPARAM=y 1098 1098 + CONFIG_SECURITY_APPARMOR=y 1099 1099 + CONFIG_SECURITY_YAMA=y 1100 1100 + CONFIG_DEFAULT_SECURITY_DAC=y 1101 1101 + CONFIG_CRYPTO_USER=m 1102 1102 + CONFIG_CRYPTO_SELFTESTS=y 1103 1103 + CONFIG_CRYPTO_PCRYPT=m 1104 1104 + CONFIG_CRYPTO_CRYPTD=m 1105 1105 + CONFIG_CRYPTO_ANUBIS=m 1106 1106 + CONFIG_CRYPTO_BLOWFISH=m 1107 1107 + CONFIG_CRYPTO_CAST5=m 1108 1108 + CONFIG_CRYPTO_CAST6=m 1109 1109 + CONFIG_CRYPTO_KHAZAD=m 1110 1110 + CONFIG_CRYPTO_SEED=m 1111 1111 + CONFIG_CRYPTO_SERPENT=m 1112 1112 + CONFIG_CRYPTO_SM4_GENERIC=m 1113 1113 + CONFIG_CRYPTO_TEA=m 1114 1114 + CONFIG_CRYPTO_TWOFISH=m 1115 1115 + CONFIG_CRYPTO_CHACHA20POLY1305=m 1116 1116 + CONFIG_CRYPTO_SM3_GENERIC=m 1117 1117 + CONFIG_CRYPTO_WP512=m 1118 1118 + CONFIG_CRYPTO_DEFLATE=m 1119 1119 + CONFIG_CRYPTO_LZO=m 1120 1120 + CONFIG_CRYPTO_842=m 1121 1121 + CONFIG_CRYPTO_LZ4=m 1122 1122 + CONFIG_CRYPTO_LZ4HC=m 1123 1123 + CONFIG_CRYPTO_USER_API_HASH=m 1124 1124 + CONFIG_CRYPTO_USER_API_SKCIPHER=m 1125 1125 + CONFIG_CRYPTO_USER_API_RNG=m 1126 1126 + CONFIG_CRYPTO_USER_API_AEAD=m 1127 1127 + CONFIG_CRYPTO_DEV_VIRTIO=m 1128 1128 + CONFIG_CRYPTO_DEV_LOONGSON_RNG=m 1129 1129 + CONFIG_DMA_CMA=y 1130 1130 + CONFIG_DMA_NUMA_CMA=y 1131 1131 + CONFIG_CMA_SIZE_MBYTES=0 1132 1132 + CONFIG_PRINTK_TIME=y 1133 1133 + CONFIG_STRIP_ASM_SYMS=y 1134 1134 + CONFIG_MAGIC_SYSRQ=y 1135 1135 + CONFIG_DEBUG_FS=y 1136 1136 + # CONFIG_SCHED_DEBUG is not set 1137 1137 + CONFIG_SCHEDSTATS=y 1138 1138 + # CONFIG_DEBUG_PREEMPT is not set 1139 1139 + # CONFIG_FTRACE is not set 1140 1140 + CONFIG_UNWINDER_ORC=y

+1

arch/loongarch/include/asm/Kbuild

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 + syscall-y += syscall_table_32.h 2 3 syscall-y += syscall_table_64.h 3 4 generated-y += orc_hash.h 4 5

+14 -1

arch/loongarch/include/asm/addrspace.h

reviewed

··· 38 38 #endif 39 39 40 40 #ifndef WRITECOMBINE_BASE 41 41 + #ifdef CONFIG_32BIT 42 42 + #define WRITECOMBINE_BASE CSR_DMW0_BASE 43 43 + #else 41 44 #define WRITECOMBINE_BASE CSR_DMW2_BASE 42 45 #endif 46 46 + #endif 43 47 48 48 + #ifdef CONFIG_32BIT 49 49 + #define DMW_PABITS 29 50 50 + #define TO_PHYS_MASK ((_UL(1) << _UL(DMW_PABITS)) - 1) 51 51 + #else 44 52 #define DMW_PABITS 48 45 45 - #define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1) 53 53 + #define TO_PHYS_MASK ((_ULL(1) << _ULL(DMW_PABITS)) - 1) 54 54 + #endif 46 55 47 56 /* 48 57 * Memory above this physical address will be considered highmem. ··· 121 112 /* 122 113 * Returns the physical address of a KPRANGEx / XKPRANGE address 123 114 */ 115 115 + #ifdef CONFIG_32BIT 116 116 + #define PHYSADDR(a) ((_ACAST32_(a)) & TO_PHYS_MASK) 117 117 + #else 124 118 #define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK) 119 119 + #endif 125 120 126 121 /* 127 122 * On LoongArch, I/O ports mappring is following:

+57 -20

arch/loongarch/include/asm/asm.h

reviewed

··· 72 72 #define INT_SUB sub.w 73 73 #define INT_L ld.w 74 74 #define INT_S st.w 75 75 - #define INT_SLL slli.w 75 75 + #define INT_SLLI slli.w 76 76 #define INT_SLLV sll.w 77 77 - #define INT_SRL srli.w 77 77 + #define INT_SRLI srli.w 78 78 #define INT_SRLV srl.w 79 79 - #define INT_SRA srai.w 79 79 + #define INT_SRAI srai.w 80 80 #define INT_SRAV sra.w 81 81 #endif 82 82 ··· 86 86 #define INT_SUB sub.d 87 87 #define INT_L ld.d 88 88 #define INT_S st.d 89 89 - #define INT_SLL slli.d 89 89 + #define INT_SLLI slli.d 90 90 #define INT_SLLV sll.d 91 91 - #define INT_SRL srli.d 91 91 + #define INT_SRLI srli.d 92 92 #define INT_SRLV srl.d 93 93 - #define INT_SRA srai.d 93 93 + #define INT_SRAI srai.d 94 94 #define INT_SRAV sra.d 95 95 #endif 96 96 ··· 100 100 #if (__SIZEOF_LONG__ == 4) 101 101 #define LONG_ADD add.w 102 102 #define LONG_ADDI addi.w 103 103 + #define LONG_ALSL alsl.w 104 104 + #define LONG_BSTRINS bstrins.w 105 105 + #define LONG_BSTRPICK bstrpick.w 103 106 #define LONG_SUB sub.w 104 107 #define LONG_L ld.w 108 108 + #define LONG_LI li.w 109 109 + #define LONG_LPTR ld.w 105 110 #define LONG_S st.w 106 106 - #define LONG_SLL slli.w 111 111 + #define LONG_SPTR st.w 112 112 + #define LONG_SLLI slli.w 107 113 #define LONG_SLLV sll.w 108 108 - #define LONG_SRL srli.w 114 114 + #define LONG_SRLI srli.w 109 115 #define LONG_SRLV srl.w 110 110 - #define LONG_SRA srai.w 116 116 + #define LONG_SRAI srai.w 111 117 #define LONG_SRAV sra.w 118 118 + #define LONG_ROTR rotr.w 119 119 + #define LONG_ROTRI rotri.w 112 120 113 121 #ifdef __ASSEMBLER__ 114 122 #define LONG .word ··· 129 121 #if (__SIZEOF_LONG__ == 8) 130 122 #define LONG_ADD add.d 131 123 #define LONG_ADDI addi.d 124 124 + #define LONG_ALSL alsl.d 125 125 + #define LONG_BSTRINS bstrins.d 126 126 + #define LONG_BSTRPICK bstrpick.d 132 127 #define LONG_SUB sub.d 133 128 #define LONG_L ld.d 129 129 + #define LONG_LI li.d 130 130 + #define LONG_LPTR ldptr.d 134 131 #define LONG_S st.d 135 135 - #define LONG_SLL slli.d 132 132 + #define LONG_SPTR stptr.d 133 133 + #define LONG_SLLI slli.d 136 134 #define LONG_SLLV sll.d 137 137 - #define LONG_SRL srli.d 135 135 + #define LONG_SRLI srli.d 138 136 #define LONG_SRLV srl.d 139 139 - #define LONG_SRA srai.d 137 137 + #define LONG_SRAI srai.d 140 138 #define LONG_SRAV sra.d 139 139 + #define LONG_ROTR rotr.d 140 140 + #define LONG_ROTRI rotri.d 141 141 142 142 #ifdef __ASSEMBLER__ 143 143 #define LONG .dword ··· 161 145 #if (__SIZEOF_POINTER__ == 4) 162 146 #define PTR_ADD add.w 163 147 #define PTR_ADDI addi.w 148 148 + #define PTR_ALSL alsl.w 149 149 + #define PTR_BSTRINS bstrins.w 150 150 + #define PTR_BSTRPICK bstrpick.w 164 151 #define PTR_SUB sub.w 165 152 #define PTR_L ld.w 166 166 - #define PTR_S st.w 167 153 #define PTR_LI li.w 168 168 - #define PTR_SLL slli.w 154 154 + #define PTR_LPTR ld.w 155 155 + #define PTR_S st.w 156 156 + #define PTR_SPTR st.w 157 157 + #define PTR_SLLI slli.w 169 158 #define PTR_SLLV sll.w 170 170 - #define PTR_SRL srli.w 159 159 + #define PTR_SRLI srli.w 171 160 #define PTR_SRLV srl.w 172 172 - #define PTR_SRA srai.w 161 161 + #define PTR_SRAI srai.w 173 162 #define PTR_SRAV sra.w 163 163 + #define PTR_ROTR rotr.w 164 164 + #define PTR_ROTRI rotri.w 174 165 175 166 #define PTR_SCALESHIFT 2 176 167 ··· 191 168 #if (__SIZEOF_POINTER__ == 8) 192 169 #define PTR_ADD add.d 193 170 #define PTR_ADDI addi.d 171 171 + #define PTR_ALSL alsl.d 172 172 + #define PTR_BSTRINS bstrins.d 173 173 + #define PTR_BSTRPICK bstrpick.d 194 174 #define PTR_SUB sub.d 195 175 #define PTR_L ld.d 196 196 - #define PTR_S st.d 197 176 #define PTR_LI li.d 198 198 - #define PTR_SLL slli.d 177 177 + #define PTR_LPTR ldptr.d 178 178 + #define PTR_S st.d 179 179 + #define PTR_SPTR stptr.d 180 180 + #define PTR_SLLI slli.d 199 181 #define PTR_SLLV sll.d 200 200 - #define PTR_SRL srli.d 182 182 + #define PTR_SRLI srli.d 201 183 #define PTR_SRLV srl.d 202 202 - #define PTR_SRA srai.d 184 184 + #define PTR_SRAI srai.d 203 185 #define PTR_SRAV sra.d 186 186 + #define PTR_ROTR rotr.d 187 187 + #define PTR_ROTRI rotri.d 204 188 205 189 #define PTR_SCALESHIFT 3 206 190 ··· 220 190 221 191 /* Annotate a function as being unsuitable for kprobes. */ 222 192 #ifdef CONFIG_KPROBES 193 193 + #ifdef CONFIG_32BIT 194 194 + #define _ASM_NOKPROBE(name) \ 195 195 + .pushsection "_kprobe_blacklist", "aw"; \ 196 196 + .long name; \ 197 197 + .popsection 198 198 + #else 223 199 #define _ASM_NOKPROBE(name) \ 224 200 .pushsection "_kprobe_blacklist", "aw"; \ 225 201 .quad name; \ 226 202 .popsection 203 203 + #endif 227 204 #else 228 205 #define _ASM_NOKPROBE(name) 229 206 #endif

+90 -28

arch/loongarch/include/asm/asmmacro.h

reviewed

··· 5 5 #ifndef _ASM_ASMMACRO_H 6 6 #define _ASM_ASMMACRO_H 7 7 8 8 + #include <linux/sizes.h> 8 9 #include <asm/asm-offsets.h> 9 10 #include <asm/regdef.h> 10 11 #include <asm/fpregdef.h> 11 12 #include <asm/loongarch.h> 12 13 14 14 + #ifdef CONFIG_64BIT 15 15 + #define TASK_STRUCT_OFFSET 0 16 16 + #else 17 17 + #define TASK_STRUCT_OFFSET 2000 18 18 + #endif 19 19 + 13 20 .macro cpu_save_nonscratch thread 14 14 - stptr.d s0, \thread, THREAD_REG23 15 15 - stptr.d s1, \thread, THREAD_REG24 16 16 - stptr.d s2, \thread, THREAD_REG25 17 17 - stptr.d s3, \thread, THREAD_REG26 18 18 - stptr.d s4, \thread, THREAD_REG27 19 19 - stptr.d s5, \thread, THREAD_REG28 20 20 - stptr.d s6, \thread, THREAD_REG29 21 21 - stptr.d s7, \thread, THREAD_REG30 22 22 - stptr.d s8, \thread, THREAD_REG31 23 23 - stptr.d sp, \thread, THREAD_REG03 24 24 - stptr.d fp, \thread, THREAD_REG22 21 21 + LONG_SPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET) 22 22 + LONG_SPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET) 23 23 + LONG_SPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET) 24 24 + LONG_SPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET) 25 25 + LONG_SPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET) 26 26 + LONG_SPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET) 27 27 + LONG_SPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET) 28 28 + LONG_SPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET) 29 29 + LONG_SPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET) 30 30 + LONG_SPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET) 31 31 + LONG_SPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET) 32 32 + LONG_SPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET) 25 33 .endm 26 34 27 35 .macro cpu_restore_nonscratch thread 28 28 - ldptr.d s0, \thread, THREAD_REG23 29 29 - ldptr.d s1, \thread, THREAD_REG24 30 30 - ldptr.d s2, \thread, THREAD_REG25 31 31 - ldptr.d s3, \thread, THREAD_REG26 32 32 - ldptr.d s4, \thread, THREAD_REG27 33 33 - ldptr.d s5, \thread, THREAD_REG28 34 34 - ldptr.d s6, \thread, THREAD_REG29 35 35 - ldptr.d s7, \thread, THREAD_REG30 36 36 - ldptr.d s8, \thread, THREAD_REG31 37 37 - ldptr.d ra, \thread, THREAD_REG01 38 38 - ldptr.d sp, \thread, THREAD_REG03 39 39 - ldptr.d fp, \thread, THREAD_REG22 36 36 + LONG_LPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET) 37 37 + LONG_LPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET) 38 38 + LONG_LPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET) 39 39 + LONG_LPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET) 40 40 + LONG_LPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET) 41 41 + LONG_LPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET) 42 42 + LONG_LPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET) 43 43 + LONG_LPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET) 44 44 + LONG_LPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET) 45 45 + LONG_LPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET) 46 46 + LONG_LPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET) 47 47 + LONG_LPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET) 40 48 .endm 41 49 42 50 .macro fpu_save_csr thread tmp 43 51 movfcsr2gr \tmp, fcsr0 52 52 + #ifdef CONFIG_32BIT 53 53 + st.w \tmp, \thread, THREAD_FCSR 54 54 + #else 44 55 stptr.w \tmp, \thread, THREAD_FCSR 56 56 + #endif 45 57 #ifdef CONFIG_CPU_HAS_LBT 46 58 /* TM bit is always 0 if LBT not supported */ 47 59 andi \tmp, \tmp, FPU_CSR_TM ··· 68 56 .endm 69 57 70 58 .macro fpu_restore_csr thread tmp0 tmp1 59 59 + #ifdef CONFIG_32BIT 60 60 + ld.w \tmp0, \thread, THREAD_FCSR 61 61 + #else 71 62 ldptr.w \tmp0, \thread, THREAD_FCSR 63 63 + #endif 72 64 movgr2fcsr fcsr0, \tmp0 73 65 #ifdef CONFIG_CPU_HAS_LBT 74 66 /* TM bit is always 0 if LBT not supported */ ··· 104 88 #endif 105 89 .endm 106 90 91 91 + #ifdef CONFIG_32BIT 107 92 .macro fpu_save_cc thread tmp0 tmp1 108 93 movcf2gr \tmp0, $fcc0 109 109 - move \tmp1, \tmp0 94 94 + move \tmp1, \tmp0 95 95 + movcf2gr \tmp0, $fcc1 96 96 + bstrins.w \tmp1, \tmp0, 15, 8 97 97 + movcf2gr \tmp0, $fcc2 98 98 + bstrins.w \tmp1, \tmp0, 23, 16 99 99 + movcf2gr \tmp0, $fcc3 100 100 + bstrins.w \tmp1, \tmp0, 31, 24 101 101 + st.w \tmp1, \thread, THREAD_FCC 102 102 + movcf2gr \tmp0, $fcc4 103 103 + move \tmp1, \tmp0 104 104 + movcf2gr \tmp0, $fcc5 105 105 + bstrins.w \tmp1, \tmp0, 15, 8 106 106 + movcf2gr \tmp0, $fcc6 107 107 + bstrins.w \tmp1, \tmp0, 23, 16 108 108 + movcf2gr \tmp0, $fcc7 109 109 + bstrins.w \tmp1, \tmp0, 31, 24 110 110 + st.w \tmp1, \thread, (THREAD_FCC + 4) 111 111 + .endm 112 112 + 113 113 + .macro fpu_restore_cc thread tmp0 tmp1 114 114 + ld.w \tmp0, \thread, THREAD_FCC 115 115 + bstrpick.w \tmp1, \tmp0, 7, 0 116 116 + movgr2cf $fcc0, \tmp1 117 117 + bstrpick.w \tmp1, \tmp0, 15, 8 118 118 + movgr2cf $fcc1, \tmp1 119 119 + bstrpick.w \tmp1, \tmp0, 23, 16 120 120 + movgr2cf $fcc2, \tmp1 121 121 + bstrpick.w \tmp1, \tmp0, 31, 24 122 122 + movgr2cf $fcc3, \tmp1 123 123 + ld.w \tmp0, \thread, (THREAD_FCC + 4) 124 124 + bstrpick.w \tmp1, \tmp0, 7, 0 125 125 + movgr2cf $fcc4, \tmp1 126 126 + bstrpick.w \tmp1, \tmp0, 15, 8 127 127 + movgr2cf $fcc5, \tmp1 128 128 + bstrpick.w \tmp1, \tmp0, 23, 16 129 129 + movgr2cf $fcc6, \tmp1 130 130 + bstrpick.w \tmp1, \tmp0, 31, 24 131 131 + movgr2cf $fcc7, \tmp1 132 132 + .endm 133 133 + #else 134 134 + .macro fpu_save_cc thread tmp0 tmp1 135 135 + movcf2gr \tmp0, $fcc0 136 136 + move \tmp1, \tmp0 110 137 movcf2gr \tmp0, $fcc1 111 138 bstrins.d \tmp1, \tmp0, 15, 8 112 139 movcf2gr \tmp0, $fcc2 ··· 168 109 .endm 169 110 170 111 .macro fpu_restore_cc thread tmp0 tmp1 171 171 - ldptr.d \tmp0, \thread, THREAD_FCC 112 112 + ldptr.d \tmp0, \thread, THREAD_FCC 172 113 bstrpick.d \tmp1, \tmp0, 7, 0 173 114 movgr2cf $fcc0, \tmp1 174 115 bstrpick.d \tmp1, \tmp0, 15, 8 ··· 186 127 bstrpick.d \tmp1, \tmp0, 63, 56 187 128 movgr2cf $fcc7, \tmp1 188 129 .endm 130 130 + #endif 189 131 190 132 .macro fpu_save_double thread tmp 191 133 li.w \tmp, THREAD_FPR0 ··· 666 606 766: 667 607 lu12i.w \reg, 0 668 608 ori \reg, \reg, 0 609 609 + #ifdef CONFIG_64BIT 669 610 lu32i.d \reg, 0 670 611 lu52i.d \reg, \reg, 0 612 612 + #endif 671 613 .pushsection ".la_abs", "aw", %progbits 672 672 - .p2align 3 673 673 - .dword 766b 674 674 - .dword \sym 614 614 + .p2align PTRLOG 615 615 + PTR 766b 616 616 + PTR \sym 675 617 .popsection 676 618 #endif 677 619 .endm

+206

arch/loongarch/include/asm/atomic-amo.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Atomic operations (AMO). 4 4 + * 5 5 + * Copyright (C) 2020-2025 Loongson Technology Corporation Limited 6 6 + */ 7 7 + 8 8 + #ifndef _ASM_ATOMIC_AMO_H 9 9 + #define _ASM_ATOMIC_AMO_H 10 10 + 11 11 + #include <linux/types.h> 12 12 + #include <asm/barrier.h> 13 13 + #include <asm/cmpxchg.h> 14 14 + 15 15 + #define ATOMIC_OP(op, I, asm_op) \ 16 16 + static inline void arch_atomic_##op(int i, atomic_t *v) \ 17 17 + { \ 18 18 + __asm__ __volatile__( \ 19 19 + "am"#asm_op".w" " $zero, %1, %0 \n" \ 20 20 + : "+ZB" (v->counter) \ 21 21 + : "r" (I) \ 22 22 + : "memory"); \ 23 23 + } 24 24 + 25 25 + #define ATOMIC_OP_RETURN(op, I, asm_op, c_op, mb, suffix) \ 26 26 + static inline int arch_atomic_##op##_return##suffix(int i, atomic_t *v) \ 27 27 + { \ 28 28 + int result; \ 29 29 + \ 30 30 + __asm__ __volatile__( \ 31 31 + "am"#asm_op#mb".w" " %1, %2, %0 \n" \ 32 32 + : "+ZB" (v->counter), "=&r" (result) \ 33 33 + : "r" (I) \ 34 34 + : "memory"); \ 35 35 + \ 36 36 + return result c_op I; \ 37 37 + } 38 38 + 39 39 + #define ATOMIC_FETCH_OP(op, I, asm_op, mb, suffix) \ 40 40 + static inline int arch_atomic_fetch_##op##suffix(int i, atomic_t *v) \ 41 41 + { \ 42 42 + int result; \ 43 43 + \ 44 44 + __asm__ __volatile__( \ 45 45 + "am"#asm_op#mb".w" " %1, %2, %0 \n" \ 46 46 + : "+ZB" (v->counter), "=&r" (result) \ 47 47 + : "r" (I) \ 48 48 + : "memory"); \ 49 49 + \ 50 50 + return result; \ 51 51 + } 52 52 + 53 53 + #define ATOMIC_OPS(op, I, asm_op, c_op) \ 54 54 + ATOMIC_OP(op, I, asm_op) \ 55 55 + ATOMIC_OP_RETURN(op, I, asm_op, c_op, _db, ) \ 56 56 + ATOMIC_OP_RETURN(op, I, asm_op, c_op, , _relaxed) \ 57 57 + ATOMIC_FETCH_OP(op, I, asm_op, _db, ) \ 58 58 + ATOMIC_FETCH_OP(op, I, asm_op, , _relaxed) 59 59 + 60 60 + ATOMIC_OPS(add, i, add, +) 61 61 + ATOMIC_OPS(sub, -i, add, +) 62 62 + 63 63 + #define arch_atomic_add_return arch_atomic_add_return 64 64 + #define arch_atomic_add_return_acquire arch_atomic_add_return 65 65 + #define arch_atomic_add_return_release arch_atomic_add_return 66 66 + #define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed 67 67 + #define arch_atomic_sub_return arch_atomic_sub_return 68 68 + #define arch_atomic_sub_return_acquire arch_atomic_sub_return 69 69 + #define arch_atomic_sub_return_release arch_atomic_sub_return 70 70 + #define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed 71 71 + #define arch_atomic_fetch_add arch_atomic_fetch_add 72 72 + #define arch_atomic_fetch_add_acquire arch_atomic_fetch_add 73 73 + #define arch_atomic_fetch_add_release arch_atomic_fetch_add 74 74 + #define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed 75 75 + #define arch_atomic_fetch_sub arch_atomic_fetch_sub 76 76 + #define arch_atomic_fetch_sub_acquire arch_atomic_fetch_sub 77 77 + #define arch_atomic_fetch_sub_release arch_atomic_fetch_sub 78 78 + #define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed 79 79 + 80 80 + #undef ATOMIC_OPS 81 81 + 82 82 + #define ATOMIC_OPS(op, I, asm_op) \ 83 83 + ATOMIC_OP(op, I, asm_op) \ 84 84 + ATOMIC_FETCH_OP(op, I, asm_op, _db, ) \ 85 85 + ATOMIC_FETCH_OP(op, I, asm_op, , _relaxed) 86 86 + 87 87 + ATOMIC_OPS(and, i, and) 88 88 + ATOMIC_OPS(or, i, or) 89 89 + ATOMIC_OPS(xor, i, xor) 90 90 + 91 91 + #define arch_atomic_fetch_and arch_atomic_fetch_and 92 92 + #define arch_atomic_fetch_and_acquire arch_atomic_fetch_and 93 93 + #define arch_atomic_fetch_and_release arch_atomic_fetch_and 94 94 + #define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed 95 95 + #define arch_atomic_fetch_or arch_atomic_fetch_or 96 96 + #define arch_atomic_fetch_or_acquire arch_atomic_fetch_or 97 97 + #define arch_atomic_fetch_or_release arch_atomic_fetch_or 98 98 + #define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed 99 99 + #define arch_atomic_fetch_xor arch_atomic_fetch_xor 100 100 + #define arch_atomic_fetch_xor_acquire arch_atomic_fetch_xor 101 101 + #define arch_atomic_fetch_xor_release arch_atomic_fetch_xor 102 102 + #define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed 103 103 + 104 104 + #undef ATOMIC_OPS 105 105 + #undef ATOMIC_FETCH_OP 106 106 + #undef ATOMIC_OP_RETURN 107 107 + #undef ATOMIC_OP 108 108 + 109 109 + #ifdef CONFIG_64BIT 110 110 + 111 111 + #define ATOMIC64_OP(op, I, asm_op) \ 112 112 + static inline void arch_atomic64_##op(long i, atomic64_t *v) \ 113 113 + { \ 114 114 + __asm__ __volatile__( \ 115 115 + "am"#asm_op".d " " $zero, %1, %0 \n" \ 116 116 + : "+ZB" (v->counter) \ 117 117 + : "r" (I) \ 118 118 + : "memory"); \ 119 119 + } 120 120 + 121 121 + #define ATOMIC64_OP_RETURN(op, I, asm_op, c_op, mb, suffix) \ 122 122 + static inline long arch_atomic64_##op##_return##suffix(long i, atomic64_t *v) \ 123 123 + { \ 124 124 + long result; \ 125 125 + __asm__ __volatile__( \ 126 126 + "am"#asm_op#mb".d " " %1, %2, %0 \n" \ 127 127 + : "+ZB" (v->counter), "=&r" (result) \ 128 128 + : "r" (I) \ 129 129 + : "memory"); \ 130 130 + \ 131 131 + return result c_op I; \ 132 132 + } 133 133 + 134 134 + #define ATOMIC64_FETCH_OP(op, I, asm_op, mb, suffix) \ 135 135 + static inline long arch_atomic64_fetch_##op##suffix(long i, atomic64_t *v) \ 136 136 + { \ 137 137 + long result; \ 138 138 + \ 139 139 + __asm__ __volatile__( \ 140 140 + "am"#asm_op#mb".d " " %1, %2, %0 \n" \ 141 141 + : "+ZB" (v->counter), "=&r" (result) \ 142 142 + : "r" (I) \ 143 143 + : "memory"); \ 144 144 + \ 145 145 + return result; \ 146 146 + } 147 147 + 148 148 + #define ATOMIC64_OPS(op, I, asm_op, c_op) \ 149 149 + ATOMIC64_OP(op, I, asm_op) \ 150 150 + ATOMIC64_OP_RETURN(op, I, asm_op, c_op, _db, ) \ 151 151 + ATOMIC64_OP_RETURN(op, I, asm_op, c_op, , _relaxed) \ 152 152 + ATOMIC64_FETCH_OP(op, I, asm_op, _db, ) \ 153 153 + ATOMIC64_FETCH_OP(op, I, asm_op, , _relaxed) 154 154 + 155 155 + ATOMIC64_OPS(add, i, add, +) 156 156 + ATOMIC64_OPS(sub, -i, add, +) 157 157 + 158 158 + #define arch_atomic64_add_return arch_atomic64_add_return 159 159 + #define arch_atomic64_add_return_acquire arch_atomic64_add_return 160 160 + #define arch_atomic64_add_return_release arch_atomic64_add_return 161 161 + #define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed 162 162 + #define arch_atomic64_sub_return arch_atomic64_sub_return 163 163 + #define arch_atomic64_sub_return_acquire arch_atomic64_sub_return 164 164 + #define arch_atomic64_sub_return_release arch_atomic64_sub_return 165 165 + #define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed 166 166 + #define arch_atomic64_fetch_add arch_atomic64_fetch_add 167 167 + #define arch_atomic64_fetch_add_acquire arch_atomic64_fetch_add 168 168 + #define arch_atomic64_fetch_add_release arch_atomic64_fetch_add 169 169 + #define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed 170 170 + #define arch_atomic64_fetch_sub arch_atomic64_fetch_sub 171 171 + #define arch_atomic64_fetch_sub_acquire arch_atomic64_fetch_sub 172 172 + #define arch_atomic64_fetch_sub_release arch_atomic64_fetch_sub 173 173 + #define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed 174 174 + 175 175 + #undef ATOMIC64_OPS 176 176 + 177 177 + #define ATOMIC64_OPS(op, I, asm_op) \ 178 178 + ATOMIC64_OP(op, I, asm_op) \ 179 179 + ATOMIC64_FETCH_OP(op, I, asm_op, _db, ) \ 180 180 + ATOMIC64_FETCH_OP(op, I, asm_op, , _relaxed) 181 181 + 182 182 + ATOMIC64_OPS(and, i, and) 183 183 + ATOMIC64_OPS(or, i, or) 184 184 + ATOMIC64_OPS(xor, i, xor) 185 185 + 186 186 + #define arch_atomic64_fetch_and arch_atomic64_fetch_and 187 187 + #define arch_atomic64_fetch_and_acquire arch_atomic64_fetch_and 188 188 + #define arch_atomic64_fetch_and_release arch_atomic64_fetch_and 189 189 + #define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed 190 190 + #define arch_atomic64_fetch_or arch_atomic64_fetch_or 191 191 + #define arch_atomic64_fetch_or_acquire arch_atomic64_fetch_or 192 192 + #define arch_atomic64_fetch_or_release arch_atomic64_fetch_or 193 193 + #define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed 194 194 + #define arch_atomic64_fetch_xor arch_atomic64_fetch_xor 195 195 + #define arch_atomic64_fetch_xor_acquire arch_atomic64_fetch_xor 196 196 + #define arch_atomic64_fetch_xor_release arch_atomic64_fetch_xor 197 197 + #define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed 198 198 + 199 199 + #undef ATOMIC64_OPS 200 200 + #undef ATOMIC64_FETCH_OP 201 201 + #undef ATOMIC64_OP_RETURN 202 202 + #undef ATOMIC64_OP 203 203 + 204 204 + #endif 205 205 + 206 206 + #endif /* _ASM_ATOMIC_AMO_H */

+100

arch/loongarch/include/asm/atomic-llsc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Atomic operations (LLSC). 4 4 + * 5 5 + * Copyright (C) 2024-2025 Loongson Technology Corporation Limited 6 6 + */ 7 7 + 8 8 + #ifndef _ASM_ATOMIC_LLSC_H 9 9 + #define _ASM_ATOMIC_LLSC_H 10 10 + 11 11 + #include <linux/types.h> 12 12 + #include <asm/barrier.h> 13 13 + #include <asm/cmpxchg.h> 14 14 + 15 15 + #define ATOMIC_OP(op, I, asm_op) \ 16 16 + static inline void arch_atomic_##op(int i, atomic_t *v) \ 17 17 + { \ 18 18 + int temp; \ 19 19 + \ 20 20 + __asm__ __volatile__( \ 21 21 + "1: ll.w %0, %1 #atomic_" #op " \n" \ 22 22 + " " #asm_op " %0, %0, %2 \n" \ 23 23 + " sc.w %0, %1 \n" \ 24 24 + " beq %0, $r0, 1b \n" \ 25 25 + :"=&r" (temp) , "+ZC"(v->counter) \ 26 26 + :"r" (I) \ 27 27 + ); \ 28 28 + } 29 29 + 30 30 + #define ATOMIC_OP_RETURN(op, I, asm_op) \ 31 31 + static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \ 32 32 + { \ 33 33 + int result, temp; \ 34 34 + \ 35 35 + __asm__ __volatile__( \ 36 36 + "1: ll.w %1, %2 # atomic_" #op "_return \n" \ 37 37 + " " #asm_op " %0, %1, %3 \n" \ 38 38 + " sc.w %0, %2 \n" \ 39 39 + " beq %0, $r0 ,1b \n" \ 40 40 + " " #asm_op " %0, %1, %3 \n" \ 41 41 + : "=&r" (result), "=&r" (temp), "+ZC"(v->counter) \ 42 42 + : "r" (I)); \ 43 43 + \ 44 44 + return result; \ 45 45 + } 46 46 + 47 47 + #define ATOMIC_FETCH_OP(op, I, asm_op) \ 48 48 + static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \ 49 49 + { \ 50 50 + int result, temp; \ 51 51 + \ 52 52 + __asm__ __volatile__( \ 53 53 + "1: ll.w %1, %2 # atomic_fetch_" #op " \n" \ 54 54 + " " #asm_op " %0, %1, %3 \n" \ 55 55 + " sc.w %0, %2 \n" \ 56 56 + " beq %0, $r0 ,1b \n" \ 57 57 + " add.w %0, %1 ,$r0 \n" \ 58 58 + : "=&r" (result), "=&r" (temp), "+ZC" (v->counter) \ 59 59 + : "r" (I)); \ 60 60 + \ 61 61 + return result; \ 62 62 + } 63 63 + 64 64 + #define ATOMIC_OPS(op,I ,asm_op, c_op) \ 65 65 + ATOMIC_OP(op, I, asm_op) \ 66 66 + ATOMIC_OP_RETURN(op, I , asm_op) \ 67 67 + ATOMIC_FETCH_OP(op, I, asm_op) 68 68 + 69 69 + ATOMIC_OPS(add, i , add.w ,+=) 70 70 + ATOMIC_OPS(sub, -i , add.w ,+=) 71 71 + 72 72 + #define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed 73 73 + #define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed 74 74 + #define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed 75 75 + #define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed 76 76 + 77 77 + #undef ATOMIC_OPS 78 78 + 79 79 + #define ATOMIC_OPS(op, I, asm_op) \ 80 80 + ATOMIC_OP(op, I, asm_op) \ 81 81 + ATOMIC_FETCH_OP(op, I, asm_op) 82 82 + 83 83 + ATOMIC_OPS(and, i, and) 84 84 + ATOMIC_OPS(or, i, or) 85 85 + ATOMIC_OPS(xor, i, xor) 86 86 + 87 87 + #define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed 88 88 + #define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed 89 89 + #define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed 90 90 + 91 91 + #undef ATOMIC_OPS 92 92 + #undef ATOMIC_FETCH_OP 93 93 + #undef ATOMIC_OP_RETURN 94 94 + #undef ATOMIC_OP 95 95 + 96 96 + #ifdef CONFIG_64BIT 97 97 + #error "64-bit LLSC atomic operations are not supported" 98 98 + #endif 99 99 + 100 100 + #endif /* _ASM_ATOMIC_LLSC_H */

+10 -187

arch/loongarch/include/asm/atomic.h

reviewed

··· 11 11 #include <asm/barrier.h> 12 12 #include <asm/cmpxchg.h> 13 13 14 14 + #ifdef CONFIG_CPU_HAS_AMO 15 15 + #include <asm/atomic-amo.h> 16 16 + #else 17 17 + #include <asm/atomic-llsc.h> 18 18 + #endif 19 19 + 20 20 + #ifdef CONFIG_GENERIC_ATOMIC64 21 21 + #include <asm-generic/atomic64.h> 22 22 + #endif 23 23 + 14 24 #if __SIZEOF_LONG__ == 4 15 25 #define __LL "ll.w " 16 26 #define __SC "sc.w " ··· 43 33 44 34 #define arch_atomic_read(v) READ_ONCE((v)->counter) 45 35 #define arch_atomic_set(v, i) WRITE_ONCE((v)->counter, (i)) 46 46 - 47 47 - #define ATOMIC_OP(op, I, asm_op) \ 48 48 - static inline void arch_atomic_##op(int i, atomic_t *v) \ 49 49 - { \ 50 50 - __asm__ __volatile__( \ 51 51 - "am"#asm_op".w" " $zero, %1, %0 \n" \ 52 52 - : "+ZB" (v->counter) \ 53 53 - : "r" (I) \ 54 54 - : "memory"); \ 55 55 - } 56 56 - 57 57 - #define ATOMIC_OP_RETURN(op, I, asm_op, c_op, mb, suffix) \ 58 58 - static inline int arch_atomic_##op##_return##suffix(int i, atomic_t *v) \ 59 59 - { \ 60 60 - int result; \ 61 61 - \ 62 62 - __asm__ __volatile__( \ 63 63 - "am"#asm_op#mb".w" " %1, %2, %0 \n" \ 64 64 - : "+ZB" (v->counter), "=&r" (result) \ 65 65 - : "r" (I) \ 66 66 - : "memory"); \ 67 67 - \ 68 68 - return result c_op I; \ 69 69 - } 70 70 - 71 71 - #define ATOMIC_FETCH_OP(op, I, asm_op, mb, suffix) \ 72 72 - static inline int arch_atomic_fetch_##op##suffix(int i, atomic_t *v) \ 73 73 - { \ 74 74 - int result; \ 75 75 - \ 76 76 - __asm__ __volatile__( \ 77 77 - "am"#asm_op#mb".w" " %1, %2, %0 \n" \ 78 78 - : "+ZB" (v->counter), "=&r" (result) \ 79 79 - : "r" (I) \ 80 80 - : "memory"); \ 81 81 - \ 82 82 - return result; \ 83 83 - } 84 84 - 85 85 - #define ATOMIC_OPS(op, I, asm_op, c_op) \ 86 86 - ATOMIC_OP(op, I, asm_op) \ 87 87 - ATOMIC_OP_RETURN(op, I, asm_op, c_op, _db, ) \ 88 88 - ATOMIC_OP_RETURN(op, I, asm_op, c_op, , _relaxed) \ 89 89 - ATOMIC_FETCH_OP(op, I, asm_op, _db, ) \ 90 90 - ATOMIC_FETCH_OP(op, I, asm_op, , _relaxed) 91 91 - 92 92 - ATOMIC_OPS(add, i, add, +) 93 93 - ATOMIC_OPS(sub, -i, add, +) 94 94 - 95 95 - #define arch_atomic_add_return arch_atomic_add_return 96 96 - #define arch_atomic_add_return_acquire arch_atomic_add_return 97 97 - #define arch_atomic_add_return_release arch_atomic_add_return 98 98 - #define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed 99 99 - #define arch_atomic_sub_return arch_atomic_sub_return 100 100 - #define arch_atomic_sub_return_acquire arch_atomic_sub_return 101 101 - #define arch_atomic_sub_return_release arch_atomic_sub_return 102 102 - #define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed 103 103 - #define arch_atomic_fetch_add arch_atomic_fetch_add 104 104 - #define arch_atomic_fetch_add_acquire arch_atomic_fetch_add 105 105 - #define arch_atomic_fetch_add_release arch_atomic_fetch_add 106 106 - #define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed 107 107 - #define arch_atomic_fetch_sub arch_atomic_fetch_sub 108 108 - #define arch_atomic_fetch_sub_acquire arch_atomic_fetch_sub 109 109 - #define arch_atomic_fetch_sub_release arch_atomic_fetch_sub 110 110 - #define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed 111 111 - 112 112 - #undef ATOMIC_OPS 113 113 - 114 114 - #define ATOMIC_OPS(op, I, asm_op) \ 115 115 - ATOMIC_OP(op, I, asm_op) \ 116 116 - ATOMIC_FETCH_OP(op, I, asm_op, _db, ) \ 117 117 - ATOMIC_FETCH_OP(op, I, asm_op, , _relaxed) 118 118 - 119 119 - ATOMIC_OPS(and, i, and) 120 120 - ATOMIC_OPS(or, i, or) 121 121 - ATOMIC_OPS(xor, i, xor) 122 122 - 123 123 - #define arch_atomic_fetch_and arch_atomic_fetch_and 124 124 - #define arch_atomic_fetch_and_acquire arch_atomic_fetch_and 125 125 - #define arch_atomic_fetch_and_release arch_atomic_fetch_and 126 126 - #define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed 127 127 - #define arch_atomic_fetch_or arch_atomic_fetch_or 128 128 - #define arch_atomic_fetch_or_acquire arch_atomic_fetch_or 129 129 - #define arch_atomic_fetch_or_release arch_atomic_fetch_or 130 130 - #define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed 131 131 - #define arch_atomic_fetch_xor arch_atomic_fetch_xor 132 132 - #define arch_atomic_fetch_xor_acquire arch_atomic_fetch_xor 133 133 - #define arch_atomic_fetch_xor_release arch_atomic_fetch_xor 134 134 - #define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed 135 135 - 136 136 - #undef ATOMIC_OPS 137 137 - #undef ATOMIC_FETCH_OP 138 138 - #undef ATOMIC_OP_RETURN 139 139 - #undef ATOMIC_OP 140 36 141 37 static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u) 142 38 { ··· 109 193 110 194 #define arch_atomic64_read(v) READ_ONCE((v)->counter) 111 195 #define arch_atomic64_set(v, i) WRITE_ONCE((v)->counter, (i)) 112 112 - 113 113 - #define ATOMIC64_OP(op, I, asm_op) \ 114 114 - static inline void arch_atomic64_##op(long i, atomic64_t *v) \ 115 115 - { \ 116 116 - __asm__ __volatile__( \ 117 117 - "am"#asm_op".d " " $zero, %1, %0 \n" \ 118 118 - : "+ZB" (v->counter) \ 119 119 - : "r" (I) \ 120 120 - : "memory"); \ 121 121 - } 122 122 - 123 123 - #define ATOMIC64_OP_RETURN(op, I, asm_op, c_op, mb, suffix) \ 124 124 - static inline long arch_atomic64_##op##_return##suffix(long i, atomic64_t *v) \ 125 125 - { \ 126 126 - long result; \ 127 127 - __asm__ __volatile__( \ 128 128 - "am"#asm_op#mb".d " " %1, %2, %0 \n" \ 129 129 - : "+ZB" (v->counter), "=&r" (result) \ 130 130 - : "r" (I) \ 131 131 - : "memory"); \ 132 132 - \ 133 133 - return result c_op I; \ 134 134 - } 135 135 - 136 136 - #define ATOMIC64_FETCH_OP(op, I, asm_op, mb, suffix) \ 137 137 - static inline long arch_atomic64_fetch_##op##suffix(long i, atomic64_t *v) \ 138 138 - { \ 139 139 - long result; \ 140 140 - \ 141 141 - __asm__ __volatile__( \ 142 142 - "am"#asm_op#mb".d " " %1, %2, %0 \n" \ 143 143 - : "+ZB" (v->counter), "=&r" (result) \ 144 144 - : "r" (I) \ 145 145 - : "memory"); \ 146 146 - \ 147 147 - return result; \ 148 148 - } 149 149 - 150 150 - #define ATOMIC64_OPS(op, I, asm_op, c_op) \ 151 151 - ATOMIC64_OP(op, I, asm_op) \ 152 152 - ATOMIC64_OP_RETURN(op, I, asm_op, c_op, _db, ) \ 153 153 - ATOMIC64_OP_RETURN(op, I, asm_op, c_op, , _relaxed) \ 154 154 - ATOMIC64_FETCH_OP(op, I, asm_op, _db, ) \ 155 155 - ATOMIC64_FETCH_OP(op, I, asm_op, , _relaxed) 156 156 - 157 157 - ATOMIC64_OPS(add, i, add, +) 158 158 - ATOMIC64_OPS(sub, -i, add, +) 159 159 - 160 160 - #define arch_atomic64_add_return arch_atomic64_add_return 161 161 - #define arch_atomic64_add_return_acquire arch_atomic64_add_return 162 162 - #define arch_atomic64_add_return_release arch_atomic64_add_return 163 163 - #define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed 164 164 - #define arch_atomic64_sub_return arch_atomic64_sub_return 165 165 - #define arch_atomic64_sub_return_acquire arch_atomic64_sub_return 166 166 - #define arch_atomic64_sub_return_release arch_atomic64_sub_return 167 167 - #define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed 168 168 - #define arch_atomic64_fetch_add arch_atomic64_fetch_add 169 169 - #define arch_atomic64_fetch_add_acquire arch_atomic64_fetch_add 170 170 - #define arch_atomic64_fetch_add_release arch_atomic64_fetch_add 171 171 - #define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed 172 172 - #define arch_atomic64_fetch_sub arch_atomic64_fetch_sub 173 173 - #define arch_atomic64_fetch_sub_acquire arch_atomic64_fetch_sub 174 174 - #define arch_atomic64_fetch_sub_release arch_atomic64_fetch_sub 175 175 - #define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed 176 176 - 177 177 - #undef ATOMIC64_OPS 178 178 - 179 179 - #define ATOMIC64_OPS(op, I, asm_op) \ 180 180 - ATOMIC64_OP(op, I, asm_op) \ 181 181 - ATOMIC64_FETCH_OP(op, I, asm_op, _db, ) \ 182 182 - ATOMIC64_FETCH_OP(op, I, asm_op, , _relaxed) 183 183 - 184 184 - ATOMIC64_OPS(and, i, and) 185 185 - ATOMIC64_OPS(or, i, or) 186 186 - ATOMIC64_OPS(xor, i, xor) 187 187 - 188 188 - #define arch_atomic64_fetch_and arch_atomic64_fetch_and 189 189 - #define arch_atomic64_fetch_and_acquire arch_atomic64_fetch_and 190 190 - #define arch_atomic64_fetch_and_release arch_atomic64_fetch_and 191 191 - #define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed 192 192 - #define arch_atomic64_fetch_or arch_atomic64_fetch_or 193 193 - #define arch_atomic64_fetch_or_acquire arch_atomic64_fetch_or 194 194 - #define arch_atomic64_fetch_or_release arch_atomic64_fetch_or 195 195 - #define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed 196 196 - #define arch_atomic64_fetch_xor arch_atomic64_fetch_xor 197 197 - #define arch_atomic64_fetch_xor_acquire arch_atomic64_fetch_xor 198 198 - #define arch_atomic64_fetch_xor_release arch_atomic64_fetch_xor 199 199 - #define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed 200 200 - 201 201 - #undef ATOMIC64_OPS 202 202 - #undef ATOMIC64_FETCH_OP 203 203 - #undef ATOMIC64_OP_RETURN 204 204 - #undef ATOMIC64_OP 205 196 206 197 static inline long arch_atomic64_fetch_add_unless(atomic64_t *v, long a, long u) 207 198 {

+11

arch/loongarch/include/asm/bitops.h

reviewed

··· 13 13 14 14 #include <asm/barrier.h> 15 15 16 16 + #ifdef CONFIG_32BIT_REDUCED 17 17 + 18 18 + #include <asm-generic/bitops/ffs.h> 19 19 + #include <asm-generic/bitops/fls.h> 20 20 + #include <asm-generic/bitops/__ffs.h> 21 21 + #include <asm-generic/bitops/__fls.h> 22 22 + 23 23 + #else /* CONFIG_32BIT_STANDARD || CONFIG_64BIT */ 24 24 + 16 25 #include <asm-generic/bitops/builtin-ffs.h> 17 26 #include <asm-generic/bitops/builtin-fls.h> 18 27 #include <asm-generic/bitops/builtin-__ffs.h> 19 28 #include <asm-generic/bitops/builtin-__fls.h> 29 29 + 30 30 + #endif 20 31 21 32 #include <asm-generic/bitops/ffz.h> 22 33 #include <asm-generic/bitops/fls64.h>

+1 -1

arch/loongarch/include/asm/bitrev.h

reviewed

··· 11 11 { 12 12 u32 ret; 13 13 14 14 - asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(__swab32(x))); 14 14 + asm("bitrev.w %0, %1" : "=r"(ret) : "r"(x)); 15 15 return ret; 16 16 } 17 17

+4

arch/loongarch/include/asm/checksum.h

reviewed

··· 9 9 #include <linux/bitops.h> 10 10 #include <linux/in6.h> 11 11 12 12 + #ifdef CONFIG_64BIT 13 13 + 12 14 #define _HAVE_ARCH_IPV6_CSUM 13 15 __sum16 csum_ipv6_magic(const struct in6_addr *saddr, 14 16 const struct in6_addr *daddr, ··· 62 60 63 61 extern unsigned int do_csum(const unsigned char *buff, int len); 64 62 #define do_csum do_csum 63 63 + 64 64 + #endif 65 65 66 66 #include <asm-generic/checksum.h> 67 67

+37 -11

arch/loongarch/include/asm/cmpxchg.h

reviewed

··· 9 9 #include <linux/build_bug.h> 10 10 #include <asm/barrier.h> 11 11 12 12 - #define __xchg_asm(amswap_db, m, val) \ 12 12 + #define __xchg_amo_asm(amswap_db, m, val) \ 13 13 ({ \ 14 14 - __typeof(val) __ret; \ 14 14 + __typeof(val) __ret; \ 15 15 \ 16 16 - __asm__ __volatile__ ( \ 17 17 - " "amswap_db" %1, %z2, %0 \n" \ 18 18 - : "+ZB" (*m), "=&r" (__ret) \ 19 19 - : "Jr" (val) \ 20 20 - : "memory"); \ 16 16 + __asm__ __volatile__ ( \ 17 17 + " "amswap_db" %1, %z2, %0 \n" \ 18 18 + : "+ZB" (*m), "=&r" (__ret) \ 19 19 + : "Jr" (val) \ 20 20 + : "memory"); \ 21 21 \ 22 22 - __ret; \ 22 22 + __ret; \ 23 23 + }) 24 24 + 25 25 + #define __xchg_llsc_asm(ld, st, m, val) \ 26 26 + ({ \ 27 27 + __typeof(val) __ret, __tmp; \ 28 28 + \ 29 29 + asm volatile ( \ 30 30 + "1: ll.w %0, %3 \n" \ 31 31 + " move %1, %z4 \n" \ 32 32 + " sc.w %1, %2 \n" \ 33 33 + " beqz %1, 1b \n" \ 34 34 + : "=&r" (__ret), "=&r" (__tmp), "=ZC" (*m) \ 35 35 + : "ZC" (*m), "Jr" (val) \ 36 36 + : "memory"); \ 37 37 + \ 38 38 + __ret; \ 23 39 }) 24 40 25 41 static inline unsigned int __xchg_small(volatile void *ptr, unsigned int val, ··· 83 67 switch (size) { 84 68 case 1: 85 69 case 2: 86 86 - return __xchg_small(ptr, x, size); 70 70 + return __xchg_small((volatile void *)ptr, x, size); 87 71 88 72 case 4: 89 89 - return __xchg_asm("amswap_db.w", (volatile u32 *)ptr, (u32)x); 73 73 + #ifdef CONFIG_CPU_HAS_AMO 74 74 + return __xchg_amo_asm("amswap_db.w", (volatile u32 *)ptr, (u32)x); 75 75 + #else 76 76 + return __xchg_llsc_asm("ll.w", "sc.w", (volatile u32 *)ptr, (u32)x); 77 77 + #endif /* CONFIG_CPU_HAS_AMO */ 90 78 79 79 + #ifdef CONFIG_64BIT 91 80 case 8: 92 92 - return __xchg_asm("amswap_db.d", (volatile u64 *)ptr, (u64)x); 81 81 + #ifdef CONFIG_CPU_HAS_AMO 82 82 + return __xchg_amo_asm("amswap_db.d", (volatile u64 *)ptr, (u64)x); 83 83 + #else 84 84 + return __xchg_llsc_asm("ll.d", "sc.d", (volatile u64 *)ptr, (u64)x); 85 85 + #endif /* CONFIG_CPU_HAS_AMO */ 86 86 + #endif /* CONFIG_64BIT */ 93 87 94 88 default: 95 89 BUILD_BUG();

-3

arch/loongarch/include/asm/cpu-features.h

reviewed

··· 20 20 #define cpu_has_loongarch64 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT) 21 21 22 22 #ifdef CONFIG_32BIT 23 23 - # define cpu_has_64bits (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT) 24 23 # define cpu_vabits 31 25 24 # define cpu_pabits 31 26 25 #endif 27 26 28 27 #ifdef CONFIG_64BIT 29 29 - # define cpu_has_64bits 1 30 28 # define cpu_vabits cpu_data[0].vabits 31 29 # define cpu_pabits cpu_data[0].pabits 32 32 - # define __NEED_ADDRBITS_PROBE 33 30 #endif 34 31 35 32 /*

+1 -1

arch/loongarch/include/asm/dmi.h

reviewed

··· 12 12 #define dmi_early_unmap(x, l) dmi_unmap(x) 13 13 #define dmi_alloc(l) memblock_alloc(l, PAGE_SIZE) 14 14 15 15 - static inline void *dmi_remap(u64 phys_addr, unsigned long size) 15 15 + static inline void *dmi_remap(phys_addr_t phys_addr, unsigned long size) 16 16 { 17 17 return ((void *)TO_CACHE(phys_addr)); 18 18 }

+31

arch/loongarch/include/asm/elf.h

reviewed

··· 120 120 #define R_LARCH_ADD_ULEB128 107 121 121 #define R_LARCH_SUB_ULEB128 108 122 122 #define R_LARCH_64_PCREL 109 123 123 + #define R_LARCH_CALL36 110 124 124 + #define R_LARCH_TLS_DESC_PC_HI20 111 125 125 + #define R_LARCH_TLS_DESC_PC_LO12 112 126 126 + #define R_LARCH_TLS_DESC64_PC_LO20 113 127 127 + #define R_LARCH_TLS_DESC64_PC_HI12 114 128 128 + #define R_LARCH_TLS_DESC_HI20 115 129 129 + #define R_LARCH_TLS_DESC_LO12 116 130 130 + #define R_LARCH_TLS_DESC64_LO20 117 131 131 + #define R_LARCH_TLS_DESC64_HI12 118 132 132 + #define R_LARCH_TLS_DESC_LD 119 133 133 + #define R_LARCH_TLS_DESC_CALL 120 134 134 + #define R_LARCH_TLS_LE_HI20_R 121 135 135 + #define R_LARCH_TLS_LE_ADD_R 122 136 136 + #define R_LARCH_TLS_LE_LO12_R 123 137 137 + #define R_LARCH_TLS_LD_PCREL20_S2 124 138 138 + #define R_LARCH_TLS_GD_PCREL20_S2 125 139 139 + #define R_LARCH_TLS_DESC_PCREL20_S2 126 140 140 + #define R_LARCH_CALL30 127 141 141 + #define R_LARCH_PCADD_HI20 128 142 142 + #define R_LARCH_PCADD_LO12 129 143 143 + #define R_LARCH_GOT_PCADD_HI20 130 144 144 + #define R_LARCH_GOT_PCADD_LO12 131 145 145 + #define R_LARCH_TLS_IE_PCADD_HI20 132 146 146 + #define R_LARCH_TLS_IE_PCADD_LO12 133 147 147 + #define R_LARCH_TLS_LD_PCADD_HI20 134 148 148 + #define R_LARCH_TLS_LD_PCADD_LO12 135 149 149 + #define R_LARCH_TLS_GD_PCADD_HI20 136 150 150 + #define R_LARCH_TLS_GD_PCADD_LO12 137 151 151 + #define R_LARCH_TLS_DESC_PCADD_HI20 138 152 152 + #define R_LARCH_TLS_DESC_PCADD_LO12 139 123 153 124 154 #ifndef ELF_ARCH 125 155 ··· 186 156 typedef double elf_fpreg_t; 187 157 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; 188 158 159 159 + void loongarch_dump_regs32(u32 *uregs, const struct pt_regs *regs); 189 160 void loongarch_dump_regs64(u64 *uregs, const struct pt_regs *regs); 190 161 191 162 #ifdef CONFIG_32BIT

+8 -4

arch/loongarch/include/asm/inst.h

reviewed

··· 438 438 439 439 static inline bool is_ra_save_ins(union loongarch_instruction *ip) 440 440 { 441 441 - /* st.d $ra, $sp, offset */ 442 442 - return ip->reg2i12_format.opcode == std_op && 441 441 + const u32 opcode = IS_ENABLED(CONFIG_32BIT) ? stw_op : std_op; 442 442 + 443 443 + /* st.w / st.d $ra, $sp, offset */ 444 444 + return ip->reg2i12_format.opcode == opcode && 443 445 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 444 446 ip->reg2i12_format.rd == LOONGARCH_GPR_RA && 445 447 !is_imm12_negative(ip->reg2i12_format.immediate); ··· 449 447 450 448 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip) 451 449 { 452 452 - /* addi.d $sp, $sp, -imm */ 453 453 - return ip->reg2i12_format.opcode == addid_op && 450 450 + const u32 opcode = IS_ENABLED(CONFIG_32BIT) ? addiw_op : addid_op; 451 451 + 452 452 + /* addi.w / addi.d $sp, $sp, -imm */ 453 453 + return ip->reg2i12_format.opcode == opcode && 454 454 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 455 455 ip->reg2i12_format.rd == LOONGARCH_GPR_SP && 456 456 is_imm12_negative(ip->reg2i12_format.immediate);

+12

arch/loongarch/include/asm/irq.h

reviewed

··· 50 50 #define NR_LEGACY_VECTORS 16 51 51 #define IRQ_MATRIX_BITS NR_VECTORS 52 52 53 53 + #define AVEC_IRQ_SHIFT 4 54 54 + #define AVEC_IRQ_BIT 8 55 55 + #define AVEC_IRQ_MASK GENMASK(AVEC_IRQ_BIT - 1, 0) 56 56 + #define AVEC_CPU_SHIFT 12 57 57 + #define AVEC_CPU_BIT 16 58 58 + #define AVEC_CPU_MASK GENMASK(AVEC_CPU_BIT - 1, 0) 59 59 + 53 60 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace 54 61 void arch_trigger_cpumask_backtrace(const struct cpumask *mask, int exclude_cpu); 55 62 63 63 + #ifdef CONFIG_32BIT 64 64 + #define MAX_IO_PICS 1 65 65 + #else 56 66 #define MAX_IO_PICS 8 67 67 + #endif 68 68 + 57 69 #define NR_IRQS (64 + NR_VECTORS * (NR_CPUS + MAX_IO_PICS)) 58 70 59 71 struct acpi_vector_group {

+10 -2

arch/loongarch/include/asm/jump_label.h

reviewed

··· 10 10 #ifndef __ASSEMBLER__ 11 11 12 12 #include <linux/types.h> 13 13 + #include <linux/stringify.h> 14 14 + #include <asm/asm.h> 13 15 14 16 #define JUMP_LABEL_NOP_SIZE 4 17 17 + 18 18 + #ifdef CONFIG_32BIT 19 19 + #define JUMP_LABEL_TYPE ".long " 20 20 + #else 21 21 + #define JUMP_LABEL_TYPE ".quad " 22 22 + #endif 15 23 16 24 /* This macro is also expanded on the Rust side. */ 17 25 #define JUMP_TABLE_ENTRY(key, label) \ 18 26 ".pushsection __jump_table, \"aw\" \n\t" \ 19 19 - ".align 3 \n\t" \ 27 27 + ".align " __stringify(PTRLOG) " \n\t" \ 20 28 ".long 1b - ., " label " - . \n\t" \ 21 21 - ".quad " key " - . \n\t" \ 29 29 + JUMP_LABEL_TYPE key " - . \n\t" \ 22 30 ".popsection \n\t" 23 31 24 32 #define ARCH_STATIC_BRANCH_ASM(key, label) \

+37

arch/loongarch/include/asm/local.h

reviewed

··· 8 8 #include <linux/percpu.h> 9 9 #include <linux/bitops.h> 10 10 #include <linux/atomic.h> 11 11 + #include <asm/asm.h> 11 12 #include <asm/cmpxchg.h> 12 13 13 14 typedef struct { ··· 28 27 /* 29 28 * Same as above, but return the result value 30 29 */ 30 30 + #ifdef CONFIG_CPU_HAS_AMO 31 31 static inline long local_add_return(long i, local_t *l) 32 32 { 33 33 unsigned long result; ··· 57 55 58 56 return result; 59 57 } 58 58 + #else 59 59 + static inline long local_add_return(long i, local_t *l) 60 60 + { 61 61 + unsigned long result, temp; 62 62 + 63 63 + __asm__ __volatile__( 64 64 + "1:" __LL "%1, %2 # local_add_return \n" 65 65 + __stringify(LONG_ADD) " %0, %1, %3 \n" 66 66 + __SC "%0, %2 \n" 67 67 + " beq %0, $r0, 1b \n" 68 68 + __stringify(LONG_ADD) " %0, %1, %3 \n" 69 69 + : "=&r" (result), "=&r" (temp), "=ZC" (l->a.counter) 70 70 + : "r" (i), "ZC" (l->a.counter) 71 71 + : "memory"); 72 72 + 73 73 + return result; 74 74 + } 75 75 + 76 76 + static inline long local_sub_return(long i, local_t *l) 77 77 + { 78 78 + unsigned long result, temp; 79 79 + 80 80 + __asm__ __volatile__( 81 81 + "1:" __LL "%1, %2 # local_sub_return \n" 82 82 + __stringify(LONG_SUB) " %0, %1, %3 \n" 83 83 + __SC "%0, %2 \n" 84 84 + " beq %0, $r0, 1b \n" 85 85 + __stringify(LONG_SUB) " %0, %1, %3 \n" 86 86 + : "=&r" (result), "=&r" (temp), "=ZC" (l->a.counter) 87 87 + : "r" (i), "ZC" (l->a.counter) 88 88 + : "memory"); 89 89 + 90 90 + return result; 91 91 + } 92 92 + #endif 60 93 61 94 static inline long local_cmpxchg(local_t *l, long old, long new) 62 95 {

+84 -18

arch/loongarch/include/asm/loongarch.h

reviewed

··· 182 182 #define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg) 183 183 #define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg) 184 184 185 185 + #ifdef CONFIG_32BIT 186 186 + #define csr_read(reg) csr_read32(reg) 187 187 + #define csr_write(val, reg) csr_write32(val, reg) 188 188 + #define csr_xchg(val, mask, reg) csr_xchg32(val, mask, reg) 189 189 + #else 190 190 + #define csr_read(reg) csr_read64(reg) 191 191 + #define csr_write(val, reg) csr_write64(val, reg) 192 192 + #define csr_xchg(val, mask, reg) csr_xchg64(val, mask, reg) 193 193 + #endif 194 194 + 185 195 /* IOCSR */ 186 196 #define iocsr_read32(reg) __iocsrrd_w(reg) 187 197 #define iocsr_read64(reg) __iocsrrd_d(reg) ··· 914 904 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */ 915 905 916 906 /* Direct Map window 0/1/2/3 */ 907 907 + 908 908 + #ifdef CONFIG_32BIT 909 909 + 910 910 + #define CSR_DMW0_PLV0 (1 << 0) 911 911 + #define CSR_DMW0_VSEG (0x4) 912 912 + #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) 913 913 + #define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0) 914 914 + 915 915 + #define CSR_DMW1_PLV0 (1 << 0) 916 916 + #define CSR_DMW1_MAT (1 << 4) 917 917 + #define CSR_DMW1_VSEG (0x5) 918 918 + #define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS) 919 919 + #define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0) 920 920 + 921 921 + #define CSR_DMW2_INIT 0x0 922 922 + 923 923 + #define CSR_DMW3_INIT 0x0 924 924 + 925 925 + #else 926 926 + 917 927 #define CSR_DMW0_PLV0 _CONST64_(1 << 0) 918 928 #define CSR_DMW0_VSEG _CONST64_(0x8000) 919 929 #define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS) ··· 952 922 #define CSR_DMW2_INIT (CSR_DMW2_BASE | CSR_DMW2_MAT | CSR_DMW2_PLV0) 953 923 954 924 #define CSR_DMW3_INIT 0x0 925 925 + 926 926 + #endif 955 927 956 928 /* Performance Counter registers */ 957 929 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */ ··· 1240 1208 1241 1209 #ifndef __ASSEMBLER__ 1242 1210 1243 1243 - static __always_inline u64 drdtime(void) 1211 1211 + #ifdef CONFIG_32BIT 1212 1212 + 1213 1213 + static __always_inline u32 rdtime_h(void) 1214 1214 + { 1215 1215 + u32 val = 0; 1216 1216 + 1217 1217 + __asm__ __volatile__( 1218 1218 + "rdtimeh.w %0, $zero\n\t" 1219 1219 + : "=r"(val) 1220 1220 + : 1221 1221 + ); 1222 1222 + return val; 1223 1223 + } 1224 1224 + 1225 1225 + static __always_inline u32 rdtime_l(void) 1226 1226 + { 1227 1227 + u32 val = 0; 1228 1228 + 1229 1229 + __asm__ __volatile__( 1230 1230 + "rdtimel.w %0, $zero\n\t" 1231 1231 + : "=r"(val) 1232 1232 + : 1233 1233 + ); 1234 1234 + return val; 1235 1235 + } 1236 1236 + 1237 1237 + #else 1238 1238 + 1239 1239 + static __always_inline u64 rdtime_d(void) 1244 1240 { 1245 1241 u64 val = 0; 1246 1242 ··· 1280 1220 return val; 1281 1221 } 1282 1222 1223 1223 + #endif 1224 1224 + 1283 1225 static inline unsigned int get_csr_cpuid(void) 1284 1226 { 1285 1227 return csr_read32(LOONGARCH_CSR_CPUID); 1286 1228 } 1287 1229 1230 1230 + #ifdef CONFIG_64BIT 1288 1231 static inline void csr_any_send(unsigned int addr, unsigned int data, 1289 1232 unsigned int data_mask, unsigned int cpu) 1290 1233 { ··· 1299 1236 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT); 1300 1237 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND); 1301 1238 } 1239 1239 + #endif 1302 1240 1303 1241 static inline unsigned int read_csr_excode(void) 1304 1242 { ··· 1323 1259 1324 1260 static inline unsigned int read_csr_tlbrefill_pagesize(void) 1325 1261 { 1326 1326 - return (csr_read64(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT; 1262 1262 + return (csr_read(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT; 1327 1263 } 1328 1264 1329 1265 static inline void write_csr_tlbrefill_pagesize(unsigned int size) 1330 1266 { 1331 1331 - csr_xchg64(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI); 1267 1267 + csr_xchg(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI); 1332 1268 } 1333 1269 1334 1270 #define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID) 1335 1271 #define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID) 1336 1336 - #define read_csr_entryhi() csr_read64(LOONGARCH_CSR_TLBEHI) 1337 1337 - #define write_csr_entryhi(val) csr_write64(val, LOONGARCH_CSR_TLBEHI) 1338 1338 - #define read_csr_entrylo0() csr_read64(LOONGARCH_CSR_TLBELO0) 1339 1339 - #define write_csr_entrylo0(val) csr_write64(val, LOONGARCH_CSR_TLBELO0) 1340 1340 - #define read_csr_entrylo1() csr_read64(LOONGARCH_CSR_TLBELO1) 1341 1341 - #define write_csr_entrylo1(val) csr_write64(val, LOONGARCH_CSR_TLBELO1) 1272 1272 + #define read_csr_entryhi() csr_read(LOONGARCH_CSR_TLBEHI) 1273 1273 + #define write_csr_entryhi(val) csr_write(val, LOONGARCH_CSR_TLBEHI) 1274 1274 + #define read_csr_entrylo0() csr_read(LOONGARCH_CSR_TLBELO0) 1275 1275 + #define write_csr_entrylo0(val) csr_write(val, LOONGARCH_CSR_TLBELO0) 1276 1276 + #define read_csr_entrylo1() csr_read(LOONGARCH_CSR_TLBELO1) 1277 1277 + #define write_csr_entrylo1(val) csr_write(val, LOONGARCH_CSR_TLBELO1) 1342 1278 #define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG) 1343 1279 #define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG) 1344 1280 #define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT) ··· 1348 1284 #define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN) 1349 1285 #define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN) 1350 1286 #define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID) 1351 1351 - #define read_csr_prcfg1() csr_read64(LOONGARCH_CSR_PRCFG1) 1352 1352 - #define write_csr_prcfg1(val) csr_write64(val, LOONGARCH_CSR_PRCFG1) 1353 1353 - #define read_csr_prcfg2() csr_read64(LOONGARCH_CSR_PRCFG2) 1354 1354 - #define write_csr_prcfg2(val) csr_write64(val, LOONGARCH_CSR_PRCFG2) 1355 1355 - #define read_csr_prcfg3() csr_read64(LOONGARCH_CSR_PRCFG3) 1356 1356 - #define write_csr_prcfg3(val) csr_write64(val, LOONGARCH_CSR_PRCFG3) 1287 1287 + #define read_csr_prcfg1() csr_read(LOONGARCH_CSR_PRCFG1) 1288 1288 + #define write_csr_prcfg1(val) csr_write(val, LOONGARCH_CSR_PRCFG1) 1289 1289 + #define read_csr_prcfg2() csr_read(LOONGARCH_CSR_PRCFG2) 1290 1290 + #define write_csr_prcfg2(val) csr_write(val, LOONGARCH_CSR_PRCFG2) 1291 1291 + #define read_csr_prcfg3() csr_read(LOONGARCH_CSR_PRCFG3) 1292 1292 + #define write_csr_prcfg3(val) csr_write(val, LOONGARCH_CSR_PRCFG3) 1357 1293 #define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE) 1358 1294 #define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE) 1359 1295 #define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG) 1360 1296 #define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG) 1361 1297 #define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR) 1362 1362 - #define read_csr_impctl1() csr_read64(LOONGARCH_CSR_IMPCTL1) 1363 1363 - #define write_csr_impctl1(val) csr_write64(val, LOONGARCH_CSR_IMPCTL1) 1364 1364 - #define write_csr_impctl2(val) csr_write64(val, LOONGARCH_CSR_IMPCTL2) 1298 1298 + #define read_csr_impctl1() csr_read(LOONGARCH_CSR_IMPCTL1) 1299 1299 + #define write_csr_impctl1(val) csr_write(val, LOONGARCH_CSR_IMPCTL1) 1300 1300 + #define write_csr_impctl2(val) csr_write(val, LOONGARCH_CSR_IMPCTL2) 1365 1301 1366 1302 #define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0) 1367 1303 #define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0) ··· 1442 1378 #define ENTRYLO_C_SHIFT 4 1443 1379 #define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT) 1444 1380 #define ENTRYLO_G (_ULCAST_(1) << 6) 1381 1381 + #ifdef CONFIG_64BIT 1445 1382 #define ENTRYLO_NR (_ULCAST_(1) << 61) 1446 1383 #define ENTRYLO_NX (_ULCAST_(1) << 62) 1384 1384 + #endif 1447 1385 1448 1386 /* Values for PageSize register */ 1449 1387 #define PS_4K 0x0000000c

+11

arch/loongarch/include/asm/module.h

reviewed

··· 38 38 39 39 struct plt_entry { 40 40 u32 inst_lu12iw; 41 41 + #ifdef CONFIG_64BIT 41 42 u32 inst_lu32id; 42 43 u32 inst_lu52id; 44 44 + #endif 43 45 u32 inst_jirl; 44 46 }; 45 47 ··· 59 57 60 58 static inline struct plt_entry emit_plt_entry(unsigned long val) 61 59 { 60 60 + #ifdef CONFIG_32BIT 61 61 + u32 lu12iw, jirl; 62 62 + 63 63 + lu12iw = larch_insn_gen_lu12iw(LOONGARCH_GPR_T1, ADDR_IMM(val, LU12IW)); 64 64 + jirl = larch_insn_gen_jirl(0, LOONGARCH_GPR_T1, ADDR_IMM(val, ORI)); 65 65 + 66 66 + return (struct plt_entry) { lu12iw, jirl }; 67 67 + #else 62 68 u32 lu12iw, lu32id, lu52id, jirl; 63 69 64 70 lu12iw = larch_insn_gen_lu12iw(LOONGARCH_GPR_T1, ADDR_IMM(val, LU12IW)); ··· 75 65 jirl = larch_insn_gen_jirl(0, LOONGARCH_GPR_T1, ADDR_IMM(val, ORI)); 76 66 77 67 return (struct plt_entry) { lu12iw, lu32id, lu52id, jirl }; 68 68 + #endif 78 69 } 79 70 80 71 static inline struct plt_idx_entry emit_plt_idx_entry(unsigned long val)

+1 -1

arch/loongarch/include/asm/page.h

reviewed

··· 10 10 11 11 #include <vdso/page.h> 12 12 13 13 - #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 13 13 + #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - PTRLOG) 14 14 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 15 15 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 16 16 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)

+21 -23

arch/loongarch/include/asm/percpu.h

reviewed

··· 13 13 * the loading address of main kernel image, but far from where the modules are 14 14 * loaded. Tell the compiler this fact when using explicit relocs. 15 15 */ 16 16 - #if defined(MODULE) && defined(CONFIG_AS_HAS_EXPLICIT_RELOCS) 16 16 + #if defined(MODULE) && defined(CONFIG_AS_HAS_EXPLICIT_RELOCS) && defined(CONFIG_64BIT) 17 17 # if __has_attribute(model) 18 18 # define PER_CPU_ATTRIBUTES __attribute__((model("extreme"))) 19 19 # else ··· 27 27 static inline void set_my_cpu_offset(unsigned long off) 28 28 { 29 29 __my_cpu_offset = off; 30 30 - csr_write64(off, PERCPU_BASE_KS); 30 30 + csr_write(off, PERCPU_BASE_KS); 31 31 } 32 32 33 33 #define __my_cpu_offset \ ··· 35 35 __asm__ __volatile__("":"+r"(__my_cpu_offset)); \ 36 36 __my_cpu_offset; \ 37 37 }) 38 38 + 39 39 + #ifdef CONFIG_CPU_HAS_AMO 38 40 39 41 #define PERCPU_OP(op, asm_op, c_op) \ 40 42 static __always_inline unsigned long __percpu_##op(void *ptr, \ ··· 70 68 PERCPU_OP(or, or, |) 71 69 #undef PERCPU_OP 72 70 73 73 - static __always_inline unsigned long __percpu_xchg(void *ptr, unsigned long val, int size) 74 74 - { 75 75 - switch (size) { 76 76 - case 1: 77 77 - case 2: 78 78 - return __xchg_small((volatile void *)ptr, val, size); 71 71 + #endif 79 72 80 80 - case 4: 81 81 - return __xchg_asm("amswap.w", (volatile u32 *)ptr, (u32)val); 82 82 - 83 83 - case 8: 84 84 - return __xchg_asm("amswap.d", (volatile u64 *)ptr, (u64)val); 85 85 - 86 86 - default: 87 87 - BUILD_BUG(); 88 88 - } 89 89 - 90 90 - return 0; 91 91 - } 73 73 + #ifdef CONFIG_64BIT 92 74 93 75 #define __pcpu_op_1(op) op ".b " 94 76 #define __pcpu_op_2(op) op ".h " ··· 101 115 : "memory"); \ 102 116 } while (0) 103 117 118 118 + #endif 119 119 + 120 120 + #define __percpu_xchg __arch_xchg 121 121 + 104 122 /* this_cpu_cmpxchg */ 105 123 #define _protect_cmpxchg_local(pcp, o, n) \ 106 124 ({ \ ··· 125 135 __retval; \ 126 136 }) 127 137 138 138 + #ifdef CONFIG_CPU_HAS_AMO 139 139 + 128 140 #define _percpu_add(pcp, val) \ 129 141 _pcp_protect(__percpu_add, pcp, val) 130 142 ··· 137 145 138 146 #define _percpu_or(pcp, val) \ 139 147 _pcp_protect(__percpu_or, pcp, val) 140 140 - 141 141 - #define _percpu_xchg(pcp, val) ((typeof(pcp)) \ 142 142 - _pcp_protect(__percpu_xchg, pcp, (unsigned long)(val))) 143 148 144 149 #define this_cpu_add_4(pcp, val) _percpu_add(pcp, val) 145 150 #define this_cpu_add_8(pcp, val) _percpu_add(pcp, val) ··· 150 161 #define this_cpu_or_4(pcp, val) _percpu_or(pcp, val) 151 162 #define this_cpu_or_8(pcp, val) _percpu_or(pcp, val) 152 163 164 164 + #endif 165 165 + 166 166 + #ifdef CONFIG_64BIT 167 167 + 153 168 #define this_cpu_read_1(pcp) _percpu_read(1, pcp) 154 169 #define this_cpu_read_2(pcp) _percpu_read(2, pcp) 155 170 #define this_cpu_read_4(pcp) _percpu_read(4, pcp) ··· 163 170 #define this_cpu_write_2(pcp, val) _percpu_write(2, pcp, val) 164 171 #define this_cpu_write_4(pcp, val) _percpu_write(4, pcp, val) 165 172 #define this_cpu_write_8(pcp, val) _percpu_write(8, pcp, val) 173 173 + 174 174 + #endif 175 175 + 176 176 + #define _percpu_xchg(pcp, val) ((typeof(pcp)) \ 177 177 + _pcp_protect(__percpu_xchg, pcp, (unsigned long)(val))) 166 178 167 179 #define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val) 168 180 #define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val)

+34 -2

arch/loongarch/include/asm/pgtable-bits.h

reviewed

··· 6 6 #define _ASM_PGTABLE_BITS_H 7 7 8 8 /* Page table bits */ 9 9 + 10 10 + #ifdef CONFIG_32BIT 11 11 + #define _PAGE_VALID_SHIFT 0 12 12 + #define _PAGE_ACCESSED_SHIFT 0 /* Reuse Valid for Accessed */ 13 13 + #define _PAGE_DIRTY_SHIFT 1 14 14 + #define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */ 15 15 + #define _CACHE_SHIFT 4 /* 4~5, two bits */ 16 16 + #define _PAGE_GLOBAL_SHIFT 6 17 17 + #define _PAGE_HUGE_SHIFT 6 /* HUGE is a PMD bit */ 18 18 + #define _PAGE_PRESENT_SHIFT 7 19 19 + #define _PAGE_PFN_SHIFT 8 20 20 + #define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */ 21 21 + #define _PAGE_SWP_EXCLUSIVE_SHIFT 13 22 22 + #define _PAGE_PFN_END_SHIFT 28 23 23 + #define _PAGE_WRITE_SHIFT 29 24 24 + #define _PAGE_MODIFIED_SHIFT 30 25 25 + #define _PAGE_PRESENT_INVALID_SHIFT 31 26 26 + #endif 27 27 + 28 28 + #ifdef CONFIG_64BIT 9 29 #define _PAGE_VALID_SHIFT 0 10 30 #define _PAGE_ACCESSED_SHIFT 0 /* Reuse Valid for Accessed */ 11 31 #define _PAGE_DIRTY_SHIFT 1 ··· 38 18 #define _PAGE_MODIFIED_SHIFT 9 39 19 #define _PAGE_PROTNONE_SHIFT 10 40 20 #define _PAGE_SPECIAL_SHIFT 11 41 41 - #define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */ 42 21 #define _PAGE_PFN_SHIFT 12 22 22 + #define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */ 43 23 #define _PAGE_SWP_EXCLUSIVE_SHIFT 23 44 24 #define _PAGE_PFN_END_SHIFT 48 45 25 #define _PAGE_PRESENT_INVALID_SHIFT 60 46 26 #define _PAGE_NO_READ_SHIFT 61 47 27 #define _PAGE_NO_EXEC_SHIFT 62 48 28 #define _PAGE_RPLV_SHIFT 63 29 29 + #endif 49 30 50 31 /* Used by software */ 51 32 #define _PAGE_PRESENT (_ULCAST_(1) << _PAGE_PRESENT_SHIFT) ··· 54 33 #define _PAGE_WRITE (_ULCAST_(1) << _PAGE_WRITE_SHIFT) 55 34 #define _PAGE_ACCESSED (_ULCAST_(1) << _PAGE_ACCESSED_SHIFT) 56 35 #define _PAGE_MODIFIED (_ULCAST_(1) << _PAGE_MODIFIED_SHIFT) 36 36 + #ifdef CONFIG_32BIT 37 37 + #define _PAGE_PROTNONE 0 38 38 + #define _PAGE_SPECIAL 0 39 39 + #else 57 40 #define _PAGE_PROTNONE (_ULCAST_(1) << _PAGE_PROTNONE_SHIFT) 58 41 #define _PAGE_SPECIAL (_ULCAST_(1) << _PAGE_SPECIAL_SHIFT) 42 42 + #endif 59 43 60 60 - /* We borrow bit 23 to store the exclusive marker in swap PTEs. */ 44 44 + /* We borrow bit 13/23 to store the exclusive marker in swap PTEs. */ 61 45 #define _PAGE_SWP_EXCLUSIVE (_ULCAST_(1) << _PAGE_SWP_EXCLUSIVE_SHIFT) 62 46 63 47 /* Used by TLB hardware (placed in EntryLo*) */ ··· 72 46 #define _PAGE_GLOBAL (_ULCAST_(1) << _PAGE_GLOBAL_SHIFT) 73 47 #define _PAGE_HUGE (_ULCAST_(1) << _PAGE_HUGE_SHIFT) 74 48 #define _PAGE_HGLOBAL (_ULCAST_(1) << _PAGE_HGLOBAL_SHIFT) 49 49 + #ifdef CONFIG_32BIT 50 50 + #define _PAGE_NO_READ 0 51 51 + #define _PAGE_NO_EXEC 0 52 52 + #define _PAGE_RPLV 0 53 53 + #else 75 54 #define _PAGE_NO_READ (_ULCAST_(1) << _PAGE_NO_READ_SHIFT) 76 55 #define _PAGE_NO_EXEC (_ULCAST_(1) << _PAGE_NO_EXEC_SHIFT) 77 56 #define _PAGE_RPLV (_ULCAST_(1) << _PAGE_RPLV_SHIFT) 57 57 + #endif 78 58 #define _CACHE_MASK (_ULCAST_(3) << _CACHE_SHIFT) 79 59 #define PFN_PTE_SHIFT (PAGE_SHIFT - 12 + _PAGE_PFN_SHIFT) 80 60

+58 -23

arch/loongarch/include/asm/pgtable.h

reviewed

··· 11 11 12 12 #include <linux/compiler.h> 13 13 #include <asm/addrspace.h> 14 14 + #include <asm/asm.h> 14 15 #include <asm/page.h> 15 16 #include <asm/pgtable-bits.h> 16 17 ··· 24 23 #endif 25 24 26 25 #if CONFIG_PGTABLE_LEVELS == 2 27 27 - #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) 26 26 + #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG)) 28 27 #elif CONFIG_PGTABLE_LEVELS == 3 29 29 - #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) 28 28 + #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG)) 30 29 #define PMD_SIZE (1UL << PMD_SHIFT) 31 30 #define PMD_MASK (~(PMD_SIZE-1)) 32 32 - #define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT - 3)) 31 31 + #define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT - PTRLOG)) 33 32 #elif CONFIG_PGTABLE_LEVELS == 4 34 34 - #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) 33 33 + #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG)) 35 34 #define PMD_SIZE (1UL << PMD_SHIFT) 36 35 #define PMD_MASK (~(PMD_SIZE-1)) 37 37 - #define PUD_SHIFT (PMD_SHIFT + (PAGE_SHIFT - 3)) 36 36 + #define PUD_SHIFT (PMD_SHIFT + (PAGE_SHIFT - PTRLOG)) 38 37 #define PUD_SIZE (1UL << PUD_SHIFT) 39 38 #define PUD_MASK (~(PUD_SIZE-1)) 40 40 - #define PGDIR_SHIFT (PUD_SHIFT + (PAGE_SHIFT - 3)) 39 39 + #define PGDIR_SHIFT (PUD_SHIFT + (PAGE_SHIFT - PTRLOG)) 41 40 #endif 42 41 43 42 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 44 43 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 45 44 46 46 - #define VA_BITS (PGDIR_SHIFT + (PAGE_SHIFT - 3)) 45 45 + #ifdef CONFIG_32BIT 46 46 + #define VA_BITS 32 47 47 + #else 48 48 + #define VA_BITS (PGDIR_SHIFT + (PAGE_SHIFT - PTRLOG)) 49 49 + #endif 47 50 48 48 - #define PTRS_PER_PGD (PAGE_SIZE >> 3) 51 51 + #define PTRS_PER_PGD (PAGE_SIZE >> PTRLOG) 49 52 #if CONFIG_PGTABLE_LEVELS > 3 50 50 - #define PTRS_PER_PUD (PAGE_SIZE >> 3) 53 53 + #define PTRS_PER_PUD (PAGE_SIZE >> PTRLOG) 51 54 #endif 52 55 #if CONFIG_PGTABLE_LEVELS > 2 53 53 - #define PTRS_PER_PMD (PAGE_SIZE >> 3) 56 56 + #define PTRS_PER_PMD (PAGE_SIZE >> PTRLOG) 54 57 #endif 55 55 - #define PTRS_PER_PTE (PAGE_SIZE >> 3) 58 58 + #define PTRS_PER_PTE (PAGE_SIZE >> PTRLOG) 56 59 60 60 + #ifdef CONFIG_32BIT 61 61 + #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 62 62 + #else 57 63 #define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1) 64 64 + #endif 58 65 59 66 #ifndef __ASSEMBLER__ 60 67 ··· 83 74 84 75 #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) 85 76 86 86 - /* 87 87 - * TLB refill handlers may also map the vmalloc area into xkvrange. 88 88 - * Avoid the first couple of pages so NULL pointer dereferences will 89 89 - * still reliably trap. 90 90 - */ 77 77 + #ifdef CONFIG_32BIT 78 78 + 79 79 + #define VMALLOC_START (vm_map_base + PCI_IOSIZE + (2 * PAGE_SIZE)) 80 80 + #define VMALLOC_END (FIXADDR_START - (2 * PAGE_SIZE)) 81 81 + 82 82 + #endif 83 83 + 84 84 + #ifdef CONFIG_64BIT 85 85 + 91 86 #define MODULES_VADDR (vm_map_base + PCI_IOSIZE + (2 * PAGE_SIZE)) 92 87 #define MODULES_END (MODULES_VADDR + SZ_256M) 93 88 ··· 118 105 119 106 #define KFENCE_AREA_START (VMEMMAP_END + 1) 120 107 #define KFENCE_AREA_END (KFENCE_AREA_START + KFENCE_AREA_SIZE - 1) 108 108 + 109 109 + #endif 121 110 122 111 #define ptep_get(ptep) READ_ONCE(*(ptep)) 123 112 #define pmdp_get(pmdp) READ_ONCE(*(pmdp)) ··· 292 277 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 293 278 * are !pte_none() && !pte_present(). 294 279 * 295 295 - * Format of swap PTEs: 280 280 + * Format of 32bit swap PTEs: 281 281 + * 282 282 + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 283 283 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 284 284 + * <------------ offset -------------> E <- type -> <-- zeroes --> 285 285 + * 286 286 + * E is the exclusive marker that is not stored in swap entries. 287 287 + * The zero'ed bits include _PAGE_PRESENT. 288 288 + * 289 289 + * Format of 64bit swap PTEs: 296 290 * 297 291 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 298 292 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 ··· 314 290 * E is the exclusive marker that is not stored in swap entries. 315 291 * The zero'ed bits include _PAGE_PRESENT and _PAGE_PROTNONE. 316 292 */ 317 317 - static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 318 318 - { pte_t pte; pte_val(pte) = ((type & 0x7f) << 16) | (offset << 24); return pte; } 319 293 320 320 - #define __swp_type(x) (((x).val >> 16) & 0x7f) 321 321 - #define __swp_offset(x) ((x).val >> 24) 294 294 + #define __SWP_TYPE_BITS (IS_ENABLED(CONFIG_32BIT) ? 5 : 7) 295 295 + #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) 296 296 + #define __SWP_TYPE_SHIFT (IS_ENABLED(CONFIG_32BIT) ? 8 : 16) 297 297 + #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT + 1) 298 298 + 299 299 + static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 300 300 + { 301 301 + pte_t pte; 302 302 + pte_val(pte) = ((type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT) | (offset << __SWP_OFFSET_SHIFT); 303 303 + return pte; 304 304 + } 305 305 + 306 306 + #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 307 307 + #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 322 308 #define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) 309 309 + 310 310 + #define __swp_entry_to_pte(x) __pte((x).val) 311 311 + #define __swp_entry_to_pmd(x) __pmd((x).val | _PAGE_HUGE) 323 312 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 324 324 - #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 325 313 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 326 326 - #define __swp_entry_to_pmd(x) ((pmd_t) { (x).val | _PAGE_HUGE }) 327 314 328 315 static inline bool pte_swp_exclusive(pte_t pte) 329 316 {

+27 -7

arch/loongarch/include/asm/stackframe.h

reviewed

··· 38 38 cfi_restore \reg \offset \docfi 39 39 .endm 40 40 41 41 + .macro SETUP_TWINS temp 42 42 + pcaddi t0, 0 43 43 + PTR_LI t1, ~TO_PHYS_MASK 44 44 + and t0, t0, t1 45 45 + ori t0, t0, (1 << 4 | 1) 46 46 + csrwr t0, LOONGARCH_CSR_DMWIN0 47 47 + PTR_LI t0, CSR_DMW1_INIT 48 48 + csrwr t0, LOONGARCH_CSR_DMWIN1 49 49 + .endm 50 50 + 51 51 + .macro SETUP_MODES temp 52 52 + /* Enable PG */ 53 53 + li.w \temp, 0xb0 # PLV=0, IE=0, PG=1 54 54 + csrwr \temp, LOONGARCH_CSR_CRMD 55 55 + li.w \temp, 0x04 # PLV=0, PIE=1, PWE=0 56 56 + csrwr \temp, LOONGARCH_CSR_PRMD 57 57 + li.w \temp, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 58 58 + csrwr \temp, LOONGARCH_CSR_EUEN 59 59 + .endm 60 60 + 41 61 .macro SETUP_DMWINS temp 42 42 - li.d \temp, CSR_DMW0_INIT # WUC, PLV0, 0x8000 xxxx xxxx xxxx 62 62 + PTR_LI \temp, CSR_DMW0_INIT # SUC, PLV0, LA32: 0x8xxx xxxx, LA64: 0x8000 xxxx xxxx xxxx 43 63 csrwr \temp, LOONGARCH_CSR_DMWIN0 44 44 - li.d \temp, CSR_DMW1_INIT # CAC, PLV0, 0x9000 xxxx xxxx xxxx 64 64 + PTR_LI \temp, CSR_DMW1_INIT # CAC, PLV0, LA32: 0xaxxx xxxx, LA64: 0x9000 xxxx xxxx xxxx 45 65 csrwr \temp, LOONGARCH_CSR_DMWIN1 46 46 - li.d \temp, CSR_DMW2_INIT # WUC, PLV0, 0xa000 xxxx xxxx xxxx 66 66 + PTR_LI \temp, CSR_DMW2_INIT # WUC, PLV0, LA32: unavailable, LA64: 0xa000 xxxx xxxx xxxx 47 67 csrwr \temp, LOONGARCH_CSR_DMWIN2 48 48 - li.d \temp, CSR_DMW3_INIT # 0x0, unused 68 68 + PTR_LI \temp, CSR_DMW3_INIT # 0x0, unused 49 69 csrwr \temp, LOONGARCH_CSR_DMWIN3 50 70 .endm 51 71 52 72 /* Jump to the runtime virtual address. */ 53 73 .macro JUMP_VIRT_ADDR temp1 temp2 54 54 - li.d \temp1, CACHE_BASE 74 74 + PTR_LI \temp1, CACHE_BASE 55 75 pcaddi \temp2, 0 56 56 - bstrins.d \temp1, \temp2, (DMW_PABITS - 1), 0 76 76 + PTR_BSTRINS \temp1, \temp2, (DMW_PABITS - 1), 0 57 77 jirl zero, \temp1, 0xc 58 78 .endm 59 79 ··· 191 171 andi t0, t0, 0x3 /* extract pplv bit */ 192 172 beqz t0, 9f 193 173 194 194 - li.d tp, ~_THREAD_MASK 174 174 + LONG_LI tp, ~_THREAD_MASK 195 175 and tp, tp, sp 196 176 cfi_st u0, PT_R21, \docfi 197 177 csrrd u0, PERCPU_BASE_KS

+2

arch/loongarch/include/asm/string.h

reviewed

··· 5 5 #ifndef _ASM_STRING_H 6 6 #define _ASM_STRING_H 7 7 8 8 + #ifdef CONFIG_64BIT 8 9 #define __HAVE_ARCH_MEMSET 9 10 extern void *memset(void *__s, int __c, size_t __count); 10 11 extern void *__memset(void *__s, int __c, size_t __count); ··· 17 16 #define __HAVE_ARCH_MEMMOVE 18 17 extern void *memmove(void *__dest, __const__ void *__src, size_t __n); 19 18 extern void *__memmove(void *__dest, __const__ void *__src, size_t __n); 19 19 + #endif 20 20 21 21 #if defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__) 22 22

+32 -1

arch/loongarch/include/asm/timex.h

reviewed

··· 18 18 19 19 static inline cycles_t get_cycles(void) 20 20 { 21 21 - return drdtime(); 21 21 + #ifdef CONFIG_32BIT 22 22 + return rdtime_l(); 23 23 + #else 24 24 + return rdtime_d(); 25 25 + #endif 26 26 + } 27 27 + 28 28 + #ifdef CONFIG_32BIT 29 29 + 30 30 + #define get_cycles_hi get_cycles_hi 31 31 + 32 32 + static inline cycles_t get_cycles_hi(void) 33 33 + { 34 34 + return rdtime_h(); 35 35 + } 36 36 + 37 37 + #endif 38 38 + 39 39 + static inline u64 get_cycles64(void) 40 40 + { 41 41 + #ifdef CONFIG_32BIT 42 42 + u32 hi, lo; 43 43 + 44 44 + do { 45 45 + hi = rdtime_h(); 46 46 + lo = rdtime_l(); 47 47 + } while (hi != rdtime_h()); 48 48 + 49 49 + return ((u64)hi << 32) | lo; 50 50 + #else 51 51 + return rdtime_d(); 52 52 + #endif 22 53 } 23 54 24 55 #endif /* __KERNEL__ */

+60 -3

arch/loongarch/include/asm/uaccess.h

reviewed

··· 19 19 #include <asm/asm-extable.h> 20 20 #include <asm-generic/access_ok.h> 21 21 22 22 + #define __LSW 0 23 23 + #define __MSW 1 24 24 + 22 25 extern u64 __ua_limit; 23 26 24 24 - #define __UA_ADDR ".dword" 27 27 + #ifdef CONFIG_64BIT 25 28 #define __UA_LIMIT __ua_limit 29 29 + #else 30 30 + #define __UA_LIMIT 0x80000000UL 31 31 + #endif 26 32 27 33 /* 28 34 * get_user: - Get a simple variable from user space. ··· 132 126 * 133 127 * Returns zero on success, or -EFAULT on error. 134 128 */ 129 129 + 135 130 #define __put_user(x, ptr) \ 136 131 ({ \ 137 132 int __pu_err = 0; \ ··· 153 146 case 1: __get_data_asm(val, "ld.b", ptr); break; \ 154 147 case 2: __get_data_asm(val, "ld.h", ptr); break; \ 155 148 case 4: __get_data_asm(val, "ld.w", ptr); break; \ 156 156 - case 8: __get_data_asm(val, "ld.d", ptr); break; \ 149 149 + case 8: __get_data_asm_8(val, ptr); break; \ 157 150 default: BUILD_BUG(); break; \ 158 151 } \ 159 152 } while (0) ··· 174 167 (val) = (__typeof__(*(ptr))) __gu_tmp; \ 175 168 } 176 169 170 170 + #ifdef CONFIG_64BIT 171 171 + #define __get_data_asm_8(val, ptr) \ 172 172 + __get_data_asm(val, "ld.d", ptr) 173 173 + #else /* !CONFIG_64BIT */ 174 174 + #define __get_data_asm_8(val, ptr) \ 175 175 + { \ 176 176 + u32 __lo, __hi; \ 177 177 + u32 __user *__ptr = (u32 __user *)(ptr); \ 178 178 + \ 179 179 + __asm__ __volatile__ ( \ 180 180 + "1:\n" \ 181 181 + " ld.w %1, %3 \n" \ 182 182 + "2:\n" \ 183 183 + " ld.w %2, %4 \n" \ 184 184 + "3:\n" \ 185 185 + _ASM_EXTABLE_UACCESS_ERR_ZERO(1b, 3b, %0, %1) \ 186 186 + _ASM_EXTABLE_UACCESS_ERR_ZERO(2b, 3b, %0, %1) \ 187 187 + : "+r" (__gu_err), "=&r" (__lo), "=r" (__hi) \ 188 188 + : "m" (__ptr[__LSW]), "m" (__ptr[__MSW])); \ 189 189 + if (__gu_err) \ 190 190 + __hi = 0; \ 191 191 + (val) = (__typeof__(val))((__typeof__((val)-(val))) \ 192 192 + ((((u64)__hi << 32) | __lo))); \ 193 193 + } 194 194 + #endif /* CONFIG_64BIT */ 195 195 + 177 196 #define __put_user_common(ptr, size) \ 178 197 do { \ 179 198 switch (size) { \ 180 199 case 1: __put_data_asm("st.b", ptr); break; \ 181 200 case 2: __put_data_asm("st.h", ptr); break; \ 182 201 case 4: __put_data_asm("st.w", ptr); break; \ 183 183 - case 8: __put_data_asm("st.d", ptr); break; \ 202 202 + case 8: __put_data_asm_8(ptr); break; \ 184 203 default: BUILD_BUG(); break; \ 185 204 } \ 186 205 } while (0) ··· 222 189 : "+r" (__pu_err), "=m" (__m(ptr)) \ 223 190 : "Jr" (__pu_val)); \ 224 191 } 192 192 + 193 193 + #ifdef CONFIG_64BIT 194 194 + #define __put_data_asm_8(ptr) \ 195 195 + __put_data_asm("st.d", ptr) 196 196 + #else /* !CONFIG_64BIT */ 197 197 + #define __put_data_asm_8(ptr) \ 198 198 + { \ 199 199 + u32 __user *__ptr = (u32 __user *)(ptr); \ 200 200 + u64 __x = (__typeof__((__pu_val)-(__pu_val)))(__pu_val); \ 201 201 + \ 202 202 + __asm__ __volatile__ ( \ 203 203 + "1:\n" \ 204 204 + " st.w %z3, %1 \n" \ 205 205 + "2:\n" \ 206 206 + " st.w %z4, %2 \n" \ 207 207 + "3:\n" \ 208 208 + _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %0) \ 209 209 + _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %0) \ 210 210 + : "+r" (__pu_err), \ 211 211 + "=m" (__ptr[__LSW]), \ 212 212 + "=m" (__ptr[__MSW]) \ 213 213 + : "rJ" (__x), "rJ" (__x >> 32)); \ 214 214 + } 215 215 + #endif /* CONFIG_64BIT */ 225 216 226 217 #define __get_kernel_nofault(dst, src, type, err_label) \ 227 218 do { \

+4

arch/loongarch/include/asm/vdso/gettimeofday.h

reviewed

··· 12 12 #include <asm/unistd.h> 13 13 #include <asm/vdso/vdso.h> 14 14 15 15 + #ifdef CONFIG_GENERIC_GETTIMEOFDAY 16 16 + 15 17 #define VDSO_HAS_CLOCK_GETRES 1 16 18 17 19 static __always_inline long gettimeofday_fallback( ··· 90 88 return true; 91 89 } 92 90 #define __arch_vdso_hres_capable loongarch_vdso_hres_capable 91 91 + 92 92 + #endif /* CONFIG_GENERIC_GETTIMEOFDAY */ 93 93 94 94 #endif /* !__ASSEMBLER__ */ 95 95

+1

arch/loongarch/include/uapi/asm/Kbuild

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 + syscall-y += unistd_32.h 2 3 syscall-y += unistd_64.h

+10

arch/loongarch/include/uapi/asm/ptrace.h

reviewed

··· 61 61 struct user_watch_state { 62 62 __u64 dbg_info; 63 63 struct { 64 64 + #if __BITS_PER_LONG == 32 65 65 + __u32 addr; 66 66 + __u32 mask; 67 67 + #else 64 68 __u64 addr; 65 69 __u64 mask; 70 70 + #endif 66 71 __u32 ctrl; 67 72 __u32 pad; 68 73 } dbg_regs[8]; ··· 76 71 struct user_watch_state_v2 { 77 72 __u64 dbg_info; 78 73 struct { 74 74 + #if __BITS_PER_LONG == 32 75 75 + __u32 addr; 76 76 + __u32 mask; 77 77 + #else 79 78 __u64 addr; 80 79 __u64 mask; 80 80 + #endif 81 81 __u32 ctrl; 82 82 __u32 pad; 83 83 } dbg_regs[14];

+6

arch/loongarch/include/uapi/asm/unistd.h

reviewed

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 2 3 3 + #include <asm/bitsperlong.h> 4 4 + 5 5 + #if __BITS_PER_LONG == 32 6 6 + #include <asm/unistd_32.h> 7 7 + #else 3 8 #include <asm/unistd_64.h> 9 9 + #endif

+1

arch/loongarch/kernel/Makefile.syscalls

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 3 3 # No special ABIs on loongarch so far 4 4 + syscall_abis_32 += 4 5 syscall_abis_64 +=

+12 -1

arch/loongarch/kernel/cpu-probe.c

reviewed

··· 106 106 107 107 static void cpu_probe_addrbits(struct cpuinfo_loongarch *c) 108 108 { 109 109 - #ifdef __NEED_ADDRBITS_PROBE 109 109 + #ifdef CONFIG_32BIT 110 110 + c->pabits = cpu_pabits; 111 111 + c->vabits = cpu_vabits; 112 112 + vm_map_base = KVRANGE; 113 113 + #else 110 114 c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4; 111 115 c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12; 112 116 vm_map_base = 0UL - (1UL << c->vabits); ··· 302 298 return; 303 299 } 304 300 301 301 + #ifdef CONFIG_64BIT 305 302 *vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR); 306 303 *cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME); 304 304 + #else 305 305 + *vendor = iocsr_read32(LOONGARCH_IOCSR_VENDOR) | 306 306 + (u64)iocsr_read32(LOONGARCH_IOCSR_VENDOR + 4) << 32; 307 307 + *cpuname = iocsr_read32(LOONGARCH_IOCSR_CPUNAME) | 308 308 + (u64)iocsr_read32(LOONGARCH_IOCSR_CPUNAME + 4) << 32; 309 309 + #endif 307 310 308 311 if (!__cpu_full_name[cpu]) { 309 312 if (((char *)vendor)[0] == 0)

+4

arch/loongarch/kernel/efi-header.S

reviewed

··· 9 9 .macro __EFI_PE_HEADER 10 10 .long IMAGE_NT_SIGNATURE 11 11 .Lcoff_header: 12 12 + #ifdef CONFIG_32BIT 13 13 + .short IMAGE_FILE_MACHINE_LOONGARCH32 /* Machine */ 14 14 + #else 12 15 .short IMAGE_FILE_MACHINE_LOONGARCH64 /* Machine */ 16 16 + #endif 13 17 .short .Lsection_count /* NumberOfSections */ 14 18 .long 0 /* TimeDateStamp */ 15 19 .long 0 /* PointerToSymbolTable */

+3 -1

arch/loongarch/kernel/efi.c

reviewed

··· 115 115 116 116 efi_systab_report_header(&efi_systab->hdr, efi_systab->fw_vendor); 117 117 118 118 - set_bit(EFI_64BIT, &efi.flags); 118 118 + if (IS_ENABLED(CONFIG_64BIT)) 119 119 + set_bit(EFI_64BIT, &efi.flags); 120 120 + 119 121 efi_nr_tables = efi_systab->nr_tables; 120 122 efi_config_table = (unsigned long)efi_systab->tables; 121 123

+11 -11

arch/loongarch/kernel/entry.S

reviewed

··· 23 23 UNWIND_HINT_UNDEFINED 24 24 csrrd t0, PERCPU_BASE_KS 25 25 la.pcrel t1, kernelsp 26 26 - add.d t1, t1, t0 26 26 + PTR_ADD t1, t1, t0 27 27 move t2, sp 28 28 - ld.d sp, t1, 0 28 28 + PTR_L sp, t1, 0 29 29 30 30 - addi.d sp, sp, -PT_SIZE 30 30 + PTR_ADDI sp, sp, -PT_SIZE 31 31 cfi_st t2, PT_R3 32 32 cfi_rel_offset sp, PT_R3 33 33 - st.d zero, sp, PT_R0 33 33 + LONG_S zero, sp, PT_R0 34 34 csrrd t2, LOONGARCH_CSR_PRMD 35 35 - st.d t2, sp, PT_PRMD 35 35 + LONG_S t2, sp, PT_PRMD 36 36 csrrd t2, LOONGARCH_CSR_CRMD 37 37 - st.d t2, sp, PT_CRMD 37 37 + LONG_S t2, sp, PT_CRMD 38 38 csrrd t2, LOONGARCH_CSR_EUEN 39 39 - st.d t2, sp, PT_EUEN 39 39 + LONG_S t2, sp, PT_EUEN 40 40 csrrd t2, LOONGARCH_CSR_ECFG 41 41 - st.d t2, sp, PT_ECFG 41 41 + LONG_S t2, sp, PT_ECFG 42 42 csrrd t2, LOONGARCH_CSR_ESTAT 43 43 - st.d t2, sp, PT_ESTAT 43 43 + LONG_S t2, sp, PT_ESTAT 44 44 cfi_st ra, PT_R1 45 45 cfi_st a0, PT_R4 46 46 cfi_st a1, PT_R5 ··· 51 51 cfi_st a6, PT_R10 52 52 cfi_st a7, PT_R11 53 53 csrrd ra, LOONGARCH_CSR_ERA 54 54 - st.d ra, sp, PT_ERA 54 54 + LONG_S ra, sp, PT_ERA 55 55 cfi_rel_offset ra, PT_ERA 56 56 57 57 cfi_st tp, PT_R2 ··· 67 67 #endif 68 68 69 69 move u0, t0 70 70 - li.d tp, ~_THREAD_MASK 70 70 + LONG_LI tp, ~_THREAD_MASK 71 71 and tp, tp, sp 72 72 73 73 move a0, sp

+4 -1

arch/loongarch/kernel/env.c

reviewed

··· 72 72 73 73 clk = of_clk_get(np, 0); 74 74 of_node_put(np); 75 75 + cpu_clock_freq = 200 * 1000 * 1000; 75 76 76 76 - if (IS_ERR(clk)) 77 77 + if (IS_ERR(clk)) { 78 78 + pr_warn("No valid CPU clock freq, assume 200MHz.\n"); 77 79 return -ENODEV; 80 80 + } 78 81 79 82 cpu_clock_freq = clk_get_rate(clk); 80 83 clk_put(clk);

+111

arch/loongarch/kernel/fpu.S

reviewed

··· 96 96 EX fld.d $f31, \base, (31 * FPU_REG_WIDTH) 97 97 .endm 98 98 99 99 + #ifdef CONFIG_32BIT 100 100 + .macro sc_save_fcc thread tmp0 tmp1 101 101 + movcf2gr \tmp0, $fcc0 102 102 + move \tmp1, \tmp0 103 103 + movcf2gr \tmp0, $fcc1 104 104 + bstrins.w \tmp1, \tmp0, 15, 8 105 105 + movcf2gr \tmp0, $fcc2 106 106 + bstrins.w \tmp1, \tmp0, 23, 16 107 107 + movcf2gr \tmp0, $fcc3 108 108 + bstrins.w \tmp1, \tmp0, 31, 24 109 109 + EX st.w \tmp1, \thread, THREAD_FCC 110 110 + movcf2gr \tmp0, $fcc4 111 111 + move \tmp1, \tmp0 112 112 + movcf2gr \tmp0, $fcc5 113 113 + bstrins.w \tmp1, \tmp0, 15, 8 114 114 + movcf2gr \tmp0, $fcc6 115 115 + bstrins.w \tmp1, \tmp0, 23, 16 116 116 + movcf2gr \tmp0, $fcc7 117 117 + bstrins.w \tmp1, \tmp0, 31, 24 118 118 + EX st.w \tmp1, \thread, (THREAD_FCC + 4) 119 119 + .endm 120 120 + 121 121 + .macro sc_restore_fcc thread tmp0 tmp1 122 122 + EX ld.w \tmp0, \thread, THREAD_FCC 123 123 + bstrpick.w \tmp1, \tmp0, 7, 0 124 124 + movgr2cf $fcc0, \tmp1 125 125 + bstrpick.w \tmp1, \tmp0, 15, 8 126 126 + movgr2cf $fcc1, \tmp1 127 127 + bstrpick.w \tmp1, \tmp0, 23, 16 128 128 + movgr2cf $fcc2, \tmp1 129 129 + bstrpick.w \tmp1, \tmp0, 31, 24 130 130 + movgr2cf $fcc3, \tmp1 131 131 + EX ld.w \tmp0, \thread, (THREAD_FCC + 4) 132 132 + bstrpick.w \tmp1, \tmp0, 7, 0 133 133 + movgr2cf $fcc4, \tmp1 134 134 + bstrpick.w \tmp1, \tmp0, 15, 8 135 135 + movgr2cf $fcc5, \tmp1 136 136 + bstrpick.w \tmp1, \tmp0, 23, 16 137 137 + movgr2cf $fcc6, \tmp1 138 138 + bstrpick.w \tmp1, \tmp0, 31, 24 139 139 + movgr2cf $fcc7, \tmp1 140 140 + .endm 141 141 + #else 99 142 .macro sc_save_fcc base, tmp0, tmp1 100 143 movcf2gr \tmp0, $fcc0 101 144 move \tmp1, \tmp0 ··· 178 135 bstrpick.d \tmp1, \tmp0, 63, 56 179 136 movgr2cf $fcc7, \tmp1 180 137 .endm 138 138 + #endif 181 139 182 140 .macro sc_save_fcsr base, tmp0 183 141 movfcsr2gr \tmp0, fcsr0 ··· 454 410 455 411 li.w t1, -1 # SNaN 456 412 413 413 + #ifdef CONFIG_32BIT 414 414 + movgr2fr.w $f0, t1 415 415 + movgr2frh.w $f0, t1 416 416 + movgr2fr.w $f1, t1 417 417 + movgr2frh.w $f1, t1 418 418 + movgr2fr.w $f2, t1 419 419 + movgr2frh.w $f2, t1 420 420 + movgr2fr.w $f3, t1 421 421 + movgr2frh.w $f3, t1 422 422 + movgr2fr.w $f4, t1 423 423 + movgr2frh.w $f4, t1 424 424 + movgr2fr.w $f5, t1 425 425 + movgr2frh.w $f5, t1 426 426 + movgr2fr.w $f6, t1 427 427 + movgr2frh.w $f6, t1 428 428 + movgr2fr.w $f7, t1 429 429 + movgr2frh.w $f7, t1 430 430 + movgr2fr.w $f8, t1 431 431 + movgr2frh.w $f8, t1 432 432 + movgr2fr.w $f9, t1 433 433 + movgr2frh.w $f9, t1 434 434 + movgr2fr.w $f10, t1 435 435 + movgr2frh.w $f10, t1 436 436 + movgr2fr.w $f11, t1 437 437 + movgr2frh.w $f11, t1 438 438 + movgr2fr.w $f12, t1 439 439 + movgr2frh.w $f12, t1 440 440 + movgr2fr.w $f13, t1 441 441 + movgr2frh.w $f13, t1 442 442 + movgr2fr.w $f14, t1 443 443 + movgr2frh.w $f14, t1 444 444 + movgr2fr.w $f15, t1 445 445 + movgr2frh.w $f15, t1 446 446 + movgr2fr.w $f16, t1 447 447 + movgr2frh.w $f16, t1 448 448 + movgr2fr.w $f17, t1 449 449 + movgr2frh.w $f17, t1 450 450 + movgr2fr.w $f18, t1 451 451 + movgr2frh.w $f18, t1 452 452 + movgr2fr.w $f19, t1 453 453 + movgr2frh.w $f19, t1 454 454 + movgr2fr.w $f20, t1 455 455 + movgr2frh.w $f20, t1 456 456 + movgr2fr.w $f21, t1 457 457 + movgr2frh.w $f21, t1 458 458 + movgr2fr.w $f22, t1 459 459 + movgr2frh.w $f22, t1 460 460 + movgr2fr.w $f23, t1 461 461 + movgr2frh.w $f23, t1 462 462 + movgr2fr.w $f24, t1 463 463 + movgr2frh.w $f24, t1 464 464 + movgr2fr.w $f25, t1 465 465 + movgr2frh.w $f25, t1 466 466 + movgr2fr.w $f26, t1 467 467 + movgr2frh.w $f26, t1 468 468 + movgr2fr.w $f27, t1 469 469 + movgr2frh.w $f27, t1 470 470 + movgr2fr.w $f28, t1 471 471 + movgr2frh.w $f28, t1 472 472 + movgr2fr.w $f29, t1 473 473 + movgr2frh.w $f29, t1 474 474 + movgr2fr.w $f30, t1 475 475 + movgr2frh.w $f30, t1 476 476 + movgr2fr.w $f31, t1 477 477 + movgr2frh.w $f31, t1 478 478 + #else 457 479 movgr2fr.d $f0, t1 458 480 movgr2fr.d $f1, t1 459 481 movgr2fr.d $f2, t1 ··· 552 442 movgr2fr.d $f29, t1 553 443 movgr2fr.d $f30, t1 554 444 movgr2fr.d $f31, t1 445 445 + #endif 555 446 556 447 jr ra 557 448 SYM_FUNC_END(_init_fpu)

+17 -22

arch/loongarch/kernel/head.S

reviewed

··· 43 43 44 44 SYM_CODE_START(kernel_entry) # kernel entry point 45 45 46 46 - /* Config direct window and set PG */ 47 47 - SETUP_DMWINS t0 46 46 + SETUP_TWINS 47 47 + SETUP_MODES t0 48 48 JUMP_VIRT_ADDR t0, t1 49 49 - 50 50 - /* Enable PG */ 51 51 - li.w t0, 0xb0 # PLV=0, IE=0, PG=1 52 52 - csrwr t0, LOONGARCH_CSR_CRMD 53 53 - li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 54 54 - csrwr t0, LOONGARCH_CSR_PRMD 55 55 - li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 56 56 - csrwr t0, LOONGARCH_CSR_EUEN 49 49 + SETUP_DMWINS t0 57 50 58 51 la.pcrel t0, __bss_start # clear .bss 59 59 - st.d zero, t0, 0 52 52 + LONG_S zero, t0, 0 60 53 la.pcrel t1, __bss_stop - LONGSIZE 61 54 1: 62 62 - addi.d t0, t0, LONGSIZE 63 63 - st.d zero, t0, 0 55 55 + PTR_ADDI t0, t0, LONGSIZE 56 56 + LONG_S zero, t0, 0 64 57 bne t0, t1, 1b 65 58 66 59 la.pcrel t0, fw_arg0 67 67 - st.d a0, t0, 0 # firmware arguments 60 60 + PTR_S a0, t0, 0 # firmware arguments 68 61 la.pcrel t0, fw_arg1 69 69 - st.d a1, t0, 0 62 62 + PTR_S a1, t0, 0 70 63 la.pcrel t0, fw_arg2 71 71 - st.d a2, t0, 0 64 64 + PTR_S a2, t0, 0 72 65 73 66 #ifdef CONFIG_PAGE_SIZE_4KB 74 74 - li.d t0, 0 75 75 - li.d t1, CSR_STFILL 67 67 + LONG_LI t0, 0 68 68 + LONG_LI t1, CSR_STFILL 76 69 csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1 77 70 #endif 78 71 /* KSave3 used for percpu base, initialized as 0 */ ··· 91 98 92 99 /* Jump to the new kernel: new_pc = current_pc + random_offset */ 93 100 pcaddi t0, 0 94 94 - add.d t0, t0, a0 101 101 + PTR_ADD t0, t0, a0 95 102 jirl zero, t0, 0xc 96 103 #endif /* CONFIG_RANDOMIZE_BASE */ 97 104 ··· 114 121 */ 115 122 SYM_CODE_START(smpboot_entry) 116 123 117 117 - SETUP_DMWINS t0 124 124 + SETUP_TWINS 125 125 + SETUP_MODES t0 118 126 JUMP_VIRT_ADDR t0, t1 127 127 + SETUP_DMWINS t0 119 128 120 129 #ifdef CONFIG_PAGE_SIZE_4KB 121 121 - li.d t0, 0 122 122 - li.d t1, CSR_STFILL 130 130 + LONG_LI t0, 0 131 131 + LONG_LI t1, CSR_STFILL 123 132 csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1 124 133 #endif 125 134 /* Enable PG */

+1

arch/loongarch/kernel/module-sections.c

reviewed

··· 93 93 (*plts)++; 94 94 break; 95 95 case R_LARCH_GOT_PC_HI20: 96 96 + case R_LARCH_GOT_PCADD_HI20: 96 97 (*gots)++; 97 98 break; 98 99 default:

+150 -54

arch/loongarch/kernel/module.c

reviewed

··· 22 22 #include <asm/inst.h> 23 23 #include <asm/unwind.h> 24 24 25 25 - static int rela_stack_push(s64 stack_value, s64 *rela_stack, size_t *rela_stack_top) 25 25 + /* 26 26 + * reloc_rela_handler() - Apply a particular relocation to a module 27 27 + * @mod: the module to apply the reloc to 28 28 + * @location: the address at which the reloc is to be applied 29 29 + * @v: the value of the reloc, with addend for RELA-style 30 30 + * @rela_stack: the stack used for store relocation info, LOCAL to THIS module 31 31 + * @rela_stac_top: where the stack operation(pop/push) applies to 32 32 + * 33 33 + * Return: 0 upon success, else -ERRNO 34 34 + */ 35 35 + typedef int (*reloc_rela_handler)(struct module *mod, u32 *location, Elf_Addr v, 36 36 + long *rela_stack, size_t *rela_stack_top, unsigned int type); 37 37 + 38 38 + static int rela_stack_push(long stack_value, long *rela_stack, size_t *rela_stack_top) 26 39 { 27 40 if (*rela_stack_top >= RELA_STACK_DEPTH) 28 41 return -ENOEXEC; 29 42 30 43 rela_stack[(*rela_stack_top)++] = stack_value; 31 31 - pr_debug("%s stack_value = 0x%llx\n", __func__, stack_value); 44 44 + pr_debug("%s stack_value = 0x%lx\n", __func__, stack_value); 32 45 33 46 return 0; 34 47 } 35 48 36 36 - static int rela_stack_pop(s64 *stack_value, s64 *rela_stack, size_t *rela_stack_top) 49 49 + static int rela_stack_pop(long *stack_value, long *rela_stack, size_t *rela_stack_top) 37 50 { 38 51 if (*rela_stack_top == 0) 39 52 return -ENOEXEC; 40 53 41 54 *stack_value = rela_stack[--(*rela_stack_top)]; 42 42 - pr_debug("%s stack_value = 0x%llx\n", __func__, *stack_value); 55 55 + pr_debug("%s stack_value = 0x%lx\n", __func__, *stack_value); 43 56 44 57 return 0; 45 58 } 46 59 47 60 static int apply_r_larch_none(struct module *mod, u32 *location, Elf_Addr v, 48 48 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 61 61 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 49 62 { 50 63 return 0; 51 64 } 52 65 53 66 static int apply_r_larch_error(struct module *me, u32 *location, Elf_Addr v, 54 54 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 67 67 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 55 68 { 56 69 pr_err("%s: Unsupport relocation type %u, please add its support.\n", me->name, type); 57 70 return -EINVAL; 58 71 } 59 72 60 73 static int apply_r_larch_32(struct module *mod, u32 *location, Elf_Addr v, 61 61 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 74 74 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 62 75 { 63 76 *location = v; 64 77 return 0; 65 78 } 66 79 80 80 + #ifdef CONFIG_32BIT 81 81 + #define apply_r_larch_64 apply_r_larch_error 82 82 + #else 67 83 static int apply_r_larch_64(struct module *mod, u32 *location, Elf_Addr v, 68 68 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 84 84 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 69 85 { 70 86 *(Elf_Addr *)location = v; 71 87 return 0; 72 88 } 89 89 + #endif 73 90 74 91 static int apply_r_larch_sop_push_pcrel(struct module *mod, u32 *location, Elf_Addr v, 75 75 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 92 92 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 76 93 { 77 77 - return rela_stack_push(v - (u64)location, rela_stack, rela_stack_top); 94 94 + return rela_stack_push(v - (unsigned long)location, rela_stack, rela_stack_top); 78 95 } 79 96 80 97 static int apply_r_larch_sop_push_absolute(struct module *mod, u32 *location, Elf_Addr v, 81 81 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 98 98 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 82 99 { 83 100 return rela_stack_push(v, rela_stack, rela_stack_top); 84 101 } 85 102 86 103 static int apply_r_larch_sop_push_dup(struct module *mod, u32 *location, Elf_Addr v, 87 87 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 104 104 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 88 105 { 89 106 int err = 0; 90 90 - s64 opr1; 107 107 + long opr1; 91 108 92 109 err = rela_stack_pop(&opr1, rela_stack, rela_stack_top); 93 110 if (err) ··· 121 104 122 105 static int apply_r_larch_sop_push_plt_pcrel(struct module *mod, 123 106 Elf_Shdr *sechdrs, u32 *location, Elf_Addr v, 124 124 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 107 107 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 125 108 { 126 109 ptrdiff_t offset = (void *)v - (void *)location; 127 110 ··· 135 118 } 136 119 137 120 static int apply_r_larch_sop(struct module *mod, u32 *location, Elf_Addr v, 138 138 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 121 121 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 139 122 { 140 123 int err = 0; 141 141 - s64 opr1, opr2, opr3; 124 124 + long opr1, opr2, opr3; 142 125 143 126 if (type == R_LARCH_SOP_IF_ELSE) { 144 127 err = rela_stack_pop(&opr3, rela_stack, rela_stack_top); ··· 181 164 } 182 165 183 166 static int apply_r_larch_sop_imm_field(struct module *mod, u32 *location, Elf_Addr v, 184 184 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 167 167 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 185 168 { 186 169 int err = 0; 187 187 - s64 opr1; 170 170 + long opr1; 188 171 union loongarch_instruction *insn = (union loongarch_instruction *)location; 189 172 190 173 err = rela_stack_pop(&opr1, rela_stack, rela_stack_top); ··· 261 244 } 262 245 263 246 overflow: 264 264 - pr_err("module %s: opr1 = 0x%llx overflow! dangerous %s (%u) relocation\n", 247 247 + pr_err("module %s: opr1 = 0x%lx overflow! dangerous %s (%u) relocation\n", 265 248 mod->name, opr1, __func__, type); 266 249 return -ENOEXEC; 267 250 268 251 unaligned: 269 269 - pr_err("module %s: opr1 = 0x%llx unaligned! dangerous %s (%u) relocation\n", 252 252 + pr_err("module %s: opr1 = 0x%lx unaligned! dangerous %s (%u) relocation\n", 270 253 mod->name, opr1, __func__, type); 271 254 return -ENOEXEC; 272 255 } 273 256 274 257 static int apply_r_larch_add_sub(struct module *mod, u32 *location, Elf_Addr v, 275 275 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 258 258 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 276 259 { 277 260 switch (type) { 278 261 case R_LARCH_ADD32: 279 262 *(s32 *)location += v; 280 263 return 0; 281 281 - case R_LARCH_ADD64: 282 282 - *(s64 *)location += v; 283 283 - return 0; 284 264 case R_LARCH_SUB32: 285 265 *(s32 *)location -= v; 286 266 return 0; 267 267 + #ifdef CONFIG_64BIT 268 268 + case R_LARCH_ADD64: 269 269 + *(s64 *)location += v; 270 270 + return 0; 287 271 case R_LARCH_SUB64: 288 272 *(s64 *)location -= v; 273 273 + #endif 289 274 return 0; 290 275 default: 291 276 pr_err("%s: Unsupport relocation type %u\n", mod->name, type); ··· 297 278 298 279 static int apply_r_larch_b26(struct module *mod, 299 280 Elf_Shdr *sechdrs, u32 *location, Elf_Addr v, 300 300 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 281 281 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 301 282 { 302 283 ptrdiff_t offset = (void *)v - (void *)location; 303 284 union loongarch_instruction *insn = (union loongarch_instruction *)location; ··· 329 310 return 0; 330 311 } 331 312 313 313 + static int apply_r_larch_pcadd(struct module *mod, u32 *location, Elf_Addr v, 314 314 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 315 315 + { 316 316 + union loongarch_instruction *insn = (union loongarch_instruction *)location; 317 317 + /* Use s32 for a sign-extension deliberately. */ 318 318 + s32 offset_hi20 = (void *)((v + 0x800)) - (void *)((Elf_Addr)location); 319 319 + 320 320 + switch (type) { 321 321 + case R_LARCH_PCADD_LO12: 322 322 + insn->reg2i12_format.immediate = v & 0xfff; 323 323 + break; 324 324 + case R_LARCH_PCADD_HI20: 325 325 + v = offset_hi20 >> 12; 326 326 + insn->reg1i20_format.immediate = v & 0xfffff; 327 327 + break; 328 328 + default: 329 329 + pr_err("%s: Unsupport relocation type %u\n", mod->name, type); 330 330 + return -EINVAL; 331 331 + } 332 332 + 333 333 + return 0; 334 334 + } 335 335 + 332 336 static int apply_r_larch_pcala(struct module *mod, u32 *location, Elf_Addr v, 333 333 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 337 337 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 334 338 { 335 339 union loongarch_instruction *insn = (union loongarch_instruction *)location; 336 340 /* Use s32 for a sign-extension deliberately. */ 337 341 s32 offset_hi20 = (void *)((v + 0x800) & ~0xfff) - 338 342 (void *)((Elf_Addr)location & ~0xfff); 343 343 + #ifdef CONFIG_64BIT 339 344 Elf_Addr anchor = (((Elf_Addr)location) & ~0xfff) + offset_hi20; 340 345 ptrdiff_t offset_rem = (void *)v - (void *)anchor; 346 346 + #endif 341 347 342 348 switch (type) { 343 349 case R_LARCH_PCALA_LO12: ··· 372 328 v = offset_hi20 >> 12; 373 329 insn->reg1i20_format.immediate = v & 0xfffff; 374 330 break; 331 331 + #ifdef CONFIG_64BIT 375 332 case R_LARCH_PCALA64_LO20: 376 333 v = offset_rem >> 32; 377 334 insn->reg1i20_format.immediate = v & 0xfffff; ··· 381 336 v = offset_rem >> 52; 382 337 insn->reg2i12_format.immediate = v & 0xfff; 383 338 break; 339 339 + #endif 384 340 default: 385 341 pr_err("%s: Unsupport relocation type %u\n", mod->name, type); 386 342 return -EINVAL; ··· 392 346 393 347 static int apply_r_larch_got_pc(struct module *mod, 394 348 Elf_Shdr *sechdrs, u32 *location, Elf_Addr v, 395 395 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 349 349 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 396 350 { 397 397 - Elf_Addr got = module_emit_got_entry(mod, sechdrs, v); 351 351 + reloc_rela_handler got_handler; 398 352 399 399 - if (!got) 400 400 - return -EINVAL; 353 353 + if (type != R_LARCH_GOT_PCADD_LO12) { 354 354 + v = module_emit_got_entry(mod, sechdrs, v); 355 355 + if (!v) 356 356 + return -EINVAL; 357 357 + } 401 358 402 359 switch (type) { 403 360 case R_LARCH_GOT_PC_LO12: 404 361 type = R_LARCH_PCALA_LO12; 362 362 + got_handler = apply_r_larch_pcala; 405 363 break; 406 364 case R_LARCH_GOT_PC_HI20: 407 365 type = R_LARCH_PCALA_HI20; 366 366 + got_handler = apply_r_larch_pcala; 367 367 + break; 368 368 + case R_LARCH_GOT_PCADD_LO12: 369 369 + type = R_LARCH_PCADD_LO12; 370 370 + got_handler = apply_r_larch_pcadd; 371 371 + break; 372 372 + case R_LARCH_GOT_PCADD_HI20: 373 373 + type = R_LARCH_PCADD_HI20; 374 374 + got_handler = apply_r_larch_pcadd; 408 375 break; 409 376 default: 410 377 pr_err("%s: Unsupport relocation type %u\n", mod->name, type); 411 378 return -EINVAL; 412 379 } 413 380 414 414 - return apply_r_larch_pcala(mod, location, got, rela_stack, rela_stack_top, type); 381 381 + return got_handler(mod, location, v, rela_stack, rela_stack_top, type); 415 382 } 416 383 417 384 static int apply_r_larch_32_pcrel(struct module *mod, u32 *location, Elf_Addr v, 418 418 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 385 385 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 419 386 { 420 387 ptrdiff_t offset = (void *)v - (void *)location; 421 388 ··· 436 377 return 0; 437 378 } 438 379 380 380 + #ifdef CONFIG_32BIT 381 381 + #define apply_r_larch_64_pcrel apply_r_larch_error 382 382 + #else 439 383 static int apply_r_larch_64_pcrel(struct module *mod, u32 *location, Elf_Addr v, 440 440 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type) 384 384 + long *rela_stack, size_t *rela_stack_top, unsigned int type) 441 385 { 442 386 ptrdiff_t offset = (void *)v - (void *)location; 443 387 444 388 *(u64 *)location = offset; 445 389 return 0; 446 390 } 447 447 - 448 448 - /* 449 449 - * reloc_handlers_rela() - Apply a particular relocation to a module 450 450 - * @mod: the module to apply the reloc to 451 451 - * @location: the address at which the reloc is to be applied 452 452 - * @v: the value of the reloc, with addend for RELA-style 453 453 - * @rela_stack: the stack used for store relocation info, LOCAL to THIS module 454 454 - * @rela_stac_top: where the stack operation(pop/push) applies to 455 455 - * 456 456 - * Return: 0 upon success, else -ERRNO 457 457 - */ 458 458 - typedef int (*reloc_rela_handler)(struct module *mod, u32 *location, Elf_Addr v, 459 459 - s64 *rela_stack, size_t *rela_stack_top, unsigned int type); 391 391 + #endif 460 392 461 393 /* The handlers for known reloc types */ 462 394 static reloc_rela_handler reloc_rela_handlers[] = { 463 463 - [R_LARCH_NONE ... R_LARCH_64_PCREL] = apply_r_larch_error, 395 395 + [R_LARCH_NONE ... R_LARCH_TLS_DESC_PCADD_LO12] = apply_r_larch_error, 464 396 465 397 [R_LARCH_NONE] = apply_r_larch_none, 466 398 [R_LARCH_32] = apply_r_larch_32, ··· 464 414 [R_LARCH_SOP_SUB ... R_LARCH_SOP_IF_ELSE] = apply_r_larch_sop, 465 415 [R_LARCH_SOP_POP_32_S_10_5 ... R_LARCH_SOP_POP_32_U] = apply_r_larch_sop_imm_field, 466 416 [R_LARCH_ADD32 ... R_LARCH_SUB64] = apply_r_larch_add_sub, 467 467 - [R_LARCH_PCALA_HI20...R_LARCH_PCALA64_HI12] = apply_r_larch_pcala, 417 417 + [R_LARCH_PCADD_HI20 ... R_LARCH_PCADD_LO12] = apply_r_larch_pcadd, 418 418 + [R_LARCH_PCALA_HI20 ... R_LARCH_PCALA64_HI12] = apply_r_larch_pcala, 468 419 [R_LARCH_32_PCREL] = apply_r_larch_32_pcrel, 469 420 [R_LARCH_64_PCREL] = apply_r_larch_64_pcrel, 470 421 }; ··· 474 423 unsigned int symindex, unsigned int relsec, 475 424 struct module *mod) 476 425 { 477 477 - int i, err; 478 478 - unsigned int type; 479 479 - s64 rela_stack[RELA_STACK_DEPTH]; 426 426 + int err; 427 427 + unsigned int i, idx, type; 428 428 + unsigned int num_relocations; 429 429 + long rela_stack[RELA_STACK_DEPTH]; 480 430 size_t rela_stack_top = 0; 481 431 reloc_rela_handler handler; 482 432 void *location; ··· 488 436 pr_debug("%s: Applying relocate section %u to %u\n", __func__, relsec, 489 437 sechdrs[relsec].sh_info); 490 438 439 439 + idx = 0; 491 440 rela_stack_top = 0; 492 492 - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { 441 441 + num_relocations = sechdrs[relsec].sh_size / sizeof(*rel); 442 442 + for (i = 0; i < num_relocations; i++) { 493 443 /* This is where to make the change */ 494 444 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + rel[i].r_offset; 495 445 /* This is the symbol it is referring to */ ··· 516 462 return -EINVAL; 517 463 } 518 464 519 519 - pr_debug("type %d st_value %llx r_addend %llx loc %llx\n", 465 465 + pr_debug("type %d st_value %lx r_addend %lx loc %lx\n", 520 466 (int)ELF_R_TYPE(rel[i].r_info), 521 521 - sym->st_value, rel[i].r_addend, (u64)location); 467 467 + (unsigned long)sym->st_value, (unsigned long)rel[i].r_addend, (unsigned long)location); 522 468 523 469 v = sym->st_value + rel[i].r_addend; 470 470 + 471 471 + if (type == R_LARCH_PCADD_LO12 || type == R_LARCH_GOT_PCADD_LO12) { 472 472 + bool found = false; 473 473 + unsigned int j = idx; 474 474 + 475 475 + do { 476 476 + u32 hi20_type = ELF_R_TYPE(rel[j].r_info); 477 477 + unsigned long hi20_location = 478 478 + sechdrs[sechdrs[relsec].sh_info].sh_addr + rel[j].r_offset; 479 479 + 480 480 + /* Find the corresponding HI20 relocation entry */ 481 481 + if ((hi20_location == sym->st_value) && (hi20_type == type - 1)) { 482 482 + s32 hi20, lo12; 483 483 + Elf_Sym *hi20_sym = 484 484 + (Elf_Sym *)sechdrs[symindex].sh_addr + ELF_R_SYM(rel[j].r_info); 485 485 + unsigned long hi20_sym_val = hi20_sym->st_value + rel[j].r_addend; 486 486 + 487 487 + /* Calculate LO12 offset */ 488 488 + size_t offset = hi20_sym_val - hi20_location; 489 489 + if (hi20_type == R_LARCH_GOT_PCADD_HI20) { 490 490 + offset = module_emit_got_entry(mod, sechdrs, hi20_sym_val); 491 491 + offset = offset - hi20_location; 492 492 + } 493 493 + hi20 = (offset + 0x800) & 0xfffff000; 494 494 + v = lo12 = offset - hi20; 495 495 + found = true; 496 496 + break; 497 497 + } 498 498 + 499 499 + j = (j + 1) % num_relocations; 500 500 + 501 501 + } while (idx != j); 502 502 + 503 503 + if (!found) { 504 504 + pr_err("%s: Can not find HI20 relocation information\n", mod->name); 505 505 + return -EINVAL; 506 506 + } 507 507 + 508 508 + idx = j; /* Record the previous j-loop end index */ 509 509 + } 510 510 + 524 511 switch (type) { 525 512 case R_LARCH_B26: 526 513 err = apply_r_larch_b26(mod, sechdrs, location, 527 514 v, rela_stack, &rela_stack_top, type); 528 515 break; 529 516 case R_LARCH_GOT_PC_HI20...R_LARCH_GOT_PC_LO12: 517 517 + case R_LARCH_GOT_PCADD_HI20...R_LARCH_GOT_PCADD_LO12: 530 518 err = apply_r_larch_got_pc(mod, sechdrs, location, 531 519 v, rela_stack, &rela_stack_top, type); 532 520 break;

+5 -5

arch/loongarch/kernel/proc.c

reviewed

··· 20 20 unsigned int prid = cpu_data[n].processor_id; 21 21 unsigned int version = cpu_data[n].processor_id & 0xff; 22 22 unsigned int fp_version = cpu_data[n].fpu_vers; 23 23 + u64 freq = cpu_clock_freq, bogomips = lpj_fine * cpu_clock_freq; 23 24 24 25 #ifdef CONFIG_SMP 25 26 if (!cpu_online(n)) 26 27 return 0; 27 28 #endif 29 29 + do_div(freq, 10000); 30 30 + do_div(bogomips, const_clock_freq * (5000/HZ)); 28 31 29 32 /* 30 33 * For the first processor also print the system type ··· 44 41 seq_printf(m, "PRID\t\t\t: %s (%08x)\n", id_to_core_name(prid), prid); 45 42 seq_printf(m, "CPU Revision\t\t: 0x%02x\n", version); 46 43 seq_printf(m, "FPU Revision\t\t: 0x%02x\n", fp_version); 47 47 - seq_printf(m, "CPU MHz\t\t\t: %llu.%02llu\n", 48 48 - cpu_clock_freq / 1000000, (cpu_clock_freq / 10000) % 100); 49 49 - seq_printf(m, "BogoMIPS\t\t: %llu.%02llu\n", 50 50 - (lpj_fine * cpu_clock_freq / const_clock_freq) / (500000/HZ), 51 51 - ((lpj_fine * cpu_clock_freq / const_clock_freq) / (5000/HZ)) % 100); 44 44 + seq_printf(m, "CPU MHz\t\t\t: %u.%02u\n", (u32)freq / 100, (u32)freq % 100); 45 45 + seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", (u32)bogomips / 100, (u32)bogomips % 100); 52 46 seq_printf(m, "TLB Entries\t\t: %d\n", cpu_data[n].tlbsize); 53 47 seq_printf(m, "Address Sizes\t\t: %d bits physical, %d bits virtual\n", 54 48 cpu_pabits + 1, cpu_vabits + 1);

+9 -2

arch/loongarch/kernel/process.c

reviewed

··· 130 130 131 131 preempt_enable(); 132 132 133 133 + if (IS_ENABLED(CONFIG_RANDSTRUCT)) { 134 134 + memcpy(dst, src, sizeof(struct task_struct)); 135 135 + return 0; 136 136 + } 137 137 + 133 138 if (!used_math()) 134 139 memcpy(dst, src, offsetof(struct task_struct, thread.fpu.fpr)); 135 140 else ··· 382 377 nmi_trigger_cpumask_backtrace(mask, exclude_cpu, raise_backtrace); 383 378 } 384 379 385 385 - #ifdef CONFIG_64BIT 380 380 + #ifdef CONFIG_32BIT 381 381 + void loongarch_dump_regs32(u32 *uregs, const struct pt_regs *regs) 382 382 + #else 386 383 void loongarch_dump_regs64(u64 *uregs, const struct pt_regs *regs) 384 384 + #endif 387 385 { 388 386 unsigned int i; 389 387 ··· 403 395 uregs[LOONGARCH_EF_CSR_ECFG] = regs->csr_ecfg; 404 396 uregs[LOONGARCH_EF_CSR_ESTAT] = regs->csr_estat; 405 397 } 406 406 - #endif /* CONFIG_64BIT */

+5

arch/loongarch/kernel/ptrace.c

reviewed

··· 650 650 struct perf_event_attr attr; 651 651 652 652 /* Kernel-space address cannot be monitored by user-space */ 653 653 + #ifdef CONFIG_32BIT 654 654 + if ((unsigned long)addr >= KPRANGE0) 655 655 + return -EINVAL; 656 656 + #else 653 657 if ((unsigned long)addr >= XKPRANGE) 654 658 return -EINVAL; 659 659 + #endif 655 660 656 661 bp = ptrace_hbp_get_initialised_bp(note_type, tsk, idx); 657 662 if (IS_ERR(bp))

+10 -3

arch/loongarch/kernel/relocate.c

reviewed

··· 68 68 69 69 for (p = begin; (void *)p < end; p++) { 70 70 long v = p->symvalue; 71 71 - uint32_t lu12iw, ori, lu32id, lu52id; 71 71 + uint32_t lu12iw, ori; 72 72 + #ifdef CONFIG_64BIT 73 73 + uint32_t lu32id, lu52id; 74 74 + #endif 72 75 union loongarch_instruction *insn = (void *)p->pc; 73 76 74 77 lu12iw = (v >> 12) & 0xfffff; 75 78 ori = v & 0xfff; 79 79 + #ifdef CONFIG_64BIT 76 80 lu32id = (v >> 32) & 0xfffff; 77 81 lu52id = v >> 52; 82 82 + #endif 78 83 79 84 insn[0].reg1i20_format.immediate = lu12iw; 80 85 insn[1].reg2i12_format.immediate = ori; 86 86 + #ifdef CONFIG_64BIT 81 87 insn[2].reg1i20_format.immediate = lu32id; 82 88 insn[3].reg2i12_format.immediate = lu52id; 89 89 + #endif 83 90 } 84 91 } 85 92 ··· 190 183 if (kaslr_disabled()) 191 184 return destination; 192 185 193 193 - kernel_length = (long)_end - (long)_text; 186 186 + kernel_length = (unsigned long)_end - (unsigned long)_text; 194 187 195 188 random_offset = get_random_boot() << 16; 196 189 random_offset &= (CONFIG_RANDOMIZE_BASE_MAX_OFFSET - 1); ··· 239 232 early_memunmap(cmdline, COMMAND_LINE_SIZE); 240 233 241 234 if (random_offset) { 242 242 - kernel_length = (long)(_end) - (long)(_text); 235 235 + kernel_length = (unsigned long)(_end) - (unsigned long)(_text); 243 236 244 237 /* Copy the kernel to it's new location */ 245 238 memcpy(location_new, _text, kernel_length);

+7 -1

arch/loongarch/kernel/setup.c

reviewed

··· 56 56 #define SMBIOS_FREQLOW_MASK 0xFF 57 57 #define SMBIOS_CORE_PACKAGE_OFFSET 0x23 58 58 #define SMBIOS_THREAD_PACKAGE_OFFSET 0x25 59 59 + #define SMBIOS_THREAD_PACKAGE_2_OFFSET 0x2E 59 60 #define LOONGSON_EFI_ENABLE (1 << 3) 60 61 61 62 unsigned long fw_arg0, fw_arg1, fw_arg2; ··· 127 126 cpu_clock_freq = freq_temp * 1000000; 128 127 129 128 loongson_sysconf.cpuname = (void *)dmi_string_parse(dm, dmi_data[16]); 130 130 - loongson_sysconf.cores_per_package = *(dmi_data + SMBIOS_THREAD_PACKAGE_OFFSET); 129 129 + loongson_sysconf.cores_per_package = *(u8 *)(dmi_data + SMBIOS_THREAD_PACKAGE_OFFSET); 130 130 + if (dm->length >= 0x30 && loongson_sysconf.cores_per_package == 0xff) { 131 131 + /* SMBIOS 3.0+ has ThreadCount2 for more than 255 threads */ 132 132 + loongson_sysconf.cores_per_package = 133 133 + *(u16 *)(dmi_data + SMBIOS_THREAD_PACKAGE_2_OFFSET); 134 134 + } 131 135 132 136 pr_info("CpuClock = %llu\n", cpu_clock_freq); 133 137 }

+18 -10

arch/loongarch/kernel/switch.S

reviewed

··· 16 16 */ 17 17 .align 5 18 18 SYM_FUNC_START(__switch_to) 19 19 - csrrd t1, LOONGARCH_CSR_PRMD 20 20 - stptr.d t1, a0, THREAD_CSRPRMD 19 19 + #ifdef CONFIG_32BIT 20 20 + PTR_ADDI a0, a0, TASK_STRUCT_OFFSET 21 21 + PTR_ADDI a1, a1, TASK_STRUCT_OFFSET 22 22 + #endif 23 23 + csrrd t1, LOONGARCH_CSR_PRMD 24 24 + LONG_SPTR t1, a0, (THREAD_CSRPRMD - TASK_STRUCT_OFFSET) 21 25 22 26 cpu_save_nonscratch a0 23 23 - stptr.d ra, a0, THREAD_REG01 24 24 - stptr.d a3, a0, THREAD_SCHED_RA 25 25 - stptr.d a4, a0, THREAD_SCHED_CFA 27 27 + LONG_SPTR a3, a0, (THREAD_SCHED_RA - TASK_STRUCT_OFFSET) 28 28 + LONG_SPTR a4, a0, (THREAD_SCHED_CFA - TASK_STRUCT_OFFSET) 29 29 + 26 30 #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 27 27 - la t7, __stack_chk_guard 28 28 - LONG_L t8, a1, TASK_STACK_CANARY 29 29 - LONG_S t8, t7, 0 31 31 + la t7, __stack_chk_guard 32 32 + LONG_LPTR t8, a1, (TASK_STACK_CANARY - TASK_STRUCT_OFFSET) 33 33 + LONG_SPTR t8, t7, 0 30 34 #endif 35 35 + 31 36 move tp, a2 32 37 cpu_restore_nonscratch a1 33 38 ··· 40 35 PTR_ADD t0, t0, tp 41 36 set_saved_sp t0, t1, t2 42 37 43 43 - ldptr.d t1, a1, THREAD_CSRPRMD 44 44 - csrwr t1, LOONGARCH_CSR_PRMD 38 38 + LONG_LPTR t1, a1, (THREAD_CSRPRMD - TASK_STRUCT_OFFSET) 39 39 + csrwr t1, LOONGARCH_CSR_PRMD 45 40 41 41 + #ifdef CONFIG_32BIT 42 42 + PTR_ADDI a0, a0, -TASK_STRUCT_OFFSET 43 43 + #endif 46 44 jr ra 47 45 SYM_FUNC_END(__switch_to)

+14 -1

arch/loongarch/kernel/syscall.c

reviewed

··· 34 34 return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT); 35 35 } 36 36 37 37 + SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, unsigned long, 38 38 + prot, unsigned long, flags, unsigned long, fd, unsigned long, offset) 39 39 + { 40 40 + if (offset & (~PAGE_MASK >> 12)) 41 41 + return -EINVAL; 42 42 + 43 43 + return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> (PAGE_SHIFT - 12)); 44 44 + } 45 45 + 37 46 void *sys_call_table[__NR_syscalls] = { 38 47 [0 ... __NR_syscalls - 1] = sys_ni_syscall, 48 48 + #ifdef CONFIG_32BIT 49 49 + #include <asm/syscall_table_32.h> 50 50 + #else 39 51 #include <asm/syscall_table_64.h> 52 52 + #endif 40 53 }; 41 54 42 55 typedef long (*sys_call_fn)(unsigned long, unsigned long, ··· 88 75 * 89 76 * The resulting 6 bits of entropy is seen in SP[9:4]. 90 77 */ 91 91 - choose_random_kstack_offset(drdtime()); 78 78 + choose_random_kstack_offset(get_cycles()); 92 79 93 80 syscall_exit_to_user_mode(regs); 94 81 }

+17 -14

arch/loongarch/kernel/time.c

reviewed

··· 18 18 #include <asm/loongarch.h> 19 19 #include <asm/paravirt.h> 20 20 #include <asm/time.h> 21 21 + #include <asm/timex.h> 21 22 22 23 u64 cpu_clock_freq; 23 24 EXPORT_SYMBOL(cpu_clock_freq); ··· 51 50 52 51 raw_spin_lock(&state_lock); 53 52 54 54 - timer_config = csr_read64(LOONGARCH_CSR_TCFG); 53 53 + timer_config = csr_read(LOONGARCH_CSR_TCFG); 55 54 timer_config |= CSR_TCFG_EN; 56 55 timer_config &= ~CSR_TCFG_PERIOD; 57 57 - csr_write64(timer_config, LOONGARCH_CSR_TCFG); 56 56 + csr_write(timer_config, LOONGARCH_CSR_TCFG); 58 57 59 58 raw_spin_unlock(&state_lock); 60 59 ··· 63 62 64 63 static int constant_set_state_periodic(struct clock_event_device *evt) 65 64 { 66 66 - unsigned long period; 67 65 unsigned long timer_config; 66 66 + u64 period = const_clock_freq; 68 67 69 68 raw_spin_lock(&state_lock); 70 69 71 71 - period = const_clock_freq / HZ; 70 70 + do_div(period, HZ); 72 71 timer_config = period & CSR_TCFG_VAL; 73 72 timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN); 74 74 - csr_write64(timer_config, LOONGARCH_CSR_TCFG); 73 73 + csr_write(timer_config, LOONGARCH_CSR_TCFG); 75 74 76 75 raw_spin_unlock(&state_lock); 77 76 ··· 84 83 85 84 raw_spin_lock(&state_lock); 86 85 87 87 - timer_config = csr_read64(LOONGARCH_CSR_TCFG); 86 86 + timer_config = csr_read(LOONGARCH_CSR_TCFG); 88 87 timer_config &= ~CSR_TCFG_EN; 89 89 - csr_write64(timer_config, LOONGARCH_CSR_TCFG); 88 88 + csr_write(timer_config, LOONGARCH_CSR_TCFG); 90 89 91 90 raw_spin_unlock(&state_lock); 92 91 ··· 99 98 100 99 delta &= CSR_TCFG_VAL; 101 100 timer_config = delta | CSR_TCFG_EN; 102 102 - csr_write64(timer_config, LOONGARCH_CSR_TCFG); 101 101 + csr_write(timer_config, LOONGARCH_CSR_TCFG); 103 102 104 103 return 0; 105 104 } ··· 121 120 122 121 static unsigned long get_loops_per_jiffy(void) 123 122 { 124 124 - unsigned long lpj = (unsigned long)const_clock_freq; 123 123 + u64 lpj = const_clock_freq; 125 124 126 125 do_div(lpj, HZ); 127 126 ··· 132 131 133 132 void save_counter(void) 134 133 { 135 135 - init_offset = drdtime(); 134 134 + init_offset = get_cycles(); 136 135 } 137 136 138 137 void sync_counter(void) 139 138 { 140 139 /* Ensure counter begin at 0 */ 141 141 - csr_write64(init_offset, LOONGARCH_CSR_CNTC); 140 140 + csr_write(init_offset, LOONGARCH_CSR_CNTC); 142 141 } 143 142 144 143 int constant_clockevent_init(void) ··· 198 197 199 198 static u64 read_const_counter(struct clocksource *clk) 200 199 { 201 201 - return drdtime(); 200 200 + return get_cycles64(); 202 201 } 203 202 204 203 static noinstr u64 sched_clock_read(void) 205 204 { 206 206 - return drdtime(); 205 205 + return get_cycles64(); 207 206 } 208 207 209 208 static struct clocksource clocksource_const = { ··· 212 211 .read = read_const_counter, 213 212 .mask = CLOCKSOURCE_MASK(64), 214 213 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 214 214 + #ifdef CONFIG_GENERIC_GETTIMEOFDAY 215 215 .vdso_clock_mode = VDSO_CLOCKMODE_CPU, 216 216 + #endif 216 217 }; 217 218 218 219 int __init constant_clocksource_init(void) ··· 238 235 else 239 236 const_clock_freq = calc_const_freq(); 240 237 241 241 - init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC)); 238 238 + init_offset = -(get_cycles() - csr_read(LOONGARCH_CSR_CNTC)); 242 239 243 240 constant_clockevent_init(); 244 241 constant_clocksource_init();

+9 -6

arch/loongarch/kernel/traps.c

reviewed

··· 625 625 bool user = user_mode(regs); 626 626 bool pie = regs_irqs_disabled(regs); 627 627 unsigned long era = exception_era(regs); 628 628 - u64 badv = 0, lower = 0, upper = ULONG_MAX; 628 628 + unsigned long badv = 0, lower = 0, upper = ULONG_MAX; 629 629 union loongarch_instruction insn; 630 630 irqentry_state_t state = irqentry_enter(regs); 631 631 ··· 1070 1070 1071 1071 asmlinkage void cache_parity_error(void) 1072 1072 { 1073 1073 + u32 merrctl = csr_read32(LOONGARCH_CSR_MERRCTL); 1074 1074 + unsigned long merrera = csr_read(LOONGARCH_CSR_MERRERA); 1075 1075 + 1073 1076 /* For the moment, report the problem and hang. */ 1074 1077 pr_err("Cache error exception:\n"); 1075 1075 - pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); 1076 1076 - pr_err("csr_merrera == %016lx\n", csr_read64(LOONGARCH_CSR_MERRERA)); 1078 1078 + pr_err("csr_merrctl == %08x\n", merrctl); 1079 1079 + pr_err("csr_merrera == %016lx\n", merrera); 1077 1080 panic("Can't handle the cache error!"); 1078 1081 } 1079 1082 ··· 1133 1130 eentry = (unsigned long)exception_handlers; 1134 1131 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 1135 1132 1136 1136 - csr_write64(eentry, LOONGARCH_CSR_EENTRY); 1137 1137 - csr_write64(__pa(eentry), LOONGARCH_CSR_MERRENTRY); 1138 1138 - csr_write64(__pa(tlbrentry), LOONGARCH_CSR_TLBRENTRY); 1133 1133 + csr_write(eentry, LOONGARCH_CSR_EENTRY); 1134 1134 + csr_write(__pa(eentry), LOONGARCH_CSR_MERRENTRY); 1135 1135 + csr_write(__pa(tlbrentry), LOONGARCH_CSR_TLBRENTRY); 1139 1136 } 1140 1137 1141 1138 void per_cpu_trap_init(int cpu)

+24 -6

arch/loongarch/kernel/unaligned.c

reviewed

··· 27 27 static u32 unaligned_instructions_kernel; 28 28 #endif 29 29 30 30 - static inline unsigned long read_fpr(unsigned int idx) 30 30 + static inline u64 read_fpr(unsigned int idx) 31 31 { 32 32 + #ifdef CONFIG_64BIT 32 33 #define READ_FPR(idx, __value) \ 33 34 __asm__ __volatile__("movfr2gr.d %0, $f"#idx"\n\t" : "=r"(__value)); 34 34 - 35 35 - unsigned long __value; 35 35 + #else 36 36 + #define READ_FPR(idx, __value) \ 37 37 + { \ 38 38 + u32 __value_lo, __value_hi; \ 39 39 + __asm__ __volatile__("movfr2gr.s %0, $f"#idx"\n\t" : "=r"(__value_lo)); \ 40 40 + __asm__ __volatile__("movfrh2gr.s %0, $f"#idx"\n\t" : "=r"(__value_hi)); \ 41 41 + __value = (__value_lo | ((u64)__value_hi << 32)); \ 42 42 + } 43 43 + #endif 44 44 + u64 __value; 36 45 37 46 switch (idx) { 38 47 case 0: ··· 147 138 return __value; 148 139 } 149 140 150 150 - static inline void write_fpr(unsigned int idx, unsigned long value) 141 141 + static inline void write_fpr(unsigned int idx, u64 value) 151 142 { 143 143 + #ifdef CONFIG_64BIT 152 144 #define WRITE_FPR(idx, value) \ 153 145 __asm__ __volatile__("movgr2fr.d $f"#idx", %0\n\t" :: "r"(value)); 154 154 - 146 146 + #else 147 147 + #define WRITE_FPR(idx, value) \ 148 148 + { \ 149 149 + u32 value_lo = value; \ 150 150 + u32 value_hi = value >> 32; \ 151 151 + __asm__ __volatile__("movgr2fr.w $f"#idx", %0\n\t" :: "r"(value_lo)); \ 152 152 + __asm__ __volatile__("movgr2frh.w $f"#idx", %0\n\t" :: "r"(value_hi)); \ 153 153 + } 154 154 + #endif 155 155 switch (idx) { 156 156 case 0: 157 157 WRITE_FPR(0, value); ··· 270 252 bool sign, write; 271 253 bool user = user_mode(regs); 272 254 unsigned int res, size = 0; 273 273 - unsigned long value = 0; 255 255 + u64 value = 0; 274 256 union loongarch_instruction insn; 275 257 276 258 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);

+3 -2

arch/loongarch/kvm/vcpu.c

reviewed

··· 9 9 #include <asm/loongarch.h> 10 10 #include <asm/setup.h> 11 11 #include <asm/time.h> 12 12 + #include <asm/timex.h> 12 13 13 14 #define CREATE_TRACE_POINTS 14 15 #include "trace.h" ··· 815 814 case KVM_REG_LOONGARCH_KVM: 816 815 switch (reg->id) { 817 816 case KVM_REG_LOONGARCH_COUNTER: 818 818 - *v = drdtime() + vcpu->kvm->arch.time_offset; 817 817 + *v = get_cycles() + vcpu->kvm->arch.time_offset; 819 818 break; 820 819 case KVM_REG_LOONGARCH_DEBUG_INST: 821 820 *v = INSN_HVCL | KVM_HCALL_SWDBG; ··· 910 909 * only set for the first time for smp system 911 910 */ 912 911 if (vcpu->vcpu_id == 0) 913 913 - vcpu->kvm->arch.time_offset = (signed long)(v - drdtime()); 912 912 + vcpu->kvm->arch.time_offset = (signed long)(v - get_cycles()); 914 913 break; 915 914 case KVM_REG_LOONGARCH_VCPU_RESET: 916 915 vcpu->arch.st.guest_addr = 0;

+13

arch/loongarch/lib/bswapdi.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + #include <linux/export.h> 3 3 + #include <linux/compiler.h> 4 4 + #include <uapi/linux/swab.h> 5 5 + 6 6 + /* To silence -Wmissing-prototypes. */ 7 7 + unsigned long long __bswapdi2(unsigned long long u); 8 8 + 9 9 + unsigned long long notrace __bswapdi2(unsigned long long u) 10 10 + { 11 11 + return ___constant_swab64(u); 12 12 + } 13 13 + EXPORT_SYMBOL(__bswapdi2);

+13

arch/loongarch/lib/bswapsi.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + #include <linux/export.h> 3 3 + #include <linux/compiler.h> 4 4 + #include <uapi/linux/swab.h> 5 5 + 6 6 + /* To silence -Wmissing-prototypes. */ 7 7 + unsigned int __bswapsi2(unsigned int u); 8 8 + 9 9 + unsigned int notrace __bswapsi2(unsigned int u) 10 10 + { 11 11 + return ___constant_swab32(u); 12 12 + } 13 13 + EXPORT_SYMBOL(__bswapsi2);

+14 -8

arch/loongarch/lib/clear_user.S

reviewed

··· 13 13 #include <asm/unwind_hints.h> 14 14 15 15 SYM_FUNC_START(__clear_user) 16 16 + #ifdef CONFIG_32BIT 17 17 + b __clear_user_generic 18 18 + #else 16 19 /* 17 20 * Some CPUs support hardware unaligned access 18 21 */ 19 22 ALTERNATIVE "b __clear_user_generic", \ 20 23 "b __clear_user_fast", CPU_FEATURE_UAL 24 24 + #endif 21 25 SYM_FUNC_END(__clear_user) 22 26 23 27 EXPORT_SYMBOL(__clear_user) ··· 33 29 * a1: size 34 30 */ 35 31 SYM_FUNC_START(__clear_user_generic) 36 36 - beqz a1, 2f 32 32 + beqz a1, 2f 37 33 38 38 - 1: st.b zero, a0, 0 39 39 - addi.d a0, a0, 1 40 40 - addi.d a1, a1, -1 41 41 - bgtz a1, 1b 34 34 + 1: st.b zero, a0, 0 35 35 + PTR_ADDI a0, a0, 1 36 36 + PTR_ADDI a1, a1, -1 37 37 + bgtz a1, 1b 42 38 43 43 - 2: move a0, a1 44 44 - jr ra 39 39 + 2: move a0, a1 40 40 + jr ra 45 41 46 46 - _asm_extable 1b, 2b 42 42 + _asm_extable 1b, 2b 47 43 SYM_FUNC_END(__clear_user_generic) 48 44 45 45 + #ifdef CONFIG_64BIT 49 46 /* 50 47 * unsigned long __clear_user_fast(void *addr, unsigned long size) 51 48 * ··· 212 207 SYM_FUNC_END(__clear_user_fast) 213 208 214 209 STACK_FRAME_NON_STANDARD __clear_user_fast 210 210 + #endif

+17 -11

arch/loongarch/lib/copy_user.S

reviewed

··· 13 13 #include <asm/unwind_hints.h> 14 14 15 15 SYM_FUNC_START(__copy_user) 16 16 + #ifdef CONFIG_32BIT 17 17 + b __copy_user_generic 18 18 + #else 16 19 /* 17 20 * Some CPUs support hardware unaligned access 18 21 */ 19 22 ALTERNATIVE "b __copy_user_generic", \ 20 23 "b __copy_user_fast", CPU_FEATURE_UAL 24 24 + #endif 21 25 SYM_FUNC_END(__copy_user) 22 26 23 27 EXPORT_SYMBOL(__copy_user) ··· 34 30 * a2: n 35 31 */ 36 32 SYM_FUNC_START(__copy_user_generic) 37 37 - beqz a2, 3f 33 33 + beqz a2, 3f 38 34 39 39 - 1: ld.b t0, a1, 0 40 40 - 2: st.b t0, a0, 0 41 41 - addi.d a0, a0, 1 42 42 - addi.d a1, a1, 1 43 43 - addi.d a2, a2, -1 44 44 - bgtz a2, 1b 35 35 + 1: ld.b t0, a1, 0 36 36 + 2: st.b t0, a0, 0 37 37 + PTR_ADDI a0, a0, 1 38 38 + PTR_ADDI a1, a1, 1 39 39 + PTR_ADDI a2, a2, -1 40 40 + bgtz a2, 1b 45 41 46 46 - 3: move a0, a2 47 47 - jr ra 42 42 + 3: move a0, a2 43 43 + jr ra 48 44 49 49 - _asm_extable 1b, 3b 50 50 - _asm_extable 2b, 3b 45 45 + _asm_extable 1b, 3b 46 46 + _asm_extable 2b, 3b 51 47 SYM_FUNC_END(__copy_user_generic) 52 48 49 49 + #ifdef CONFIG_64BIT 53 50 /* 54 51 * unsigned long __copy_user_fast(void *to, const void *from, unsigned long n) 55 52 * ··· 286 281 SYM_FUNC_END(__copy_user_fast) 287 282 288 283 STACK_FRAME_NON_STANDARD __copy_user_fast 284 284 + #endif

+11 -3

arch/loongarch/lib/dump_tlb.c

reviewed

··· 20 20 21 21 pr_info("Index : 0x%0x\n", read_csr_tlbidx()); 22 22 pr_info("PageSize : 0x%0x\n", read_csr_pagesize()); 23 23 - pr_info("EntryHi : 0x%0*lx\n", field, read_csr_entryhi()); 24 24 - pr_info("EntryLo0 : 0x%0*lx\n", field, read_csr_entrylo0()); 25 25 - pr_info("EntryLo1 : 0x%0*lx\n", field, read_csr_entrylo1()); 23 23 + pr_info("EntryHi : 0x%0*lx\n", field, (unsigned long)read_csr_entryhi()); 24 24 + pr_info("EntryLo0 : 0x%0*lx\n", field, (unsigned long)read_csr_entrylo0()); 25 25 + pr_info("EntryLo1 : 0x%0*lx\n", field, (unsigned long)read_csr_entrylo1()); 26 26 } 27 27 28 28 static void dump_tlb(int first, int last) ··· 73 73 vwidth, (entryhi & ~0x1fffUL), asidwidth, asid & asidmask); 74 74 75 75 /* NR/NX are in awkward places, so mask them off separately */ 76 76 + #ifdef CONFIG_64BIT 76 77 pa = entrylo0 & ~(ENTRYLO_NR | ENTRYLO_NX); 78 78 + #endif 77 79 pa = pa & PAGE_MASK; 78 80 pr_cont("\n\t["); 81 81 + #ifdef CONFIG_64BIT 79 82 pr_cont("nr=%d nx=%d ", 80 83 (entrylo0 & ENTRYLO_NR) ? 1 : 0, 81 84 (entrylo0 & ENTRYLO_NX) ? 1 : 0); 85 85 + #endif 82 86 pr_cont("pa=0x%0*llx c=%d d=%d v=%d g=%d plv=%lld] [", 83 87 pwidth, pa, c0, 84 88 (entrylo0 & ENTRYLO_D) ? 1 : 0, ··· 90 86 (entrylo0 & ENTRYLO_G) ? 1 : 0, 91 87 (entrylo0 & ENTRYLO_PLV) >> ENTRYLO_PLV_SHIFT); 92 88 /* NR/NX are in awkward places, so mask them off separately */ 89 89 + #ifdef CONFIG_64BIT 93 90 pa = entrylo1 & ~(ENTRYLO_NR | ENTRYLO_NX); 91 91 + #endif 94 92 pa = pa & PAGE_MASK; 93 93 + #ifdef CONFIG_64BIT 95 94 pr_cont("nr=%d nx=%d ", 96 95 (entrylo1 & ENTRYLO_NR) ? 1 : 0, 97 96 (entrylo1 & ENTRYLO_NX) ? 1 : 0); 97 97 + #endif 98 98 pr_cont("pa=0x%0*llx c=%d d=%d v=%d g=%d plv=%lld]\n", 99 99 pwidth, pa, c1, 100 100 (entrylo1 & ENTRYLO_D) ? 1 : 0,

+36 -36

arch/loongarch/lib/unaligned.S

reviewed

··· 24 24 * a3: sign 25 25 */ 26 26 SYM_FUNC_START(unaligned_read) 27 27 - beqz a2, 5f 27 27 + beqz a2, 5f 28 28 29 29 - li.w t2, 0 30 30 - addi.d t0, a2, -1 31 31 - slli.d t1, t0, 3 32 32 - add.d a0, a0, t0 29 29 + li.w t2, 0 30 30 + LONG_ADDI t0, a2, -1 31 31 + PTR_SLLI t1, t0, LONGLOG 32 32 + PTR_ADD a0, a0, t0 33 33 34 34 - beqz a3, 2f 35 35 - 1: ld.b t3, a0, 0 36 36 - b 3f 34 34 + beqz a3, 2f 35 35 + 1: ld.b t3, a0, 0 36 36 + b 3f 37 37 38 38 - 2: ld.bu t3, a0, 0 39 39 - 3: sll.d t3, t3, t1 40 40 - or t2, t2, t3 41 41 - addi.d t1, t1, -8 42 42 - addi.d a0, a0, -1 43 43 - addi.d a2, a2, -1 44 44 - bgtz a2, 2b 45 45 - 4: st.d t2, a1, 0 38 38 + 2: ld.bu t3, a0, 0 39 39 + 3: LONG_SLLV t3, t3, t1 40 40 + or t2, t2, t3 41 41 + LONG_ADDI t1, t1, -8 42 42 + PTR_ADDI a0, a0, -1 43 43 + PTR_ADDI a2, a2, -1 44 44 + bgtz a2, 2b 45 45 + 4: LONG_S t2, a1, 0 46 46 47 47 - move a0, a2 48 48 - jr ra 47 47 + move a0, a2 48 48 + jr ra 49 49 50 50 - 5: li.w a0, -EFAULT 51 51 - jr ra 50 50 + 5: li.w a0, -EFAULT 51 51 + jr ra 52 52 53 53 - _asm_extable 1b, .L_fixup_handle_unaligned 54 54 - _asm_extable 2b, .L_fixup_handle_unaligned 55 55 - _asm_extable 4b, .L_fixup_handle_unaligned 53 53 + _asm_extable 1b, .L_fixup_handle_unaligned 54 54 + _asm_extable 2b, .L_fixup_handle_unaligned 55 55 + _asm_extable 4b, .L_fixup_handle_unaligned 56 56 SYM_FUNC_END(unaligned_read) 57 57 58 58 /* ··· 63 63 * a2: n 64 64 */ 65 65 SYM_FUNC_START(unaligned_write) 66 66 - beqz a2, 3f 66 66 + beqz a2, 3f 67 67 68 68 - li.w t0, 0 69 69 - 1: srl.d t1, a1, t0 70 70 - 2: st.b t1, a0, 0 71 71 - addi.d t0, t0, 8 72 72 - addi.d a2, a2, -1 73 73 - addi.d a0, a0, 1 74 74 - bgtz a2, 1b 68 68 + li.w t0, 0 69 69 + 1: LONG_SRLV t1, a1, t0 70 70 + 2: st.b t1, a0, 0 71 71 + LONG_ADDI t0, t0, 8 72 72 + PTR_ADDI a2, a2, -1 73 73 + PTR_ADDI a0, a0, 1 74 74 + bgtz a2, 1b 75 75 76 76 - move a0, a2 77 77 - jr ra 76 76 + move a0, a2 77 77 + jr ra 78 78 79 79 - 3: li.w a0, -EFAULT 80 80 - jr ra 79 79 + 3: li.w a0, -EFAULT 80 80 + jr ra 81 81 82 82 - _asm_extable 2b, .L_fixup_handle_unaligned 82 82 + _asm_extable 2b, .L_fixup_handle_unaligned 83 83 SYM_FUNC_END(unaligned_write)

+2 -2

arch/loongarch/mm/init.c

reviewed

··· 224 224 pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss; 225 225 EXPORT_SYMBOL(invalid_pte_table); 226 226 227 227 - #ifdef CONFIG_EXECMEM 227 227 + #if defined(CONFIG_EXECMEM) && defined(MODULES_VADDR) 228 228 static struct execmem_info execmem_info __ro_after_init; 229 229 230 230 struct execmem_info __init *execmem_arch_setup(void) ··· 242 242 243 243 return &execmem_info; 244 244 } 245 245 - #endif /* CONFIG_EXECMEM */ 245 245 + #endif /* CONFIG_EXECMEM && MODULES_VADDR */

+59 -59

arch/loongarch/mm/page.S

reviewed

··· 10 10 11 11 .align 5 12 12 SYM_FUNC_START(clear_page) 13 13 - lu12i.w t0, 1 << (PAGE_SHIFT - 12) 14 14 - add.d t0, t0, a0 13 13 + lu12i.w t0, 1 << (PAGE_SHIFT - 12) 14 14 + PTR_ADD t0, t0, a0 15 15 1: 16 16 - st.d zero, a0, 0 17 17 - st.d zero, a0, 8 18 18 - st.d zero, a0, 16 19 19 - st.d zero, a0, 24 20 20 - st.d zero, a0, 32 21 21 - st.d zero, a0, 40 22 22 - st.d zero, a0, 48 23 23 - st.d zero, a0, 56 24 24 - addi.d a0, a0, 128 25 25 - st.d zero, a0, -64 26 26 - st.d zero, a0, -56 27 27 - st.d zero, a0, -48 28 28 - st.d zero, a0, -40 29 29 - st.d zero, a0, -32 30 30 - st.d zero, a0, -24 31 31 - st.d zero, a0, -16 32 32 - st.d zero, a0, -8 33 33 - bne t0, a0, 1b 16 16 + LONG_S zero, a0, (LONGSIZE * 0) 17 17 + LONG_S zero, a0, (LONGSIZE * 1) 18 18 + LONG_S zero, a0, (LONGSIZE * 2) 19 19 + LONG_S zero, a0, (LONGSIZE * 3) 20 20 + LONG_S zero, a0, (LONGSIZE * 4) 21 21 + LONG_S zero, a0, (LONGSIZE * 5) 22 22 + LONG_S zero, a0, (LONGSIZE * 6) 23 23 + LONG_S zero, a0, (LONGSIZE * 7) 24 24 + PTR_ADDI a0, a0, (LONGSIZE * 16) 25 25 + LONG_S zero, a0, -(LONGSIZE * 8) 26 26 + LONG_S zero, a0, -(LONGSIZE * 7) 27 27 + LONG_S zero, a0, -(LONGSIZE * 6) 28 28 + LONG_S zero, a0, -(LONGSIZE * 5) 29 29 + LONG_S zero, a0, -(LONGSIZE * 4) 30 30 + LONG_S zero, a0, -(LONGSIZE * 3) 31 31 + LONG_S zero, a0, -(LONGSIZE * 2) 32 32 + LONG_S zero, a0, -(LONGSIZE * 1) 33 33 + bne t0, a0, 1b 34 34 35 35 - jr ra 35 35 + jr ra 36 36 SYM_FUNC_END(clear_page) 37 37 EXPORT_SYMBOL(clear_page) 38 38 39 39 .align 5 40 40 SYM_FUNC_START(copy_page) 41 41 - lu12i.w t8, 1 << (PAGE_SHIFT - 12) 42 42 - add.d t8, t8, a0 41 41 + lu12i.w t8, 1 << (PAGE_SHIFT - 12) 42 42 + PTR_ADD t8, t8, a0 43 43 1: 44 44 - ld.d t0, a1, 0 45 45 - ld.d t1, a1, 8 46 46 - ld.d t2, a1, 16 47 47 - ld.d t3, a1, 24 48 48 - ld.d t4, a1, 32 49 49 - ld.d t5, a1, 40 50 50 - ld.d t6, a1, 48 51 51 - ld.d t7, a1, 56 44 44 + LONG_L t0, a1, (LONGSIZE * 0) 45 45 + LONG_L t1, a1, (LONGSIZE * 1) 46 46 + LONG_L t2, a1, (LONGSIZE * 2) 47 47 + LONG_L t3, a1, (LONGSIZE * 3) 48 48 + LONG_L t4, a1, (LONGSIZE * 4) 49 49 + LONG_L t5, a1, (LONGSIZE * 5) 50 50 + LONG_L t6, a1, (LONGSIZE * 6) 51 51 + LONG_L t7, a1, (LONGSIZE * 7) 52 52 53 53 - st.d t0, a0, 0 54 54 - st.d t1, a0, 8 55 55 - ld.d t0, a1, 64 56 56 - ld.d t1, a1, 72 57 57 - st.d t2, a0, 16 58 58 - st.d t3, a0, 24 59 59 - ld.d t2, a1, 80 60 60 - ld.d t3, a1, 88 61 61 - st.d t4, a0, 32 62 62 - st.d t5, a0, 40 63 63 - ld.d t4, a1, 96 64 64 - ld.d t5, a1, 104 65 65 - st.d t6, a0, 48 66 66 - st.d t7, a0, 56 67 67 - ld.d t6, a1, 112 68 68 - ld.d t7, a1, 120 69 69 - addi.d a0, a0, 128 70 70 - addi.d a1, a1, 128 53 53 + LONG_S t0, a0, (LONGSIZE * 0) 54 54 + LONG_S t1, a0, (LONGSIZE * 1) 55 55 + LONG_L t0, a1, (LONGSIZE * 8) 56 56 + LONG_L t1, a1, (LONGSIZE * 9) 57 57 + LONG_S t2, a0, (LONGSIZE * 2) 58 58 + LONG_S t3, a0, (LONGSIZE * 3) 59 59 + LONG_L t2, a1, (LONGSIZE * 10) 60 60 + LONG_L t3, a1, (LONGSIZE * 11) 61 61 + LONG_S t4, a0, (LONGSIZE * 4) 62 62 + LONG_S t5, a0, (LONGSIZE * 5) 63 63 + LONG_L t4, a1, (LONGSIZE * 12) 64 64 + LONG_L t5, a1, (LONGSIZE * 13) 65 65 + LONG_S t6, a0, (LONGSIZE * 6) 66 66 + LONG_S t7, a0, (LONGSIZE * 7) 67 67 + LONG_L t6, a1, (LONGSIZE * 14) 68 68 + LONG_L t7, a1, (LONGSIZE * 15) 69 69 + PTR_ADDI a0, a0, (LONGSIZE * 16) 70 70 + PTR_ADDI a1, a1, (LONGSIZE * 16) 71 71 72 72 - st.d t0, a0, -64 73 73 - st.d t1, a0, -56 74 74 - st.d t2, a0, -48 75 75 - st.d t3, a0, -40 76 76 - st.d t4, a0, -32 77 77 - st.d t5, a0, -24 78 78 - st.d t6, a0, -16 79 79 - st.d t7, a0, -8 72 72 + LONG_S t0, a0, -(LONGSIZE * 8) 73 73 + LONG_S t1, a0, -(LONGSIZE * 7) 74 74 + LONG_S t2, a0, -(LONGSIZE * 6) 75 75 + LONG_S t3, a0, -(LONGSIZE * 5) 76 76 + LONG_S t4, a0, -(LONGSIZE * 4) 77 77 + LONG_S t5, a0, -(LONGSIZE * 3) 78 78 + LONG_S t6, a0, -(LONGSIZE * 2) 79 79 + LONG_S t7, a0, -(LONGSIZE * 1) 80 80 81 81 - bne t8, a0, 1b 82 82 - jr ra 81 81 + bne t8, a0, 1b 82 82 + jr ra 83 83 SYM_FUNC_END(copy_page) 84 84 EXPORT_SYMBOL(copy_page)

+7 -5

arch/loongarch/mm/tlb.c

reviewed

··· 229 229 if (cpu_has_ptw) 230 230 pwctl1 |= CSR_PWCTL1_PTW; 231 231 232 232 - csr_write64(pwctl0, LOONGARCH_CSR_PWCTL0); 233 233 - csr_write64(pwctl1, LOONGARCH_CSR_PWCTL1); 234 234 - csr_write64((long)swapper_pg_dir, LOONGARCH_CSR_PGDH); 235 235 - csr_write64((long)invalid_pg_dir, LOONGARCH_CSR_PGDL); 236 236 - csr_write64((long)smp_processor_id(), LOONGARCH_CSR_TMID); 232 232 + csr_write(pwctl0, LOONGARCH_CSR_PWCTL0); 233 233 + csr_write(pwctl1, LOONGARCH_CSR_PWCTL1); 234 234 + csr_write((long)swapper_pg_dir, LOONGARCH_CSR_PGDH); 235 235 + csr_write((long)invalid_pg_dir, LOONGARCH_CSR_PGDL); 236 236 + csr_write((long)smp_processor_id(), LOONGARCH_CSR_TMID); 237 237 } 238 238 239 239 static void output_pgtable_bits_defines(void) ··· 251 251 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 252 252 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 253 253 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 254 254 + #ifdef CONFIG_64BIT 254 255 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 255 256 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 257 257 + #endif 256 258 pr_define("PFN_PTE_SHIFT %d\n", PFN_PTE_SHIFT); 257 259 pr_debug("\n"); 258 260 }

+216 -106

arch/loongarch/mm/tlbex.S

reviewed

··· 11 11 12 12 #define INVTLB_ADDR_GFALSE_AND_ASID 5 13 13 14 14 - #define PTRS_PER_PGD_BITS (PAGE_SHIFT - 3) 15 15 - #define PTRS_PER_PUD_BITS (PAGE_SHIFT - 3) 16 16 - #define PTRS_PER_PMD_BITS (PAGE_SHIFT - 3) 17 17 - #define PTRS_PER_PTE_BITS (PAGE_SHIFT - 3) 14 14 + #define PTRS_PER_PGD_BITS (PAGE_SHIFT - PTRLOG) 15 15 + #define PTRS_PER_PUD_BITS (PAGE_SHIFT - PTRLOG) 16 16 + #define PTRS_PER_PMD_BITS (PAGE_SHIFT - PTRLOG) 17 17 + #define PTRS_PER_PTE_BITS (PAGE_SHIFT - PTRLOG) 18 18 + 19 19 + #ifdef CONFIG_32BIT 20 20 + #define PTE_LL ll.w 21 21 + #define PTE_SC sc.w 22 22 + #else 23 23 + #define PTE_LL ll.d 24 24 + #define PTE_SC sc.d 25 25 + #endif 18 26 19 27 .macro tlb_do_page_fault, write 20 28 SYM_CODE_START(tlb_do_page_fault_\write) ··· 68 60 69 61 vmalloc_done_load: 70 62 /* Get PGD offset in bytes */ 71 71 - bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT 72 72 - alsl.d t1, ra, t1, 3 63 63 + #ifdef CONFIG_32BIT 64 64 + PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT 65 65 + #else 66 66 + PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT 67 67 + #endif 68 68 + PTR_ALSL t1, ra, t1, _PGD_T_LOG2 69 69 + 73 70 #if CONFIG_PGTABLE_LEVELS > 3 74 74 - ld.d t1, t1, 0 75 75 - bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT 76 76 - alsl.d t1, ra, t1, 3 71 71 + PTR_L t1, t1, 0 72 72 + PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT 73 73 + PTR_ALSL t1, ra, t1, _PMD_T_LOG2 74 74 + 77 75 #endif 78 76 #if CONFIG_PGTABLE_LEVELS > 2 79 79 - ld.d t1, t1, 0 80 80 - bstrpick.d ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT 81 81 - alsl.d t1, ra, t1, 3 77 77 + PTR_L t1, t1, 0 78 78 + PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT 79 79 + PTR_ALSL t1, ra, t1, _PMD_T_LOG2 80 80 + 82 81 #endif 83 83 - ld.d ra, t1, 0 82 82 + PTR_L ra, t1, 0 84 83 85 84 /* 86 85 * For huge tlb entries, pmde doesn't contain an address but 87 86 * instead contains the tlb pte. Check the PAGE_HUGE bit and 88 87 * see if we need to jump to huge tlb processing. 89 88 */ 90 90 - rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1 89 89 + PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1 91 90 bltz ra, tlb_huge_update_load 92 91 93 93 - rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) 94 94 - bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT 95 95 - alsl.d t1, t0, ra, _PTE_T_LOG2 92 92 + PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1) 93 93 + PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT 94 94 + PTR_ALSL t1, t0, ra, _PTE_T_LOG2 96 95 97 96 #ifdef CONFIG_SMP 98 97 smp_pgtable_change_load: 99 99 - ll.d t0, t1, 0 98 98 + PTE_LL t0, t1, 0 100 99 #else 101 101 - ld.d t0, t1, 0 100 100 + PTR_L t0, t1, 0 102 101 #endif 103 102 andi ra, t0, _PAGE_PRESENT 104 103 beqz ra, nopage_tlb_load 105 104 106 105 ori t0, t0, _PAGE_VALID 106 106 + 107 107 #ifdef CONFIG_SMP 108 108 - sc.d t0, t1, 0 108 108 + PTE_SC t0, t1, 0 109 109 beqz t0, smp_pgtable_change_load 110 110 #else 111 111 - st.d t0, t1, 0 111 111 + PTR_S t0, t1, 0 112 112 #endif 113 113 + 113 114 tlbsrch 114 114 - bstrins.d t1, zero, 3, 3 115 115 - ld.d t0, t1, 0 116 116 - ld.d t1, t1, 8 115 115 + PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2 116 116 + PTR_L t0, t1, 0 117 117 + PTR_L t1, t1, _PTE_T_SIZE 117 118 csrwr t0, LOONGARCH_CSR_TLBELO0 118 119 csrwr t1, LOONGARCH_CSR_TLBELO1 119 120 tlbwr ··· 132 115 csrrd ra, EXCEPTION_KS2 133 116 ertn 134 117 135 135 - #ifdef CONFIG_64BIT 136 118 vmalloc_load: 137 119 la_abs t1, swapper_pg_dir 138 120 b vmalloc_done_load 139 139 - #endif 140 121 141 122 /* This is the entry point of a huge page. */ 142 123 tlb_huge_update_load: 143 124 #ifdef CONFIG_SMP 144 144 - ll.d ra, t1, 0 125 125 + PTE_LL ra, t1, 0 145 126 #else 146 146 - rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) 127 127 + PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1) 147 128 #endif 148 129 andi t0, ra, _PAGE_PRESENT 149 130 beqz t0, nopage_tlb_load 150 131 151 132 #ifdef CONFIG_SMP 152 133 ori t0, ra, _PAGE_VALID 153 153 - sc.d t0, t1, 0 134 134 + PTE_SC t0, t1, 0 154 135 beqz t0, tlb_huge_update_load 155 136 ori t0, ra, _PAGE_VALID 156 137 #else 157 138 ori t0, ra, _PAGE_VALID 158 158 - st.d t0, t1, 0 139 139 + PTR_S t0, t1, 0 159 140 #endif 160 141 csrrd ra, LOONGARCH_CSR_ASID 161 142 csrrd t1, LOONGARCH_CSR_BADV ··· 173 158 xori t0, t0, _PAGE_HUGE 174 159 lu12i.w t1, _PAGE_HGLOBAL >> 12 175 160 and t1, t0, t1 176 176 - srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) 161 161 + PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) 177 162 or t0, t0, t1 178 163 179 164 move ra, t0 180 165 csrwr ra, LOONGARCH_CSR_TLBELO0 181 166 182 167 /* Convert to entrylo1 */ 183 183 - addi.d t1, zero, 1 184 184 - slli.d t1, t1, (HPAGE_SHIFT - 1) 185 185 - add.d t0, t0, t1 168 168 + PTR_ADDI t1, zero, 1 169 169 + PTR_SLLI t1, t1, (HPAGE_SHIFT - 1) 170 170 + PTR_ADD t0, t0, t1 186 171 csrwr t0, LOONGARCH_CSR_TLBELO1 187 172 188 173 /* Set huge page tlb entry size */ 189 189 - addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) 190 190 - addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) 174 174 + PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16 175 175 + PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT)) 191 176 csrxchg t1, t0, LOONGARCH_CSR_TLBIDX 192 177 193 178 tlbfill 194 179 195 195 - addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) 196 196 - addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) 180 180 + PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16 181 181 + PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT)) 197 182 csrxchg t1, t0, LOONGARCH_CSR_TLBIDX 198 183 199 184 csrrd t0, EXCEPTION_KS0 ··· 231 216 232 217 vmalloc_done_store: 233 218 /* Get PGD offset in bytes */ 234 234 - bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT 235 235 - alsl.d t1, ra, t1, 3 219 219 + #ifdef CONFIG_32BIT 220 220 + PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT 221 221 + #else 222 222 + PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT 223 223 + #endif 224 224 + PTR_ALSL t1, ra, t1, _PGD_T_LOG2 225 225 + 236 226 #if CONFIG_PGTABLE_LEVELS > 3 237 237 - ld.d t1, t1, 0 238 238 - bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT 239 239 - alsl.d t1, ra, t1, 3 227 227 + PTR_L t1, t1, 0 228 228 + PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT 229 229 + PTR_ALSL t1, ra, t1, _PMD_T_LOG2 240 230 #endif 241 231 #if CONFIG_PGTABLE_LEVELS > 2 242 242 - ld.d t1, t1, 0 243 243 - bstrpick.d ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT 244 244 - alsl.d t1, ra, t1, 3 232 232 + PTR_L t1, t1, 0 233 233 + PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT 234 234 + PTR_ALSL t1, ra, t1, _PMD_T_LOG2 245 235 #endif 246 246 - ld.d ra, t1, 0 236 236 + PTR_L ra, t1, 0 247 237 248 238 /* 249 239 * For huge tlb entries, pmde doesn't contain an address but 250 240 * instead contains the tlb pte. Check the PAGE_HUGE bit and 251 241 * see if we need to jump to huge tlb processing. 252 242 */ 253 253 - rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1 243 243 + PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1 254 244 bltz ra, tlb_huge_update_store 255 245 256 256 - rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) 257 257 - bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT 258 258 - alsl.d t1, t0, ra, _PTE_T_LOG2 246 246 + PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1) 247 247 + PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT 248 248 + PTR_ALSL t1, t0, ra, _PTE_T_LOG2 259 249 260 250 #ifdef CONFIG_SMP 261 251 smp_pgtable_change_store: 262 262 - ll.d t0, t1, 0 252 252 + PTE_LL t0, t1, 0 263 253 #else 264 264 - ld.d t0, t1, 0 254 254 + PTR_L t0, t1, 0 265 255 #endif 256 256 + 257 257 + #ifdef CONFIG_64BIT 266 258 andi ra, t0, _PAGE_PRESENT | _PAGE_WRITE 267 259 xori ra, ra, _PAGE_PRESENT | _PAGE_WRITE 260 260 + #else 261 261 + PTR_LI ra, _PAGE_PRESENT | _PAGE_WRITE 262 262 + and ra, ra, t0 263 263 + nor ra, ra, zero 264 264 + #endif 268 265 bnez ra, nopage_tlb_store 269 266 267 267 + #ifdef CONFIG_64BIT 270 268 ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 269 269 + #else 270 270 + PTR_LI ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 271 271 + or t0, ra, t0 272 272 + #endif 273 273 + 271 274 #ifdef CONFIG_SMP 272 272 - sc.d t0, t1, 0 275 275 + PTE_SC t0, t1, 0 273 276 beqz t0, smp_pgtable_change_store 274 277 #else 275 275 - st.d t0, t1, 0 278 278 + PTR_S t0, t1, 0 276 279 #endif 277 280 tlbsrch 278 278 - bstrins.d t1, zero, 3, 3 279 279 - ld.d t0, t1, 0 280 280 - ld.d t1, t1, 8 281 281 + PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2 282 282 + PTR_L t0, t1, 0 283 283 + PTR_L t1, t1, _PTE_T_SIZE 281 284 csrwr t0, LOONGARCH_CSR_TLBELO0 282 285 csrwr t1, LOONGARCH_CSR_TLBELO1 283 286 tlbwr ··· 305 272 csrrd ra, EXCEPTION_KS2 306 273 ertn 307 274 308 308 - #ifdef CONFIG_64BIT 309 275 vmalloc_store: 310 276 la_abs t1, swapper_pg_dir 311 277 b vmalloc_done_store 312 312 - #endif 313 278 314 279 /* This is the entry point of a huge page. */ 315 280 tlb_huge_update_store: 316 281 #ifdef CONFIG_SMP 317 317 - ll.d ra, t1, 0 282 282 + PTE_LL ra, t1, 0 318 283 #else 319 319 - rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) 284 284 + PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1) 320 285 #endif 286 286 + 287 287 + #ifdef CONFIG_64BIT 321 288 andi t0, ra, _PAGE_PRESENT | _PAGE_WRITE 322 289 xori t0, t0, _PAGE_PRESENT | _PAGE_WRITE 290 290 + #else 291 291 + PTR_LI t0, _PAGE_PRESENT | _PAGE_WRITE 292 292 + and t0, t0, ra 293 293 + nor t0, t0, zero 294 294 + #endif 295 295 + 323 296 bnez t0, nopage_tlb_store 324 297 325 298 #ifdef CONFIG_SMP 326 299 ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 327 327 - sc.d t0, t1, 0 300 300 + PTE_SC t0, t1, 0 328 301 beqz t0, tlb_huge_update_store 329 302 ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 330 303 #else 304 304 + #ifdef CONFIG_64BIT 331 305 ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 332 332 - st.d t0, t1, 0 306 306 + #else 307 307 + PTR_LI t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 308 308 + or t0, ra, t0 309 309 + #endif 310 310 + PTR_S t0, t1, 0 333 311 #endif 334 312 csrrd ra, LOONGARCH_CSR_ASID 335 313 csrrd t1, LOONGARCH_CSR_BADV ··· 360 316 xori t0, t0, _PAGE_HUGE 361 317 lu12i.w t1, _PAGE_HGLOBAL >> 12 362 318 and t1, t0, t1 363 363 - srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) 319 319 + PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) 364 320 or t0, t0, t1 365 321 366 322 move ra, t0 367 323 csrwr ra, LOONGARCH_CSR_TLBELO0 368 324 369 325 /* Convert to entrylo1 */ 370 370 - addi.d t1, zero, 1 371 371 - slli.d t1, t1, (HPAGE_SHIFT - 1) 372 372 - add.d t0, t0, t1 326 326 + PTR_ADDI t1, zero, 1 327 327 + PTR_SLLI t1, t1, (HPAGE_SHIFT - 1) 328 328 + PTR_ADD t0, t0, t1 373 329 csrwr t0, LOONGARCH_CSR_TLBELO1 374 330 375 331 /* Set huge page tlb entry size */ 376 376 - addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) 377 377 - addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) 332 332 + PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16 333 333 + PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT)) 378 334 csrxchg t1, t0, LOONGARCH_CSR_TLBIDX 379 335 380 336 tlbfill 381 337 382 338 /* Reset default page size */ 383 383 - addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) 384 384 - addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) 339 339 + PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16 340 340 + PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT)) 385 341 csrxchg t1, t0, LOONGARCH_CSR_TLBIDX 386 342 387 343 csrrd t0, EXCEPTION_KS0 ··· 419 375 420 376 vmalloc_done_modify: 421 377 /* Get PGD offset in bytes */ 422 422 - bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT 423 423 - alsl.d t1, ra, t1, 3 378 378 + #ifdef CONFIG_32BIT 379 379 + PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT 380 380 + #else 381 381 + PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT 382 382 + #endif 383 383 + PTR_ALSL t1, ra, t1, _PGD_T_LOG2 384 384 + 424 385 #if CONFIG_PGTABLE_LEVELS > 3 425 425 - ld.d t1, t1, 0 426 426 - bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT 427 427 - alsl.d t1, ra, t1, 3 386 386 + PTR_L t1, t1, 0 387 387 + PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT 388 388 + PTR_ALSL t1, ra, t1, _PMD_T_LOG2 428 389 #endif 429 390 #if CONFIG_PGTABLE_LEVELS > 2 430 430 - ld.d t1, t1, 0 431 431 - bstrpick.d ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT 432 432 - alsl.d t1, ra, t1, 3 391 391 + PTR_L t1, t1, 0 392 392 + PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT 393 393 + PTR_ALSL t1, ra, t1, _PMD_T_LOG2 433 394 #endif 434 434 - ld.d ra, t1, 0 395 395 + PTR_L ra, t1, 0 435 396 436 397 /* 437 398 * For huge tlb entries, pmde doesn't contain an address but 438 399 * instead contains the tlb pte. Check the PAGE_HUGE bit and 439 400 * see if we need to jump to huge tlb processing. 440 401 */ 441 441 - rotri.d ra, ra, _PAGE_HUGE_SHIFT + 1 402 402 + PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1 442 403 bltz ra, tlb_huge_update_modify 443 404 444 444 - rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) 445 445 - bstrpick.d t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT 446 446 - alsl.d t1, t0, ra, _PTE_T_LOG2 405 405 + PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1) 406 406 + PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT 407 407 + PTR_ALSL t1, t0, ra, _PTE_T_LOG2 447 408 448 409 #ifdef CONFIG_SMP 449 410 smp_pgtable_change_modify: 450 450 - ll.d t0, t1, 0 411 411 + PTE_LL t0, t1, 0 451 412 #else 452 452 - ld.d t0, t1, 0 413 413 + PTR_L t0, t1, 0 453 414 #endif 415 415 + #ifdef CONFIG_64BIT 454 416 andi ra, t0, _PAGE_WRITE 417 417 + #else 418 418 + PTR_LI ra, _PAGE_WRITE 419 419 + and ra, t0, ra 420 420 + #endif 421 421 + 455 422 beqz ra, nopage_tlb_modify 456 423 424 424 + #ifdef CONFIG_64BIT 457 425 ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 426 426 + #else 427 427 + PTR_LI ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 428 428 + or t0, ra, t0 429 429 + #endif 430 430 + 458 431 #ifdef CONFIG_SMP 459 459 - sc.d t0, t1, 0 432 432 + PTE_SC t0, t1, 0 460 433 beqz t0, smp_pgtable_change_modify 461 434 #else 462 462 - st.d t0, t1, 0 435 435 + PTR_S t0, t1, 0 463 436 #endif 464 437 tlbsrch 465 465 - bstrins.d t1, zero, 3, 3 466 466 - ld.d t0, t1, 0 467 467 - ld.d t1, t1, 8 438 438 + PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2 439 439 + PTR_L t0, t1, 0 440 440 + PTR_L t1, t1, _PTE_T_SIZE 468 441 csrwr t0, LOONGARCH_CSR_TLBELO0 469 442 csrwr t1, LOONGARCH_CSR_TLBELO1 470 443 tlbwr ··· 491 430 csrrd ra, EXCEPTION_KS2 492 431 ertn 493 432 494 494 - #ifdef CONFIG_64BIT 495 433 vmalloc_modify: 496 434 la_abs t1, swapper_pg_dir 497 435 b vmalloc_done_modify 498 498 - #endif 499 436 500 437 /* This is the entry point of a huge page. */ 501 438 tlb_huge_update_modify: 502 439 #ifdef CONFIG_SMP 503 503 - ll.d ra, t1, 0 440 440 + PTE_LL ra, t1, 0 504 441 #else 505 505 - rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1) 442 442 + PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1) 506 443 #endif 444 444 + 445 445 + #ifdef CONFIG_64BIT 507 446 andi t0, ra, _PAGE_WRITE 447 447 + #else 448 448 + PTR_LI t0, _PAGE_WRITE 449 449 + and t0, ra, t0 450 450 + #endif 451 451 + 508 452 beqz t0, nopage_tlb_modify 509 453 510 454 #ifdef CONFIG_SMP 511 455 ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 512 512 - sc.d t0, t1, 0 456 456 + PTE_SC t0, t1, 0 513 457 beqz t0, tlb_huge_update_modify 514 458 ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 515 459 #else 460 460 + #ifdef CONFIG_64BIT 516 461 ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 517 517 - st.d t0, t1, 0 462 462 + #else 463 463 + PTR_LI t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) 464 464 + or t0, ra, t0 465 465 + #endif 466 466 + PTR_S t0, t1, 0 518 467 #endif 519 468 csrrd ra, LOONGARCH_CSR_ASID 520 469 csrrd t1, LOONGARCH_CSR_BADV ··· 544 473 xori t0, t0, _PAGE_HUGE 545 474 lu12i.w t1, _PAGE_HGLOBAL >> 12 546 475 and t1, t0, t1 547 547 - srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) 476 476 + PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) 548 477 or t0, t0, t1 549 478 550 479 move ra, t0 551 480 csrwr ra, LOONGARCH_CSR_TLBELO0 552 481 553 482 /* Convert to entrylo1 */ 554 554 - addi.d t1, zero, 1 555 555 - slli.d t1, t1, (HPAGE_SHIFT - 1) 556 556 - add.d t0, t0, t1 483 483 + PTR_ADDI t1, zero, 1 484 484 + PTR_SLLI t1, t1, (HPAGE_SHIFT - 1) 485 485 + PTR_ADD t0, t0, t1 557 486 csrwr t0, LOONGARCH_CSR_TLBELO1 558 487 559 488 /* Set huge page tlb entry size */ 560 560 - addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) 561 561 - addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) 489 489 + PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16 490 490 + PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT)) 562 491 csrxchg t1, t0, LOONGARCH_CSR_TLBIDX 563 492 564 493 tlbfill 565 494 566 495 /* Reset default page size */ 567 567 - addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) 568 568 - addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) 496 496 + PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16 497 497 + PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT)) 569 498 csrxchg t1, t0, LOONGARCH_CSR_TLBIDX 570 499 571 500 csrrd t0, EXCEPTION_KS0 ··· 588 517 jr t0 589 518 SYM_CODE_END(handle_tlb_modify_ptw) 590 519 520 520 + #ifdef CONFIG_32BIT 521 521 + SYM_CODE_START(handle_tlb_refill) 522 522 + UNWIND_HINT_UNDEFINED 523 523 + csrwr t0, EXCEPTION_KS0 524 524 + csrwr t1, EXCEPTION_KS1 525 525 + csrwr ra, EXCEPTION_KS2 526 526 + li.w ra, 0x1fffffff 527 527 + 528 528 + csrrd t0, LOONGARCH_CSR_PGD 529 529 + csrrd t1, LOONGARCH_CSR_TLBRBADV 530 530 + srli.w t1, t1, PGDIR_SHIFT 531 531 + slli.w t1, t1, 0x2 532 532 + add.w t0, t0, t1 533 533 + and t0, t0, ra 534 534 + 535 535 + ld.w t0, t0, 0 536 536 + csrrd t1, LOONGARCH_CSR_TLBRBADV 537 537 + slli.w t1, t1, (32 - PGDIR_SHIFT) 538 538 + srli.w t1, t1, (32 - PGDIR_SHIFT + PAGE_SHIFT + 1) 539 539 + slli.w t1, t1, (0x2 + 1) 540 540 + add.w t0, t0, t1 541 541 + and t0, t0, ra 542 542 + 543 543 + ld.w t1, t0, 0x0 544 544 + csrwr t1, LOONGARCH_CSR_TLBRELO0 545 545 + 546 546 + ld.w t1, t0, 0x4 547 547 + csrwr t1, LOONGARCH_CSR_TLBRELO1 548 548 + 549 549 + tlbfill 550 550 + csrrd t0, EXCEPTION_KS0 551 551 + csrrd t1, EXCEPTION_KS1 552 552 + csrrd ra, EXCEPTION_KS2 553 553 + ertn 554 554 + SYM_CODE_END(handle_tlb_refill) 555 555 + #endif 556 556 + 557 557 + #ifdef CONFIG_64BIT 591 558 SYM_CODE_START(handle_tlb_refill) 592 559 UNWIND_HINT_UNDEFINED 593 560 csrwr t0, LOONGARCH_CSR_TLBRSAVE ··· 643 534 csrrd t0, LOONGARCH_CSR_TLBRSAVE 644 535 ertn 645 536 SYM_CODE_END(handle_tlb_refill) 537 537 + #endif

+2

arch/loongarch/pci/pci.c

reviewed

··· 14 14 #define PCI_DEVICE_ID_LOONGSON_HOST 0x7a00 15 15 #define PCI_DEVICE_ID_LOONGSON_DC1 0x7a06 16 16 #define PCI_DEVICE_ID_LOONGSON_DC2 0x7a36 17 17 + #define PCI_DEVICE_ID_LOONGSON_DC3 0x7a46 17 18 18 19 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 19 20 int reg, int len, u32 *val) ··· 98 97 } 99 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC1, pci_fixup_vgadev); 100 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC2, pci_fixup_vgadev); 100 100 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DC3, pci_fixup_vgadev);

+3 -3

arch/loongarch/power/hibernate.c

reviewed

··· 10 10 static u32 saved_prmd; 11 11 static u32 saved_euen; 12 12 static u32 saved_ecfg; 13 13 - static u64 saved_pcpu_base; 13 13 + static unsigned long saved_pcpu_base; 14 14 struct pt_regs saved_regs; 15 15 16 16 void save_processor_state(void) ··· 20 20 saved_prmd = csr_read32(LOONGARCH_CSR_PRMD); 21 21 saved_euen = csr_read32(LOONGARCH_CSR_EUEN); 22 22 saved_ecfg = csr_read32(LOONGARCH_CSR_ECFG); 23 23 - saved_pcpu_base = csr_read64(PERCPU_BASE_KS); 23 23 + saved_pcpu_base = csr_read(PERCPU_BASE_KS); 24 24 25 25 if (is_fpu_owner()) 26 26 save_fp(current); ··· 33 33 csr_write32(saved_prmd, LOONGARCH_CSR_PRMD); 34 34 csr_write32(saved_euen, LOONGARCH_CSR_EUEN); 35 35 csr_write32(saved_ecfg, LOONGARCH_CSR_ECFG); 36 36 - csr_write64(saved_pcpu_base, PERCPU_BASE_KS); 36 36 + csr_write(saved_pcpu_base, PERCPU_BASE_KS); 37 37 38 38 if (is_fpu_owner()) 39 39 restore_fp(current);

+2 -2

arch/loongarch/power/platform.c

reviewed

··· 72 72 status = acpi_evaluate_integer(NULL, "\\SADR", NULL, &suspend_addr); 73 73 if (ACPI_FAILURE(status) || !suspend_addr) { 74 74 pr_info("ACPI S3 supported with hardware register default\n"); 75 75 - loongson_sysconf.suspend_addr = (u64)default_suspend_addr; 75 75 + loongson_sysconf.suspend_addr = (unsigned long)default_suspend_addr; 76 76 } else { 77 77 pr_info("ACPI S3 supported with Loongson ACPI SADR extension\n"); 78 78 - loongson_sysconf.suspend_addr = (u64)phys_to_virt(PHYSADDR(suspend_addr)); 78 78 + loongson_sysconf.suspend_addr = (unsigned long)phys_to_virt(PHYSADDR(suspend_addr)); 79 79 } 80 80 #endif 81 81 return 0;

+12 -12

arch/loongarch/power/suspend.c

reviewed

··· 20 20 struct saved_registers { 21 21 u32 ecfg; 22 22 u32 euen; 23 23 - u64 pgd; 24 24 - u64 kpgd; 25 23 u32 pwctl0; 26 24 u32 pwctl1; 27 27 - u64 pcpu_base; 25 25 + unsigned long pgd; 26 26 + unsigned long kpgd; 27 27 + unsigned long pcpu_base; 28 28 }; 29 29 static struct saved_registers saved_regs; 30 30 31 31 void loongarch_common_suspend(void) 32 32 { 33 33 save_counter(); 34 34 - saved_regs.pgd = csr_read64(LOONGARCH_CSR_PGDL); 35 35 - saved_regs.kpgd = csr_read64(LOONGARCH_CSR_PGDH); 34 34 + saved_regs.pgd = csr_read(LOONGARCH_CSR_PGDL); 35 35 + saved_regs.kpgd = csr_read(LOONGARCH_CSR_PGDH); 36 36 saved_regs.pwctl0 = csr_read32(LOONGARCH_CSR_PWCTL0); 37 37 saved_regs.pwctl1 = csr_read32(LOONGARCH_CSR_PWCTL1); 38 38 saved_regs.ecfg = csr_read32(LOONGARCH_CSR_ECFG); 39 39 saved_regs.euen = csr_read32(LOONGARCH_CSR_EUEN); 40 40 - saved_regs.pcpu_base = csr_read64(PERCPU_BASE_KS); 40 40 + saved_regs.pcpu_base = csr_read(PERCPU_BASE_KS); 41 41 42 42 loongarch_suspend_addr = loongson_sysconf.suspend_addr; 43 43 } ··· 46 46 { 47 47 sync_counter(); 48 48 local_flush_tlb_all(); 49 49 - csr_write64(eentry, LOONGARCH_CSR_EENTRY); 50 50 - csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 51 51 - csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 49 49 + csr_write(eentry, LOONGARCH_CSR_EENTRY); 50 50 + csr_write(eentry, LOONGARCH_CSR_MERRENTRY); 51 51 + csr_write(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 52 52 53 53 - csr_write64(saved_regs.pgd, LOONGARCH_CSR_PGDL); 54 54 - csr_write64(saved_regs.kpgd, LOONGARCH_CSR_PGDH); 53 53 + csr_write(saved_regs.pgd, LOONGARCH_CSR_PGDL); 54 54 + csr_write(saved_regs.kpgd, LOONGARCH_CSR_PGDH); 55 55 csr_write32(saved_regs.pwctl0, LOONGARCH_CSR_PWCTL0); 56 56 csr_write32(saved_regs.pwctl1, LOONGARCH_CSR_PWCTL1); 57 57 csr_write32(saved_regs.ecfg, LOONGARCH_CSR_ECFG); 58 58 csr_write32(saved_regs.euen, LOONGARCH_CSR_EUEN); 59 59 - csr_write64(saved_regs.pcpu_base, PERCPU_BASE_KS); 59 59 + csr_write(saved_regs.pcpu_base, PERCPU_BASE_KS); 60 60 } 61 61 62 62 int loongarch_acpi_suspend(void)

+36 -36

arch/loongarch/power/suspend_asm.S

reviewed

··· 14 14 15 15 /* preparatory stuff */ 16 16 .macro SETUP_SLEEP 17 17 - addi.d sp, sp, -PT_SIZE 18 18 - st.d $r1, sp, PT_R1 19 19 - st.d $r2, sp, PT_R2 20 20 - st.d $r3, sp, PT_R3 21 21 - st.d $r4, sp, PT_R4 22 22 - st.d $r21, sp, PT_R21 23 23 - st.d $r22, sp, PT_R22 24 24 - st.d $r23, sp, PT_R23 25 25 - st.d $r24, sp, PT_R24 26 26 - st.d $r25, sp, PT_R25 27 27 - st.d $r26, sp, PT_R26 28 28 - st.d $r27, sp, PT_R27 29 29 - st.d $r28, sp, PT_R28 30 30 - st.d $r29, sp, PT_R29 31 31 - st.d $r30, sp, PT_R30 32 32 - st.d $r31, sp, PT_R31 17 17 + PTR_ADDI sp, sp, -PT_SIZE 18 18 + REG_S $r1, sp, PT_R1 19 19 + REG_S $r2, sp, PT_R2 20 20 + REG_S $r3, sp, PT_R3 21 21 + REG_S $r4, sp, PT_R4 22 22 + REG_S $r21, sp, PT_R21 23 23 + REG_S $r22, sp, PT_R22 24 24 + REG_S $r23, sp, PT_R23 25 25 + REG_S $r24, sp, PT_R24 26 26 + REG_S $r25, sp, PT_R25 27 27 + REG_S $r26, sp, PT_R26 28 28 + REG_S $r27, sp, PT_R27 29 29 + REG_S $r28, sp, PT_R28 30 30 + REG_S $r29, sp, PT_R29 31 31 + REG_S $r30, sp, PT_R30 32 32 + REG_S $r31, sp, PT_R31 33 33 .endm 34 34 35 35 .macro SETUP_WAKEUP 36 36 - ld.d $r1, sp, PT_R1 37 37 - ld.d $r2, sp, PT_R2 38 38 - ld.d $r3, sp, PT_R3 39 39 - ld.d $r4, sp, PT_R4 40 40 - ld.d $r21, sp, PT_R21 41 41 - ld.d $r22, sp, PT_R22 42 42 - ld.d $r23, sp, PT_R23 43 43 - ld.d $r24, sp, PT_R24 44 44 - ld.d $r25, sp, PT_R25 45 45 - ld.d $r26, sp, PT_R26 46 46 - ld.d $r27, sp, PT_R27 47 47 - ld.d $r28, sp, PT_R28 48 48 - ld.d $r29, sp, PT_R29 49 49 - ld.d $r30, sp, PT_R30 50 50 - ld.d $r31, sp, PT_R31 51 51 - addi.d sp, sp, PT_SIZE 36 36 + REG_L $r1, sp, PT_R1 37 37 + REG_L $r2, sp, PT_R2 38 38 + REG_L $r3, sp, PT_R3 39 39 + REG_L $r4, sp, PT_R4 40 40 + REG_L $r21, sp, PT_R21 41 41 + REG_L $r22, sp, PT_R22 42 42 + REG_L $r23, sp, PT_R23 43 43 + REG_L $r24, sp, PT_R24 44 44 + REG_L $r25, sp, PT_R25 45 45 + REG_L $r26, sp, PT_R26 46 46 + REG_L $r27, sp, PT_R27 47 47 + REG_L $r28, sp, PT_R28 48 48 + REG_L $r29, sp, PT_R29 49 49 + REG_L $r30, sp, PT_R30 50 50 + REG_L $r31, sp, PT_R31 51 51 + PTR_ADDI sp, sp, PT_SIZE 52 52 .endm 53 53 54 54 .text ··· 59 59 SETUP_SLEEP 60 60 61 61 la.pcrel t0, acpi_saved_sp 62 62 - st.d sp, t0, 0 62 62 + REG_S sp, t0, 0 63 63 64 64 bl __flush_cache_all 65 65 66 66 /* Pass RA and SP to BIOS */ 67 67 - addi.d a1, sp, 0 67 67 + PTR_ADDI a1, sp, 0 68 68 la.pcrel a0, loongarch_wakeup_start 69 69 la.pcrel t0, loongarch_suspend_addr 70 70 - ld.d t0, t0, 0 70 70 + REG_L t0, t0, 0 71 71 jirl ra, t0, 0 /* Call BIOS's STR sleep routine */ 72 72 73 73 /* ··· 83 83 csrwr t0, LOONGARCH_CSR_CRMD 84 84 85 85 la.pcrel t0, acpi_saved_sp 86 86 - ld.d sp, t0, 0 86 86 + REG_L sp, t0, 0 87 87 88 88 SETUP_WAKEUP 89 89 jr ra

+6 -1

arch/loongarch/vdso/Makefile

reviewed

··· 4 4 # Include the generic Makefile to check the built vdso. 5 5 include $(srctree)/lib/vdso/Makefile.include 6 6 7 7 - obj-vdso-y := elf.o vgetcpu.o vgettimeofday.o vgetrandom.o \ 7 7 + obj-vdso-y := elf.o vgetcpu.o vgetrandom.o \ 8 8 vgetrandom-chacha.o sigreturn.o 9 9 + obj-vdso-$(CONFIG_GENERIC_GETTIMEOFDAY) += vgettimeofday.o 9 10 10 11 # Common compiler flags between ABIs. 11 12 ccflags-vdso := \ ··· 16 15 $(filter -m%-float,$(KBUILD_CFLAGS)) \ 17 16 $(CLANG_FLAGS) \ 18 17 -D__VDSO__ 18 18 + 19 19 + ifdef CONFIG_32BIT 20 20 + ccflags-vdso += -DBUILD_VDSO32 21 21 + endif 19 22 20 23 cflags-vdso := $(ccflags-vdso) \ 21 24 -isystem $(shell $(CC) -print-file-name=include) \

+2 -2

arch/loongarch/vdso/vdso.lds.S

reviewed

··· 7 7 #include <generated/asm-offsets.h> 8 8 #include <vdso/datapage.h> 9 9 10 10 - OUTPUT_FORMAT("elf64-loongarch", "elf64-loongarch", "elf64-loongarch") 11 11 - 12 10 OUTPUT_ARCH(loongarch) 13 11 14 12 SECTIONS ··· 61 63 LINUX_5.10 { 62 64 global: 63 65 __vdso_getcpu; 66 66 + #ifdef CONFIG_GENERIC_GETTIMEOFDAY 64 67 __vdso_clock_getres; 65 68 __vdso_clock_gettime; 66 69 __vdso_gettimeofday; 70 70 + #endif 67 71 __vdso_getrandom; 68 72 __vdso_rt_sigreturn; 69 73 local: *;

+8

arch/loongarch/vdso/vgetcpu.c

reviewed

··· 10 10 { 11 11 int cpu_id; 12 12 13 13 + #ifdef CONFIG_64BIT 13 14 __asm__ __volatile__( 14 15 " rdtime.d $zero, %0\n" 15 16 : "=r" (cpu_id) 16 17 : 17 18 : "memory"); 19 19 + #else 20 20 + __asm__ __volatile__( 21 21 + " rdtimel.w $zero, %0\n" 22 22 + : "=r" (cpu_id) 23 23 + : 24 24 + : "memory"); 25 25 + #endif 18 26 19 27 return cpu_id; 20 28 }

+4 -4

drivers/firmware/efi/libstub/loongarch.c

reviewed

··· 72 72 desc_ver, priv.runtime_map); 73 73 74 74 /* Config Direct Mapping */ 75 75 - csr_write64(CSR_DMW0_INIT, LOONGARCH_CSR_DMWIN0); 76 76 - csr_write64(CSR_DMW1_INIT, LOONGARCH_CSR_DMWIN1); 77 77 - csr_write64(CSR_DMW2_INIT, LOONGARCH_CSR_DMWIN2); 78 78 - csr_write64(CSR_DMW3_INIT, LOONGARCH_CSR_DMWIN3); 75 75 + csr_write(CSR_DMW0_INIT, LOONGARCH_CSR_DMWIN0); 76 76 + csr_write(CSR_DMW1_INIT, LOONGARCH_CSR_DMWIN1); 77 77 + csr_write(CSR_DMW2_INIT, LOONGARCH_CSR_DMWIN2); 78 78 + csr_write(CSR_DMW3_INIT, LOONGARCH_CSR_DMWIN3); 79 79 80 80 real_kernel_entry = (void *)kernel_entry_address(kernel_addr, image); 81 81

+3 -2

drivers/irqchip/irq-loongarch-avec.c

reviewed

··· 209 209 struct avecintc_data *adata = irq_data_get_irq_chip_data(d); 210 210 211 211 msg->address_hi = 0x0; 212 212 - msg->address_lo = (loongarch_avec.msi_base_addr | (adata->vec & 0xff) << 4) 213 213 - | ((cpu_logical_map(adata->cpu & 0xffff)) << 12); 212 212 + msg->address_lo = (loongarch_avec.msi_base_addr | 213 213 + (adata->vec & AVEC_IRQ_MASK) << AVEC_IRQ_SHIFT) | 214 214 + ((cpu_logical_map(adata->cpu & AVEC_CPU_MASK)) << AVEC_CPU_SHIFT); 214 215 msg->data = 0x0; 215 216 } 216 217