Merge branch 'net-dsa-microchip-adjust-ptp-handling-to-ease-ksz8463-integration'

+14 -1

drivers/net/dsa/microchip/ksz_common.c

··· 569 569 [S_START_CTRL] = 0x01, 570 570 [S_BROADCAST_CTRL] = 0x06, 571 571 [S_MULTICAST_CTRL] = 0x04, 572 + [PTP_CLK_CTRL] = 0x0600, 573 + [PTP_RTC_NANOSEC] = 0x0604, 574 + [PTP_RTC_SEC] = 0x0608, 575 + [PTP_RTC_SUB_NANOSEC] = 0x060C, 576 + [PTP_SUBNANOSEC_RATE] = 0x0610, 577 + [PTP_MSG_CONF1] = 0x0620, 572 578 }; 573 579 574 580 static const u32 ksz8463_masks[] = { ··· 809 803 [REG_SW_PME_CTRL] = 0x0006, 810 804 [REG_PORT_PME_STATUS] = 0x0013, 811 805 [REG_PORT_PME_CTRL] = 0x0017, 806 + [PTP_CLK_CTRL] = 0x0500, 807 + [PTP_RTC_SUB_NANOSEC] = 0x0502, 808 + [PTP_RTC_NANOSEC] = 0x0504, 809 + [PTP_RTC_SEC] = 0x0508, 810 + [PTP_SUBNANOSEC_RATE] = 0x050C, 811 + [PTP_MSG_CONF1] = 0x0514, 812 812 }; 813 813 814 814 static const u32 ksz9477_masks[] = { ··· 2917 2905 int ret, n; 2918 2906 2919 2907 kirq->dev = dev; 2920 - kirq->masked = ~0; 2921 2908 2922 2909 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0, 2923 2910 &ksz_irq_domain_ops, kirq); ··· 2946 2935 girq->nirqs = dev->info->port_cnt; 2947 2936 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2948 2937 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2938 + girq->masked = ~0; 2949 2939 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2950 2940 2951 2941 girq->irq_num = dev->irq; ··· 2961 2949 pirq->nirqs = dev->info->port_nirqs; 2962 2950 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2963 2951 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2952 + pirq->masked = ~0; 2964 2953 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2965 2954 2966 2955 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);

+7

drivers/net/dsa/microchip/ksz_common.h

··· 108 108 int irq_num; 109 109 char name[16]; 110 110 struct ksz_device *dev; 111 + u16 irq0_offset; 111 112 }; 112 113 113 114 struct ksz_ptp_irq { ··· 271 270 REG_SW_PME_CTRL, 272 271 REG_PORT_PME_STATUS, 273 272 REG_PORT_PME_CTRL, 273 + PTP_CLK_CTRL, 274 + PTP_RTC_NANOSEC, 275 + PTP_RTC_SEC, 276 + PTP_RTC_SUB_NANOSEC, 277 + PTP_SUBNANOSEC_RATE, 278 + PTP_MSG_CONF1, 274 279 }; 275 280 276 281 enum ksz_masks {

+39 -24

drivers/net/dsa/microchip/ksz_ptp.c

··· 263 263 { 264 264 struct ksz_tagger_data *tagger_data = ksz_tagger_data(dev->ds); 265 265 struct ksz_ptp_data *ptp_data = &dev->ptp_data; 266 + const u16 *regs = dev->info->regs; 266 267 struct ksz_port *prt; 267 268 struct dsa_port *dp; 268 269 bool tag_en = false; ··· 284 283 285 284 tagger_data->hwtstamp_set_state(dev->ds, tag_en); 286 285 287 - return ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_ENABLE, 286 + return ksz_rmw16(dev, regs[PTP_MSG_CONF1], PTP_ENABLE, 288 287 tag_en ? PTP_ENABLE : 0); 289 288 } 290 289 ··· 336 335 struct ksz_port *prt, 337 336 struct kernel_hwtstamp_config *config) 338 337 { 338 + const u16 *regs = dev->info->regs; 339 339 int ret; 340 340 341 341 if (config->flags) ··· 355 353 prt->ptpmsg_irq[KSZ_PDRES_MSG].ts_en = false; 356 354 prt->hwts_tx_en = true; 357 355 358 - ret = ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_1STEP, PTP_1STEP); 356 + ret = ksz_rmw16(dev, regs[PTP_MSG_CONF1], PTP_1STEP, PTP_1STEP); 359 357 if (ret) 360 358 return ret; 361 359 ··· 369 367 prt->ptpmsg_irq[KSZ_PDRES_MSG].ts_en = true; 370 368 prt->hwts_tx_en = true; 371 369 372 - ret = ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_1STEP, 0); 370 + ret = ksz_rmw16(dev, regs[PTP_MSG_CONF1], PTP_1STEP, 0); 373 371 if (ret) 374 372 return ret; 375 373 ··· 587 585 588 586 static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts) 589 587 { 588 + const u16 *regs = dev->info->regs; 590 589 u32 nanoseconds; 591 590 u32 seconds; 592 591 u8 phase; 593 592 int ret; 594 593 595 594 /* Copy current PTP clock into shadow registers and read */ 596 - ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_READ_TIME, PTP_READ_TIME); 595 + ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_READ_TIME, PTP_READ_TIME); 597 596 if (ret) 598 597 return ret; 599 598 600 - ret = ksz_read8(dev, REG_PTP_RTC_SUB_NANOSEC__2, &phase); 599 + ret = ksz_read8(dev, regs[PTP_RTC_SUB_NANOSEC], &phase); 601 600 if (ret) 602 601 return ret; 603 602 604 - ret = ksz_read32(dev, REG_PTP_RTC_NANOSEC, &nanoseconds); 603 + ret = ksz_read32(dev, regs[PTP_RTC_NANOSEC], &nanoseconds); 605 604 if (ret) 606 605 return ret; 607 606 608 - ret = ksz_read32(dev, REG_PTP_RTC_SEC, &seconds); 607 + ret = ksz_read32(dev, regs[PTP_RTC_SEC], &seconds); 609 608 if (ret) 610 609 return ret; 611 610 ··· 679 676 { 680 677 struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); 681 678 struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); 679 + const u16 *regs = dev->info->regs; 682 680 int ret; 683 681 684 682 mutex_lock(&ptp_data->lock); 685 683 686 684 /* Write to shadow registers and Load PTP clock */ 687 - ret = ksz_write16(dev, REG_PTP_RTC_SUB_NANOSEC__2, PTP_RTC_0NS); 685 + ret = ksz_write16(dev, regs[PTP_RTC_SUB_NANOSEC], PTP_RTC_0NS); 688 686 if (ret) 689 687 goto unlock; 690 688 691 - ret = ksz_write32(dev, REG_PTP_RTC_NANOSEC, ts->tv_nsec); 689 + ret = ksz_write32(dev, regs[PTP_RTC_NANOSEC], ts->tv_nsec); 692 690 if (ret) 693 691 goto unlock; 694 692 695 - ret = ksz_write32(dev, REG_PTP_RTC_SEC, ts->tv_sec); 693 + ret = ksz_write32(dev, regs[PTP_RTC_SEC], ts->tv_sec); 696 694 if (ret) 697 695 goto unlock; 698 696 699 - ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_LOAD_TIME, PTP_LOAD_TIME); 697 + ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_LOAD_TIME, PTP_LOAD_TIME); 700 698 if (ret) 701 699 goto unlock; 702 700 ··· 727 723 { 728 724 struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); 729 725 struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); 726 + const u16 *regs = dev->info->regs; 730 727 u64 base, adj; 731 728 bool negative; 732 729 u32 data32; ··· 744 739 if (!negative) 745 740 data32 |= PTP_RATE_DIR; 746 741 747 - ret = ksz_write32(dev, REG_PTP_SUBNANOSEC_RATE, data32); 742 + ret = ksz_write32(dev, regs[PTP_SUBNANOSEC_RATE], data32); 748 743 if (ret) 749 744 goto unlock; 750 745 751 - ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE, 746 + ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ADJ_ENABLE, 752 747 PTP_CLK_ADJ_ENABLE); 753 748 if (ret) 754 749 goto unlock; 755 750 } else { 756 - ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE, 0); 751 + ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ADJ_ENABLE, 0); 757 752 if (ret) 758 753 goto unlock; 759 754 } ··· 768 763 struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp); 769 764 struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data); 770 765 struct timespec64 delta64 = ns_to_timespec64(delta); 766 + const u16 *regs = dev->info->regs; 771 767 s32 sec, nsec; 772 768 u16 data16; 773 769 int ret; ··· 780 774 */ 781 775 sec = div_s64_rem(delta, NSEC_PER_SEC, &nsec); 782 776 783 - ret = ksz_write32(dev, REG_PTP_RTC_NANOSEC, abs(nsec)); 777 + ret = ksz_write32(dev, regs[PTP_RTC_NANOSEC], abs(nsec)); 784 778 if (ret) 785 779 goto unlock; 786 780 787 - ret = ksz_write32(dev, REG_PTP_RTC_SEC, abs(sec)); 781 + ret = ksz_write32(dev, regs[PTP_RTC_SEC], abs(sec)); 788 782 if (ret) 789 783 goto unlock; 790 784 791 - ret = ksz_read16(dev, REG_PTP_CLK_CTRL, &data16); 785 + ret = ksz_read16(dev, regs[PTP_CLK_CTRL], &data16); 792 786 if (ret) 793 787 goto unlock; 794 788 ··· 800 794 else 801 795 data16 |= PTP_STEP_DIR; 802 796 803 - ret = ksz_write16(dev, REG_PTP_CLK_CTRL, data16); 797 + ret = ksz_write16(dev, regs[PTP_CLK_CTRL], data16); 804 798 if (ret) 805 799 goto unlock; 806 800 ··· 888 882 static int ksz_ptp_start_clock(struct ksz_device *dev) 889 883 { 890 884 struct ksz_ptp_data *ptp_data = &dev->ptp_data; 885 + const u16 *regs = dev->info->regs; 891 886 int ret; 892 887 893 - ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ENABLE, PTP_CLK_ENABLE); 888 + ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ENABLE, PTP_CLK_ENABLE); 894 889 if (ret) 895 890 return ret; 896 891 ··· 904 897 int ksz_ptp_clock_register(struct dsa_switch *ds) 905 898 { 906 899 struct ksz_device *dev = ds->priv; 900 + const u16 *regs = dev->info->regs; 907 901 struct ksz_ptp_data *ptp_data; 908 902 int ret; 909 903 u8 i; ··· 944 936 /* Currently only P2P mode is supported. When 802_1AS bit is set, it 945 937 * forwards all PTP packets to host port and none to other ports. 946 938 */ 947 - ret = ksz_rmw16(dev, REG_PTP_MSG_CONF1, PTP_TC_P2P | PTP_802_1AS, 939 + ret = ksz_rmw16(dev, regs[PTP_MSG_CONF1], PTP_TC_P2P | PTP_802_1AS, 948 940 PTP_TC_P2P | PTP_802_1AS); 949 941 if (ret) 950 942 return ret; ··· 967 959 ptp_clock_unregister(ptp_data->clock); 968 960 } 969 961 962 + static int ksz_read_ts(struct ksz_port *port, u16 reg, u32 *ts) 963 + { 964 + return ksz_read32(port->ksz_dev, reg, ts); 965 + } 966 + 970 967 static irqreturn_t ksz_ptp_msg_thread_fn(int irq, void *dev_id) 971 968 { 972 969 struct ksz_ptp_irq *ptpmsg_irq = dev_id; ··· 985 972 dev = port->ksz_dev; 986 973 987 974 if (ptpmsg_irq->ts_en) { 988 - ret = ksz_read32(dev, ptpmsg_irq->ts_reg, &tstamp_raw); 975 + ret = ksz_read_ts(port, ptpmsg_irq->ts_reg, &tstamp_raw); 989 976 if (ret) 990 977 return IRQ_NONE; 991 978 ··· 1021 1008 return IRQ_NONE; 1022 1009 1023 1010 for (n = 0; n < ptpirq->nirqs; ++n) { 1024 - if (data & BIT(n + KSZ_PTP_INT_START)) { 1011 + if (data & BIT(n + ptpirq->irq0_offset)) { 1025 1012 sub_irq = irq_find_mapping(ptpirq->domain, n); 1026 1013 handle_nested_irq(sub_irq); 1027 1014 ++nhandled; ··· 1036 1023 { 1037 1024 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1038 1025 1039 - kirq->masked &= ~BIT(d->hwirq + KSZ_PTP_INT_START); 1026 + kirq->masked &= ~BIT(d->hwirq + kirq->irq0_offset); 1040 1027 } 1041 1028 1042 1029 static void ksz_ptp_irq_unmask(struct irq_data *d) 1043 1030 { 1044 1031 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1045 1032 1046 - kirq->masked |= BIT(d->hwirq + KSZ_PTP_INT_START); 1033 + kirq->masked |= BIT(d->hwirq + kirq->irq0_offset); 1047 1034 } 1048 1035 1049 1036 static void ksz_ptp_irq_bus_lock(struct irq_data *d) ··· 1139 1126 ptpirq->reg_mask = ops->get_port_addr(p, REG_PTP_PORT_TX_INT_ENABLE__2); 1140 1127 ptpirq->reg_status = ops->get_port_addr(p, 1141 1128 REG_PTP_PORT_TX_INT_STATUS__2); 1129 + ptpirq->irq0_offset = KSZ_PTP_INT_START; 1130 + 1142 1131 snprintf(ptpirq->name, sizeof(ptpirq->name), "ptp-irq-%d", p); 1143 1132 1144 1133 init_completion(&port->tstamp_msg_comp);

+4 -12

drivers/net/dsa/microchip/ksz_ptp_reg.h

··· 15 15 #define LED_SRC_PTP_GPIO_2 BIT(2) 16 16 17 17 /* 5 - PTP Clock */ 18 - #define REG_PTP_CLK_CTRL 0x0500 19 - 18 + /* REG_PTP_CLK_CTRL */ 20 19 #define PTP_STEP_ADJ BIT(6) 21 20 #define PTP_STEP_DIR BIT(5) 22 21 #define PTP_READ_TIME BIT(4) ··· 24 25 #define PTP_CLK_ENABLE BIT(1) 25 26 #define PTP_CLK_RESET BIT(0) 26 27 27 - #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502 28 - 28 + /* REG_PTP_RTC_SUB_NANOSEC */ 29 29 #define PTP_RTC_SUB_NANOSEC_M 0x0007 30 30 #define PTP_RTC_0NS 0x00 31 31 32 - #define REG_PTP_RTC_NANOSEC 0x0504 33 - 34 - #define REG_PTP_RTC_SEC 0x0508 35 - 36 - #define REG_PTP_SUBNANOSEC_RATE 0x050C 37 - 32 + /* REG_PTP_SUBNANOSEC_RATE */ 38 33 #define PTP_SUBNANOSEC_M 0x3FFFFFFF 39 34 #define PTP_RATE_DIR BIT(31) 40 35 #define PTP_TMP_RATE_ENABLE BIT(30) ··· 39 46 #define REG_PTP_RATE_DURATION_H 0x0510 40 47 #define REG_PTP_RATE_DURATION_L 0x0512 41 48 42 - #define REG_PTP_MSG_CONF1 0x0514 43 - 49 + /* REG_PTP_MSG_CONF1 */ 44 50 #define PTP_802_1AS BIT(7) 45 51 #define PTP_ENABLE BIT(6) 46 52 #define PTP_ETH_ENABLE BIT(5)

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