tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"A collection of fixes from this week, it's been pretty quiet and
nothing really stands out as particularly noteworthy here -- mostly
minor fixes across the field:

- ODROID booting was fixed due to PMIC interrupts missing in DT
- a collection of i.MX fixes
- minor Tegra fix for regulators
- Rockchip fix and addition of SoC-specific mailing list to make it
easier to find posted patches"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
bus: arm-ccn: Fix warning message
ARM: shmobile: koelsch: Remove non-existent i2c6 pinmux
ARM: tegra: apalis/colibri t30: fix on-module 5v0 supplies
MAINTAINERS: add new Rockchip SoC list
ARM: dts: rockchip: readd missing mmc0 pinctrl settings
ARM: dts: ODROID i2c improvements
ARM: dts: Enable PMIC interrupts on ODROID
ARM: dts: imx6sx: fix the pad setting for uart CTS_B
ARM: dts: i.MX53: fix apparent bug in VPU clks
ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
ARM: dts: imx6: edmqmx6: change enet reset pin
ARM: dts: vf610-twr: Fix pinctrl_esdhc1 pin definitions.
ARM: imx: remove unnecessary ARCH_HAS_OPP select
ARM: imx: fix TLB missing of IOMUXC base address during suspend
ARM: imx6: fix SMP compilation again
ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodes

Linus Torvalds 959dc258 fa7f78e0

+76 -30
+1
MAINTAINERS
··· 1277 1277 ARM/Rockchip SoC support 1278 1278 M: Heiko Stuebner <heiko@sntech.de> 1279 1279 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1280 + L: linux-rockchip@lists.infradead.org 1280 1281 S: Maintained 1281 1282 F: arch/arm/mach-rockchip/ 1282 1283 F: drivers/*/*rockchip*
+13
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
··· 134 134 i2c@13860000 { 135 135 pinctrl-0 = <&i2c0_bus>; 136 136 pinctrl-names = "default"; 137 + samsung,i2c-sda-delay = <100>; 138 + samsung,i2c-max-bus-freq = <400000>; 137 139 status = "okay"; 138 140 139 141 usb3503: usb3503@08 { ··· 150 148 151 149 max77686: pmic@09 { 152 150 compatible = "maxim,max77686"; 151 + interrupt-parent = <&gpx3>; 152 + interrupts = <2 0>; 153 + pinctrl-names = "default"; 154 + pinctrl-0 = <&max77686_irq>; 153 155 reg = <0x09>; 154 156 #clock-cells = <1>; 155 157 ··· 373 367 gpio_power_key: power_key { 374 368 samsung,pins = "gpx1-3"; 375 369 samsung,pin-pud = <0>; 370 + }; 371 + 372 + max77686_irq: max77686-irq { 373 + samsung,pins = "gpx3-2"; 374 + samsung,pin-function = <0>; 375 + samsung,pin-pud = <0>; 376 + samsung,pin-drv = <0>; 376 377 }; 377 378 };
+1 -1
arch/arm/boot/dts/imx53.dtsi
··· 731 731 compatible = "fsl,imx53-vpu"; 732 732 reg = <0x63ff4000 0x1000>; 733 733 interrupts = <9>; 734 - clocks = <&clks IMX5_CLK_VPU_GATE>, 734 + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 735 735 <&clks IMX5_CLK_VPU_GATE>; 736 736 clock-names = "per", "ahb"; 737 737 resets = <&src 1>;
+2 -1
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
··· 119 119 pinctrl-names = "default"; 120 120 pinctrl-0 = <&pinctrl_enet>; 121 121 phy-mode = "rgmii"; 122 - phy-reset-gpios = <&gpio3 23 0>; 122 + phy-reset-gpios = <&gpio1 25 0>; 123 123 phy-supply = <&vgen2_1v2_eth>; 124 124 status = "okay"; 125 125 }; ··· 339 339 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 340 340 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 341 341 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 342 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 342 343 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 343 344 >; 344 345 };
+13 -13
arch/arm/boot/dts/imx6sx-pinfunc.h
··· 78 78 #define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1 79 79 #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 80 80 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 81 - #define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1 81 + #define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 82 82 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 83 83 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 84 84 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 ··· 96 96 #define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0 97 97 #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 98 98 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 99 - #define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1 99 + #define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 100 100 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 101 101 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 102 102 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 ··· 213 213 #define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1 214 214 #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 215 215 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 216 - #define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1 216 + #define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 217 217 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 218 218 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 219 219 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 ··· 254 254 #define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0 255 255 #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 256 256 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 257 - #define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3 257 + #define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 258 258 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 259 259 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 260 260 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 ··· 352 352 #define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0 353 353 #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 354 354 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 355 - #define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 355 + #define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 356 356 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 357 357 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 358 358 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 ··· 404 404 #define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0 405 405 #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 406 406 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 407 - #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3 407 + #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 408 408 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 409 409 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 410 410 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 ··· 423 423 #define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0 424 424 #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 425 425 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 426 - #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3 426 + #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 427 427 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 428 428 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 429 429 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 ··· 815 815 #define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0 816 816 #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 817 817 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 818 - #define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1 818 + #define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 819 819 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 820 820 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 821 821 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 ··· 957 957 #define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0 958 958 #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 959 959 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 960 - #define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 960 + #define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 961 961 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 962 962 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 963 963 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 ··· 1236 1236 #define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1 1237 1237 #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 1238 1238 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 1239 - #define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2 1239 + #define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 1240 1240 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 1241 1241 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 1242 1242 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 ··· 1315 1315 #define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0 1316 1316 #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 1317 1317 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 1318 - #define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0 1318 + #define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 1319 1319 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 1320 1320 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 1321 1321 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 ··· 1409 1409 #define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0 1410 1410 #define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 1411 1411 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 1412 - #define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3 1412 + #define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 1413 1413 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 1414 1414 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 1415 1415 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 ··· 1510 1510 #define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0 1511 1511 #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 1512 1512 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 1513 - #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1 1513 + #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 1514 1514 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 1515 1515 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 1516 1516 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
-7
arch/arm/boot/dts/r8a7791-koelsch.dts
··· 275 275 renesas,function = "msiof0"; 276 276 }; 277 277 278 - i2c6_pins: i2c6 { 279 - renesas,groups = "i2c6"; 280 - renesas,function = "i2c6"; 281 - }; 282 - 283 278 usb0_pins: usb0 { 284 279 renesas,groups = "usb0"; 285 280 renesas,function = "usb0"; ··· 415 420 }; 416 421 417 422 &i2c6 { 418 - pinctrl-names = "default"; 419 - pinctrl-0 = <&i2c6_pins>; 420 423 status = "okay"; 421 424 clock-frequency = <100000>; 422 425
+2
arch/arm/boot/dts/rk3066a-bqcurie2.dts
··· 149 149 &mmc0 { /* sdmmc */ 150 150 num-slots = <1>; 151 151 status = "okay"; 152 + pinctrl-names = "default"; 153 + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 152 154 vmmc-supply = <&vcc_sd0>; 153 155 154 156 slot@0 {
+2
arch/arm/boot/dts/rk3188-radxarock.dts
··· 179 179 &mmc0 { 180 180 num-slots = <1>; 181 181 status = "okay"; 182 + pinctrl-names = "default"; 183 + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; 182 184 vmmc-supply = <&vcc_sd0>; 183 185 184 186 slot@0 {
+8
arch/arm/boot/dts/sun6i-a31.dtsi
··· 660 660 clock-frequency = <100000>; 661 661 resets = <&apb2_rst 0>; 662 662 status = "disabled"; 663 + #address-cells = <1>; 664 + #size-cells = <0>; 663 665 }; 664 666 665 667 i2c1: i2c@01c2b000 { ··· 672 670 clock-frequency = <100000>; 673 671 resets = <&apb2_rst 1>; 674 672 status = "disabled"; 673 + #address-cells = <1>; 674 + #size-cells = <0>; 675 675 }; 676 676 677 677 i2c2: i2c@01c2b400 { ··· 684 680 clock-frequency = <100000>; 685 681 resets = <&apb2_rst 2>; 686 682 status = "disabled"; 683 + #address-cells = <1>; 684 + #size-cells = <0>; 687 685 }; 688 686 689 687 i2c3: i2c@01c2b800 { ··· 696 690 clock-frequency = <100000>; 697 691 resets = <&apb2_rst 3>; 698 692 status = "disabled"; 693 + #address-cells = <1>; 694 + #size-cells = <0>; 699 695 }; 700 696 701 697 gmac: ethernet@01c30000 {
+10 -1
arch/arm/boot/dts/tegra30-apalis.dtsi
··· 423 423 vcc4-supply = <&sys_3v3_reg>; 424 424 vcc5-supply = <&sys_3v3_reg>; 425 425 vcc6-supply = <&vio_reg>; 426 - vcc7-supply = <&sys_5v0_reg>; 426 + vcc7-supply = <&charge_pump_5v0_reg>; 427 427 vccio-supply = <&sys_3v3_reg>; 428 428 429 429 regulators { ··· 672 672 regulator-name = "3v3"; 673 673 regulator-min-microvolt = <3300000>; 674 674 regulator-max-microvolt = <3300000>; 675 + regulator-always-on; 676 + }; 677 + 678 + charge_pump_5v0_reg: regulator@101 { 679 + compatible = "regulator-fixed"; 680 + reg = <101>; 681 + regulator-name = "5v0"; 682 + regulator-min-microvolt = <5000000>; 683 + regulator-max-microvolt = <5000000>; 675 684 regulator-always-on; 676 685 }; 677 686 };
+10 -1
arch/arm/boot/dts/tegra30-colibri.dtsi
··· 201 201 vcc4-supply = <&sys_3v3_reg>; 202 202 vcc5-supply = <&sys_3v3_reg>; 203 203 vcc6-supply = <&vio_reg>; 204 - vcc7-supply = <&sys_5v0_reg>; 204 + vcc7-supply = <&charge_pump_5v0_reg>; 205 205 vccio-supply = <&sys_3v3_reg>; 206 206 207 207 regulators { ··· 371 371 regulator-name = "3v3"; 372 372 regulator-min-microvolt = <3300000>; 373 373 regulator-max-microvolt = <3300000>; 374 + regulator-always-on; 375 + }; 376 + 377 + charge_pump_5v0_reg: regulator@101 { 378 + compatible = "regulator-fixed"; 379 + reg = <101>; 380 + regulator-name = "5v0"; 381 + regulator-min-microvolt = <5000000>; 382 + regulator-max-microvolt = <5000000>; 374 383 regulator-always-on; 375 384 }; 376 385 };
+1 -1
arch/arm/boot/dts/vf610-twr.dts
··· 168 168 }; 169 169 170 170 pinctrl_esdhc1: esdhc1grp { 171 - fsl,fsl,pins = < 171 + fsl,pins = < 172 172 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 173 173 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 174 174 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
-2
arch/arm/mach-imx/Kconfig
··· 85 85 86 86 config SOC_IMX27 87 87 bool 88 - select ARCH_HAS_OPP 89 88 select CPU_ARM926T 90 89 select IMX_HAVE_IOMUX_V1 91 90 select MXC_AVIC ··· 658 659 659 660 config SOC_IMX5 660 661 bool 661 - select ARCH_HAS_OPP 662 662 select HAVE_IMX_SRC 663 663 select MXC_TZIC 664 664
+2
arch/arm/mach-imx/Makefile
··· 93 93 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 94 94 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o 95 95 obj-$(CONFIG_HAVE_IMX_SRC) += src.o 96 + ifdef CONFIG_SOC_IMX6 96 97 AFLAGS_headsmp.o :=-Wa,-march=armv7-a 97 98 obj-$(CONFIG_SMP) += headsmp.o platsmp.o 98 99 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 100 + endif 99 101 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 100 102 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o 101 103 obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
+8 -2
arch/arm/mach-imx/clk-imx6q.c
··· 194 194 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 195 195 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 196 196 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); 197 + if (cpu_is_imx6dl()) { 198 + clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); 199 + clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); 200 + } 197 201 198 202 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 199 203 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); ··· 221 217 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 222 218 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 223 219 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 224 - clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 225 - clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 220 + if (cpu_is_imx6q()) { 221 + clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 222 + clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 223 + } 226 224 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 227 225 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 228 226 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
+2
arch/arm/mach-imx/suspend-imx6.S
··· 173 173 ldr r6, [r11, #0x0] 174 174 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] 175 175 ldr r6, [r11, #0x0] 176 + ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] 177 + ldr r6, [r11, #0x0] 176 178 177 179 /* use r11 to store the IO address */ 178 180 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
+1 -1
drivers/bus/arm-ccn.c
··· 662 662 } 663 663 if (e->num_vcs && vc >= e->num_vcs) { 664 664 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n", 665 - port, node_xp); 665 + vc, node_xp); 666 666 return -EINVAL; 667 667 } 668 668 valid = 1;