Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon: fix page flipping hangs on r300/r400
drm/radeon: add pageflip hooks for fusion
+5
-18
-17
drivers/gpu/drm/radeon/r100.c
-17
drivers/gpu/drm/radeon/r100.c
···
70
70
71
71
void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72
72
{
73
-
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
74
-
u32 tmp;
75
-
76
-
/* make sure flip is at vb rather than hb */
77
-
tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
78
-
tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
79
-
/* make sure pending bit is asserted */
80
-
tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
81
-
WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
82
-
83
-
/* set pageflip to happen as late as possible in the vblank interval.
84
-
* same field for crtc1/2
85
-
*/
86
-
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
87
-
tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
88
-
WREG32(RADEON_CRTC_GEN_CNTL, tmp);
89
-
90
73
/* enable the pflip int */
91
74
radeon_irq_kms_pflip_irq_get(rdev, crtc);
92
75
}
+3
drivers/gpu/drm/radeon/radeon_asic.c
+3
drivers/gpu/drm/radeon/radeon_asic.c
···
834
834
.pm_finish = &evergreen_pm_finish,
835
835
.pm_init_profile = &rs780_pm_init_profile,
836
836
.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
837
+
.pre_page_flip = &evergreen_pre_page_flip,
838
+
.page_flip = &evergreen_page_flip,
839
+
.post_page_flip = &evergreen_post_page_flip,
837
840
};
838
841
839
842
static struct radeon_asic btc_asic = {
+2
-1
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+2
-1
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
···
443
443
(target_fb->bits_per_pixel * 8));
444
444
crtc_pitch |= crtc_pitch << 16;
445
445
446
-
446
+
crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
447
447
if (tiling_flags & RADEON_TILING_MACRO) {
448
448
if (ASIC_IS_R300(rdev))
449
449
crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
···
502
502
gen_cntl_val = RREG32(gen_cntl_reg);
503
503
gen_cntl_val &= ~(0xf << 8);
504
504
gen_cntl_val |= (format << 8);
505
+
gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
505
506
WREG32(gen_cntl_reg, gen_cntl_val);
506
507
507
508
crtc_offset = (u32)base;