Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 perf event updates from Ingo Molnar:
- Fix address filtering for Intel/PT,ARM/CoreSight
- Enable Intel/PEBS format 5
- Allow more fixed-function counters for x86
- Intel/PT: Enable not recording Taken-Not-Taken packets
- Add a few branch-types
* tag 'perf-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel/uncore: Fix the build on !CONFIG_PHYS_ADDR_T_64BIT
perf: Add irq and exception return branch types
perf/x86/intel/uncore: Make uncore_discovery clean for 64 bit addresses
perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
perf/x86/intel/pt: Add a capability and config bit for event tracing
perf/x86/intel: Increase max number of the fixed counters
KVM: x86: use the KVM side max supported fixed counter
perf/x86/intel: Enable PEBS format 5
perf/core: Allow kernel address filter when not filtering the kernel
perf/x86/intel/pt: Fix address filter config for 32-bit kernel
perf/core: Fix address filter parser for multiple filters
x86: Share definition of __is_canonical_address()
perf/x86/intel/pt: Relax address filter validation
+161
-54
+39
-1
arch/x86/events/intel/core.c
+39
-1
arch/x86/events/intel/core.c
···
181
181
EVENT_CONSTRAINT_END
182
182
};
183
183
184
+
static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
185
+
{
186
+
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187
+
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188
+
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
189
+
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
190
+
FIXED_EVENT_CONSTRAINT(0x0500, 4),
191
+
FIXED_EVENT_CONSTRAINT(0x0600, 5),
192
+
FIXED_EVENT_CONSTRAINT(0x0700, 6),
193
+
FIXED_EVENT_CONSTRAINT(0x0800, 7),
194
+
FIXED_EVENT_CONSTRAINT(0x0900, 8),
195
+
FIXED_EVENT_CONSTRAINT(0x0a00, 9),
196
+
FIXED_EVENT_CONSTRAINT(0x0b00, 10),
197
+
FIXED_EVENT_CONSTRAINT(0x0c00, 11),
198
+
FIXED_EVENT_CONSTRAINT(0x0d00, 12),
199
+
FIXED_EVENT_CONSTRAINT(0x0e00, 13),
200
+
FIXED_EVENT_CONSTRAINT(0x0f00, 14),
201
+
FIXED_EVENT_CONSTRAINT(0x1000, 15),
202
+
EVENT_CONSTRAINT_END
203
+
};
204
+
184
205
static struct event_constraint intel_slm_event_constraints[] __read_mostly =
185
206
{
186
207
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
···
6329
6308
pr_cont("generic architected perfmon v1, ");
6330
6309
name = "generic_arch_v1";
6331
6310
break;
6332
-
default:
6311
+
case 2:
6312
+
case 3:
6313
+
case 4:
6333
6314
/*
6334
6315
* default constraints for v2 and up
6335
6316
*/
6336
6317
x86_pmu.event_constraints = intel_gen_event_constraints;
6337
6318
pr_cont("generic architected perfmon, ");
6338
6319
name = "generic_arch_v2+";
6320
+
break;
6321
+
default:
6322
+
/*
6323
+
* The default constraints for v5 and up can support up to
6324
+
* 16 fixed counters. For the fixed counters 4 and later,
6325
+
* the pseudo-encoding is applied.
6326
+
* The constraints may be cut according to the CPUID enumeration
6327
+
* by inserting the EVENT_CONSTRAINT_END.
6328
+
*/
6329
+
if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED)
6330
+
x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
6331
+
intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1;
6332
+
x86_pmu.event_constraints = intel_v5_gen_event_constraints;
6333
+
pr_cont("generic architected perfmon, ");
6334
+
name = "generic_arch_v5+";
6339
6335
break;
6340
6336
}
6341
6337
}
+11
-3
arch/x86/events/intel/ds.c
+11
-3
arch/x86/events/intel/ds.c
···
1203
1203
if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1204
1204
base = MSR_RELOAD_FIXED_CTR0;
1205
1205
idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1206
-
value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
1206
+
if (x86_pmu.intel_cap.pebs_format < 5)
1207
+
value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
1208
+
else
1209
+
value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
1207
1210
}
1208
1211
wrmsrl(base + idx, value);
1209
1212
}
···
1235
1232
}
1236
1233
}
1237
1234
1238
-
if (idx >= INTEL_PMC_IDX_FIXED)
1239
-
idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1235
+
if (idx >= INTEL_PMC_IDX_FIXED) {
1236
+
if (x86_pmu.intel_cap.pebs_format < 5)
1237
+
idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
1238
+
else
1239
+
idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1240
+
}
1240
1241
1241
1242
/*
1242
1243
* Use auto-reload if possible to save a MSR write in the PMI.
···
2211
2204
break;
2212
2205
2213
2206
case 4:
2207
+
case 5:
2214
2208
x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2215
2209
x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2216
2210
if (x86_pmu.intel_cap.pebs_baseline) {
+2
-2
arch/x86/events/intel/lbr.c
+2
-2
arch/x86/events/intel/lbr.c
···
1329
1329
PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
1330
1330
PERF_BR_SYSRET, /* X86_BR_SYSRET */
1331
1331
PERF_BR_UNKNOWN, /* X86_BR_INT */
1332
-
PERF_BR_UNKNOWN, /* X86_BR_IRET */
1332
+
PERF_BR_ERET, /* X86_BR_IRET */
1333
1333
PERF_BR_COND, /* X86_BR_JCC */
1334
1334
PERF_BR_UNCOND, /* X86_BR_JMP */
1335
-
PERF_BR_UNKNOWN, /* X86_BR_IRQ */
1335
+
PERF_BR_IRQ, /* X86_BR_IRQ */
1336
1336
PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
1337
1337
PERF_BR_UNKNOWN, /* X86_BR_ABORT */
1338
1338
PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
+57
-14
arch/x86/events/intel/pt.c
+57
-14
arch/x86/events/intel/pt.c
···
13
13
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
14
15
15
#include <linux/types.h>
16
+
#include <linux/bits.h>
17
+
#include <linux/limits.h>
16
18
#include <linux/slab.h>
17
19
#include <linux/device.h>
18
20
···
59
57
PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
60
58
PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
61
59
PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
60
+
PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
61
+
PT_CAP(tnt_disable, 0, CPUID_EBX, BIT(8)),
62
62
PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
63
63
PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
64
64
PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
···
112
108
PMU_FORMAT_ATTR(noretcomp, "config:11" );
113
109
PMU_FORMAT_ATTR(ptw, "config:12" );
114
110
PMU_FORMAT_ATTR(branch, "config:13" );
111
+
PMU_FORMAT_ATTR(event, "config:31" );
112
+
PMU_FORMAT_ATTR(notnt, "config:55" );
115
113
PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
116
114
PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
117
115
PMU_FORMAT_ATTR(psb_period, "config:24-27" );
···
122
116
&format_attr_pt.attr,
123
117
&format_attr_cyc.attr,
124
118
&format_attr_pwr_evt.attr,
119
+
&format_attr_event.attr,
120
+
&format_attr_notnt.attr,
125
121
&format_attr_fup_on_ptw.attr,
126
122
&format_attr_mtc.attr,
127
123
&format_attr_tsc.attr,
···
304
296
RTIT_CTL_CYC_PSB | \
305
297
RTIT_CTL_MTC | \
306
298
RTIT_CTL_PWR_EVT_EN | \
299
+
RTIT_CTL_EVENT_EN | \
300
+
RTIT_CTL_NOTNT | \
307
301
RTIT_CTL_FUP_ON_PTW | \
308
302
RTIT_CTL_PTW_EN)
309
303
···
358
348
359
349
if (config & RTIT_CTL_PWR_EVT_EN &&
360
350
!intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
351
+
return false;
352
+
353
+
if (config & RTIT_CTL_EVENT_EN &&
354
+
!intel_pt_validate_hw_cap(PT_CAP_event_trace))
355
+
return false;
356
+
357
+
if (config & RTIT_CTL_NOTNT &&
358
+
!intel_pt_validate_hw_cap(PT_CAP_tnt_disable))
361
359
return false;
362
360
363
361
if (config & RTIT_CTL_PTW) {
···
490
472
pt->filters.filter[range].msr_b = filter->msr_b;
491
473
}
492
474
493
-
rtit_ctl |= filter->config << pt_address_ranges[range].reg_off;
475
+
rtit_ctl |= (u64)filter->config << pt_address_ranges[range].reg_off;
494
476
}
495
477
496
478
return rtit_ctl;
···
1366
1348
event->hw.addr_filters = NULL;
1367
1349
}
1368
1350
1369
-
static inline bool valid_kernel_ip(unsigned long ip)
1351
+
#ifdef CONFIG_X86_64
1352
+
/* Clamp to a canonical address greater-than-or-equal-to the address given */
1353
+
static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits)
1370
1354
{
1371
-
return virt_addr_valid(ip) && kernel_ip(ip);
1355
+
return __is_canonical_address(vaddr, vaddr_bits) ?
1356
+
vaddr :
1357
+
-BIT_ULL(vaddr_bits - 1);
1372
1358
}
1359
+
1360
+
/* Clamp to a canonical address less-than-or-equal-to the address given */
1361
+
static u64 clamp_to_le_canonical_addr(u64 vaddr, u8 vaddr_bits)
1362
+
{
1363
+
return __is_canonical_address(vaddr, vaddr_bits) ?
1364
+
vaddr :
1365
+
BIT_ULL(vaddr_bits - 1) - 1;
1366
+
}
1367
+
#else
1368
+
#define clamp_to_ge_canonical_addr(x, y) (x)
1369
+
#define clamp_to_le_canonical_addr(x, y) (x)
1370
+
#endif
1373
1371
1374
1372
static int pt_event_addr_filters_validate(struct list_head *filters)
1375
1373
{
···
1400
1366
if (!filter->size ||
1401
1367
filter->action == PERF_ADDR_FILTER_ACTION_START)
1402
1368
return -EOPNOTSUPP;
1403
-
1404
-
if (!filter->path.dentry) {
1405
-
if (!valid_kernel_ip(filter->offset))
1406
-
return -EINVAL;
1407
-
1408
-
if (!valid_kernel_ip(filter->offset + filter->size))
1409
-
return -EINVAL;
1410
-
}
1411
1369
1412
1370
if (++range > intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1413
1371
return -EOPNOTSUPP;
···
1424
1398
if (filter->path.dentry && !fr[range].start) {
1425
1399
msr_a = msr_b = 0;
1426
1400
} else {
1427
-
/* apply the offset */
1428
-
msr_a = fr[range].start;
1429
-
msr_b = msr_a + fr[range].size - 1;
1401
+
unsigned long n = fr[range].size - 1;
1402
+
unsigned long a = fr[range].start;
1403
+
unsigned long b;
1404
+
1405
+
if (a > ULONG_MAX - n)
1406
+
b = ULONG_MAX;
1407
+
else
1408
+
b = a + n;
1409
+
/*
1410
+
* Apply the offset. 64-bit addresses written to the
1411
+
* MSRs must be canonical, but the range can encompass
1412
+
* non-canonical addresses. Since software cannot
1413
+
* execute at non-canonical addresses, adjusting to
1414
+
* canonical addresses does not affect the result of the
1415
+
* address filter.
1416
+
*/
1417
+
msr_a = clamp_to_ge_canonical_addr(a, boot_cpu_data.x86_virt_bits);
1418
+
msr_b = clamp_to_le_canonical_addr(b, boot_cpu_data.x86_virt_bits);
1419
+
if (msr_b < msr_a)
1420
+
msr_a = msr_b = 0;
1430
1421
}
1431
1422
1432
1423
filters->filter[range].msr_a = msr_a;
+12
-4
arch/x86/events/intel/uncore_discovery.c
+12
-4
arch/x86/events/intel/uncore_discovery.c
···
215
215
216
216
pci_read_config_dword(dev, bar_offset, &val);
217
217
218
-
if (val & UNCORE_DISCOVERY_MASK)
218
+
if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64)
219
219
return -EINVAL;
220
220
221
-
addr = (resource_size_t)(val & ~UNCORE_DISCOVERY_MASK);
221
+
addr = (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK);
222
+
#ifdef CONFIG_PHYS_ADDR_T_64BIT
223
+
if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
224
+
u32 val2;
225
+
226
+
pci_read_config_dword(dev, bar_offset + 4, &val2);
227
+
addr |= ((resource_size_t)val2) << 32;
228
+
}
229
+
#endif
222
230
size = UNCORE_DISCOVERY_GLOBAL_MAP_SIZE;
223
231
io_addr = ioremap(addr, size);
224
232
if (!io_addr)
···
452
444
453
445
#define UNCORE_GENERIC_MMIO_SIZE 0x4000
454
446
455
-
static unsigned int generic_uncore_mmio_box_ctl(struct intel_uncore_box *box)
447
+
static u64 generic_uncore_mmio_box_ctl(struct intel_uncore_box *box)
456
448
{
457
449
struct intel_uncore_type *type = box->pmu->type;
458
450
···
464
456
465
457
void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box)
466
458
{
467
-
unsigned int box_ctl = generic_uncore_mmio_box_ctl(box);
459
+
u64 box_ctl = generic_uncore_mmio_box_ctl(box);
468
460
struct intel_uncore_type *type = box->pmu->type;
469
461
resource_size_t addr;
470
462
-2
arch/x86/events/intel/uncore_discovery.h
-2
arch/x86/events/intel/uncore_discovery.h
···
18
18
#define UNCORE_DISCOVERY_BIR_BASE 0x10
19
19
/* Discovery table BAR step */
20
20
#define UNCORE_DISCOVERY_BIR_STEP 0x4
21
-
/* Mask of the discovery table offset */
22
-
#define UNCORE_DISCOVERY_MASK 0xf
23
21
/* Global discovery table size */
24
22
#define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20
25
23
+3
-2
arch/x86/include/asm/intel_ds.h
+3
-2
arch/x86/include/asm/intel_ds.h
···
7
7
#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
8
8
9
9
/* The maximal number of PEBS events: */
10
-
#define MAX_PEBS_EVENTS 8
11
-
#define MAX_FIXED_PEBS_EVENTS 4
10
+
#define MAX_PEBS_EVENTS_FMT4 8
11
+
#define MAX_PEBS_EVENTS 32
12
+
#define MAX_FIXED_PEBS_EVENTS 16
12
13
13
14
/*
14
15
* A debug store configuration.
+2
arch/x86/include/asm/intel_pt.h
+2
arch/x86/include/asm/intel_pt.h
+2
-1
arch/x86/include/asm/kvm_host.h
+2
-1
arch/x86/include/asm/kvm_host.h
···
498
498
bool intr;
499
499
};
500
500
501
+
#define KVM_PMC_MAX_FIXED 3
501
502
struct kvm_pmu {
502
503
unsigned nr_arch_gp_counters;
503
504
unsigned nr_arch_fixed_counters;
···
512
511
u64 reserved_bits;
513
512
u8 version;
514
513
struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
515
-
struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
514
+
struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
516
515
struct irq_work irq_work;
517
516
DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
518
517
DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
+2
arch/x86/include/asm/msr-index.h
+2
arch/x86/include/asm/msr-index.h
···
205
205
#define RTIT_CTL_DISRETC BIT(11)
206
206
#define RTIT_CTL_PTW_EN BIT(12)
207
207
#define RTIT_CTL_BRANCH_EN BIT(13)
208
+
#define RTIT_CTL_EVENT_EN BIT(31)
209
+
#define RTIT_CTL_NOTNT BIT_ULL(55)
208
210
#define RTIT_CTL_MTC_RANGE_OFFSET 14
209
211
#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
210
212
#define RTIT_CTL_CYC_THRESH_OFFSET 19
+10
arch/x86/include/asm/page.h
+10
arch/x86/include/asm/page.h
···
71
71
extern bool __virt_addr_valid(unsigned long kaddr);
72
72
#define virt_addr_valid(kaddr) __virt_addr_valid((unsigned long) (kaddr))
73
73
74
+
static __always_inline u64 __canonical_address(u64 vaddr, u8 vaddr_bits)
75
+
{
76
+
return ((s64)vaddr << (64 - vaddr_bits)) >> (64 - vaddr_bits);
77
+
}
78
+
79
+
static __always_inline u64 __is_canonical_address(u64 vaddr, u8 vaddr_bits)
80
+
{
81
+
return __canonical_address(vaddr, vaddr_bits) == vaddr;
82
+
}
83
+
74
84
#endif /* __ASSEMBLY__ */
75
85
76
86
#include <asm-generic/memory_model.h>
+1
-1
arch/x86/include/asm/perf_event.h
+1
-1
arch/x86/include/asm/perf_event.h
+2
-1
arch/x86/kvm/cpuid.c
+2
-1
arch/x86/kvm/cpuid.c
···
879
879
eax.split.bit_width = cap.bit_width_gp;
880
880
eax.split.mask_length = cap.events_mask_len;
881
881
882
-
edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS);
882
+
edx.split.num_counters_fixed =
883
+
min(cap.num_counters_fixed, KVM_PMC_MAX_FIXED);
883
884
edx.split.bit_width_fixed = cap.bit_width_fixed;
884
885
if (cap.version)
885
886
edx.split.anythread_deprecated = 1;
+2
-2
arch/x86/kvm/emulate.c
+2
-2
arch/x86/kvm/emulate.c
···
680
680
static inline bool emul_is_noncanonical_address(u64 la,
681
681
struct x86_emulate_ctxt *ctxt)
682
682
{
683
-
return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
683
+
return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt));
684
684
}
685
685
686
686
/*
···
730
730
case X86EMUL_MODE_PROT64:
731
731
*linear = la;
732
732
va_bits = ctxt_virt_addr_bits(ctxt);
733
-
if (get_canonical(la, va_bits) != la)
733
+
if (!__is_canonical_address(la, va_bits))
734
734
goto bad;
735
735
736
736
*max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
-2
arch/x86/kvm/pmu.h
-2
arch/x86/kvm/pmu.h
+2
-2
arch/x86/kvm/vmx/pmu_intel.c
+2
-2
arch/x86/kvm/vmx/pmu_intel.c
···
565
565
pmu->gp_counters[i].current_config = 0;
566
566
}
567
567
568
-
for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
568
+
for (i = 0; i < KVM_PMC_MAX_FIXED; i++) {
569
569
pmu->fixed_counters[i].type = KVM_PMC_FIXED;
570
570
pmu->fixed_counters[i].vcpu = vcpu;
571
571
pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
···
591
591
pmc->counter = pmc->eventsel = 0;
592
592
}
593
593
594
-
for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
594
+
for (i = 0; i < KVM_PMC_MAX_FIXED; i++) {
595
595
pmc = &pmu->fixed_counters[i];
596
596
597
597
pmc_stop_counter(pmc);
+2
-2
arch/x86/kvm/x86.c
+2
-2
arch/x86/kvm/x86.c
···
1749
1749
* value, and that something deterministic happens if the guest
1750
1750
* invokes 64-bit SYSENTER.
1751
1751
*/
1752
-
data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1752
+
data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1753
1753
break;
1754
1754
case MSR_TSC_AUX:
1755
1755
if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
···
6529
6529
u32 dummy[2];
6530
6530
unsigned i;
6531
6531
6532
-
BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
6532
+
BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
6533
6533
"Please update the fixed PMCs in msrs_to_saved_all[]");
6534
6534
6535
6535
perf_get_x86_pmu_capability(&x86_pmu);
+1
-6
arch/x86/kvm/x86.h
+1
-6
arch/x86/kvm/x86.h
···
166
166
return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
167
167
}
168
168
169
-
static inline u64 get_canonical(u64 la, u8 vaddr_bits)
170
-
{
171
-
return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
172
-
}
173
-
174
169
static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
175
170
{
176
-
return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
171
+
return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu));
177
172
}
178
173
179
174
static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
+1
-6
arch/x86/mm/maccess.c
+1
-6
arch/x86/mm/maccess.c
···
4
4
#include <linux/kernel.h>
5
5
6
6
#ifdef CONFIG_X86_64
7
-
static __always_inline u64 canonical_address(u64 vaddr, u8 vaddr_bits)
8
-
{
9
-
return ((s64)vaddr << (64 - vaddr_bits)) >> (64 - vaddr_bits);
10
-
}
11
-
12
7
bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
13
8
{
14
9
unsigned long vaddr = (unsigned long)unsafe_src;
···
14
19
* we also need to include the userspace guard page.
15
20
*/
16
21
return vaddr >= TASK_SIZE_MAX + PAGE_SIZE &&
17
-
canonical_address(vaddr, boot_cpu_data.x86_virt_bits) == vaddr;
22
+
__is_canonical_address(vaddr, boot_cpu_data.x86_virt_bits);
18
23
}
19
24
#else
20
25
bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
+2
include/uapi/linux/perf_event.h
+2
include/uapi/linux/perf_event.h
···
251
251
PERF_BR_SYSRET = 8, /* syscall return */
252
252
PERF_BR_COND_CALL = 9, /* conditional function call */
253
253
PERF_BR_COND_RET = 10, /* conditional function return */
254
+
PERF_BR_ERET = 11, /* exception return */
255
+
PERF_BR_IRQ = 12, /* irq */
254
256
PERF_BR_MAX,
255
257
};
256
258
+3
-2
kernel/events/core.c
+3
-2
kernel/events/core.c
···
10531
10531
*/
10532
10532
if (state == IF_STATE_END) {
10533
10533
ret = -EINVAL;
10534
-
if (kernel && event->attr.exclude_kernel)
10535
-
goto fail;
10536
10534
10537
10535
/*
10538
10536
* ACTION "filter" must have a non-zero length region
···
10572
10574
}
10573
10575
10574
10576
/* ready to consume more filters */
10577
+
kfree(filename);
10578
+
filename = NULL;
10575
10579
state = IF_STATE_ACTION;
10576
10580
filter = NULL;
10581
+
kernel = 0;
10577
10582
}
10578
10583
}
10579
10584
+2
tools/include/uapi/linux/perf_event.h
+2
tools/include/uapi/linux/perf_event.h
···
251
251
PERF_BR_SYSRET = 8, /* syscall return */
252
252
PERF_BR_COND_CALL = 9, /* conditional function call */
253
253
PERF_BR_COND_RET = 10, /* conditional function return */
254
+
PERF_BR_ERET = 11, /* exception return */
255
+
PERF_BR_IRQ = 12, /* irq */
254
256
PERF_BR_MAX,
255
257
};
256
258