Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-04-18' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Since Easter is looming for me, I'm just pushing whatever is in my
tree, I'll see what else turns up and maybe I'll send another pull
early next week if there is anything.
tegra:
- stream id programming fix
- avoid divide by 0 for bad hdmi audio setup code
ttm:
- Hugepages fix
- refcount imbalance in error path fix
amdgpu:
- GPU VM fixes for Vega/RV
- DC AUX fix for active DP-DVI dongles
- DC fix for multihead regression"
* tag 'drm-fixes-2019-04-18' of git://anongit.freedesktop.org/drm/drm:
drm/tegra: hdmi: Setup audio only if configured
drm/amd/display: If one stream full updates, full update all planes
drm/amdgpu/gmc9: fix VM_L2_CNTL3 programming
drm/amdgpu: shadow in shadow_list without tbo.mem.start cause page fault in sriov TDR
gpu: host1x: Program stream ID to bypass without SMMU
drm/amd/display: extending AUX SW Timeout
drm/ttm: fix dma_fence refcount imbalance on error path
drm/ttm: fix incrementing the page pointer for huge pages
drm/ttm: fix start page for huge page check in ttm_put_pages()
drm/ttm: fix out-of-bounds read in ttm_put_pages() v2
+58
-18
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+19
drivers/gpu/drm/amd/display/dc/core/dc.c
+19
drivers/gpu/drm/amd/display/dc/core/dc.c
···
1377
1377
return UPDATE_TYPE_FULL;
1378
1378
}
1379
1379
1380
+
if (u->surface->force_full_update) {
1381
+
update_flags->bits.full_update = 1;
1382
+
return UPDATE_TYPE_FULL;
1383
+
}
1384
+
1380
1385
type = get_plane_info_update_type(u);
1381
1386
elevate_update_type(&overall_type, type);
1382
1387
···
1807
1802
}
1808
1803
1809
1804
dc_resource_state_copy_construct(state, context);
1805
+
1806
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
1807
+
struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
1808
+
struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1809
+
1810
+
if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
1811
+
new_pipe->plane_state->force_full_update = true;
1812
+
}
1810
1813
}
1811
1814
1812
1815
···
1851
1838
dc->current_state = context;
1852
1839
dc_release_state(old);
1853
1840
1841
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
1842
+
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1843
+
1844
+
if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
1845
+
pipe_ctx->plane_state->force_full_update = false;
1846
+
}
1854
1847
}
1855
1848
/*let's use current_state to update watermark etc*/
1856
1849
if (update_type >= UPDATE_TYPE_FULL)
+3
drivers/gpu/drm/amd/display/dc/dc.h
+3
drivers/gpu/drm/amd/display/dc/dc.h
···
503
503
struct dc_plane_status status;
504
504
struct dc_context *ctx;
505
505
506
+
/* HACK: Workaround for forcing full reprogramming under some conditions */
507
+
bool force_full_update;
508
+
506
509
/* private to dc_surface.c */
507
510
enum dc_irq_source irq_source;
508
511
struct kref refcount;
+6
-3
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+6
-3
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
···
190
190
1,
191
191
0);
192
192
}
193
+
194
+
REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
195
+
196
+
REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
197
+
10, aux110->timeout_period/10);
198
+
193
199
/* set the delay and the number of bytes to write */
194
200
195
201
/* The length include
···
248
242
}
249
243
}
250
244
251
-
REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
252
-
REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
253
-
10, aux110->timeout_period/10);
254
245
REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
255
246
}
256
247
+3
-3
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+3
-3
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
···
71
71
* at most within ~240usec. That means,
72
72
* increasing this timeout will not affect normal operation,
73
73
* and we'll timeout after
74
-
* SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
74
+
* SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec.
75
75
* This timeout is especially important for
76
-
* resume from S3 and CTS.
76
+
* converters, resume from S3, and CTS.
77
77
*/
78
-
SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
78
+
SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6
79
79
};
80
80
81
81
struct dce_aux {
+9
-3
drivers/gpu/drm/tegra/hdmi.c
+9
-3
drivers/gpu/drm/tegra/hdmi.c
···
1260
1260
1261
1261
hdmi->dvi = !tegra_output_is_hdmi(output);
1262
1262
if (!hdmi->dvi) {
1263
-
err = tegra_hdmi_setup_audio(hdmi);
1264
-
if (err < 0)
1265
-
hdmi->dvi = true;
1263
+
/*
1264
+
* Make sure that the audio format has been configured before
1265
+
* enabling audio, otherwise we may try to divide by zero.
1266
+
*/
1267
+
if (hdmi->format.sample_rate > 0) {
1268
+
err = tegra_hdmi_setup_audio(hdmi);
1269
+
if (err < 0)
1270
+
hdmi->dvi = true;
1271
+
}
1266
1272
}
1267
1273
1268
1274
if (hdmi->config->has_hda)
+3
-1
drivers/gpu/drm/ttm/ttm_bo.c
+3
-1
drivers/gpu/drm/ttm/ttm_bo.c
···
876
876
reservation_object_add_shared_fence(bo->resv, fence);
877
877
878
878
ret = reservation_object_reserve_shared(bo->resv, 1);
879
-
if (unlikely(ret))
879
+
if (unlikely(ret)) {
880
+
dma_fence_put(fence);
880
881
return ret;
882
+
}
881
883
882
884
dma_fence_put(bo->moving);
883
885
bo->moving = fence;
+7
-6
drivers/gpu/drm/ttm/ttm_page_alloc.c
+7
-6
drivers/gpu/drm/ttm/ttm_page_alloc.c
···
730
730
}
731
731
732
732
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
733
-
if (!(flags & TTM_PAGE_FLAG_DMA32)) {
734
-
for (j = 0; j < HPAGE_PMD_NR; ++j)
735
-
if (p++ != pages[i + j])
733
+
if (!(flags & TTM_PAGE_FLAG_DMA32) &&
734
+
(npages - i) >= HPAGE_PMD_NR) {
735
+
for (j = 1; j < HPAGE_PMD_NR; ++j)
736
+
if (++p != pages[i + j])
736
737
break;
737
738
738
739
if (j == HPAGE_PMD_NR)
···
760
759
unsigned max_size, n2free;
761
760
762
761
spin_lock_irqsave(&huge->lock, irq_flags);
763
-
while (i < npages) {
762
+
while ((npages - i) >= HPAGE_PMD_NR) {
764
763
struct page *p = pages[i];
765
764
unsigned j;
766
765
767
766
if (!p)
768
767
break;
769
768
770
-
for (j = 0; j < HPAGE_PMD_NR; ++j)
771
-
if (p++ != pages[i + j])
769
+
for (j = 1; j < HPAGE_PMD_NR; ++j)
770
+
if (++p != pages[i + j])
772
771
break;
773
772
774
773
if (j != HPAGE_PMD_NR)
+6
-2
drivers/gpu/host1x/hw/channel_hw.c
+6
-2
drivers/gpu/host1x/hw/channel_hw.c
···
114
114
115
115
static void host1x_channel_set_streamid(struct host1x_channel *channel)
116
116
{
117
-
#if IS_ENABLED(CONFIG_IOMMU_API) && HOST1X_HW >= 6
117
+
#if HOST1X_HW >= 6
118
+
u32 sid = 0x7f;
119
+
#ifdef CONFIG_IOMMU_API
118
120
struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
119
-
u32 sid = spec ? spec->ids[0] & 0xffff : 0x7f;
121
+
if (spec)
122
+
sid = spec->ids[0] & 0xffff;
123
+
#endif
120
124
121
125
host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
122
126
#endif