Merge branch 'parisc-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

+1 -1

arch/parisc/Kconfig

··· 285 285 On a uniprocessor machine, the kernel will run faster if you say N. 286 286 287 287 See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO 288 - available at <http://www.tldp.org/docs.html#howto>. 288 + available at <https://www.tldp.org/docs.html#howto>. 289 289 290 290 If you don't know what to do here, say N. 291 291

+13 -28

arch/parisc/include/asm/bitops.h

··· 12 12 #include <asm/barrier.h> 13 13 #include <linux/atomic.h> 14 14 15 - /* 16 - * HP-PARISC specific bit operations 17 - * for a detailed description of the functions please refer 18 - * to include/asm-i386/bitops.h or kerneldoc 19 - */ 20 - 21 - #if __BITS_PER_LONG == 64 22 - #define SHIFT_PER_LONG 6 23 - #else 24 - #define SHIFT_PER_LONG 5 25 - #endif 26 - 27 - #define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1)) 28 - 29 - 30 15 /* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion 31 16 * on use of volatile and __*_bit() (set/clear/change): 32 17 * *_bit() want use of volatile. ··· 20 35 21 36 static __inline__ void set_bit(int nr, volatile unsigned long * addr) 22 37 { 23 - unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); 38 + unsigned long mask = BIT_MASK(nr); 24 39 unsigned long flags; 25 40 26 - addr += (nr >> SHIFT_PER_LONG); 41 + addr += BIT_WORD(nr); 27 42 _atomic_spin_lock_irqsave(addr, flags); 28 43 *addr |= mask; 29 44 _atomic_spin_unlock_irqrestore(addr, flags); ··· 31 46 32 47 static __inline__ void clear_bit(int nr, volatile unsigned long * addr) 33 48 { 34 - unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr)); 49 + unsigned long mask = BIT_MASK(nr); 35 50 unsigned long flags; 36 51 37 - addr += (nr >> SHIFT_PER_LONG); 52 + addr += BIT_WORD(nr); 38 53 _atomic_spin_lock_irqsave(addr, flags); 39 - *addr &= mask; 54 + *addr &= ~mask; 40 55 _atomic_spin_unlock_irqrestore(addr, flags); 41 56 } 42 57 43 58 static __inline__ void change_bit(int nr, volatile unsigned long * addr) 44 59 { 45 - unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); 60 + unsigned long mask = BIT_MASK(nr); 46 61 unsigned long flags; 47 62 48 - addr += (nr >> SHIFT_PER_LONG); 63 + addr += BIT_WORD(nr); 49 64 _atomic_spin_lock_irqsave(addr, flags); 50 65 *addr ^= mask; 51 66 _atomic_spin_unlock_irqrestore(addr, flags); ··· 53 68 54 69 static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) 55 70 { 56 - unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); 71 + unsigned long mask = BIT_MASK(nr); 57 72 unsigned long old; 58 73 unsigned long flags; 59 74 int set; 60 75 61 - addr += (nr >> SHIFT_PER_LONG); 76 + addr += BIT_WORD(nr); 62 77 _atomic_spin_lock_irqsave(addr, flags); 63 78 old = *addr; 64 79 set = (old & mask) ? 1 : 0; ··· 71 86 72 87 static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) 73 88 { 74 - unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); 89 + unsigned long mask = BIT_MASK(nr); 75 90 unsigned long old; 76 91 unsigned long flags; 77 92 int set; 78 93 79 - addr += (nr >> SHIFT_PER_LONG); 94 + addr += BIT_WORD(nr); 80 95 _atomic_spin_lock_irqsave(addr, flags); 81 96 old = *addr; 82 97 set = (old & mask) ? 1 : 0; ··· 89 104 90 105 static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) 91 106 { 92 - unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); 107 + unsigned long mask = BIT_MASK(nr); 93 108 unsigned long oldbit; 94 109 unsigned long flags; 95 110 96 - addr += (nr >> SHIFT_PER_LONG); 111 + addr += BIT_WORD(nr); 97 112 _atomic_spin_lock_irqsave(addr, flags); 98 113 oldbit = *addr; 99 114 *addr = oldbit ^ mask;

+1 -1

arch/parisc/include/asm/elf.h

··· 152 152 /* The following are PA function descriptors 153 153 * 154 154 * addr: the absolute address of the function 155 - * gp: either the data pointer (r27) for non-PIC code or the 155 + * gp: either the data pointer (r27) for non-PIC code or 156 156 * the PLT pointer (r19) for PIC code */ 157 157 158 158 /* Format for the Elf32 Function descriptor */

+12 -25

arch/parisc/include/asm/spinlock.h

··· 10 10 static inline int arch_spin_is_locked(arch_spinlock_t *x) 11 11 { 12 12 volatile unsigned int *a = __ldcw_align(x); 13 - smp_mb(); 14 13 return *a == 0; 15 14 } 16 15 17 - static inline void arch_spin_lock(arch_spinlock_t *x) 16 + #define arch_spin_lock(lock) arch_spin_lock_flags(lock, 0) 17 + 18 + static inline void arch_spin_lock_flags(arch_spinlock_t *x, 19 + unsigned long flags) 18 20 { 19 21 volatile unsigned int *a; 20 22 21 23 a = __ldcw_align(x); 22 24 while (__ldcw(a) == 0) 23 25 while (*a == 0) 24 - cpu_relax(); 25 - } 26 - 27 - static inline void arch_spin_lock_flags(arch_spinlock_t *x, 28 - unsigned long flags) 29 - { 30 - volatile unsigned int *a; 31 - unsigned long flags_dis; 32 - 33 - a = __ldcw_align(x); 34 - while (__ldcw(a) == 0) { 35 - local_save_flags(flags_dis); 36 - local_irq_restore(flags); 37 - while (*a == 0) 38 - cpu_relax(); 39 - local_irq_restore(flags_dis); 40 - } 26 + if (flags & PSW_SM_I) { 27 + local_irq_enable(); 28 + cpu_relax(); 29 + local_irq_disable(); 30 + } else 31 + cpu_relax(); 41 32 } 42 33 #define arch_spin_lock_flags arch_spin_lock_flags 43 34 ··· 37 46 volatile unsigned int *a; 38 47 39 48 a = __ldcw_align(x); 40 - #ifdef CONFIG_SMP 41 - (void) __ldcw(a); 42 - #else 43 - mb(); 44 - #endif 45 - *a = 1; 49 + /* Release with ordered store. */ 50 + __asm__ __volatile__("stw,ma %0,0(%1)" : : "r"(1), "r"(a) : "memory"); 46 51 } 47 52 48 53 static inline int arch_spin_trylock(arch_spinlock_t *x)

+25 -23

arch/parisc/kernel/entry.S

··· 454 454 nop 455 455 LDREG 0(\ptp),\pte 456 456 bb,<,n \pte,_PAGE_PRESENT_BIT,3f 457 - LDCW 0(\tmp),\tmp1 458 457 b \fault 459 458 stw \spc,0(\tmp) 460 459 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) ··· 463 464 3: 464 465 .endm 465 466 466 - /* Release pa_tlb_lock lock without reloading lock address. */ 467 - .macro tlb_unlock0 spc,tmp,tmp1 467 + /* Release pa_tlb_lock lock without reloading lock address. 468 + Note that the values in the register spc are limited to 469 + NR_SPACE_IDS (262144). Thus, the stw instruction always 470 + stores a nonzero value even when register spc is 64 bits. 471 + We use an ordered store to ensure all prior accesses are 472 + performed prior to releasing the lock. */ 473 + .macro tlb_unlock0 spc,tmp 468 474 #ifdef CONFIG_SMP 469 475 98: or,COND(=) %r0,\spc,%r0 470 - LDCW 0(\tmp),\tmp1 471 - or,COND(=) %r0,\spc,%r0 472 - stw \spc,0(\tmp) 476 + stw,ma \spc,0(\tmp) 473 477 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 474 478 #endif 475 479 .endm 476 480 477 481 /* Release pa_tlb_lock lock. */ 478 - .macro tlb_unlock1 spc,tmp,tmp1 482 + .macro tlb_unlock1 spc,tmp 479 483 #ifdef CONFIG_SMP 480 484 98: load_pa_tlb_lock \tmp 481 485 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 482 - tlb_unlock0 \spc,\tmp,\tmp1 486 + tlb_unlock0 \spc,\tmp 483 487 #endif 484 488 .endm 485 489 ··· 1165 1163 1166 1164 idtlbt pte,prot 1167 1165 1168 - tlb_unlock1 spc,t0,t1 1166 + tlb_unlock1 spc,t0 1169 1167 rfir 1170 1168 nop 1171 1169 ··· 1191 1189 1192 1190 idtlbt pte,prot 1193 1191 1194 - tlb_unlock1 spc,t0,t1 1192 + tlb_unlock1 spc,t0 1195 1193 rfir 1196 1194 nop 1197 1195 ··· 1225 1223 1226 1224 mtsp t1, %sr1 /* Restore sr1 */ 1227 1225 1228 - tlb_unlock1 spc,t0,t1 1226 + tlb_unlock1 spc,t0 1229 1227 rfir 1230 1228 nop 1231 1229 ··· 1258 1256 1259 1257 mtsp t1, %sr1 /* Restore sr1 */ 1260 1258 1261 - tlb_unlock1 spc,t0,t1 1259 + tlb_unlock1 spc,t0 1262 1260 rfir 1263 1261 nop 1264 1262 ··· 1287 1285 1288 1286 idtlbt pte,prot 1289 1287 1290 - tlb_unlock1 spc,t0,t1 1288 + tlb_unlock1 spc,t0 1291 1289 rfir 1292 1290 nop 1293 1291 ··· 1315 1313 1316 1314 idtlbt pte,prot 1317 1315 1318 - tlb_unlock1 spc,t0,t1 1316 + tlb_unlock1 spc,t0 1319 1317 rfir 1320 1318 nop 1321 1319 ··· 1422 1420 1423 1421 iitlbt pte,prot 1424 1422 1425 - tlb_unlock1 spc,t0,t1 1423 + tlb_unlock1 spc,t0 1426 1424 rfir 1427 1425 nop 1428 1426 ··· 1446 1444 1447 1445 iitlbt pte,prot 1448 1446 1449 - tlb_unlock1 spc,t0,t1 1447 + tlb_unlock1 spc,t0 1450 1448 rfir 1451 1449 nop 1452 1450 ··· 1480 1478 1481 1479 mtsp t1, %sr1 /* Restore sr1 */ 1482 1480 1483 - tlb_unlock1 spc,t0,t1 1481 + tlb_unlock1 spc,t0 1484 1482 rfir 1485 1483 nop 1486 1484 ··· 1504 1502 1505 1503 mtsp t1, %sr1 /* Restore sr1 */ 1506 1504 1507 - tlb_unlock1 spc,t0,t1 1505 + tlb_unlock1 spc,t0 1508 1506 rfir 1509 1507 nop 1510 1508 ··· 1534 1532 1535 1533 iitlbt pte,prot 1536 1534 1537 - tlb_unlock1 spc,t0,t1 1535 + tlb_unlock1 spc,t0 1538 1536 rfir 1539 1537 nop 1540 1538 ··· 1554 1552 1555 1553 iitlbt pte,prot 1556 1554 1557 - tlb_unlock1 spc,t0,t1 1555 + tlb_unlock1 spc,t0 1558 1556 rfir 1559 1557 nop 1560 1558 ··· 1584 1582 1585 1583 idtlbt pte,prot 1586 1584 1587 - tlb_unlock0 spc,t0,t1 1585 + tlb_unlock0 spc,t0 1588 1586 rfir 1589 1587 nop 1590 1588 #else ··· 1610 1608 1611 1609 mtsp t1, %sr1 /* Restore sr1 */ 1612 1610 1613 - tlb_unlock0 spc,t0,t1 1611 + tlb_unlock0 spc,t0 1614 1612 rfir 1615 1613 nop 1616 1614 ··· 1630 1628 1631 1629 idtlbt pte,prot 1632 1630 1633 - tlb_unlock0 spc,t0,t1 1631 + tlb_unlock0 spc,t0 1634 1632 rfir 1635 1633 nop 1636 1634 #endif

+3

arch/parisc/kernel/pdt.c

··· 18 18 #include <linux/kthread.h> 19 19 #include <linux/initrd.h> 20 20 #include <linux/pgtable.h> 21 + #include <linux/swap.h> 22 + #include <linux/swapops.h> 21 23 22 24 #include <asm/pdc.h> 23 25 #include <asm/pdcpat.h> ··· 232 230 233 231 /* mark memory page bad */ 234 232 memblock_reserve(pdt_entry[i] & PAGE_MASK, PAGE_SIZE); 233 + num_poisoned_pages_inc(); 235 234 } 236 235 } 237 236

+4 -20

arch/parisc/kernel/syscall.S

··· 640 640 sub,<> %r28, %r25, %r0 641 641 2: stw %r24, 0(%r26) 642 642 /* Free lock */ 643 - #ifdef CONFIG_SMP 644 - 98: LDCW 0(%sr2,%r20), %r1 /* Barrier */ 645 - 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 646 - #endif 647 - stw %r20, 0(%sr2,%r20) 643 + stw,ma %r20, 0(%sr2,%r20) 648 644 #if ENABLE_LWS_DEBUG 649 645 /* Clear thread register indicator */ 650 646 stw %r0, 4(%sr2,%r20) ··· 654 658 3: 655 659 /* Error occurred on load or store */ 656 660 /* Free lock */ 657 - #ifdef CONFIG_SMP 658 - 98: LDCW 0(%sr2,%r20), %r1 /* Barrier */ 659 - 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 660 - #endif 661 - stw %r20, 0(%sr2,%r20) 661 + stw,ma %r20, 0(%sr2,%r20) 662 662 #if ENABLE_LWS_DEBUG 663 663 stw %r0, 4(%sr2,%r20) 664 664 #endif ··· 855 863 856 864 cas2_end: 857 865 /* Free lock */ 858 - #ifdef CONFIG_SMP 859 - 98: LDCW 0(%sr2,%r20), %r1 /* Barrier */ 860 - 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 861 - #endif 862 - stw %r20, 0(%sr2,%r20) 866 + stw,ma %r20, 0(%sr2,%r20) 863 867 /* Enable interrupts */ 864 868 ssm PSW_SM_I, %r0 865 869 /* Return to userspace, set no error */ ··· 865 877 22: 866 878 /* Error occurred on load or store */ 867 879 /* Free lock */ 868 - #ifdef CONFIG_SMP 869 - 98: LDCW 0(%sr2,%r20), %r1 /* Barrier */ 870 - 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 871 - #endif 872 - stw %r20, 0(%sr2,%r20) 880 + stw,ma %r20, 0(%sr2,%r20) 873 881 ssm PSW_SM_I, %r0 874 882 ldo 1(%r0),%r28 875 883 b lws_exit

+3 -3

arch/parisc/kernel/traps.c

··· 75 75 lvl, f, (x), (x+3), (r)[(x)+0], (r)[(x)+1], \ 76 76 (r)[(x)+2], (r)[(x)+3]) 77 77 78 - static void print_gr(char *level, struct pt_regs *regs) 78 + static void print_gr(const char *level, struct pt_regs *regs) 79 79 { 80 80 int i; 81 81 char buf[64]; ··· 89 89 PRINTREGS(level, regs->gr, "r", RFMT, i); 90 90 } 91 91 92 - static void print_fr(char *level, struct pt_regs *regs) 92 + static void print_fr(const char *level, struct pt_regs *regs) 93 93 { 94 94 int i; 95 95 char buf[64]; ··· 119 119 void show_regs(struct pt_regs *regs) 120 120 { 121 121 int i, user; 122 - char *level; 122 + const char *level; 123 123 unsigned long cr30, cr31; 124 124 125 125 user = user_mode(regs);

+6 -6

arch/parisc/mm/init.c

··· 750 750 free_space_ids--; 751 751 752 752 index = find_next_zero_bit(space_id, NR_SPACE_IDS, space_id_index); 753 - space_id[index >> SHIFT_PER_LONG] |= (1L << (index & (BITS_PER_LONG - 1))); 753 + space_id[BIT_WORD(index)] |= BIT_MASK(index); 754 754 space_id_index = index; 755 755 756 756 spin_unlock(&sid_lock); ··· 761 761 void free_sid(unsigned long spaceid) 762 762 { 763 763 unsigned long index = spaceid >> SPACEID_SHIFT; 764 - unsigned long *dirty_space_offset; 764 + unsigned long *dirty_space_offset, mask; 765 765 766 - dirty_space_offset = dirty_space_id + (index >> SHIFT_PER_LONG); 767 - index &= (BITS_PER_LONG - 1); 766 + dirty_space_offset = &dirty_space_id[BIT_WORD(index)]; 767 + mask = BIT_MASK(index); 768 768 769 769 spin_lock(&sid_lock); 770 770 771 - BUG_ON(*dirty_space_offset & (1L << index)); /* attempt to free space id twice */ 771 + BUG_ON(*dirty_space_offset & mask); /* attempt to free space id twice */ 772 772 773 - *dirty_space_offset |= (1L << index); 773 + *dirty_space_offset |= mask; 774 774 dirty_space_ids++; 775 775 776 776 spin_unlock(&sid_lock);

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