Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2023-09-15' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Regular rc2 fixes pull, mostly made up of amdgpu stuff, one i915, and
a bunch of others, one vkms locking violation is reverted.
connector:
- doc fix
exec:
- workaround lockdep issue
tests:
- fix a UAF
vkms:
- revert hrtimer fix
fbdev:
- g364fb: fix build failure with mips
i915:
- Only check eDP HPD when AUX CH is shared.
amdgpu:
- GC 9.4.3 fixes
- Fix white screen issues with S/G display on system with >= 64G of ram
- Replay fixes
- SMU 13.0.6 fixes
- AUX backlight fix
- NBIO 4.3 SR-IOV fixes for HDP
- RAS fixes
- DP MST resume fix
- Fix segfault on systems with no vbios
- DPIA fixes
amdkfd:
- CWSR grace period fix
- Unaligned doorbell fix
- CRIU fix for GFX11
- Add missing TLB flush on gfx10 and newer
radeon:
- make fence wait in suballocator uninterrruptable
gm12u320:
- Fix the timeout usage for usb_bulk_msg()"
* tag 'drm-fixes-2023-09-15' of git://anongit.freedesktop.org/drm/drm: (29 commits)
drm/tests: helpers: Avoid a driver uaf
Revert "drm/vkms: Fix race-condition between the hrtimer and the atomic commit"
drm/amdkfd: Insert missing TLB flush on GFX10 and later
drm/i915: Only check eDP HPD when AUX CH is shared
drm/amd/display: Fix 2nd DPIA encoder Assignment
drm/amd/display: Add DPIA Link Encoder Assignment Fix
drm/amd/display: fix replay_mode kernel-doc warning
drm/amdgpu: Handle null atom context in VBIOS info ioctl
drm/amdkfd: Checkpoint and restore queues on GFX11
drm/amd/display: Adjust the MST resume flow
drm/amdgpu: fallback to old RAS error message for aqua_vanjaram
drm/amdgpu/nbio4.3: set proper rmmio_remap.reg_offset for SR-IOV
drm/amdgpu/soc21: don't remap HDP registers for SR-IOV
drm/amd/display: Don't check registers, if using AUX BL control
drm/amdgpu: fix retry loop test
drm/amd/display: Add dirty rect support for Replay
Revert "drm/amd: Disable S/G for APUs when 64GB or more host memory"
drm/amd/display: fix the white screen issue when >= 64GB DRAM
drm/amdkfd: Update CU masking for GFX 9.4.3
drm/amdkfd: Update cache info reporting for GFX v9.4.3
...
+460
-231
-1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
-1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
···
1293
1293
void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1294
1294
int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1295
1295
bool amdgpu_device_need_post(struct amdgpu_device *adev);
1296
-
bool amdgpu_sg_display_supported(struct amdgpu_device *adev);
1297
1296
bool amdgpu_device_pcie_dynamic_switching_supported(void);
1298
1297
bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1299
1298
bool amdgpu_device_aspm_support_quirk(void);
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
···
478
478
cu_info->cu_active_number = acu_info.number;
479
479
cu_info->cu_ao_mask = acu_info.ao_cu_mask;
480
480
memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
481
-
sizeof(acu_info.bitmap));
481
+
sizeof(cu_info->cu_bitmap));
482
482
cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
483
483
cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
484
484
cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
+1
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+1
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+1
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
+1
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h
+2
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+2
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
···
1103
1103
uint32_t wait_times,
1104
1104
uint32_t grace_period,
1105
1105
uint32_t *reg_offset,
1106
-
uint32_t *reg_data,
1107
-
uint32_t inst)
1106
+
uint32_t *reg_data)
1108
1107
{
1109
1108
*reg_data = wait_times;
1110
1109
···
1119
1120
SCH_WAVE,
1120
1121
grace_period);
1121
1122
1122
-
*reg_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, inst),
1123
-
mmCP_IQ_WAIT_TIME2);
1123
+
*reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);
1124
1124
}
1125
1125
1126
1126
void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
+1
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+1
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
-26
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-26
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
1245
1245
}
1246
1246
1247
1247
/*
1248
-
* On APUs with >= 64GB white flickering has been observed w/ SG enabled.
1249
-
* Disable S/G on such systems until we have a proper fix.
1250
-
* https://gitlab.freedesktop.org/drm/amd/-/issues/2354
1251
-
* https://gitlab.freedesktop.org/drm/amd/-/issues/2735
1252
-
*/
1253
-
bool amdgpu_sg_display_supported(struct amdgpu_device *adev)
1254
-
{
1255
-
switch (amdgpu_sg_display) {
1256
-
case -1:
1257
-
break;
1258
-
case 0:
1259
-
return false;
1260
-
case 1:
1261
-
return true;
1262
-
default:
1263
-
return false;
1264
-
}
1265
-
if ((totalram_pages() << (PAGE_SHIFT - 10)) +
1266
-
(adev->gmc.real_vram_size / 1024) >= 64000000) {
1267
-
DRM_WARN("Disabling S/G due to >=64GB RAM\n");
1268
-
return false;
1269
-
}
1270
-
return true;
1271
-
}
1272
-
1273
-
/*
1274
1248
* Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
1275
1249
* speed switching. Until we have confirmation from Intel that a specific host
1276
1250
* supports it, it's safer that we keep it disabled for all.
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
···
43
43
#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
44
44
45
45
#define AMDGPU_MAX_GC_INSTANCES 8
46
+
#define KGD_MAX_QUEUES 128
46
47
47
48
#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
48
49
#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
···
258
257
uint32_t number;
259
258
uint32_t ao_cu_mask;
260
259
uint32_t ao_cu_bitmap[4][4];
261
-
uint32_t bitmap[4][4];
260
+
uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];
262
261
};
263
262
264
263
struct amdgpu_gfx_ras {
+12
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+12
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
···
839
839
memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
840
840
sizeof(adev->gfx.cu_info.ao_cu_bitmap));
841
841
memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
842
-
sizeof(adev->gfx.cu_info.bitmap));
842
+
sizeof(dev_info->cu_bitmap));
843
843
dev_info->vram_type = adev->gmc.vram_type;
844
844
dev_info->vram_bit_width = adev->gmc.vram_width;
845
845
dev_info->vce_harvest_config = adev->vce.harvest_config;
···
940
940
struct atom_context *atom_context;
941
941
942
942
atom_context = adev->mode_info.atom_context;
943
-
memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
944
-
memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
945
-
vbios_info.version = atom_context->version;
946
-
memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
947
-
sizeof(atom_context->vbios_ver_str));
948
-
memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
943
+
if (atom_context) {
944
+
memcpy(vbios_info.name, atom_context->name,
945
+
sizeof(atom_context->name));
946
+
memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
947
+
sizeof(atom_context->vbios_pn));
948
+
vbios_info.version = atom_context->version;
949
+
memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
950
+
sizeof(atom_context->vbios_ver_str));
951
+
memcpy(vbios_info.date, atom_context->date,
952
+
sizeof(atom_context->date));
953
+
}
949
954
950
955
return copy_to_user(out, &vbios_info,
951
956
min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
+4
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+4
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
···
1052
1052
info->ce_count = obj->err_data.ce_count;
1053
1053
1054
1054
if (err_data.ce_count) {
1055
-
if (adev->smuio.funcs &&
1055
+
if (!adev->aid_mask &&
1056
+
adev->smuio.funcs &&
1056
1057
adev->smuio.funcs->get_socket_id &&
1057
1058
adev->smuio.funcs->get_die_id) {
1058
1059
dev_info(adev->dev, "socket: %d, die: %d "
···
1073
1072
}
1074
1073
}
1075
1074
if (err_data.ue_count) {
1076
-
if (adev->smuio.funcs &&
1075
+
if (!adev->aid_mask &&
1076
+
adev->smuio.funcs &&
1077
1077
adev->smuio.funcs->get_socket_id &&
1078
1078
adev->smuio.funcs->get_die_id) {
1079
1079
dev_info(adev->dev, "socket: %d, die: %d "
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
9449
9449
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9450
9450
adev, disable_masks[i * 2 + j]);
9451
9451
bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9452
-
cu_info->bitmap[i][j] = bitmap;
9452
+
cu_info->bitmap[0][i][j] = bitmap;
9453
9453
9454
9454
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9455
9455
if (bitmap & mask) {
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
···
6368
6368
* SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6369
6369
* SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6370
6370
*/
6371
-
cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap;
6371
+
cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
6372
6372
6373
6373
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6374
6374
if (bitmap & mask)
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
···
3577
3577
gfx_v6_0_set_user_cu_inactive_bitmap(
3578
3578
adev, disable_masks[i * 2 + j]);
3579
3579
bitmap = gfx_v6_0_get_cu_enabled(adev);
3580
-
cu_info->bitmap[i][j] = bitmap;
3580
+
cu_info->bitmap[0][i][j] = bitmap;
3581
3581
3582
3582
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3583
3583
if (bitmap & mask) {
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
···
5119
5119
gfx_v7_0_set_user_cu_inactive_bitmap(
5120
5120
adev, disable_masks[i * 2 + j]);
5121
5121
bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5122
-
cu_info->bitmap[i][j] = bitmap;
5122
+
cu_info->bitmap[0][i][j] = bitmap;
5123
5123
5124
5124
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5125
5125
if (bitmap & mask) {
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
7121
7121
gfx_v8_0_set_user_cu_inactive_bitmap(
7122
7122
adev, disable_masks[i * 2 + j]);
7123
7123
bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7124
-
cu_info->bitmap[i][j] = bitmap;
7124
+
cu_info->bitmap[0][i][j] = bitmap;
7125
7125
7126
7126
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7127
7127
if (bitmap & mask) {
+2
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
1499
1499
amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0);
1500
1500
1501
1501
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
1502
-
if (cu_info->bitmap[i][j] & mask) {
1502
+
if (cu_info->bitmap[0][i][j] & mask) {
1503
1503
if (counter == pg_always_on_cu_num)
1504
1504
WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
1505
1505
if (counter < always_on_cu_num)
···
7233
7233
* SE6,SH0 --> bitmap[2][1]
7234
7234
* SE7,SH0 --> bitmap[3][1]
7235
7235
*/
7236
-
cu_info->bitmap[i % 4][j + i / 4] = bitmap;
7236
+
cu_info->bitmap[0][i % 4][j + i / 4] = bitmap;
7237
7237
7238
7238
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7239
7239
if (bitmap & mask) {
+32
-40
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+32
-40
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
···
4259
4259
}
4260
4260
4261
4261
static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4262
-
u32 bitmap)
4262
+
u32 bitmap, int xcc_id)
4263
4263
{
4264
4264
u32 data;
4265
4265
···
4269
4269
data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4270
4270
data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4271
4271
4272
-
WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data);
4272
+
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);
4273
4273
}
4274
4274
4275
-
static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev)
4275
+
static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id)
4276
4276
{
4277
4277
u32 data, mask;
4278
4278
4279
-
data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG);
4280
-
data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG);
4279
+
data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);
4280
+
data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);
4281
4281
4282
4282
data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4283
4283
data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
···
4290
4290
static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
4291
4291
struct amdgpu_cu_info *cu_info)
4292
4292
{
4293
-
int i, j, k, counter, active_cu_number = 0;
4293
+
int i, j, k, counter, xcc_id, active_cu_number = 0;
4294
4294
u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4295
4295
unsigned disable_masks[4 * 4];
4296
4296
···
4309
4309
adev->gfx.config.max_sh_per_se);
4310
4310
4311
4311
mutex_lock(&adev->grbm_idx_mutex);
4312
-
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4313
-
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4314
-
mask = 1;
4315
-
ao_bitmap = 0;
4316
-
counter = 0;
4317
-
gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0);
4318
-
gfx_v9_4_3_set_user_cu_inactive_bitmap(
4319
-
adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
4320
-
bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev);
4312
+
for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
4313
+
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4314
+
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4315
+
mask = 1;
4316
+
ao_bitmap = 0;
4317
+
counter = 0;
4318
+
gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id);
4319
+
gfx_v9_4_3_set_user_cu_inactive_bitmap(
4320
+
adev,
4321
+
disable_masks[i * adev->gfx.config.max_sh_per_se + j],
4322
+
xcc_id);
4323
+
bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id);
4321
4324
4322
-
/*
4323
-
* The bitmap(and ao_cu_bitmap) in cu_info structure is
4324
-
* 4x4 size array, and it's usually suitable for Vega
4325
-
* ASICs which has 4*2 SE/SH layout.
4326
-
* But for Arcturus, SE/SH layout is changed to 8*1.
4327
-
* To mostly reduce the impact, we make it compatible
4328
-
* with current bitmap array as below:
4329
-
* SE4,SH0 --> bitmap[0][1]
4330
-
* SE5,SH0 --> bitmap[1][1]
4331
-
* SE6,SH0 --> bitmap[2][1]
4332
-
* SE7,SH0 --> bitmap[3][1]
4333
-
*/
4334
-
cu_info->bitmap[i % 4][j + i / 4] = bitmap;
4325
+
cu_info->bitmap[xcc_id][i][j] = bitmap;
4335
4326
4336
-
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4337
-
if (bitmap & mask) {
4338
-
if (counter < adev->gfx.config.max_cu_per_sh)
4339
-
ao_bitmap |= mask;
4340
-
counter++;
4327
+
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4328
+
if (bitmap & mask) {
4329
+
if (counter < adev->gfx.config.max_cu_per_sh)
4330
+
ao_bitmap |= mask;
4331
+
counter++;
4332
+
}
4333
+
mask <<= 1;
4341
4334
}
4342
-
mask <<= 1;
4335
+
active_cu_number += counter;
4336
+
if (i < 2 && j < 2)
4337
+
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4338
+
cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4343
4339
}
4344
-
active_cu_number += counter;
4345
-
if (i < 2 && j < 2)
4346
-
ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4347
-
cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
4348
4340
}
4341
+
gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4342
+
xcc_id);
4349
4343
}
4350
-
gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4351
-
0);
4352
4344
mutex_unlock(&adev->grbm_idx_mutex);
4353
4345
4354
4346
cu_info->number = active_cu_number;
+3
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+3
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
···
345
345
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
346
346
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
347
347
}
348
+
if (amdgpu_sriov_vf(adev))
349
+
adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
350
+
regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
348
351
}
349
352
350
353
static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
+1
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
+1
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
···
766
766
* for the purpose of expose those registers
767
767
* to process space
768
768
*/
769
-
if (adev->nbio.funcs->remap_hdp_registers)
769
+
if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
770
770
adev->nbio.funcs->remap_hdp_registers(adev);
771
771
/* enable the doorbell aperture */
772
772
adev->nbio.funcs->enable_doorbell_aperture(adev, true);
+2
-1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+2
-1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
···
2087
2087
2088
2088
amdgpu_amdkfd_get_cu_info(kdev->adev, &cu_info);
2089
2089
cu->num_simd_per_cu = cu_info.simd_per_cu;
2090
-
cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number;
2090
+
cu->num_simd_cores = cu_info.simd_per_cu *
2091
+
(cu_info.cu_active_number / kdev->kfd->num_nodes);
2091
2092
cu->max_waves_simd = cu_info.max_waves_per_simd;
2092
2093
2093
2094
cu->wave_front_size = cu_info.wave_front_size;
+4
drivers/gpu/drm/amd/amdkfd/kfd_crat.h
+4
drivers/gpu/drm/amd/amdkfd/kfd_crat.h
+1
-2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+1
-2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+2
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
+2
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
···
162
162
return NULL;
163
163
164
164
*doorbell_off = amdgpu_doorbell_index_on_bar(kfd->adev, kfd->doorbells, inx);
165
+
inx *= 2;
165
166
166
167
pr_debug("Get kernel queue doorbell\n"
167
168
" doorbell offset == 0x%08X\n"
···
177
176
unsigned int inx;
178
177
179
178
inx = (unsigned int)(db_addr - kfd->doorbell_kernel_ptr);
179
+
inx /= 2;
180
180
181
181
mutex_lock(&kfd->doorbell_mutex);
182
182
__clear_bit(inx, kfd->doorbell_bitmap);
+26
-8
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+26
-8
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
···
97
97
98
98
void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
99
99
const uint32_t *cu_mask, uint32_t cu_mask_count,
100
-
uint32_t *se_mask)
100
+
uint32_t *se_mask, uint32_t inst)
101
101
{
102
102
struct kfd_cu_info cu_info;
103
103
uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
104
104
bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);
105
105
uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;
106
-
int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1;
106
+
int i, se, sh, cu, cu_bitmap_sh_mul, cu_inc = wgp_mode_req ? 2 : 1;
107
+
uint32_t cu_active_per_node;
108
+
int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask);
109
+
int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1;
107
110
108
111
amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
109
112
110
-
if (cu_mask_count > cu_info.cu_active_number)
111
-
cu_mask_count = cu_info.cu_active_number;
113
+
cu_active_per_node = cu_info.cu_active_number / mm->dev->kfd->num_nodes;
114
+
if (cu_mask_count > cu_active_per_node)
115
+
cu_mask_count = cu_active_per_node;
112
116
113
117
/* Exceeding these bounds corrupts the stack and indicates a coding error.
114
118
* Returning with no CU's enabled will hang the queue, which should be
···
145
141
for (se = 0; se < cu_info.num_shader_engines; se++)
146
142
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
147
143
cu_per_sh[se][sh] = hweight32(
148
-
cu_info.cu_bitmap[se % 4][sh + (se / 4) * cu_bitmap_sh_mul]);
144
+
cu_info.cu_bitmap[xcc_inst][se % 4][sh + (se / 4) *
145
+
cu_bitmap_sh_mul]);
149
146
150
147
/* Symmetrically map cu_mask to all SEs & SHs:
151
148
* se_mask programs up to 2 SH in the upper and lower 16 bits.
···
169
164
* cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1)
170
165
* ...
171
166
*
167
+
* For GFX 9.4.3, the following code only looks at a
168
+
* subset of the cu_mask corresponding to the inst parameter.
169
+
* If we have n XCCs under one GPU node
170
+
* cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0)
171
+
* cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0)
172
+
* ..
173
+
* cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0)
174
+
* cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0)
175
+
*
176
+
* For example, if there are 6 XCCs under 1 KFD node, this code
177
+
* running for each inst, will look at the bits as:
178
+
* inst, inst + 6, inst + 12...
179
+
*
172
180
* First ensure all CUs are disabled, then enable user specified CUs.
173
181
*/
174
182
for (i = 0; i < cu_info.num_shader_engines; i++)
175
183
se_mask[i] = 0;
176
184
177
-
i = 0;
178
-
for (cu = 0; cu < 16; cu += inc) {
185
+
i = inst;
186
+
for (cu = 0; cu < 16; cu += cu_inc) {
179
187
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
180
188
for (se = 0; se < cu_info.num_shader_engines; se++) {
181
189
if (cu_per_sh[se][sh] > cu) {
182
190
if (cu_mask[i / 32] & (en_mask << (i % 32)))
183
191
se_mask[se] |= en_mask << (cu + sh * 16);
184
192
i += inc;
185
-
if (i == cu_mask_count)
193
+
if (i >= cu_mask_count)
186
194
return;
187
195
}
188
196
}
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
···
138
138
139
139
void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
140
140
const uint32_t *cu_mask, uint32_t cu_mask_count,
141
-
uint32_t *se_mask);
141
+
uint32_t *se_mask, uint32_t inst);
142
142
143
143
int kfd_hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,
144
144
uint32_t pipe_id, uint32_t queue_id,
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
+42
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+42
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
···
71
71
}
72
72
73
73
mqd_symmetrically_map_cu_mask(mm,
74
-
minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
74
+
minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);
75
75
76
76
m->compute_static_thread_mgmt_se0 = se_mask[0];
77
77
m->compute_static_thread_mgmt_se1 = se_mask[1];
···
321
321
return 0;
322
322
}
323
323
324
+
static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
325
+
{
326
+
struct v11_compute_mqd *m;
327
+
328
+
m = get_mqd(mqd);
329
+
330
+
memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd));
331
+
}
332
+
333
+
static void restore_mqd(struct mqd_manager *mm, void **mqd,
334
+
struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
335
+
struct queue_properties *qp,
336
+
const void *mqd_src,
337
+
const void *ctl_stack_src, const u32 ctl_stack_size)
338
+
{
339
+
uint64_t addr;
340
+
struct v11_compute_mqd *m;
341
+
342
+
m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
343
+
addr = mqd_mem_obj->gpu_addr;
344
+
345
+
memcpy(m, mqd_src, sizeof(*m));
346
+
347
+
*mqd = m;
348
+
if (gart_addr)
349
+
*gart_addr = addr;
350
+
351
+
m->cp_hqd_pq_doorbell_control =
352
+
qp->doorbell_off <<
353
+
CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
354
+
pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
355
+
m->cp_hqd_pq_doorbell_control);
356
+
357
+
qp->is_active = 0;
358
+
}
359
+
360
+
324
361
static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
325
362
struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
326
363
struct queue_properties *q)
···
495
458
mqd->mqd_size = sizeof(struct v11_compute_mqd);
496
459
mqd->get_wave_state = get_wave_state;
497
460
mqd->mqd_stride = kfd_mqd_stride;
461
+
mqd->checkpoint_mqd = checkpoint_mqd;
462
+
mqd->restore_mqd = restore_mqd;
498
463
#if defined(CONFIG_DEBUG_FS)
499
464
mqd->debugfs_show_mqd = debugfs_show_mqd;
500
465
#endif
···
541
502
mqd->update_mqd = update_mqd_sdma;
542
503
mqd->destroy_mqd = kfd_destroy_mqd_sdma;
543
504
mqd->is_occupied = kfd_is_occupied_sdma;
505
+
mqd->checkpoint_mqd = checkpoint_mqd;
506
+
mqd->restore_mqd = restore_mqd;
544
507
mqd->mqd_size = sizeof(struct v11_sdma_mqd);
545
508
mqd->mqd_stride = kfd_mqd_stride;
546
509
#if defined(CONFIG_DEBUG_FS)
+28
-16
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+28
-16
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
···
60
60
}
61
61
62
62
static void update_cu_mask(struct mqd_manager *mm, void *mqd,
63
-
struct mqd_update_info *minfo)
63
+
struct mqd_update_info *minfo, uint32_t inst)
64
64
{
65
65
struct v9_mqd *m;
66
66
uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
···
69
69
return;
70
70
71
71
mqd_symmetrically_map_cu_mask(mm,
72
-
minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
72
+
minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst);
73
73
74
74
m = get_mqd(mqd);
75
+
75
76
m->compute_static_thread_mgmt_se0 = se_mask[0];
76
77
m->compute_static_thread_mgmt_se1 = se_mask[1];
77
78
m->compute_static_thread_mgmt_se2 = se_mask[2];
78
79
m->compute_static_thread_mgmt_se3 = se_mask[3];
79
-
m->compute_static_thread_mgmt_se4 = se_mask[4];
80
-
m->compute_static_thread_mgmt_se5 = se_mask[5];
81
-
m->compute_static_thread_mgmt_se6 = se_mask[6];
82
-
m->compute_static_thread_mgmt_se7 = se_mask[7];
80
+
if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3)) {
81
+
m->compute_static_thread_mgmt_se4 = se_mask[4];
82
+
m->compute_static_thread_mgmt_se5 = se_mask[5];
83
+
m->compute_static_thread_mgmt_se6 = se_mask[6];
84
+
m->compute_static_thread_mgmt_se7 = se_mask[7];
83
85
84
-
pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
85
-
m->compute_static_thread_mgmt_se0,
86
-
m->compute_static_thread_mgmt_se1,
87
-
m->compute_static_thread_mgmt_se2,
88
-
m->compute_static_thread_mgmt_se3,
89
-
m->compute_static_thread_mgmt_se4,
90
-
m->compute_static_thread_mgmt_se5,
91
-
m->compute_static_thread_mgmt_se6,
92
-
m->compute_static_thread_mgmt_se7);
86
+
pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
87
+
m->compute_static_thread_mgmt_se0,
88
+
m->compute_static_thread_mgmt_se1,
89
+
m->compute_static_thread_mgmt_se2,
90
+
m->compute_static_thread_mgmt_se3,
91
+
m->compute_static_thread_mgmt_se4,
92
+
m->compute_static_thread_mgmt_se5,
93
+
m->compute_static_thread_mgmt_se6,
94
+
m->compute_static_thread_mgmt_se7);
95
+
} else {
96
+
pr_debug("inst: %u, update cu mask to %#x %#x %#x %#x\n",
97
+
inst, m->compute_static_thread_mgmt_se0,
98
+
m->compute_static_thread_mgmt_se1,
99
+
m->compute_static_thread_mgmt_se2,
100
+
m->compute_static_thread_mgmt_se3);
101
+
}
93
102
}
94
103
95
104
static void set_priority(struct v9_mqd *m, struct queue_properties *q)
···
299
290
if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address)
300
291
m->cp_hqd_ctx_save_control = 0;
301
292
302
-
update_cu_mask(mm, mqd, minfo);
293
+
if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3))
294
+
update_cu_mask(mm, mqd, minfo, 0);
303
295
set_priority(m, q);
304
296
305
297
q->is_active = QUEUE_IS_ACTIVE(*q);
···
685
675
for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {
686
676
m = get_mqd(mqd + size * xcc);
687
677
update_mqd(mm, m, q, minfo);
678
+
679
+
update_cu_mask(mm, mqd, minfo, xcc);
688
680
689
681
if (q->format == KFD_QUEUE_FORMAT_AQL) {
690
682
switch (xcc) {
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+1
-2
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+1
-2
drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c
+1
-2
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+1
-2
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
···
1466
1466
1467
1467
static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
1468
1468
{
1469
-
return KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||
1470
-
KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) ||
1469
+
return KFD_GC_VERSION(dev) > IP_VERSION(9, 4, 2) ||
1471
1470
(KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) ||
1472
1471
KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
1473
1472
}
+42
-33
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+42
-33
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
···
450
450
sysfs_show_32bit_prop(buffer, offs, "cpu_cores_count",
451
451
dev->node_props.cpu_cores_count);
452
452
sysfs_show_32bit_prop(buffer, offs, "simd_count",
453
-
dev->gpu ? (dev->node_props.simd_count *
454
-
NUM_XCC(dev->gpu->xcc_mask)) : 0);
453
+
dev->gpu ? dev->node_props.simd_count : 0);
455
454
sysfs_show_32bit_prop(buffer, offs, "mem_banks_count",
456
455
dev->node_props.mem_banks_count);
457
456
sysfs_show_32bit_prop(buffer, offs, "caches_count",
···
1596
1597
static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext,
1597
1598
struct kfd_gpu_cache_info *pcache_info,
1598
1599
struct kfd_cu_info *cu_info,
1599
-
int cache_type, unsigned int cu_processor_id)
1600
+
int cache_type, unsigned int cu_processor_id,
1601
+
struct kfd_node *knode)
1600
1602
{
1601
1603
unsigned int cu_sibling_map_mask;
1602
1604
int first_active_cu;
1603
-
int i, j, k;
1605
+
int i, j, k, xcc, start, end;
1604
1606
struct kfd_cache_properties *pcache = NULL;
1605
1607
1606
-
cu_sibling_map_mask = cu_info->cu_bitmap[0][0];
1608
+
start = ffs(knode->xcc_mask) - 1;
1609
+
end = start + NUM_XCC(knode->xcc_mask);
1610
+
cu_sibling_map_mask = cu_info->cu_bitmap[start][0][0];
1607
1611
cu_sibling_map_mask &=
1608
1612
((1 << pcache_info[cache_type].num_cu_shared) - 1);
1609
1613
first_active_cu = ffs(cu_sibling_map_mask);
···
1641
1639
cu_sibling_map_mask = cu_sibling_map_mask >> (first_active_cu - 1);
1642
1640
k = 0;
1643
1641
1644
-
for (i = 0; i < cu_info->num_shader_engines; i++) {
1645
-
for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) {
1646
-
pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1647
-
pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1648
-
pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1649
-
pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1650
-
k += 4;
1642
+
for (xcc = start; xcc < end; xcc++) {
1643
+
for (i = 0; i < cu_info->num_shader_engines; i++) {
1644
+
for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) {
1645
+
pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1646
+
pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1647
+
pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1648
+
pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1649
+
k += 4;
1651
1650
1652
-
cu_sibling_map_mask = cu_info->cu_bitmap[i % 4][j + i / 4];
1653
-
cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1651
+
cu_sibling_map_mask = cu_info->cu_bitmap[xcc][i % 4][j + i / 4];
1652
+
cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1653
+
}
1654
1654
}
1655
1655
}
1656
1656
pcache->sibling_map_size = k;
···
1670
1666
static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct kfd_node *kdev)
1671
1667
{
1672
1668
struct kfd_gpu_cache_info *pcache_info = NULL;
1673
-
int i, j, k;
1669
+
int i, j, k, xcc, start, end;
1674
1670
int ct = 0;
1675
1671
unsigned int cu_processor_id;
1676
1672
int ret;
···
1704
1700
* then it will consider only one CU from
1705
1701
* the shared unit
1706
1702
*/
1703
+
start = ffs(kdev->xcc_mask) - 1;
1704
+
end = start + NUM_XCC(kdev->xcc_mask);
1705
+
1707
1706
for (ct = 0; ct < num_of_cache_types; ct++) {
1708
1707
cu_processor_id = gpu_processor_id;
1709
1708
if (pcache_info[ct].cache_level == 1) {
1710
-
for (i = 0; i < pcu_info->num_shader_engines; i++) {
1711
-
for (j = 0; j < pcu_info->num_shader_arrays_per_engine; j++) {
1712
-
for (k = 0; k < pcu_info->num_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
1709
+
for (xcc = start; xcc < end; xcc++) {
1710
+
for (i = 0; i < pcu_info->num_shader_engines; i++) {
1711
+
for (j = 0; j < pcu_info->num_shader_arrays_per_engine; j++) {
1712
+
for (k = 0; k < pcu_info->num_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
1713
1713
1714
-
ret = fill_in_l1_pcache(&props_ext, pcache_info, pcu_info,
1715
-
pcu_info->cu_bitmap[i % 4][j + i / 4], ct,
1714
+
ret = fill_in_l1_pcache(&props_ext, pcache_info, pcu_info,
1715
+
pcu_info->cu_bitmap[xcc][i % 4][j + i / 4], ct,
1716
1716
cu_processor_id, k);
1717
1717
1718
-
if (ret < 0)
1719
-
break;
1718
+
if (ret < 0)
1719
+
break;
1720
1720
1721
-
if (!ret) {
1722
-
num_of_entries++;
1723
-
list_add_tail(&props_ext->list, &dev->cache_props);
1721
+
if (!ret) {
1722
+
num_of_entries++;
1723
+
list_add_tail(&props_ext->list, &dev->cache_props);
1724
+
}
1725
+
1726
+
/* Move to next CU block */
1727
+
num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
1728
+
pcu_info->num_cu_per_sh) ?
1729
+
pcache_info[ct].num_cu_shared :
1730
+
(pcu_info->num_cu_per_sh - k);
1731
+
cu_processor_id += num_cu_shared;
1724
1732
}
1725
-
1726
-
/* Move to next CU block */
1727
-
num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
1728
-
pcu_info->num_cu_per_sh) ?
1729
-
pcache_info[ct].num_cu_shared :
1730
-
(pcu_info->num_cu_per_sh - k);
1731
-
cu_processor_id += num_cu_shared;
1732
1733
}
1733
1734
}
1734
1735
}
1735
1736
} else {
1736
1737
ret = fill_in_l2_l3_pcache(&props_ext, pcache_info,
1737
-
pcu_info, ct, cu_processor_id);
1738
+
pcu_info, ct, cu_processor_id, kdev);
1738
1739
1739
1740
if (ret < 0)
1740
1741
break;
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+94
-21
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+94
-21
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1274
1274
1275
1275
pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1276
1276
1277
-
page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1278
-
page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1279
-
page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1280
-
page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1281
-
page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1277
+
page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1278
+
AMDGPU_GPU_PAGE_SHIFT);
1279
+
page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1280
+
AMDGPU_GPU_PAGE_SHIFT);
1281
+
page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1282
+
AMDGPU_GPU_PAGE_SHIFT);
1283
+
page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1284
+
AMDGPU_GPU_PAGE_SHIFT);
1285
+
page_table_base.high_part = upper_32_bits(pt_base);
1282
1286
page_table_base.low_part = lower_32_bits(pt_base);
1283
1287
1284
1288
pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
···
1644
1640
}
1645
1641
break;
1646
1642
}
1647
-
if (init_data.flags.gpu_vm_support)
1648
-
init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev);
1643
+
if (init_data.flags.gpu_vm_support &&
1644
+
(amdgpu_sg_display == 0))
1645
+
init_data.flags.gpu_vm_support = false;
1649
1646
1650
1647
if (init_data.flags.gpu_vm_support)
1651
1648
adev->mode_info.gpu_vm_support = true;
···
2340
2335
return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2341
2336
}
2342
2337
2338
+
static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2339
+
{
2340
+
int ret;
2341
+
u8 guid[16];
2342
+
u64 tmp64;
2343
+
2344
+
mutex_lock(&mgr->lock);
2345
+
if (!mgr->mst_primary)
2346
+
goto out_fail;
2347
+
2348
+
if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2349
+
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2350
+
goto out_fail;
2351
+
}
2352
+
2353
+
ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2354
+
DP_MST_EN |
2355
+
DP_UP_REQ_EN |
2356
+
DP_UPSTREAM_IS_SRC);
2357
+
if (ret < 0) {
2358
+
drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2359
+
goto out_fail;
2360
+
}
2361
+
2362
+
/* Some hubs forget their guids after they resume */
2363
+
ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2364
+
if (ret != 16) {
2365
+
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2366
+
goto out_fail;
2367
+
}
2368
+
2369
+
if (memchr_inv(guid, 0, 16) == NULL) {
2370
+
tmp64 = get_jiffies_64();
2371
+
memcpy(&guid[0], &tmp64, sizeof(u64));
2372
+
memcpy(&guid[8], &tmp64, sizeof(u64));
2373
+
2374
+
ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2375
+
2376
+
if (ret != 16) {
2377
+
drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2378
+
goto out_fail;
2379
+
}
2380
+
}
2381
+
2382
+
memcpy(mgr->mst_primary->guid, guid, 16);
2383
+
2384
+
out_fail:
2385
+
mutex_unlock(&mgr->lock);
2386
+
}
2387
+
2343
2388
static void s3_handle_mst(struct drm_device *dev, bool suspend)
2344
2389
{
2345
2390
struct amdgpu_dm_connector *aconnector;
2346
2391
struct drm_connector *connector;
2347
2392
struct drm_connector_list_iter iter;
2348
2393
struct drm_dp_mst_topology_mgr *mgr;
2349
-
int ret;
2350
-
bool need_hotplug = false;
2351
2394
2352
2395
drm_connector_list_iter_begin(dev, &iter);
2353
2396
drm_for_each_connector_iter(connector, &iter) {
···
2417
2364
if (!dp_is_lttpr_present(aconnector->dc_link))
2418
2365
try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2419
2366
2420
-
ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2421
-
if (ret < 0) {
2422
-
dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2423
-
aconnector->dc_link);
2424
-
need_hotplug = true;
2425
-
}
2367
+
/* TODO: move resume_mst_branch_status() into drm mst resume again
2368
+
* once topology probing work is pulled out from mst resume into mst
2369
+
* resume 2nd step. mst resume 2nd step should be called after old
2370
+
* state getting restored (i.e. drm_atomic_helper_resume()).
2371
+
*/
2372
+
resume_mst_branch_status(mgr);
2426
2373
}
2427
2374
}
2428
2375
drm_connector_list_iter_end(&iter);
2429
-
2430
-
if (need_hotplug)
2431
-
drm_kms_helper_hotplug_event(dev);
2432
2376
}
2433
2377
2434
2378
static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
···
2819
2769
struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2820
2770
enum dc_connection_type new_connection_type = dc_connection_none;
2821
2771
struct dc_state *dc_state;
2822
-
int i, r, j;
2772
+
int i, r, j, ret;
2773
+
bool need_hotplug = false;
2823
2774
2824
2775
if (amdgpu_in_reset(adev)) {
2825
2776
dc_state = dm->cached_dc_state;
···
2918
2867
continue;
2919
2868
2920
2869
/*
2921
-
* this is the case when traversing through already created
2870
+
* this is the case when traversing through already created end sink
2922
2871
* MST connectors, should be skipped
2923
2872
*/
2924
2873
if (aconnector && aconnector->mst_root)
···
2977
2926
drm_atomic_helper_resume(ddev, dm->cached_state);
2978
2927
2979
2928
dm->cached_state = NULL;
2929
+
2930
+
/* Do mst topology probing after resuming cached state*/
2931
+
drm_connector_list_iter_begin(ddev, &iter);
2932
+
drm_for_each_connector_iter(connector, &iter) {
2933
+
aconnector = to_amdgpu_dm_connector(connector);
2934
+
if (aconnector->dc_link->type != dc_connection_mst_branch ||
2935
+
aconnector->mst_root)
2936
+
continue;
2937
+
2938
+
ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2939
+
2940
+
if (ret < 0) {
2941
+
dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2942
+
aconnector->dc_link);
2943
+
need_hotplug = true;
2944
+
}
2945
+
}
2946
+
drm_connector_list_iter_end(&iter);
2947
+
2948
+
if (need_hotplug)
2949
+
drm_kms_helper_hotplug_event(ddev);
2980
2950
2981
2951
amdgpu_dm_irq_resume_late(adev);
2982
2952
···
8145
8073
bundle->surface_updates[planes_count].plane_info =
8146
8074
&bundle->plane_infos[planes_count];
8147
8075
8148
-
if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8076
+
if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8077
+
acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8149
8078
fill_dc_dirty_rects(plane, old_plane_state,
8150
8079
new_plane_state, new_crtc_state,
8151
8080
&bundle->flip_addrs[planes_count],
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+28
-7
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+28
-7
drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
···
169
169
/* Return first available DIG link encoder. */
170
170
static enum engine_id find_first_avail_link_enc(
171
171
const struct dc_context *ctx,
172
-
const struct dc_state *state)
172
+
const struct dc_state *state,
173
+
enum engine_id eng_id_requested)
173
174
{
174
175
enum engine_id eng_id = ENGINE_ID_UNKNOWN;
175
176
int i;
177
+
178
+
if (eng_id_requested != ENGINE_ID_UNKNOWN) {
179
+
180
+
for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
181
+
eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i];
182
+
if (eng_id == eng_id_requested)
183
+
return eng_id;
184
+
}
185
+
}
186
+
187
+
eng_id = ENGINE_ID_UNKNOWN;
176
188
177
189
for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
178
190
eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i];
···
299
287
struct dc_stream_state *streams[],
300
288
uint8_t stream_count)
301
289
{
302
-
enum engine_id eng_id = ENGINE_ID_UNKNOWN;
290
+
enum engine_id eng_id = ENGINE_ID_UNKNOWN, eng_id_req = ENGINE_ID_UNKNOWN;
303
291
int i;
304
292
int j;
305
293
···
389
377
* assigned to that endpoint.
390
378
*/
391
379
link_enc = get_link_enc_used_by_link(state, stream->link);
392
-
if (link_enc == NULL)
393
-
eng_id = find_first_avail_link_enc(stream->ctx, state);
380
+
if (link_enc == NULL) {
381
+
382
+
if (stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
383
+
stream->link->dpia_preferred_eng_id != ENGINE_ID_UNKNOWN)
384
+
eng_id_req = stream->link->dpia_preferred_eng_id;
385
+
386
+
eng_id = find_first_avail_link_enc(stream->ctx, state, eng_id_req);
387
+
}
394
388
else
395
389
eng_id = link_enc->preferred_engine;
396
390
···
420
402
DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n",
421
403
__func__,
422
404
assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
423
-
assignment.ep_id.link_id.enum_id - 1,
405
+
assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
406
+
assignment.ep_id.link_id.enum_id :
407
+
assignment.ep_id.link_id.enum_id - 1,
424
408
assignment.eng_id);
425
409
}
426
410
for (i = 0; i < MAX_PIPES; i++) {
···
433
413
DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n",
434
414
__func__,
435
415
assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA",
436
-
assignment.ep_id.link_id.enum_id - 1,
416
+
assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ?
417
+
assignment.ep_id.link_id.enum_id :
418
+
assignment.ep_id.link_id.enum_id - 1,
437
419
assignment.eng_id);
438
420
}
439
421
···
500
478
if (stream)
501
479
link = stream->link;
502
480
503
-
// dm_output_to_console("%s: No link using DIG(%d).\n", __func__, eng_id);
504
481
return link;
505
482
}
506
483
+1
drivers/gpu/drm/amd/display/dc/dc.h
+1
drivers/gpu/drm/amd/display/dc/dc.h
+3
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+3
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
···
964
964
return;
965
965
}
966
966
967
-
if (link->panel_cntl) {
967
+
if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
968
+
link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
969
+
link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
968
970
bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
969
971
970
972
if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
+23
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+23
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
···
1032
1032
I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1033
1033
};
1034
1034
1035
+
/* ========================================================== */
1036
+
1037
+
/*
1038
+
* DPIA index | Preferred Encoder | Host Router
1039
+
* 0 | C | 0
1040
+
* 1 | First Available | 0
1041
+
* 2 | D | 1
1042
+
* 3 | First Available | 1
1043
+
*/
1044
+
/* ========================================================== */
1045
+
static const enum engine_id dpia_to_preferred_enc_id_table[] = {
1046
+
ENGINE_ID_DIGC,
1047
+
ENGINE_ID_DIGC,
1048
+
ENGINE_ID_DIGD,
1049
+
ENGINE_ID_DIGD
1050
+
};
1051
+
1052
+
static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
1053
+
{
1054
+
return dpia_to_preferred_enc_id_table[dpia_index];
1055
+
}
1056
+
1035
1057
static struct dce_i2c_hw *dcn31_i2c_hw_create(
1036
1058
struct dc_context *ctx,
1037
1059
uint32_t inst)
···
1807
1785
.update_bw_bounding_box = dcn314_update_bw_bounding_box,
1808
1786
.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1809
1787
.get_panel_config_defaults = dcn314_get_panel_config_defaults,
1788
+
.get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
1810
1789
};
1811
1790
1812
1791
static struct clock_source *dcn30_clock_source_create(
+1
drivers/gpu/drm/amd/display/dc/inc/core_types.h
+1
drivers/gpu/drm/amd/display/dc/inc/core_types.h
+4
drivers/gpu/drm/amd/display/dc/link/link_factory.c
+4
drivers/gpu/drm/amd/display/dc/link/link_factory.c
···
791
791
/* Set dpia port index : 0 to number of dpia ports */
792
792
link->ddc_hw_inst = init_params->connector_index;
793
793
794
+
// Assign Dpia preferred eng_id
795
+
if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)
796
+
link->dpia_preferred_eng_id = link->dc->res_pool->funcs->get_preferred_eng_id_dpia(link->ddc_hw_inst);
797
+
794
798
/* TODO: Create link encoder */
795
799
796
800
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
+4
-5
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+4
-5
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
···
31
31
#include <linux/types.h>
32
32
#include <linux/bitmap.h>
33
33
#include <linux/dma-fence.h>
34
+
#include "amdgpu_irq.h"
35
+
#include "amdgpu_gfx.h"
34
36
35
37
struct pci_dev;
36
38
struct amdgpu_device;
37
-
38
-
#define KGD_MAX_QUEUES 128
39
39
40
40
struct kfd_dev;
41
41
struct kgd_mem;
···
68
68
uint32_t wave_front_size;
69
69
uint32_t max_scratch_slots_per_cu;
70
70
uint32_t lds_size;
71
-
uint32_t cu_bitmap[4][4];
71
+
uint32_t cu_bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];
72
72
};
73
73
74
74
/* For getting GPU local memory information from KGD */
···
326
326
uint32_t wait_times,
327
327
uint32_t grace_period,
328
328
uint32_t *reg_offset,
329
-
uint32_t *reg_data,
330
-
uint32_t inst);
329
+
uint32_t *reg_data);
331
330
void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid,
332
331
int *wave_cnt, int *max_waves_per_cu, uint32_t inst);
333
332
void (*program_trap_handler_settings)(struct amdgpu_device *adev,
+1
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+1
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+2
drivers/gpu/drm/drm_connector.c
+2
drivers/gpu/drm/drm_connector.c
···
2203
2203
/**
2204
2204
* drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property
2205
2205
* @connector: connector to create the Colorspace property on.
2206
+
* @supported_colorspaces: bitmap of supported color spaces
2206
2207
*
2207
2208
* Called by a driver the first time it's needed, must be attached to desired
2208
2209
* HDMI connectors.
···
2228
2227
/**
2229
2228
* drm_mode_create_dp_colorspace_property - create dp colorspace property
2230
2229
* @connector: connector to create the Colorspace property on.
2230
+
* @supported_colorspaces: bitmap of supported color spaces
2231
2231
*
2232
2232
* Called by a driver the first time it's needed, must be attached to desired
2233
2233
* DP connectors.
+1
-1
drivers/gpu/drm/drm_exec.c
+1
-1
drivers/gpu/drm/drm_exec.c
+21
drivers/gpu/drm/i915/display/intel_bios.c
+21
drivers/gpu/drm/i915/display/intel_bios.c
···
3540
3540
return map_aux_ch(devdata->i915, devdata->child.aux_channel);
3541
3541
}
3542
3542
3543
+
bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata)
3544
+
{
3545
+
struct drm_i915_private *i915;
3546
+
u8 aux_channel;
3547
+
int count = 0;
3548
+
3549
+
if (!devdata || !devdata->child.aux_channel)
3550
+
return false;
3551
+
3552
+
i915 = devdata->i915;
3553
+
aux_channel = devdata->child.aux_channel;
3554
+
3555
+
list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
3556
+
if (intel_bios_encoder_supports_dp(devdata) &&
3557
+
aux_channel == devdata->child.aux_channel)
3558
+
count++;
3559
+
}
3560
+
3561
+
return count > 1;
3562
+
}
3563
+
3543
3564
int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata)
3544
3565
{
3545
3566
if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
+1
drivers/gpu/drm/i915/display/intel_bios.h
+1
drivers/gpu/drm/i915/display/intel_bios.h
···
273
273
int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata);
274
274
int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata);
275
275
int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata);
276
+
bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata);
276
277
int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
277
278
int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata);
278
279
int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata);
+6
-1
drivers/gpu/drm/i915/display/intel_dp.c
+6
-1
drivers/gpu/drm/i915/display/intel_dp.c
···
5512
5512
/*
5513
5513
* VBT and straps are liars. Also check HPD as that seems
5514
5514
* to be the most reliable piece of information available.
5515
+
*
5516
+
* ... expect on devices that forgot to hook HPD up for eDP
5517
+
* (eg. Acer Chromebook C710), so we'll check it only if multiple
5518
+
* ports are attempting to use the same AUX CH, according to VBT.
5515
5519
*/
5516
-
if (!intel_digital_port_connected(encoder)) {
5520
+
if (intel_bios_dp_has_shared_aux_ch(encoder->devdata) &&
5521
+
!intel_digital_port_connected(encoder)) {
5517
5522
/*
5518
5523
* If this fails, presume the DPCD answer came
5519
5524
* from some other port using the same AUX CH.
+1
-1
drivers/gpu/drm/radeon/radeon_sa.c
+1
-1
drivers/gpu/drm/radeon/radeon_sa.c
+5
-5
drivers/gpu/drm/tiny/gm12u320.c
+5
-5
drivers/gpu/drm/tiny/gm12u320.c
···
70
70
#define READ_STATUS_SIZE 13
71
71
#define MISC_VALUE_SIZE 4
72
72
73
-
#define CMD_TIMEOUT msecs_to_jiffies(200)
74
-
#define DATA_TIMEOUT msecs_to_jiffies(1000)
75
-
#define IDLE_TIMEOUT msecs_to_jiffies(2000)
76
-
#define FIRST_FRAME_TIMEOUT msecs_to_jiffies(2000)
73
+
#define CMD_TIMEOUT 200
74
+
#define DATA_TIMEOUT 1000
75
+
#define IDLE_TIMEOUT 2000
76
+
#define FIRST_FRAME_TIMEOUT 2000
77
77
78
78
#define MISC_REQ_GET_SET_ECO_A 0xff
79
79
#define MISC_REQ_GET_SET_ECO_B 0x35
···
389
389
* switches back to showing its logo.
390
390
*/
391
391
queue_delayed_work(system_long_wq, &gm12u320->fb_update.work,
392
-
IDLE_TIMEOUT);
392
+
msecs_to_jiffies(IDLE_TIMEOUT));
393
393
394
394
return;
395
395
err:
+2
-7
drivers/gpu/drm/vkms/vkms_composer.c
+2
-7
drivers/gpu/drm/vkms/vkms_composer.c
···
408
408
if (enabled)
409
409
drm_crtc_vblank_get(&out->crtc);
410
410
411
-
mutex_lock(&out->enabled_lock);
411
+
spin_lock_irq(&out->lock);
412
412
old_enabled = out->composer_enabled;
413
413
out->composer_enabled = enabled;
414
-
415
-
/* the composition wasn't enabled, so unlock the lock to make sure the lock
416
-
* will be balanced even if we have a failed commit
417
-
*/
418
-
if (!out->composer_enabled)
419
-
mutex_unlock(&out->enabled_lock);
414
+
spin_unlock_irq(&out->lock);
420
415
421
416
if (old_enabled)
422
417
drm_crtc_vblank_put(&out->crtc);
+4
-5
drivers/gpu/drm/vkms/vkms_crtc.c
+4
-5
drivers/gpu/drm/vkms/vkms_crtc.c
···
16
16
struct drm_crtc *crtc = &output->crtc;
17
17
struct vkms_crtc_state *state;
18
18
u64 ret_overrun;
19
-
bool ret, fence_cookie, composer_enabled;
19
+
bool ret, fence_cookie;
20
20
21
21
fence_cookie = dma_fence_begin_signalling();
22
22
···
25
25
if (ret_overrun != 1)
26
26
pr_warn("%s: vblank timer overrun\n", __func__);
27
27
28
+
spin_lock(&output->lock);
28
29
ret = drm_crtc_handle_vblank(crtc);
29
30
if (!ret)
30
31
DRM_ERROR("vkms failure on handling vblank");
31
32
32
33
state = output->composer_state;
33
-
composer_enabled = output->composer_enabled;
34
-
mutex_unlock(&output->enabled_lock);
34
+
spin_unlock(&output->lock);
35
35
36
-
if (state && composer_enabled) {
36
+
if (state && output->composer_enabled) {
37
37
u64 frame = drm_crtc_accurate_vblank_count(crtc);
38
38
39
39
/* update frame_start only if a queued vkms_composer_worker()
···
295
295
296
296
spin_lock_init(&vkms_out->lock);
297
297
spin_lock_init(&vkms_out->composer_lock);
298
-
mutex_init(&vkms_out->enabled_lock);
299
298
300
299
vkms_out->composer_workq = alloc_ordered_workqueue("vkms_composer", 0);
301
300
if (!vkms_out->composer_workq)
+1
-3
drivers/gpu/drm/vkms/vkms_drv.h
+1
-3
drivers/gpu/drm/vkms/vkms_drv.h
···
108
108
struct workqueue_struct *composer_workq;
109
109
/* protects concurrent access to composer */
110
110
spinlock_t lock;
111
-
/* guarantees that if the composer is enabled, a job will be queued */
112
-
struct mutex enabled_lock;
113
111
114
-
/* protected by @enabled_lock */
112
+
/* protected by @lock */
115
113
bool composer_enabled;
116
114
struct vkms_crtc_state *composer_state;
117
115
+31
-4
include/drm/drm_exec.h
+31
-4
include/drm/drm_exec.h
···
52
52
};
53
53
54
54
/**
55
+
* drm_exec_obj() - Return the object for a give drm_exec index
56
+
* @exec: Pointer to the drm_exec context
57
+
* @index: The index.
58
+
*
59
+
* Return: Pointer to the locked object corresponding to @index if
60
+
* index is within the number of locked objects. NULL otherwise.
61
+
*/
62
+
static inline struct drm_gem_object *
63
+
drm_exec_obj(struct drm_exec *exec, unsigned long index)
64
+
{
65
+
return index < exec->num_objects ? exec->objects[index] : NULL;
66
+
}
67
+
68
+
/**
55
69
* drm_exec_for_each_locked_object - iterate over all the locked objects
56
70
* @exec: drm_exec object
57
71
* @index: unsigned long index for the iteration
···
73
59
*
74
60
* Iterate over all the locked GEM objects inside the drm_exec object.
75
61
*/
76
-
#define drm_exec_for_each_locked_object(exec, index, obj) \
77
-
for (index = 0, obj = (exec)->objects[0]; \
78
-
index < (exec)->num_objects; \
79
-
++index, obj = (exec)->objects[index])
62
+
#define drm_exec_for_each_locked_object(exec, index, obj) \
63
+
for ((index) = 0; ((obj) = drm_exec_obj(exec, index)); ++(index))
64
+
65
+
/**
66
+
* drm_exec_for_each_locked_object_reverse - iterate over all the locked
67
+
* objects in reverse locking order
68
+
* @exec: drm_exec object
69
+
* @index: unsigned long index for the iteration
70
+
* @obj: the current GEM object
71
+
*
72
+
* Iterate over all the locked GEM objects inside the drm_exec object in
73
+
* reverse locking order. Note that @index may go below zero and wrap,
74
+
* but that will be caught by drm_exec_obj(), returning a NULL object.
75
+
*/
76
+
#define drm_exec_for_each_locked_object_reverse(exec, index, obj) \
77
+
for ((index) = (exec)->num_objects - 1; \
78
+
((obj) = drm_exec_obj(exec, index)); --(index))
80
79
81
80
/**
82
81
* drm_exec_until_all_locked - loop until all GEM objects are locked
+3
-1
include/drm/drm_kunit_helpers.h
+3
-1
include/drm/drm_kunit_helpers.h
···
3
3
#ifndef DRM_KUNIT_HELPERS_H_
4
4
#define DRM_KUNIT_HELPERS_H_
5
5
6
+
#include <linux/device.h>
7
+
6
8
#include <kunit/test.h>
7
9
8
10
struct drm_device;
···
53
51
{
54
52
struct drm_driver *driver;
55
53
56
-
driver = kunit_kzalloc(test, sizeof(*driver), GFP_KERNEL);
54
+
driver = devm_kzalloc(dev, sizeof(*driver), GFP_KERNEL);
57
55
KUNIT_ASSERT_NOT_NULL(test, driver);
58
56
59
57
driver->driver_features = features;