Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Add support for "input-schmitt-microvolt" property, as used in the
Sophgo SoC
New drivers:
- Mobileye EyeQ5 pin controller, I think this is an automotive SoC
- Rockchip rk3576 pin control support
- Sophgo CV1800 series pin controllers: CV1800B, CV1812H and SG2000
Improvements:
- Gradual improvements to Renesas, Samsung, Qualcomm, Nuvoton and a
few other drivers"
* tag 'pinctrl-v6.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (67 commits)
pinctrl: intel: Constify struct intel_pinctrl parameter
pinctrl: Remove redundant null pointer checks in pinctrl_remove_device_debugfs()
pinctrl: baytrail: Drop duplicate return statement
pinctrl: intel: Inline intel_gpio_community_irq_handler()
dt-bindings: pinctrl: qcom: add missing type to GPIO hogs
pinctrl: madera: Simplify with dev_err_probe()
pinctrl: k210: Use devm_clk_get_enabled() helpers
pinctrl: Join split messages and remove double whitespace
pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases
pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration
pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API
pinctrl: mvebu: Fix devinit_dove_pinctrl_probe function
pinctrl: sunxi: Use devm_clk_get_enabled() helpers
pinctrl: sophgo: cv18xx: fix missed __iomem type identifier
pinctrl: stmfx: Use string_choices API instead of ternary operator
pinctrl: nomadik: Use kmemdup_array instead of kmemdup for multiple allocation
pinctrl: intel: Introduce for_each_intel_gpio_group() helper et al.
pinctrl: intel: Constify intel_get_community() returned object
pinctrl: intel: Implement high impedance support
pinctrl: intel: Add __intel_gpio_get_direction() helper
...
+6002
-1275
-242
Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml
-242
Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Mobileye EyeQ5 pin controller
8
-
9
-
description: >
10
-
The EyeQ5 pin controller handles the two pin banks of the system. It belongs
11
-
to a system-controller block called OLB.
12
-
13
-
Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin
14
-
muxing supports two functions for each pin: first is GPIO, second is
15
-
pin-dependent.
16
-
17
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Pins and groups are bijective.
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-
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maintainers:
20
-
- Grégory Clement <gregory.clement@bootlin.com>
21
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- Théo Lebrun <theo.lebrun@bootlin.com>
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- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
23
-
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$ref: pinctrl.yaml#
25
-
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properties:
27
-
compatible:
28
-
enum:
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- mobileye,eyeq5-pinctrl
30
-
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reg:
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-
maxItems: 1
33
-
34
-
patternProperties:
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-
"-pins?$":
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type: object
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-
description: Pin muxing configuration.
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-
$ref: pinmux-node.yaml#
39
-
additionalProperties: false
40
-
properties:
41
-
pins: true
42
-
function:
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-
enum: [gpio,
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-
# Bank A
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timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
46
-
spi1, refclk0,
47
-
# Bank B
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timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
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-
bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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-
required:
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-
- pins
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-
- function
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-
allOf:
57
-
- if:
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-
properties:
59
-
function:
60
-
const: gpio
61
-
then:
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-
properties:
63
-
pins:
64
-
items: # PA0 - PA28, PB0 - PB22
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-
pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
66
-
- if:
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-
properties:
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-
function:
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-
const: timer0
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-
then:
71
-
properties:
72
-
pins:
73
-
items:
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-
enum: [PA0, PA1]
75
-
- if:
76
-
properties:
77
-
function:
78
-
const: timer1
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-
then:
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-
properties:
81
-
pins:
82
-
items:
83
-
enum: [PA2, PA3]
84
-
- if:
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-
properties:
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-
function:
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-
const: timer2
88
-
then:
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-
properties:
90
-
pins:
91
-
items:
92
-
enum: [PA4, PA5]
93
-
- if:
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-
properties:
95
-
function:
96
-
const: timer5
97
-
then:
98
-
properties:
99
-
pins:
100
-
items:
101
-
enum: [PA6, PA7, PA8, PA9]
102
-
- if:
103
-
properties:
104
-
function:
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-
const: uart0
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-
then:
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-
properties:
108
-
pins:
109
-
items:
110
-
enum: [PA10, PA11]
111
-
- if:
112
-
properties:
113
-
function:
114
-
const: uart1
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-
then:
116
-
properties:
117
-
pins:
118
-
items:
119
-
enum: [PA12, PA13]
120
-
- if:
121
-
properties:
122
-
function:
123
-
const: can0
124
-
then:
125
-
properties:
126
-
pins:
127
-
items:
128
-
enum: [PA14, PA15]
129
-
- if:
130
-
properties:
131
-
function:
132
-
const: can1
133
-
then:
134
-
properties:
135
-
pins:
136
-
items:
137
-
enum: [PA16, PA17]
138
-
- if:
139
-
properties:
140
-
function:
141
-
const: spi0
142
-
then:
143
-
properties:
144
-
pins:
145
-
items:
146
-
enum: [PA18, PA19, PA20, PA21, PA22]
147
-
- if:
148
-
properties:
149
-
function:
150
-
const: spi1
151
-
then:
152
-
properties:
153
-
pins:
154
-
items:
155
-
enum: [PA23, PA24, PA25, PA26, PA27]
156
-
- if:
157
-
properties:
158
-
function:
159
-
const: refclk0
160
-
then:
161
-
properties:
162
-
pins:
163
-
items:
164
-
enum: [PA28]
165
-
- if:
166
-
properties:
167
-
function:
168
-
const: timer3
169
-
then:
170
-
properties:
171
-
pins:
172
-
items:
173
-
enum: [PB0, PB1]
174
-
- if:
175
-
properties:
176
-
function:
177
-
const: timer4
178
-
then:
179
-
properties:
180
-
pins:
181
-
items:
182
-
enum: [PB2, PB3]
183
-
- if:
184
-
properties:
185
-
function:
186
-
const: timer6
187
-
then:
188
-
properties:
189
-
pins:
190
-
items:
191
-
enum: [PB4, PB5, PB6, PB7]
192
-
- if:
193
-
properties:
194
-
function:
195
-
const: uart2
196
-
then:
197
-
properties:
198
-
pins:
199
-
items:
200
-
enum: [PB8, PB9]
201
-
- if:
202
-
properties:
203
-
function:
204
-
const: can2
205
-
then:
206
-
properties:
207
-
pins:
208
-
items:
209
-
enum: [PB10, PB11]
210
-
- if:
211
-
properties:
212
-
function:
213
-
const: spi2
214
-
then:
215
-
properties:
216
-
pins:
217
-
items:
218
-
enum: [PB12, PB13, PB14, PB15, PB16]
219
-
- if:
220
-
properties:
221
-
function:
222
-
const: spi3
223
-
then:
224
-
properties:
225
-
pins:
226
-
items:
227
-
enum: [PB17, PB18, PB19, PB20, PB21]
228
-
- if:
229
-
properties:
230
-
function:
231
-
const: mclk0
232
-
then:
233
-
properties:
234
-
pins:
235
-
items:
236
-
enum: [PB22]
237
-
238
-
required:
239
-
- compatible
240
-
- reg
241
-
242
-
additionalProperties: false
+34
-36
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
+34
-36
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
···
71
71
One or more groups of pins to mux to a certain function
72
72
items:
73
73
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
74
-
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
75
-
smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
76
-
smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
77
-
spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
78
-
spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
79
-
bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
80
-
r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
81
-
fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
82
-
fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
83
-
pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
84
-
ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
85
-
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
86
-
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
87
-
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
88
-
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
89
-
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
90
-
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
91
-
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
92
-
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
93
-
bu4b, bu5, bu5b, bu6, gpo187 ]
74
+
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
75
+
smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
76
+
smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
77
+
spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
78
+
smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
79
+
bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
80
+
fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
81
+
fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
82
+
fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
83
+
r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
84
+
i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
85
+
smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
86
+
pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
87
+
mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
88
+
smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
89
+
spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
90
+
smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
91
+
spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
92
+
hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]
94
93
95
94
function:
96
95
description:
97
96
The function that a group of pins is muxed to
98
-
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
99
-
smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
100
-
smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
101
-
smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
102
-
spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
103
-
spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
104
-
bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
105
-
r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
106
-
fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
97
+
enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
98
+
smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
99
+
smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
100
+
smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
101
+
spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
102
+
uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
103
+
r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
104
+
fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
107
105
fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
108
106
pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
109
107
ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
110
108
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
111
109
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
112
-
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
113
-
scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
114
-
smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
115
-
spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
116
-
wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
117
-
hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
118
-
bu4b, bu5, bu5b, bu6, gpo187 ]
110
+
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
111
+
smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
112
+
faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
113
+
smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
114
+
smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
115
+
hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
116
+
bu6, gpo187 ]
119
117
120
118
dependencies:
121
119
groups: [ function ]
+3
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+3
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
···
96
96
type: boolean
97
97
description: disable schmitt-trigger mode
98
98
99
+
input-schmitt-microvolt:
100
+
description: threshold strength for schmitt-trigger
101
+
99
102
input-debounce:
100
103
$ref: /schemas/types.yaml#/definitions/uint32-array
101
104
description: Takes the debounce time in usec as argument or 0 to disable
-95
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
-95
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
···
1
-
Qualcomm APQ8064 TLMM block
2
-
3
-
Required properties:
4
-
- compatible: "qcom,apq8064-pinctrl"
5
-
- reg: Should be the base address and length of the TLMM block.
6
-
- interrupts: Should be the parent IRQ of the TLMM block.
7
-
- interrupt-controller: Marks the device node as an interrupt controller.
8
-
- #interrupt-cells: Should be two.
9
-
- gpio-controller: Marks the device node as a GPIO controller.
10
-
- #gpio-cells : Should be two.
11
-
The first cell is the gpio pin number and the
12
-
second cell is used for optional parameters.
13
-
- gpio-ranges: see ../gpio/gpio.txt
14
-
15
-
Optional properties:
16
-
17
-
- gpio-reserved-ranges: see ../gpio/gpio.txt
18
-
19
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
20
-
a general description of GPIO and interrupt bindings.
21
-
22
-
Please refer to pinctrl-bindings.txt in this directory for details of the
23
-
common pinctrl bindings used by client devices, including the meaning of the
24
-
phrase "pin configuration node".
25
-
26
-
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
27
-
subnodes. Each of these subnodes represents some desired configuration for a
28
-
pin, a group, or a list of pins or groups. This configuration can include the
29
-
mux function to select on those pin(s)/group(s), and various pin configuration
30
-
parameters, such as pull-up, drive strength, etc.
31
-
32
-
The name of each subnode is not important; all subnodes should be enumerated
33
-
and processed purely based on their content.
34
-
35
-
Each subnode only affects those parameters that are explicitly listed. In
36
-
other words, a subnode that lists a mux function but no pin configuration
37
-
parameters implies no information about any pin configuration parameters.
38
-
Similarly, a pin subnode that describes a pullup parameter implies no
39
-
information about e.g. the mux function.
40
-
41
-
42
-
The following generic properties as defined in pinctrl-bindings.txt are valid
43
-
to specify in a pin configuration subnode:
44
-
45
-
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
46
-
output-low, output-high.
47
-
48
-
Non-empty subnodes must specify the 'pins' property.
49
-
50
-
Valid values for pins are:
51
-
gpio0-gpio89
52
-
53
-
Valid values for function are:
54
-
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
55
-
gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
56
-
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
57
-
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
58
-
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
59
-
riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
60
-
61
-
Example:
62
-
63
-
msmgpio: pinctrl@800000 {
64
-
compatible = "qcom,apq8064-pinctrl";
65
-
reg = <0x800000 0x4000>;
66
-
67
-
gpio-controller;
68
-
#gpio-cells = <2>;
69
-
interrupt-controller;
70
-
#interrupt-cells = <2>;
71
-
interrupts = <0 16 0x4>;
72
-
73
-
pinctrl-names = "default";
74
-
pinctrl-0 = <&gsbi5_uart_default>;
75
-
gpio-ranges = <&msmgpio 0 0 90>;
76
-
77
-
gsbi5_uart_default: gsbi5_uart_default {
78
-
mux {
79
-
pins = "gpio51", "gpio52";
80
-
function = "gsbi5";
81
-
};
82
-
83
-
tx {
84
-
pins = "gpio51";
85
-
drive-strength = <4>;
86
-
bias-disable;
87
-
};
88
-
89
-
rx {
90
-
pins = "gpio52";
91
-
drive-strength = <2>;
92
-
bias-pull-up;
93
-
};
94
-
};
95
-
};
+110
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml
+110
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. APQ8064 TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
description: |
13
+
Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,apq8064-pinctrl
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges: true
29
+
30
+
patternProperties:
31
+
"-state$":
32
+
oneOf:
33
+
- $ref: "#/$defs/qcom-apq8064-tlmm-state"
34
+
- patternProperties:
35
+
"-pins$":
36
+
$ref: "#/$defs/qcom-apq8064-tlmm-state"
37
+
additionalProperties: false
38
+
39
+
$defs:
40
+
qcom-apq8064-tlmm-state:
41
+
type: object
42
+
description:
43
+
Pinctrl node's client devices use subnodes for desired pin configuration.
44
+
Client device subnodes use below standard properties.
45
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
46
+
unevaluatedProperties: false
47
+
48
+
properties:
49
+
pins:
50
+
description:
51
+
List of gpio pins affected by the properties specified in this
52
+
subnode.
53
+
items:
54
+
oneOf:
55
+
- pattern: "^gpio([0-9]|[1-8][0-9])$"
56
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, sdc3_data ]
57
+
minItems: 1
58
+
maxItems: 36
59
+
60
+
function:
61
+
description:
62
+
Specify the alternative function to be configured for the specified
63
+
pins.
64
+
enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a,
65
+
gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b,
66
+
gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c,
67
+
gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3,
68
+
gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3,
69
+
gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3,
70
+
gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan,
71
+
sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
72
+
ps_hold ]
73
+
74
+
required:
75
+
- pins
76
+
77
+
required:
78
+
- compatible
79
+
- reg
80
+
81
+
unevaluatedProperties: false
82
+
83
+
examples:
84
+
- |
85
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
86
+
tlmm: pinctrl@800000 {
87
+
compatible = "qcom,apq8064-pinctrl";
88
+
reg = <0x800000 0x4000>;
89
+
90
+
gpio-controller;
91
+
#gpio-cells = <2>;
92
+
gpio-ranges = <&tlmm 0 0 90>;
93
+
interrupt-controller;
94
+
#interrupt-cells = <2>;
95
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
96
+
97
+
uart-state {
98
+
rx-pins {
99
+
pins = "gpio52";
100
+
function = "gsbi5";
101
+
bias-pull-up;
102
+
};
103
+
104
+
tx-pins {
105
+
pins = "gpio51";
106
+
function = "gsbi5";
107
+
bias-disable;
108
+
};
109
+
};
110
+
};
-188
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
-188
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
···
1
-
Qualcomm APQ8084 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8960 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,apq8084-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode. Valid pins are:
85
-
gpio0-gpio146,
86
-
sdc1_clk,
87
-
sdc1_cmd,
88
-
sdc1_data
89
-
sdc2_clk,
90
-
sdc2_cmd,
91
-
sdc2_data
92
-
93
-
- function:
94
-
Usage: required
95
-
Value type: <string>
96
-
Definition: Specify the alternative function to be configured for the
97
-
specified pins. Functions are only valid for gpio pins.
98
-
Valid values are:
99
-
adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
100
-
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
101
-
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
102
-
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
103
-
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
104
-
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
105
-
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
106
-
blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
107
-
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
108
-
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
109
-
blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
110
-
cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
111
-
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
112
-
edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
113
-
gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
114
-
hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
115
-
ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
116
-
pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
117
-
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
118
-
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
119
-
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
120
-
tsif2, uim, uim_batt_alarm
121
-
122
-
- bias-disable:
123
-
Usage: optional
124
-
Value type: <none>
125
-
Definition: The specified pins should be configured as no pull.
126
-
127
-
- bias-pull-down:
128
-
Usage: optional
129
-
Value type: <none>
130
-
Definition: The specified pins should be configured as pull down.
131
-
132
-
- bias-pull-up:
133
-
Usage: optional
134
-
Value type: <none>
135
-
Definition: The specified pins should be configured as pull up.
136
-
137
-
- output-high:
138
-
Usage: optional
139
-
Value type: <none>
140
-
Definition: The specified pins are configured in output mode, driven
141
-
high.
142
-
Not valid for sdc pins.
143
-
144
-
- output-low:
145
-
Usage: optional
146
-
Value type: <none>
147
-
Definition: The specified pins are configured in output mode, driven
148
-
low.
149
-
Not valid for sdc pins.
150
-
151
-
- drive-strength:
152
-
Usage: optional
153
-
Value type: <u32>
154
-
Definition: Selects the drive strength for the specified pins, in mA.
155
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
156
-
157
-
Example:
158
-
159
-
tlmm: pinctrl@fd510000 {
160
-
compatible = "qcom,apq8084-pinctrl";
161
-
reg = <0xfd510000 0x4000>;
162
-
163
-
gpio-controller;
164
-
#gpio-cells = <2>;
165
-
gpio-ranges = <&tlmm 0 0 147>;
166
-
interrupt-controller;
167
-
#interrupt-cells = <2>;
168
-
interrupts = <0 208 0>;
169
-
170
-
uart2: uart2-default {
171
-
mux {
172
-
pins = "gpio4", "gpio5";
173
-
function = "blsp_uart2";
174
-
};
175
-
176
-
tx {
177
-
pins = "gpio4";
178
-
drive-strength = <4>;
179
-
bias-disable;
180
-
};
181
-
182
-
rx {
183
-
pins = "gpio5";
184
-
drive-strength = <2>;
185
-
bias-pull-up;
186
-
};
187
-
};
188
-
};
+129
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml
+129
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. APQ8084 TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
description: |
13
+
Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,apq8084-pinctrl
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges: true
29
+
30
+
patternProperties:
31
+
"-state$":
32
+
oneOf:
33
+
- $ref: "#/$defs/qcom-apq8084-tlmm-state"
34
+
- patternProperties:
35
+
"-pins$":
36
+
$ref: "#/$defs/qcom-apq8084-tlmm-state"
37
+
additionalProperties: false
38
+
39
+
$defs:
40
+
qcom-apq8084-tlmm-state:
41
+
type: object
42
+
description:
43
+
Pinctrl node's client devices use subnodes for desired pin configuration.
44
+
Client device subnodes use below standard properties.
45
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
46
+
unevaluatedProperties: false
47
+
48
+
properties:
49
+
pins:
50
+
description:
51
+
List of gpio pins affected by the properties specified in this
52
+
subnode.
53
+
items:
54
+
oneOf:
55
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$"
56
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
57
+
sdc2_data ]
58
+
minItems: 1
59
+
maxItems: 36
60
+
61
+
function:
62
+
description:
63
+
Specify the alternative function to be configured for the specified
64
+
pins.
65
+
enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
66
+
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
67
+
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
68
+
blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
69
+
blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
70
+
blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
71
+
blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
72
+
blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
73
+
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
74
+
blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6,
75
+
blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10,
76
+
blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2,
77
+
blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7,
78
+
blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
79
+
blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
80
+
cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
81
+
cci_timer0, cci_timer1, cci_timer2, cci_timer3,
82
+
cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3,
83
+
gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2,
84
+
gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest,
85
+
hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update,
86
+
mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1,
87
+
pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
88
+
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
89
+
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
90
+
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s,
91
+
tsif1, tsif2, uim, uim_batt_alarm ]
92
+
93
+
required:
94
+
- pins
95
+
96
+
required:
97
+
- compatible
98
+
- reg
99
+
100
+
unevaluatedProperties: false
101
+
102
+
examples:
103
+
- |
104
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
105
+
tlmm: pinctrl@fd510000 {
106
+
compatible = "qcom,apq8084-pinctrl";
107
+
reg = <0xfd510000 0x4000>;
108
+
109
+
gpio-controller;
110
+
#gpio-cells = <2>;
111
+
gpio-ranges = <&tlmm 0 0 147>;
112
+
interrupt-controller;
113
+
#interrupt-cells = <2>;
114
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
115
+
116
+
uart-state {
117
+
rx-pins {
118
+
pins = "gpio5";
119
+
function = "blsp_uart2";
120
+
bias-pull-up;
121
+
};
122
+
123
+
tx-pins {
124
+
pins = "gpio4";
125
+
function = "blsp_uart2";
126
+
bias-disable;
127
+
};
128
+
};
129
+
};
-85
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
-85
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
···
1
-
Qualcomm Atheros IPQ4019 TLMM block
2
-
3
-
This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
4
-
platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
5
-
6
-
Required properties:
7
-
- compatible: "qcom,ipq4019-pinctrl"
8
-
- reg: Should be the base address and length of the TLMM block.
9
-
- interrupts: Should be the parent IRQ of the TLMM block.
10
-
- interrupt-controller: Marks the device node as an interrupt controller.
11
-
- #interrupt-cells: Should be two.
12
-
- gpio-controller: Marks the device node as a GPIO controller.
13
-
- #gpio-cells : Should be two.
14
-
The first cell is the gpio pin number and the
15
-
second cell is used for optional parameters.
16
-
- gpio-ranges: see ../gpio/gpio.txt
17
-
18
-
Optional properties:
19
-
20
-
- gpio-reserved-ranges: see ../gpio/gpio.txt
21
-
22
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
23
-
a general description of GPIO and interrupt bindings.
24
-
25
-
Please refer to pinctrl-bindings.txt in this directory for details of the
26
-
common pinctrl bindings used by client devices, including the meaning of the
27
-
phrase "pin configuration node".
28
-
29
-
The pin configuration nodes act as a container for an arbitrary number of
30
-
subnodes. Each of these subnodes represents some desired configuration for a
31
-
pin, a group, or a list of pins or groups. This configuration can include the
32
-
mux function to select on those pin(s)/group(s), and various pin configuration
33
-
parameters, such as pull-up, drive strength, etc.
34
-
35
-
The name of each subnode is not important; all subnodes should be enumerated
36
-
and processed purely based on their content.
37
-
38
-
Each subnode only affects those parameters that are explicitly listed. In
39
-
other words, a subnode that lists a mux function but no pin configuration
40
-
parameters implies no information about any pin configuration parameters.
41
-
Similarly, a pin subnode that describes a pullup parameter implies no
42
-
information about e.g. the mux function.
43
-
44
-
45
-
The following generic properties as defined in pinctrl-bindings.txt are valid
46
-
to specify in a pin configuration subnode:
47
-
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
48
-
drive-strength.
49
-
50
-
Non-empty subnodes must specify the 'pins' property.
51
-
Note that not all properties are valid for all pins.
52
-
53
-
54
-
Valid values for qcom,pins are:
55
-
gpio0-gpio99
56
-
Supports mux, bias and drive-strength
57
-
58
-
Valid values for qcom,function are:
59
-
aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
60
-
blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
61
-
jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
62
-
mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
63
-
smart2, smart3, tm, wifi0, wifi1
64
-
65
-
Example:
66
-
67
-
tlmm: pinctrl@1000000 {
68
-
compatible = "qcom,ipq4019-pinctrl";
69
-
reg = <0x1000000 0x300000>;
70
-
71
-
gpio-controller;
72
-
#gpio-cells = <2>;
73
-
gpio-ranges = <&tlmm 0 0 100>;
74
-
interrupt-controller;
75
-
#interrupt-cells = <2>;
76
-
interrupts = <0 208 0>;
77
-
78
-
serial_pins: serial_pinmux {
79
-
mux {
80
-
pins = "gpio60", "gpio61";
81
-
function = "blsp_uart0";
82
-
bias-disable;
83
-
};
84
-
};
85
-
};
+103
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml
+103
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. IPQ4019 TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
description: |
13
+
Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,ipq4019-pinctrl
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges: true
29
+
30
+
patternProperties:
31
+
"-state$":
32
+
oneOf:
33
+
- $ref: "#/$defs/qcom-ipq4019-tlmm-state"
34
+
- patternProperties:
35
+
"-pins$":
36
+
$ref: "#/$defs/qcom-ipq4019-tlmm-state"
37
+
additionalProperties: false
38
+
39
+
"-hog(-[0-9]+)?$":
40
+
type: object
41
+
required:
42
+
- gpio-hog
43
+
44
+
$defs:
45
+
qcom-ipq4019-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
pattern: "^gpio([0-9]|[1-9][0-9])$"
60
+
minItems: 1
61
+
maxItems: 36
62
+
63
+
function:
64
+
description:
65
+
Specify the alternative function to be configured for the specified
66
+
pins.
67
+
enum: [ aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0,
68
+
blsp_spi1, blsp_uart0, blsp_uart1, chip_rst, gpio,
69
+
i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
70
+
jtag, led0, led1, led2, led3, led4, led5, led6, led7,
71
+
led8, led9, led10, led11, mdc, mdio, pcie, pmu,
72
+
prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
73
+
smart2, smart3, tm, wifi0, wifi1 ]
74
+
75
+
required:
76
+
- pins
77
+
78
+
required:
79
+
- compatible
80
+
- reg
81
+
82
+
unevaluatedProperties: false
83
+
84
+
examples:
85
+
- |
86
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87
+
tlmm: pinctrl@1000000 {
88
+
compatible = "qcom,ipq4019-pinctrl";
89
+
reg = <0x01000000 0x300000>;
90
+
91
+
gpio-controller;
92
+
#gpio-cells = <2>;
93
+
gpio-ranges = <&tlmm 0 0 100>;
94
+
interrupt-controller;
95
+
#interrupt-cells = <2>;
96
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
97
+
98
+
uart-state {
99
+
pins = "gpio16", "gpio17";
100
+
function = "blsp_uart0";
101
+
bias-disable;
102
+
};
103
+
};
-101
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
-101
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
···
1
-
Qualcomm IPQ8064 TLMM block
2
-
3
-
Required properties:
4
-
- compatible: "qcom,ipq8064-pinctrl"
5
-
- reg: Should be the base address and length of the TLMM block.
6
-
- interrupts: Should be the parent IRQ of the TLMM block.
7
-
- interrupt-controller: Marks the device node as an interrupt controller.
8
-
- #interrupt-cells: Should be two.
9
-
- gpio-controller: Marks the device node as a GPIO controller.
10
-
- #gpio-cells : Should be two.
11
-
The first cell is the gpio pin number and the
12
-
second cell is used for optional parameters.
13
-
- gpio-ranges: see ../gpio/gpio.txt
14
-
15
-
Optional properties:
16
-
17
-
- gpio-reserved-ranges: see ../gpio/gpio.txt
18
-
19
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
20
-
a general description of GPIO and interrupt bindings.
21
-
22
-
Please refer to pinctrl-bindings.txt in this directory for details of the
23
-
common pinctrl bindings used by client devices, including the meaning of the
24
-
phrase "pin configuration node".
25
-
26
-
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
27
-
subnodes. Each of these subnodes represents some desired configuration for a
28
-
pin, a group, or a list of pins or groups. This configuration can include the
29
-
mux function to select on those pin(s)/group(s), and various pin configuration
30
-
parameters, such as pull-up, drive strength, etc.
31
-
32
-
The name of each subnode is not important; all subnodes should be enumerated
33
-
and processed purely based on their content.
34
-
35
-
Each subnode only affects those parameters that are explicitly listed. In
36
-
other words, a subnode that lists a mux function but no pin configuration
37
-
parameters implies no information about any pin configuration parameters.
38
-
Similarly, a pin subnode that describes a pullup parameter implies no
39
-
information about e.g. the mux function.
40
-
41
-
42
-
The following generic properties as defined in pinctrl-bindings.txt are valid
43
-
to specify in a pin configuration subnode:
44
-
45
-
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
46
-
output-low, output-high.
47
-
48
-
Non-empty subnodes must specify the 'pins' property.
49
-
50
-
Valid values for qcom,pins are:
51
-
gpio0-gpio68
52
-
Supports mux, bias, and drive-strength
53
-
54
-
sdc3_clk, sdc3_cmd, sdc3_data
55
-
Supports bias and drive-strength
56
-
57
-
58
-
Valid values for function are:
59
-
mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
60
-
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
61
-
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
62
-
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
63
-
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
64
-
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
65
-
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
66
-
67
-
Example:
68
-
69
-
pinmux: pinctrl@800000 {
70
-
compatible = "qcom,ipq8064-pinctrl";
71
-
reg = <0x800000 0x4000>;
72
-
73
-
gpio-controller;
74
-
#gpio-cells = <2>;
75
-
gpio-ranges = <&pinmux 0 0 69>;
76
-
interrupt-controller;
77
-
#interrupt-cells = <2>;
78
-
interrupts = <0 32 0x4>;
79
-
80
-
pinctrl-names = "default";
81
-
pinctrl-0 = <&gsbi5_uart_default>;
82
-
83
-
gsbi5_uart_default: gsbi5_uart_default {
84
-
mux {
85
-
pins = "gpio18", "gpio19";
86
-
function = "gsbi5";
87
-
};
88
-
89
-
tx {
90
-
pins = "gpio18";
91
-
drive-strength = <4>;
92
-
bias-disable;
93
-
};
94
-
95
-
rx {
96
-
pins = "gpio19";
97
-
drive-strength = <2>;
98
-
bias-pull-up;
99
-
};
100
-
};
101
-
};
+108
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml
+108
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. IPQ8064 TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
+
12
+
description: |
13
+
Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,ipq8064-pinctrl
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges: true
29
+
30
+
patternProperties:
31
+
"-state$":
32
+
oneOf:
33
+
- $ref: "#/$defs/qcom-ipq8064-tlmm-state"
34
+
- patternProperties:
35
+
"-pins$":
36
+
$ref: "#/$defs/qcom-ipq8064-tlmm-state"
37
+
additionalProperties: false
38
+
39
+
$defs:
40
+
qcom-ipq8064-tlmm-state:
41
+
type: object
42
+
description:
43
+
Pinctrl node's client devices use subnodes for desired pin configuration.
44
+
Client device subnodes use below standard properties.
45
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
46
+
unevaluatedProperties: false
47
+
48
+
properties:
49
+
pins:
50
+
description:
51
+
List of gpio pins affected by the properties specified in this
52
+
subnode.
53
+
items:
54
+
oneOf:
55
+
- pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$"
56
+
- enum: [ sdc3_clk, sdc3_cmd, sdc3_data ]
57
+
minItems: 1
58
+
maxItems: 36
59
+
60
+
function:
61
+
description:
62
+
Specify the alternative function to be configured for the specified
63
+
pins.
64
+
enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
65
+
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
66
+
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
67
+
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
68
+
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
69
+
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
70
+
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ]
71
+
72
+
required:
73
+
- pins
74
+
75
+
required:
76
+
- compatible
77
+
- reg
78
+
79
+
unevaluatedProperties: false
80
+
81
+
examples:
82
+
- |
83
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
84
+
tlmm: pinctrl@800000 {
85
+
compatible = "qcom,ipq8064-pinctrl";
86
+
reg = <0x00800000 0x4000>;
87
+
88
+
gpio-controller;
89
+
#gpio-cells = <2>;
90
+
gpio-ranges = <&tlmm 0 0 69>;
91
+
interrupt-controller;
92
+
#interrupt-cells = <2>;
93
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
94
+
95
+
uart-state {
96
+
rx-pins {
97
+
pins = "gpio19";
98
+
function = "gsbi5";
99
+
bias-pull-up;
100
+
};
101
+
102
+
tx-pins {
103
+
pins = "gpio18";
104
+
function = "gsbi5";
105
+
bias-disable;
106
+
};
107
+
};
108
+
};
+1
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+1
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+1
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
+1
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
+1
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
+1
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
+1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+122
Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml
+122
Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Sophgo CV1800 Pin Controller
8
+
9
+
maintainers:
10
+
- Inochi Amaoto <inochiama@outlook.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- sophgo,cv1800b-pinctrl
16
+
- sophgo,cv1812h-pinctrl
17
+
- sophgo,sg2000-pinctrl
18
+
- sophgo,sg2002-pinctrl
19
+
20
+
reg:
21
+
items:
22
+
- description: pinctrl for system domain
23
+
- description: pinctrl for rtc domain
24
+
25
+
reg-names:
26
+
items:
27
+
- const: sys
28
+
- const: rtc
29
+
30
+
resets:
31
+
maxItems: 1
32
+
33
+
patternProperties:
34
+
'-cfg$':
35
+
type: object
36
+
description:
37
+
A pinctrl node should contain at least one subnode representing the
38
+
pinctrl groups available on the machine.
39
+
40
+
additionalProperties: false
41
+
42
+
patternProperties:
43
+
'-pins$':
44
+
type: object
45
+
description: |
46
+
Each subnode will list the pins it needs, and how they should
47
+
be configured, with regard to muxer configuration, bias, input
48
+
enable/disable, input schmitt trigger, slew-rate, drive strength
49
+
and bus hold state. In addition, all pins in the same subnode
50
+
should have the same power domain. For configuration detail,
51
+
refer to https://github.com/sophgo/sophgo-doc/.
52
+
53
+
allOf:
54
+
- $ref: pincfg-node.yaml#
55
+
- $ref: pinmux-node.yaml#
56
+
57
+
properties:
58
+
pinmux:
59
+
description: |
60
+
The list of GPIOs and their mux settings that properties in the
61
+
node apply to. This should be set using the GPIOMUX or GPIOMUX2
62
+
macro.
63
+
64
+
bias-pull-up:
65
+
type: boolean
66
+
67
+
bias-pull-down:
68
+
type: boolean
69
+
70
+
drive-strength-microamp:
71
+
description: typical current when output high level.
72
+
73
+
input-schmitt-microvolt:
74
+
description: typical threshold for schmitt trigger.
75
+
76
+
power-source:
77
+
description: power supplies at X mV.
78
+
enum: [ 1800, 3300 ]
79
+
80
+
slew-rate:
81
+
description: slew rate for output buffer (0 is fast, 1 is slow)
82
+
enum: [ 0, 1 ]
83
+
84
+
bias-bus-hold: true
85
+
86
+
required:
87
+
- pinmux
88
+
- power-source
89
+
90
+
additionalProperties: false
91
+
92
+
required:
93
+
- compatible
94
+
- reg
95
+
- reg-names
96
+
97
+
additionalProperties: false
98
+
99
+
examples:
100
+
- |
101
+
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
102
+
103
+
pinctrl@3001000 {
104
+
compatible = "sophgo,cv1800b-pinctrl";
105
+
reg = <0x03001000 0x1000>,
106
+
<0x05027000 0x1000>;
107
+
reg-names = "sys", "rtc";
108
+
109
+
uart0_cfg: uart0-cfg {
110
+
uart0-pins {
111
+
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
112
+
<PINMUX(PIN_UART0_RX, 0)>;
113
+
bias-pull-up;
114
+
drive-strength-microamp = <10800>;
115
+
input-schmitt-microvolt = <0>;
116
+
power-source = <3300>;
117
+
slew-rate = <0>;
118
+
};
119
+
};
120
+
};
121
+
122
+
...
+16
drivers/pinctrl/Kconfig
+16
drivers/pinctrl/Kconfig
···
213
213
desired pin functions, configure GPIO attributes for LGM SoC pins.
214
214
Pin muxing and pin config settings are retrieved from device tree.
215
215
216
+
config PINCTRL_EYEQ5
217
+
bool "Mobileye EyeQ5 pinctrl driver"
218
+
depends on OF
219
+
depends on MACH_EYEQ5 || COMPILE_TEST
220
+
select PINMUX
221
+
select GENERIC_PINCONF
222
+
select AUXILIARY_BUS
223
+
default MACH_EYEQ5
224
+
help
225
+
Pin controller driver for the Mobileye EyeQ5 platform. It does both
226
+
pin config & pin muxing. It does not handle GPIO.
227
+
228
+
Pin muxing supports two functions for each pin: first is GPIO, second
229
+
is pin-dependent. Pin config is about bias & drive strength.
230
+
216
231
config PINCTRL_GEMINI
217
232
bool
218
233
depends on ARCH_GEMINI
···
598
583
source "drivers/pinctrl/realtek/Kconfig"
599
584
source "drivers/pinctrl/renesas/Kconfig"
600
585
source "drivers/pinctrl/samsung/Kconfig"
586
+
source "drivers/pinctrl/sophgo/Kconfig"
601
587
source "drivers/pinctrl/spear/Kconfig"
602
588
source "drivers/pinctrl/sprd/Kconfig"
603
589
source "drivers/pinctrl/starfive/Kconfig"
+2
drivers/pinctrl/Makefile
+2
drivers/pinctrl/Makefile
···
23
23
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
24
24
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
25
25
obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
26
+
obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o
26
27
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
27
28
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
28
29
obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o
···
74
73
obj-$(CONFIG_ARCH_REALTEK) += realtek/
75
74
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
76
75
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
76
+
obj-y += sophgo/
77
77
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
78
78
obj-y += sprd/
79
79
obj-$(CONFIG_SOC_STARFIVE) += starfive/
+1
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+1
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+3
-6
drivers/pinctrl/cirrus/pinctrl-madera-core.c
+3
-6
drivers/pinctrl/cirrus/pinctrl-madera-core.c
···
1063
1063
if (pdata->gpio_configs) {
1064
1064
ret = pinctrl_register_mappings(pdata->gpio_configs,
1065
1065
pdata->n_gpio_configs);
1066
-
if (ret) {
1067
-
dev_err(priv->dev,
1068
-
"Failed to register pdata mappings (%d)\n",
1069
-
ret);
1070
-
return ret;
1071
-
}
1066
+
if (ret)
1067
+
return dev_err_probe(priv->dev, ret,
1068
+
"Failed to register pdata mappings\n");
1072
1069
}
1073
1070
1074
1071
ret = pinctrl_enable(priv->pctl);
+1
-1
drivers/pinctrl/core.c
+1
-1
drivers/pinctrl/core.c
···
1971
1971
static void pinctrl_init_debugfs(void)
1972
1972
{
1973
1973
debugfs_root = debugfs_create_dir("pinctrl", NULL);
1974
-
if (IS_ERR(debugfs_root) || !debugfs_root) {
1974
+
if (IS_ERR(debugfs_root)) {
1975
1975
pr_warn("failed to create debugfs directory\n");
1976
1976
debugfs_root = NULL;
1977
1977
return;
+1
-1
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
+1
-1
drivers/pinctrl/freescale/pinctrl-imx-scmi.c
···
130
130
cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG, input_val);
131
131
}
132
132
133
-
configs = kmemdup(cfg, ncfg * sizeof(unsigned long), GFP_KERNEL);
133
+
configs = kmemdup_array(cfg, ncfg, sizeof(unsigned long), GFP_KERNEL);
134
134
135
135
new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
136
136
new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_id);
+3
-4
drivers/pinctrl/freescale/pinctrl-imx.c
+3
-4
drivers/pinctrl/freescale/pinctrl-imx.c
···
804
804
}
805
805
EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
806
806
807
-
static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
807
+
static int imx_pinctrl_suspend(struct device *dev)
808
808
{
809
809
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
810
810
811
811
return pinctrl_force_sleep(ipctl->pctl);
812
812
}
813
813
814
-
static int __maybe_unused imx_pinctrl_resume(struct device *dev)
814
+
static int imx_pinctrl_resume(struct device *dev)
815
815
{
816
816
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
817
817
···
819
819
}
820
820
821
821
const struct dev_pm_ops imx_pinctrl_pm_ops = {
822
-
SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
823
-
imx_pinctrl_resume)
822
+
LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, imx_pinctrl_resume)
824
823
};
825
824
EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
826
825
+1
-1
drivers/pinctrl/freescale/pinctrl-imx8mq.c
+1
-1
drivers/pinctrl/freescale/pinctrl-imx8mq.c
+3
-4
drivers/pinctrl/intel/pinctrl-baytrail.c
+3
-4
drivers/pinctrl/intel/pinctrl-baytrail.c
···
560
560
static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
561
561
int reg)
562
562
{
563
-
struct intel_community *comm = intel_get_community(vg, offset);
563
+
const struct intel_community *comm;
564
564
u32 reg_offset;
565
565
566
+
comm = intel_get_community(vg, offset);
566
567
if (!comm)
567
568
return NULL;
568
569
···
1542
1541
}
1543
1542
1544
1543
ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1545
-
if (ret) {
1544
+
if (ret)
1546
1545
dev_err(vg->dev, "failed adding byt-gpio chip\n");
1547
-
return ret;
1548
-
}
1549
1546
1550
1547
return ret;
1551
1548
}
+184
-142
drivers/pinctrl/intel/pinctrl-intel.c
+184
-142
drivers/pinctrl/intel/pinctrl-intel.c
···
70
70
#define PADCFG0_PMODE_SHIFT 10
71
71
#define PADCFG0_PMODE_MASK GENMASK(13, 10)
72
72
#define PADCFG0_PMODE_GPIO 0
73
+
#define PADCFG0_GPIODIS_SHIFT 8
74
+
#define PADCFG0_GPIODIS_MASK GENMASK(9, 8)
75
+
#define PADCFG0_GPIODIS_NONE 0
76
+
#define PADCFG0_GPIODIS_OUTPUT 1
77
+
#define PADCFG0_GPIODIS_INPUT 2
78
+
#define PADCFG0_GPIODIS_FULL 3
73
79
#define PADCFG0_GPIORXDIS BIT(9)
74
80
#define PADCFG0_GPIOTXDIS BIT(8)
75
81
#define PADCFG0_GPIORXSTATE BIT(1)
···
114
108
#define pin_to_padno(c, p) ((p) - (c)->pin_base)
115
109
#define padgroup_offset(g, p) ((p) - (g)->base)
116
110
117
-
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin)
118
-
{
119
-
struct intel_community *community;
120
-
int i;
111
+
#define for_each_intel_pin_community(pctrl, community) \
112
+
for (unsigned int __ci = 0; \
113
+
__ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \
114
+
__ci++) \
121
115
122
-
for (i = 0; i < pctrl->ncommunities; i++) {
123
-
community = &pctrl->communities[i];
116
+
#define for_each_intel_community_pad_group(community, grp) \
117
+
for (unsigned int __gi = 0; \
118
+
__gi < community->ngpps && (grp = &community->gpps[__gi]); \
119
+
__gi++) \
120
+
121
+
#define for_each_intel_pad_group(pctrl, community, grp) \
122
+
for_each_intel_pin_community(pctrl, community) \
123
+
for_each_intel_community_pad_group(community, grp)
124
+
125
+
#define for_each_intel_gpio_group(pctrl, community, grp) \
126
+
for_each_intel_pad_group(pctrl, community, grp) \
127
+
if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
128
+
129
+
const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
130
+
unsigned int pin)
131
+
{
132
+
const struct intel_community *community;
133
+
134
+
for_each_intel_pin_community(pctrl, community) {
124
135
if (pin >= community->pin_base &&
125
136
pin < community->pin_base + community->npins)
126
137
return community;
···
152
129
intel_community_get_padgroup(const struct intel_community *community,
153
130
unsigned int pin)
154
131
{
155
-
int i;
132
+
const struct intel_padgroup *padgrp;
156
133
157
-
for (i = 0; i < community->ngpps; i++) {
158
-
const struct intel_padgroup *padgrp = &community->gpps[i];
159
-
134
+
for_each_intel_community_pad_group(community, padgrp) {
160
135
if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
161
136
return padgrp;
162
137
}
···
182
161
return community->pad_regs + reg + padno * nregs * 4;
183
162
}
184
163
185
-
static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
164
+
static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin)
186
165
{
187
166
const struct intel_community *community;
188
167
const struct intel_padgroup *padgrp;
···
207
186
return !(readl(padown) & PADOWN_MASK(gpp_offset));
208
187
}
209
188
210
-
static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
189
+
static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin)
211
190
{
212
191
const struct intel_community *community;
213
192
const struct intel_padgroup *padgrp;
···
233
212
234
213
/**
235
214
* enum - Locking variants of the pad configuration
236
-
*
237
215
* @PAD_UNLOCKED: pad is fully controlled by the configuration registers
238
216
* @PAD_LOCKED: pad configuration registers, except TX state, are locked
239
217
* @PAD_LOCKED_TX: pad configuration TX state is locked
···
249
229
PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
250
230
};
251
231
252
-
static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
232
+
static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin)
253
233
{
254
-
struct intel_community *community;
234
+
const struct intel_community *community;
255
235
const struct intel_padgroup *padgrp;
256
236
unsigned int offset, gpp_offset;
257
237
u32 value;
···
287
267
return ret;
288
268
}
289
269
290
-
static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
270
+
static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin)
291
271
{
292
272
return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
293
273
}
294
274
295
-
static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
275
+
static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin)
296
276
{
297
277
return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
298
278
}
299
279
300
280
int intel_get_groups_count(struct pinctrl_dev *pctldev)
301
281
{
302
-
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
282
+
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
303
283
304
284
return pctrl->soc->ngroups;
305
285
}
···
307
287
308
288
const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
309
289
{
310
-
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
290
+
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
311
291
312
292
return pctrl->soc->groups[group].grp.name;
313
293
}
···
316
296
int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
317
297
const unsigned int **pins, unsigned int *npins)
318
298
{
319
-
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
299
+
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
320
300
321
301
*pins = pctrl->soc->groups[group].grp.pins;
322
302
*npins = pctrl->soc->groups[group].grp.npins;
···
384
364
385
365
int intel_get_functions_count(struct pinctrl_dev *pctldev)
386
366
{
387
-
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
367
+
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
388
368
389
369
return pctrl->soc->nfunctions;
390
370
}
···
392
372
393
373
const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
394
374
{
395
-
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
375
+
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
396
376
397
377
return pctrl->soc->functions[function].func.name;
398
378
}
···
401
381
int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
402
382
const char * const **groups, unsigned int * const ngroups)
403
383
{
404
-
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
384
+
const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
405
385
406
386
*groups = pctrl->soc->functions[function].func.groups;
407
387
*ngroups = pctrl->soc->functions[function].func.ngroups;
···
449
429
return 0;
450
430
}
451
431
452
-
static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
453
-
{
454
-
u32 value;
432
+
/**
433
+
* enum - Possible pad physical connections
434
+
* @PAD_CONNECT_NONE: pad is fully disconnected
435
+
* @PAD_CONNECT_INPUT: pad is in input only mode
436
+
* @PAD_CONNECT_OUTPUT: pad is in output only mode
437
+
* @PAD_CONNECT_FULL: pad is fully connected
438
+
*/
439
+
enum {
440
+
PAD_CONNECT_NONE = 0,
441
+
PAD_CONNECT_INPUT = 1,
442
+
PAD_CONNECT_OUTPUT = 2,
443
+
PAD_CONNECT_FULL = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT,
444
+
};
455
445
456
-
value = readl(padcfg0);
457
-
if (input) {
446
+
static int __intel_gpio_get_direction(u32 value)
447
+
{
448
+
switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) {
449
+
case PADCFG0_GPIODIS_FULL:
450
+
return PAD_CONNECT_NONE;
451
+
case PADCFG0_GPIODIS_OUTPUT:
452
+
return PAD_CONNECT_INPUT;
453
+
case PADCFG0_GPIODIS_INPUT:
454
+
return PAD_CONNECT_OUTPUT;
455
+
case PADCFG0_GPIODIS_NONE:
456
+
return PAD_CONNECT_FULL;
457
+
default:
458
+
return -ENOTSUPP;
459
+
};
460
+
}
461
+
462
+
static u32 __intel_gpio_set_direction(u32 value, bool input, bool output)
463
+
{
464
+
if (input)
458
465
value &= ~PADCFG0_GPIORXDIS;
459
-
value |= PADCFG0_GPIOTXDIS;
460
-
} else {
461
-
value &= ~PADCFG0_GPIOTXDIS;
466
+
else
462
467
value |= PADCFG0_GPIORXDIS;
463
-
}
464
-
writel(value, padcfg0);
468
+
469
+
if (output)
470
+
value &= ~PADCFG0_GPIOTXDIS;
471
+
else
472
+
value |= PADCFG0_GPIOTXDIS;
473
+
474
+
return value;
465
475
}
466
476
467
477
static int __intel_gpio_get_gpio_mode(u32 value)
···
515
465
value |= PADCFG0_PMODE_GPIO;
516
466
517
467
/* Disable TX buffer and enable RX (this will be input) */
518
-
value &= ~PADCFG0_GPIORXDIS;
519
-
value |= PADCFG0_GPIOTXDIS;
468
+
value = __intel_gpio_set_direction(value, true, false);
520
469
521
470
/* Disable SCI/SMI/NMI generation */
522
471
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
···
561
512
{
562
513
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
563
514
void __iomem *padcfg0;
515
+
u32 value;
564
516
565
517
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
566
518
567
519
guard(raw_spinlock_irqsave)(&pctrl->lock);
568
520
569
-
__intel_gpio_set_direction(padcfg0, input);
521
+
value = readl(padcfg0);
522
+
if (input)
523
+
value = __intel_gpio_set_direction(value, true, false);
524
+
else
525
+
value = __intel_gpio_set_direction(value, false, true);
526
+
writel(value, padcfg0);
570
527
571
528
return 0;
572
529
}
···
667
612
return 0;
668
613
}
669
614
615
+
static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin,
616
+
enum pin_config_param param, u32 *arg)
617
+
{
618
+
void __iomem *padcfg0;
619
+
u32 value;
620
+
621
+
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
622
+
623
+
scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
624
+
value = readl(padcfg0);
625
+
626
+
if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE)
627
+
return -EINVAL;
628
+
629
+
return 0;
630
+
}
631
+
670
632
static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
671
633
enum pin_config_param param, u32 *arg)
672
634
{
···
723
651
case PIN_CONFIG_BIAS_PULL_UP:
724
652
case PIN_CONFIG_BIAS_PULL_DOWN:
725
653
ret = intel_config_get_pull(pctrl, pin, param, &arg);
654
+
if (ret)
655
+
return ret;
656
+
break;
657
+
658
+
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
659
+
ret = intel_config_get_high_impedance(pctrl, pin, param, &arg);
726
660
if (ret)
727
661
return ret;
728
662
break;
···
831
753
return 0;
832
754
}
833
755
756
+
static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin)
757
+
{
758
+
void __iomem *padcfg0;
759
+
u32 value;
760
+
761
+
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
762
+
763
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
764
+
765
+
value = readl(padcfg0);
766
+
value = __intel_gpio_set_direction(value, false, false);
767
+
writel(value, padcfg0);
768
+
}
769
+
834
770
static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
835
771
unsigned int pin, unsigned int debounce)
836
772
{
837
773
void __iomem *padcfg0, *padcfg2;
838
774
u32 value0, value2;
775
+
unsigned long v;
776
+
777
+
if (debounce) {
778
+
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
779
+
if (v < 3 || v > 15)
780
+
return -EINVAL;
781
+
} else {
782
+
v = 0;
783
+
}
839
784
840
785
padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
841
786
if (!padcfg2)
···
871
770
value0 = readl(padcfg0);
872
771
value2 = readl(padcfg2);
873
772
874
-
/* Disable glitch filter and debouncer */
875
-
value0 &= ~PADCFG0_PREGFRXSEL;
876
-
value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
877
-
878
-
if (debounce) {
879
-
unsigned long v;
880
-
881
-
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
882
-
if (v < 3 || v > 15)
883
-
return -EINVAL;
884
-
773
+
value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT);
774
+
if (v) {
885
775
/* Enable glitch filter and debouncer */
886
776
value0 |= PADCFG0_PREGFRXSEL;
887
-
value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
888
777
value2 |= PADCFG2_DEBEN;
778
+
} else {
779
+
/* Disable glitch filter and debouncer */
780
+
value0 &= ~PADCFG0_PREGFRXSEL;
781
+
value2 &= ~PADCFG2_DEBEN;
889
782
}
890
783
891
784
writel(value0, padcfg0);
···
905
810
ret = intel_config_set_pull(pctrl, pin, configs[i]);
906
811
if (ret)
907
812
return ret;
813
+
break;
814
+
815
+
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
816
+
intel_gpio_set_high_impedance(pctrl, pin);
908
817
break;
909
818
910
819
case PIN_CONFIG_INPUT_DEBOUNCE:
···
953
854
* Return: a pin number and pointers to the community and pad group, which
954
855
* the pin belongs to, or negative error code if translation can't be done.
955
856
*/
956
-
static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
857
+
static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset,
957
858
const struct intel_community **community,
958
859
const struct intel_padgroup **padgrp)
959
860
{
960
-
int i;
861
+
const struct intel_community *comm;
862
+
const struct intel_padgroup *grp;
961
863
962
-
for (i = 0; i < pctrl->ncommunities; i++) {
963
-
const struct intel_community *comm = &pctrl->communities[i];
964
-
int j;
864
+
for_each_intel_gpio_group(pctrl, comm, grp) {
865
+
if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) {
866
+
if (community)
867
+
*community = comm;
868
+
if (padgrp)
869
+
*padgrp = grp;
965
870
966
-
for (j = 0; j < comm->ngpps; j++) {
967
-
const struct intel_padgroup *pgrp = &comm->gpps[j];
968
-
969
-
if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
970
-
continue;
971
-
972
-
if (offset >= pgrp->gpio_base &&
973
-
offset < pgrp->gpio_base + pgrp->size) {
974
-
int pin;
975
-
976
-
pin = pgrp->base + offset - pgrp->gpio_base;
977
-
if (community)
978
-
*community = comm;
979
-
if (padgrp)
980
-
*padgrp = pgrp;
981
-
982
-
return pin;
983
-
}
871
+
return grp->base + offset - grp->gpio_base;
984
872
}
985
873
}
986
874
···
983
897
*
984
898
* Return: a GPIO offset, or negative error code if translation can't be done.
985
899
*/
986
-
static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
900
+
static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin)
987
901
{
988
902
const struct intel_community *community;
989
903
const struct intel_padgroup *padgrp;
···
1015
929
return -EINVAL;
1016
930
1017
931
padcfg0 = readl(reg);
1018
-
if (!(padcfg0 & PADCFG0_GPIOTXDIS))
932
+
if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
1019
933
return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
1020
934
1021
935
return !!(padcfg0 & PADCFG0_GPIORXSTATE);
···
1068
982
if (padcfg0 & PADCFG0_PMODE_MASK)
1069
983
return -EINVAL;
1070
984
1071
-
if (padcfg0 & PADCFG0_GPIOTXDIS)
1072
-
return GPIO_LINE_DIRECTION_IN;
985
+
if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
986
+
return GPIO_LINE_DIRECTION_OUT;
1073
987
1074
-
return GPIO_LINE_DIRECTION_OUT;
988
+
return GPIO_LINE_DIRECTION_IN;
1075
989
}
1076
990
1077
991
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
···
1257
1171
GPIOCHIP_IRQ_RESOURCE_HELPERS,
1258
1172
};
1259
1173
1260
-
static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1261
-
const struct intel_community *community)
1174
+
static irqreturn_t intel_gpio_irq(int irq, void *data)
1262
1175
{
1263
-
struct gpio_chip *gc = &pctrl->chip;
1264
-
unsigned int gpp;
1176
+
const struct intel_community *community;
1177
+
const struct intel_padgroup *padgrp;
1178
+
struct intel_pinctrl *pctrl = data;
1265
1179
int ret = 0;
1266
1180
1267
-
for (gpp = 0; gpp < community->ngpps; gpp++) {
1268
-
const struct intel_padgroup *padgrp = &community->gpps[gpp];
1181
+
/* Need to check all communities for pending interrupts */
1182
+
for_each_intel_pad_group(pctrl, community, padgrp) {
1183
+
struct gpio_chip *gc = &pctrl->chip;
1269
1184
unsigned long pending, enabled;
1270
1185
unsigned int gpp, gpp_offset;
1271
1186
void __iomem *reg, *is;
···
1290
1203
ret += pending ? 1 : 0;
1291
1204
}
1292
1205
1293
-
return ret;
1294
-
}
1295
-
1296
-
static irqreturn_t intel_gpio_irq(int irq, void *data)
1297
-
{
1298
-
const struct intel_community *community;
1299
-
struct intel_pinctrl *pctrl = data;
1300
-
unsigned int i;
1301
-
int ret = 0;
1302
-
1303
-
/* Need to check all communities for pending interrupts */
1304
-
for (i = 0; i < pctrl->ncommunities; i++) {
1305
-
community = &pctrl->communities[i];
1306
-
ret += intel_gpio_community_irq_handler(pctrl, community);
1307
-
}
1308
-
1309
1206
return IRQ_RETVAL(ret);
1310
1207
}
1311
1208
1312
1209
static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1313
1210
{
1314
-
int i;
1211
+
const struct intel_community *community;
1315
1212
1316
-
for (i = 0; i < pctrl->ncommunities; i++) {
1317
-
const struct intel_community *community;
1213
+
for_each_intel_pin_community(pctrl, community) {
1318
1214
void __iomem *reg, *is;
1319
1215
unsigned int gpp;
1320
-
1321
-
community = &pctrl->communities[i];
1322
1216
1323
1217
for (gpp = 0; gpp < community->ngpps; gpp++) {
1324
1218
reg = community->regs + community->ie_offset + gpp * 4;
···
1325
1257
return 0;
1326
1258
}
1327
1259
1328
-
static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1329
-
const struct intel_community *community)
1330
-
{
1331
-
int ret = 0, i;
1332
-
1333
-
for (i = 0; i < community->ngpps; i++) {
1334
-
const struct intel_padgroup *gpp = &community->gpps[i];
1335
-
1336
-
if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1337
-
continue;
1338
-
1339
-
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1340
-
gpp->gpio_base, gpp->base,
1341
-
gpp->size);
1342
-
if (ret)
1343
-
return ret;
1344
-
}
1345
-
1346
-
return ret;
1347
-
}
1348
-
1349
1260
static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1350
1261
{
1351
1262
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1352
-
int ret, i;
1263
+
const struct intel_community *community;
1264
+
const struct intel_padgroup *grp;
1265
+
int ret;
1353
1266
1354
-
for (i = 0; i < pctrl->ncommunities; i++) {
1355
-
struct intel_community *community = &pctrl->communities[i];
1356
-
1357
-
ret = intel_gpio_add_community_ranges(pctrl, community);
1267
+
for_each_intel_gpio_group(pctrl, community, grp) {
1268
+
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1269
+
grp->gpio_base, grp->base,
1270
+
grp->size);
1358
1271
if (ret) {
1359
1272
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1360
1273
return ret;
···
1348
1299
static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1349
1300
{
1350
1301
const struct intel_community *community;
1302
+
const struct intel_padgroup *grp;
1351
1303
unsigned int ngpio = 0;
1352
-
int i, j;
1353
1304
1354
-
for (i = 0; i < pctrl->ncommunities; i++) {
1355
-
community = &pctrl->communities[i];
1356
-
for (j = 0; j < community->ngpps; j++) {
1357
-
const struct intel_padgroup *gpp = &community->gpps[j];
1358
-
1359
-
if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1360
-
continue;
1361
-
1362
-
if (gpp->gpio_base + gpp->size > ngpio)
1363
-
ngpio = gpp->gpio_base + gpp->size;
1364
-
}
1305
+
for_each_intel_gpio_group(pctrl, community, grp) {
1306
+
if (grp->gpio_base + grp->size > ngpio)
1307
+
ngpio = grp->gpio_base + grp->size;
1365
1308
}
1366
1309
1367
1310
return ngpio;
···
1723
1682
1724
1683
static bool __intel_gpio_is_direct_irq(u32 value)
1725
1684
{
1726
-
return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1685
+
return (value & PADCFG0_GPIROUTIOXAPIC) &&
1686
+
(__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) &&
1727
1687
(__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1728
1688
}
1729
1689
+2
-1
drivers/pinctrl/intel/pinctrl-intel.h
+2
-1
drivers/pinctrl/intel/pinctrl-intel.h
···
264
264
265
265
extern const struct dev_pm_ops intel_pinctrl_pm_ops;
266
266
267
-
struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin);
267
+
const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
268
+
unsigned int pin);
268
269
269
270
int intel_get_groups_count(struct pinctrl_dev *pctldev);
270
271
const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
+1
-1
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+1
-1
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+2
-5
drivers/pinctrl/mediatek/pinctrl-paris.c
+2
-5
drivers/pinctrl/mediatek/pinctrl-paris.c
···
1044
1044
1045
1045
hw->nbase = hw->soc->nbase_names;
1046
1046
1047
-
if (of_find_property(hw->dev->of_node,
1048
-
"mediatek,rsel-resistance-in-si-unit", NULL))
1049
-
hw->rsel_si_unit = true;
1050
-
else
1051
-
hw->rsel_si_unit = false;
1047
+
hw->rsel_si_unit = of_property_read_bool(hw->dev->of_node,
1048
+
"mediatek,rsel-resistance-in-si-unit");
1052
1049
1053
1050
spin_lock_init(&hw->lock);
1054
1051
+6
-6
drivers/pinctrl/meson/pinctrl-amlogic-c3.c
+6
-6
drivers/pinctrl/meson/pinctrl-amlogic-c3.c
···
375
375
static const unsigned int gen_clk_a4_pins[] = { GPIOA_4 };
376
376
static const unsigned int clk12_24_a_pins[] = { GPIOA_5 };
377
377
378
-
static struct meson_pmx_group c3_periphs_groups[] = {
378
+
static const struct meson_pmx_group c3_periphs_groups[] = {
379
379
GPIO_GROUP(GPIOE_0),
380
380
GPIO_GROUP(GPIOE_1),
381
381
GPIO_GROUP(GPIOE_2),
···
987
987
"lcd_clk_a", "lcd_clk_x", "lcd_hs", "lcd_vs",
988
988
};
989
989
990
-
static struct meson_pmx_func c3_periphs_functions[] = {
990
+
static const struct meson_pmx_func c3_periphs_functions[] = {
991
991
FUNCTION(gpio_periphs),
992
992
FUNCTION(uart_a),
993
993
FUNCTION(uart_b),
···
1036
1036
FUNCTION(lcd),
1037
1037
};
1038
1038
1039
-
static struct meson_bank c3_periphs_banks[] = {
1039
+
static const struct meson_bank c3_periphs_banks[] = {
1040
1040
/* name first last irq pullen pull dir out in ds */
1041
1041
BANK_DS("X", GPIOX_0, GPIOX_13, 40, 53,
1042
1042
0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
···
1054
1054
0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0),
1055
1055
};
1056
1056
1057
-
static struct meson_pmx_bank c3_periphs_pmx_banks[] = {
1057
+
static const struct meson_pmx_bank c3_periphs_pmx_banks[] = {
1058
1058
/* name first last reg offset */
1059
1059
BANK_PMX("B", GPIOB_0, GPIOB_14, 0x00, 0),
1060
1060
BANK_PMX("X", GPIOX_0, GPIOX_13, 0x03, 0),
···
1065
1065
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x02, 0),
1066
1066
};
1067
1067
1068
-
static struct meson_axg_pmx_data c3_periphs_pmx_banks_data = {
1068
+
static const struct meson_axg_pmx_data c3_periphs_pmx_banks_data = {
1069
1069
.pmx_banks = c3_periphs_pmx_banks,
1070
1070
.num_pmx_banks = ARRAY_SIZE(c3_periphs_pmx_banks),
1071
1071
};
1072
1072
1073
-
static struct meson_pinctrl_data c3_periphs_pinctrl_data = {
1073
+
static const struct meson_pinctrl_data c3_periphs_pinctrl_data = {
1074
1074
.name = "periphs-banks",
1075
1075
.pins = c3_periphs_pins,
1076
1076
.groups = c3_periphs_groups,
+6
-6
drivers/pinctrl/meson/pinctrl-amlogic-t7.c
+6
-6
drivers/pinctrl/meson/pinctrl-amlogic-t7.c
···
535
535
/* Bank H func3 */
536
536
static const unsigned int pcieck_reqn_h_pins[] = { GPIOH_2 };
537
537
538
-
static struct meson_pmx_group t7_periphs_groups[] = {
538
+
static const struct meson_pmx_group t7_periphs_groups[] = {
539
539
GPIO_GROUP(GPIOB_0),
540
540
GPIO_GROUP(GPIOB_1),
541
541
GPIO_GROUP(GPIOB_2),
···
1443
1443
"mic_mute_key", "mic_mute_led",
1444
1444
};
1445
1445
1446
-
static struct meson_pmx_func t7_periphs_functions[] = {
1446
+
static const struct meson_pmx_func t7_periphs_functions[] = {
1447
1447
FUNCTION(gpio_periphs),
1448
1448
FUNCTION(emmc),
1449
1449
FUNCTION(nor),
···
1524
1524
FUNCTION(mic_mute),
1525
1525
};
1526
1526
1527
-
static struct meson_bank t7_periphs_banks[] = {
1527
+
static const struct meson_bank t7_periphs_banks[] = {
1528
1528
/* name first last irq pullen pull dir out in ds */
1529
1529
BANK_DS("D", GPIOD_0, GPIOD_12, 57, 69,
1530
1530
0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0),
···
1552
1552
0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
1553
1553
};
1554
1554
1555
-
static struct meson_pmx_bank t7_periphs_pmx_banks[] = {
1555
+
static const struct meson_pmx_bank t7_periphs_pmx_banks[] = {
1556
1556
/* name first last reg offset */
1557
1557
BANK_PMX("D", GPIOD_0, GPIOD_12, 0x0a, 0),
1558
1558
BANK_PMX("E", GPIOE_0, GPIOE_6, 0x0c, 0),
···
1568
1568
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x09, 0),
1569
1569
};
1570
1570
1571
-
static struct meson_axg_pmx_data t7_periphs_pmx_banks_data = {
1571
+
static const struct meson_axg_pmx_data t7_periphs_pmx_banks_data = {
1572
1572
.pmx_banks = t7_periphs_pmx_banks,
1573
1573
.num_pmx_banks = ARRAY_SIZE(t7_periphs_pmx_banks),
1574
1574
};
1575
1575
1576
-
static struct meson_pinctrl_data t7_periphs_pinctrl_data = {
1576
+
static const struct meson_pinctrl_data t7_periphs_pinctrl_data = {
1577
1577
.name = "periphs-banks",
1578
1578
.pins = t7_periphs_pins,
1579
1579
.groups = t7_periphs_groups,
+6
-6
drivers/pinctrl/meson/pinctrl-meson-a1.c
+6
-6
drivers/pinctrl/meson/pinctrl-meson-a1.c
···
339
339
static const unsigned int mute_key_pins[] = { GPIOA_4 };
340
340
static const unsigned int mute_en_pins[] = { GPIOA_5 };
341
341
342
-
static struct meson_pmx_group meson_a1_periphs_groups[] = {
342
+
static const struct meson_pmx_group meson_a1_periphs_groups[] = {
343
343
GPIO_GROUP(GPIOP_0),
344
344
GPIO_GROUP(GPIOP_1),
345
345
GPIO_GROUP(GPIOP_2),
···
832
832
"mute_key", "mute_en",
833
833
};
834
834
835
-
static struct meson_pmx_func meson_a1_periphs_functions[] = {
835
+
static const struct meson_pmx_func meson_a1_periphs_functions[] = {
836
836
FUNCTION(gpio_periphs),
837
837
FUNCTION(psram),
838
838
FUNCTION(pwm_a),
···
875
875
FUNCTION(mute),
876
876
};
877
877
878
-
static struct meson_bank meson_a1_periphs_banks[] = {
878
+
static const struct meson_bank meson_a1_periphs_banks[] = {
879
879
/* name first last irq pullen pull dir out in ds*/
880
880
BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0,
881
881
0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0),
···
889
889
0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0),
890
890
};
891
891
892
-
static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
892
+
static const struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
893
893
/* name first lask reg offset */
894
894
BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
895
895
BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
···
898
898
BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
899
899
};
900
900
901
-
static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
901
+
static const struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
902
902
.pmx_banks = meson_a1_periphs_pmx_banks,
903
903
.num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
904
904
};
905
905
906
-
static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
906
+
static const struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
907
907
.name = "periphs-banks",
908
908
.pins = meson_a1_periphs_pins,
909
909
.groups = meson_a1_periphs_groups,
+6
-6
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+6
-6
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
···
27
27
28
28
static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
29
29
unsigned int pin,
30
-
struct meson_pmx_bank **bank)
30
+
const struct meson_pmx_bank **bank)
31
31
{
32
32
int i;
33
-
struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
33
+
const struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
34
34
35
35
for (i = 0; i < pmx->num_pmx_banks; i++)
36
36
if (pin >= pmx->pmx_banks[i].first &&
···
42
42
return -EINVAL;
43
43
}
44
44
45
-
static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
45
+
static int meson_pmx_calc_reg_and_offset(const struct meson_pmx_bank *bank,
46
46
unsigned int pin, unsigned int *reg,
47
47
unsigned int *offset)
48
48
{
···
59
59
static int meson_axg_pmx_update_function(struct meson_pinctrl *pc,
60
60
unsigned int pin, unsigned int func)
61
61
{
62
+
const struct meson_pmx_bank *bank;
62
63
int ret;
63
64
int reg;
64
65
int offset;
65
-
struct meson_pmx_bank *bank;
66
66
67
67
ret = meson_axg_pmx_get_bank(pc, pin, &bank);
68
68
if (ret)
···
82
82
int i;
83
83
int ret;
84
84
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
85
-
struct meson_pmx_func *func = &pc->data->funcs[func_num];
86
-
struct meson_pmx_group *group = &pc->data->groups[group_num];
85
+
const struct meson_pmx_func *func = &pc->data->funcs[func_num];
86
+
const struct meson_pmx_group *group = &pc->data->groups[group_num];
87
87
struct meson_pmx_axg_data *pmx_data =
88
88
(struct meson_pmx_axg_data *)group->data;
89
89
+1
-1
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
+1
-1
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
+12
-12
drivers/pinctrl/meson/pinctrl-meson-axg.c
+12
-12
drivers/pinctrl/meson/pinctrl-meson-axg.c
···
352
352
static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
353
353
static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
354
354
355
-
static struct meson_pmx_group meson_axg_periphs_groups[] = {
355
+
static const struct meson_pmx_group meson_axg_periphs_groups[] = {
356
356
GPIO_GROUP(GPIOZ_0),
357
357
GPIO_GROUP(GPIOZ_1),
358
358
GPIO_GROUP(GPIOZ_2),
···
675
675
/* gen_clk */
676
676
static const unsigned int gen_clk_ee_pins[] = {GPIOAO_13};
677
677
678
-
static struct meson_pmx_group meson_axg_aobus_groups[] = {
678
+
static const struct meson_pmx_group meson_axg_aobus_groups[] = {
679
679
GPIO_GROUP(GPIOAO_0),
680
680
GPIO_GROUP(GPIOAO_1),
681
681
GPIO_GROUP(GPIOAO_2),
···
955
955
"gen_clk_ee",
956
956
};
957
957
958
-
static struct meson_pmx_func meson_axg_periphs_functions[] = {
958
+
static const struct meson_pmx_func meson_axg_periphs_functions[] = {
959
959
FUNCTION(gpio_periphs),
960
960
FUNCTION(emmc),
961
961
FUNCTION(nor),
···
987
987
FUNCTION(tdmc),
988
988
};
989
989
990
-
static struct meson_pmx_func meson_axg_aobus_functions[] = {
990
+
static const struct meson_pmx_func meson_axg_aobus_functions[] = {
991
991
FUNCTION(gpio_aobus),
992
992
FUNCTION(uart_ao_a),
993
993
FUNCTION(uart_ao_b),
···
1003
1003
FUNCTION(gen_clk_ee),
1004
1004
};
1005
1005
1006
-
static struct meson_bank meson_axg_periphs_banks[] = {
1006
+
static const struct meson_bank meson_axg_periphs_banks[] = {
1007
1007
/* name first last irq pullen pull dir out in */
1008
1008
BANK("Z", GPIOZ_0, GPIOZ_10, 14, 24, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
1009
1009
BANK("BOOT", BOOT_0, BOOT_14, 25, 39, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
···
1012
1012
BANK("Y", GPIOY_0, GPIOY_15, 84, 99, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
1013
1013
};
1014
1014
1015
-
static struct meson_bank meson_axg_aobus_banks[] = {
1015
+
static const struct meson_bank meson_axg_aobus_banks[] = {
1016
1016
/* name first last irq pullen pull dir out in */
1017
1017
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
1018
1018
};
1019
1019
1020
-
static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
1020
+
static const struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = {
1021
1021
/* name first lask reg offset */
1022
1022
BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0),
1023
1023
BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0),
···
1026
1026
BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0),
1027
1027
};
1028
1028
1029
-
static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
1029
+
static const struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = {
1030
1030
.pmx_banks = meson_axg_periphs_pmx_banks,
1031
1031
.num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks),
1032
1032
};
1033
1033
1034
-
static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
1034
+
static const struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = {
1035
1035
BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0),
1036
1036
};
1037
1037
1038
-
static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
1038
+
static const struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = {
1039
1039
.pmx_banks = meson_axg_aobus_pmx_banks,
1040
1040
.num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks),
1041
1041
};
1042
1042
1043
-
static struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
1043
+
static const struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = {
1044
1044
.name = "periphs-banks",
1045
1045
.pins = meson_axg_periphs_pins,
1046
1046
.groups = meson_axg_periphs_groups,
···
1054
1054
.pmx_data = &meson_axg_periphs_pmx_banks_data,
1055
1055
};
1056
1056
1057
-
static struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
1057
+
static const struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = {
1058
1058
.name = "aobus-banks",
1059
1059
.pins = meson_axg_aobus_pins,
1060
1060
.groups = meson_axg_aobus_groups,
+12
-12
drivers/pinctrl/meson/pinctrl-meson-g12a.c
+12
-12
drivers/pinctrl/meson/pinctrl-meson-g12a.c
···
436
436
static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 };
437
437
static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 };
438
438
439
-
static struct meson_pmx_group meson_g12a_periphs_groups[] = {
439
+
static const struct meson_pmx_group meson_g12a_periphs_groups[] = {
440
440
GPIO_GROUP(GPIOZ_0),
441
441
GPIO_GROUP(GPIOZ_1),
442
442
GPIO_GROUP(GPIOZ_2),
···
860
860
/* mclk0_ao */
861
861
static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 };
862
862
863
-
static struct meson_pmx_group meson_g12a_aobus_groups[] = {
863
+
static const struct meson_pmx_group meson_g12a_aobus_groups[] = {
864
864
GPIO_GROUP(GPIOAO_0),
865
865
GPIO_GROUP(GPIOAO_1),
866
866
GPIO_GROUP(GPIOAO_2),
···
1253
1253
"mclk0_ao",
1254
1254
};
1255
1255
1256
-
static struct meson_pmx_func meson_g12a_periphs_functions[] = {
1256
+
static const struct meson_pmx_func meson_g12a_periphs_functions[] = {
1257
1257
FUNCTION(gpio_periphs),
1258
1258
FUNCTION(emmc),
1259
1259
FUNCTION(nor),
···
1295
1295
FUNCTION(tdm_c),
1296
1296
};
1297
1297
1298
-
static struct meson_pmx_func meson_g12a_aobus_functions[] = {
1298
+
static const struct meson_pmx_func meson_g12a_aobus_functions[] = {
1299
1299
FUNCTION(gpio_aobus),
1300
1300
FUNCTION(uart_ao_a),
1301
1301
FUNCTION(uart_ao_b),
···
1317
1317
FUNCTION(mclk0_ao),
1318
1318
};
1319
1319
1320
-
static struct meson_bank meson_g12a_periphs_banks[] = {
1320
+
static const struct meson_bank meson_g12a_periphs_banks[] = {
1321
1321
/* name first last irq pullen pull dir out in ds */
1322
1322
BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15,
1323
1323
4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0),
···
1333
1333
2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0),
1334
1334
};
1335
1335
1336
-
static struct meson_bank meson_g12a_aobus_banks[] = {
1336
+
static const struct meson_bank meson_g12a_aobus_banks[] = {
1337
1337
/* name first last irq pullen pull dir out in ds */
1338
1338
BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11,
1339
1339
3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0),
···
1342
1342
3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0),
1343
1343
};
1344
1344
1345
-
static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
1345
+
static const struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = {
1346
1346
/* name first last reg offset */
1347
1347
BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0),
1348
1348
BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0),
···
1352
1352
BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
1353
1353
};
1354
1354
1355
-
static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = {
1355
+
static const struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = {
1356
1356
.pmx_banks = meson_g12a_periphs_pmx_banks,
1357
1357
.num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks),
1358
1358
};
1359
1359
1360
-
static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = {
1360
+
static const struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = {
1361
1361
BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0),
1362
1362
BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16),
1363
1363
};
1364
1364
1365
-
static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = {
1365
+
static const struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = {
1366
1366
.pmx_banks = meson_g12a_aobus_pmx_banks,
1367
1367
.num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks),
1368
1368
};
···
1375
1375
return 0;
1376
1376
}
1377
1377
1378
-
static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
1378
+
static const struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
1379
1379
.name = "periphs-banks",
1380
1380
.pins = meson_g12a_periphs_pins,
1381
1381
.groups = meson_g12a_periphs_groups,
···
1389
1389
.pmx_data = &meson_g12a_periphs_pmx_banks_data,
1390
1390
};
1391
1391
1392
-
static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = {
1392
+
static const struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = {
1393
1393
.name = "aobus-banks",
1394
1394
.pins = meson_g12a_aobus_pins,
1395
1395
.groups = meson_g12a_aobus_groups,
+8
-8
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+8
-8
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
···
307
307
static const unsigned int ao_cec_pins[] = { GPIOAO_12 };
308
308
static const unsigned int ee_cec_pins[] = { GPIOAO_12 };
309
309
310
-
static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
310
+
static const struct meson_pmx_group meson_gxbb_periphs_groups[] = {
311
311
GPIO_GROUP(GPIOZ_0),
312
312
GPIO_GROUP(GPIOZ_1),
313
313
GPIO_GROUP(GPIOZ_2),
···
541
541
GROUP(sdcard_clk, 2, 11),
542
542
};
543
543
544
-
static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
544
+
static const struct meson_pmx_group meson_gxbb_aobus_groups[] = {
545
545
GPIO_GROUP(GPIOAO_0),
546
546
GPIO_GROUP(GPIOAO_1),
547
547
GPIO_GROUP(GPIOAO_2),
···
798
798
"ao_cec", "ee_cec",
799
799
};
800
800
801
-
static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
801
+
static const struct meson_pmx_func meson_gxbb_periphs_functions[] = {
802
802
FUNCTION(gpio_periphs),
803
803
FUNCTION(emmc),
804
804
FUNCTION(nor),
···
829
829
FUNCTION(tsin_b),
830
830
};
831
831
832
-
static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
832
+
static const struct meson_pmx_func meson_gxbb_aobus_functions[] = {
833
833
FUNCTION(gpio_aobus),
834
834
FUNCTION(uart_ao),
835
835
FUNCTION(uart_ao_b),
···
845
845
FUNCTION(cec_ao),
846
846
};
847
847
848
-
static struct meson_bank meson_gxbb_periphs_banks[] = {
848
+
static const struct meson_bank meson_gxbb_periphs_banks[] = {
849
849
/* name first last irq pullen pull dir out in */
850
850
BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
851
851
BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
···
857
857
BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
858
858
};
859
859
860
-
static struct meson_bank meson_gxbb_aobus_banks[] = {
860
+
static const struct meson_bank meson_gxbb_aobus_banks[] = {
861
861
/* name first last irq pullen pull dir out in */
862
862
BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
863
863
};
864
864
865
-
static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
865
+
static const struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
866
866
.name = "periphs-banks",
867
867
.pins = meson_gxbb_periphs_pins,
868
868
.groups = meson_gxbb_periphs_groups,
···
875
875
.pmx_ops = &meson8_pmx_ops,
876
876
};
877
877
878
-
static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
878
+
static const struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
879
879
.name = "aobus-banks",
880
880
.pins = meson_gxbb_aobus_pins,
881
881
.groups = meson_gxbb_aobus_groups,
+8
-8
drivers/pinctrl/meson/pinctrl-meson-gxl.c
+8
-8
drivers/pinctrl/meson/pinctrl-meson-gxl.c
···
301
301
static const unsigned int ao_cec_pins[] = { GPIOAO_8 };
302
302
static const unsigned int ee_cec_pins[] = { GPIOAO_8 };
303
303
304
-
static struct meson_pmx_group meson_gxl_periphs_groups[] = {
304
+
static const struct meson_pmx_group meson_gxl_periphs_groups[] = {
305
305
GPIO_GROUP(GPIOZ_0),
306
306
GPIO_GROUP(GPIOZ_1),
307
307
GPIO_GROUP(GPIOZ_2),
···
527
527
GROUP(pwm_f_clk, 8, 30),
528
528
};
529
529
530
-
static struct meson_pmx_group meson_gxl_aobus_groups[] = {
530
+
static const struct meson_pmx_group meson_gxl_aobus_groups[] = {
531
531
GPIO_GROUP(GPIOAO_0),
532
532
GPIO_GROUP(GPIOAO_1),
533
533
GPIO_GROUP(GPIOAO_2),
···
763
763
"ao_cec", "ee_cec",
764
764
};
765
765
766
-
static struct meson_pmx_func meson_gxl_periphs_functions[] = {
766
+
static const struct meson_pmx_func meson_gxl_periphs_functions[] = {
767
767
FUNCTION(gpio_periphs),
768
768
FUNCTION(emmc),
769
769
FUNCTION(nor),
···
793
793
FUNCTION(tsin_b),
794
794
};
795
795
796
-
static struct meson_pmx_func meson_gxl_aobus_functions[] = {
796
+
static const struct meson_pmx_func meson_gxl_aobus_functions[] = {
797
797
FUNCTION(gpio_aobus),
798
798
FUNCTION(uart_ao),
799
799
FUNCTION(uart_ao_b),
···
807
807
FUNCTION(cec_ao),
808
808
};
809
809
810
-
static struct meson_bank meson_gxl_periphs_banks[] = {
810
+
static const struct meson_bank meson_gxl_periphs_banks[] = {
811
811
/* name first last irq pullen pull dir out in */
812
812
BANK("X", GPIOX_0, GPIOX_18, 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
813
813
BANK("DV", GPIODV_0, GPIODV_29, 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
···
818
818
BANK("CLK", GPIOCLK_0, GPIOCLK_1, 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
819
819
};
820
820
821
-
static struct meson_bank meson_gxl_aobus_banks[] = {
821
+
static const struct meson_bank meson_gxl_aobus_banks[] = {
822
822
/* name first last irq pullen pull dir out in */
823
823
BANK("AO", GPIOAO_0, GPIOAO_9, 0, 9, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
824
824
};
825
825
826
-
static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
826
+
static const struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
827
827
.name = "periphs-banks",
828
828
.pins = meson_gxl_periphs_pins,
829
829
.groups = meson_gxl_periphs_groups,
···
836
836
.pmx_ops = &meson8_pmx_ops,
837
837
};
838
838
839
-
static struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
839
+
static const struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
840
840
.name = "aobus-banks",
841
841
.pins = meson_gxl_aobus_pins,
842
842
.groups = meson_gxl_aobus_groups,
+6
-6
drivers/pinctrl/meson/pinctrl-meson-s4.c
+6
-6
drivers/pinctrl/meson/pinctrl-meson-s4.c
···
411
411
static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 };
412
412
static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 };
413
413
414
-
static struct meson_pmx_group meson_s4_periphs_groups[] = {
414
+
static const struct meson_pmx_group meson_s4_periphs_groups[] = {
415
415
GPIO_GROUP(GPIOE_0),
416
416
GPIO_GROUP(GPIOE_1),
417
417
···
1100
1100
"s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0",
1101
1101
};
1102
1102
1103
-
static struct meson_pmx_func meson_s4_periphs_functions[] = {
1103
+
static const struct meson_pmx_func meson_s4_periphs_functions[] = {
1104
1104
FUNCTION(gpio_periphs),
1105
1105
FUNCTION(i2c0),
1106
1106
FUNCTION(i2c1),
···
1160
1160
FUNCTION(s2_demod),
1161
1161
};
1162
1162
1163
-
static struct meson_bank meson_s4_periphs_banks[] = {
1163
+
static const struct meson_bank meson_s4_periphs_banks[] = {
1164
1164
/* name first last irq pullen pull dir out in */
1165
1165
BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13,
1166
1166
0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0),
···
1180
1180
0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0),
1181
1181
};
1182
1182
1183
-
static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
1183
+
static const struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
1184
1184
/*name first lask reg offset*/
1185
1185
BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0),
1186
1186
BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
···
1192
1192
BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0)
1193
1193
};
1194
1194
1195
-
static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
1195
+
static const struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
1196
1196
.pmx_banks = meson_s4_periphs_pmx_banks,
1197
1197
.num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks),
1198
1198
};
1199
1199
1200
-
static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
1200
+
static const struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
1201
1201
.name = "periphs-banks",
1202
1202
.pins = meson_s4_periphs_pins,
1203
1203
.groups = meson_s4_periphs_groups,
+13
-12
drivers/pinctrl/meson/pinctrl-meson.c
+13
-12
drivers/pinctrl/meson/pinctrl-meson.c
···
70
70
* Return: 0 on success, a negative value on error
71
71
*/
72
72
static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
73
-
struct meson_bank **bank)
73
+
const struct meson_bank **bank)
74
74
{
75
75
int i;
76
76
···
94
94
* @reg: the computed register offset
95
95
* @bit: the computed bit
96
96
*/
97
-
static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
97
+
static void meson_calc_reg_and_bit(const struct meson_bank *bank,
98
+
unsigned int pin,
98
99
enum meson_reg_type reg_type,
99
100
unsigned int *reg, unsigned int *bit)
100
101
{
101
-
struct meson_reg_desc *desc = &bank->regs[reg_type];
102
+
const struct meson_reg_desc *desc = &bank->regs[reg_type];
102
103
103
104
*bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
104
105
*reg = (desc->reg + (*bit / 32)) * 4;
···
182
181
unsigned int reg_type,
183
182
bool arg)
184
183
{
185
-
struct meson_bank *bank;
184
+
const struct meson_bank *bank;
186
185
unsigned int reg, bit;
187
186
int ret;
188
187
···
199
198
unsigned int pin,
200
199
unsigned int reg_type)
201
200
{
202
-
struct meson_bank *bank;
201
+
const struct meson_bank *bank;
203
202
unsigned int reg, bit, val;
204
203
int ret;
205
204
···
262
261
static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
263
262
unsigned int pin)
264
263
{
265
-
struct meson_bank *bank;
264
+
const struct meson_bank *bank;
266
265
unsigned int reg, bit = 0;
267
266
int ret;
268
267
···
281
280
static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
282
281
bool pull_up)
283
282
{
284
-
struct meson_bank *bank;
283
+
const struct meson_bank *bank;
285
284
unsigned int reg, bit, val = 0;
286
285
int ret;
287
286
···
309
308
unsigned int pin,
310
309
u16 drive_strength_ua)
311
310
{
312
-
struct meson_bank *bank;
311
+
const struct meson_bank *bank;
313
312
unsigned int reg, bit, ds_val;
314
313
int ret;
315
314
···
400
399
401
400
static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
402
401
{
403
-
struct meson_bank *bank;
402
+
const struct meson_bank *bank;
404
403
unsigned int reg, bit, val;
405
404
int ret, conf;
406
405
···
436
435
unsigned int pin,
437
436
u16 *drive_strength_ua)
438
437
{
439
-
struct meson_bank *bank;
438
+
const struct meson_bank *bank;
440
439
unsigned int reg, bit;
441
440
unsigned int val;
442
441
int ret;
···
529
528
unsigned long *configs, unsigned num_configs)
530
529
{
531
530
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
532
-
struct meson_pmx_group *group = &pc->data->groups[num_group];
531
+
const struct meson_pmx_group *group = &pc->data->groups[num_group];
533
532
int i;
534
533
535
534
dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
···
588
587
static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
589
588
{
590
589
struct meson_pinctrl *pc = gpiochip_get_data(chip);
590
+
const struct meson_bank *bank;
591
591
unsigned int reg, bit, val;
592
-
struct meson_bank *bank;
593
592
int ret;
594
593
595
594
ret = meson_get_bank(pc, gpio, &bank);
+4
-4
drivers/pinctrl/meson/pinctrl-meson.h
+4
-4
drivers/pinctrl/meson/pinctrl-meson.h
···
110
110
struct meson_pinctrl_data {
111
111
const char *name;
112
112
const struct pinctrl_pin_desc *pins;
113
-
struct meson_pmx_group *groups;
114
-
struct meson_pmx_func *funcs;
113
+
const struct meson_pmx_group *groups;
114
+
const struct meson_pmx_func *funcs;
115
115
unsigned int num_pins;
116
116
unsigned int num_groups;
117
117
unsigned int num_funcs;
118
-
struct meson_bank *banks;
118
+
const struct meson_bank *banks;
119
119
unsigned int num_banks;
120
120
const struct pinmux_ops *pmx_ops;
121
-
void *pmx_data;
121
+
const void *pmx_data;
122
122
int (*parse_dt)(struct meson_pinctrl *pc);
123
123
};
124
124
+3
-3
drivers/pinctrl/meson/pinctrl-meson8-pmx.c
+3
-3
drivers/pinctrl/meson/pinctrl-meson8-pmx.c
···
32
32
static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc,
33
33
unsigned int pin, int sel_group)
34
34
{
35
-
struct meson_pmx_group *group;
35
+
const struct meson_pmx_group *group;
36
36
struct meson8_pmx_data *pmx_data;
37
37
int i, j;
38
38
···
57
57
unsigned group_num)
58
58
{
59
59
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
60
-
struct meson_pmx_func *func = &pc->data->funcs[func_num];
61
-
struct meson_pmx_group *group = &pc->data->groups[group_num];
60
+
const struct meson_pmx_func *func = &pc->data->funcs[func_num];
61
+
const struct meson_pmx_group *group = &pc->data->groups[group_num];
62
62
struct meson8_pmx_data *pmx_data =
63
63
(struct meson8_pmx_data *)group->data;
64
64
int i, ret = 0;
+8
-8
drivers/pinctrl/meson/pinctrl-meson8.c
+8
-8
drivers/pinctrl/meson/pinctrl-meson8.c
···
405
405
406
406
static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
407
407
408
-
static struct meson_pmx_group meson8_cbus_groups[] = {
408
+
static const struct meson_pmx_group meson8_cbus_groups[] = {
409
409
GPIO_GROUP(GPIOX_0),
410
410
GPIO_GROUP(GPIOX_1),
411
411
GPIO_GROUP(GPIOX_2),
···
745
745
GROUP(sdxc_cmd_b, 2, 4),
746
746
};
747
747
748
-
static struct meson_pmx_group meson8_aobus_groups[] = {
748
+
static const struct meson_pmx_group meson8_aobus_groups[] = {
749
749
GPIO_GROUP(GPIOAO_0),
750
750
GPIO_GROUP(GPIOAO_1),
751
751
GPIO_GROUP(GPIOAO_2),
···
1015
1015
"hdmi_cec_ao"
1016
1016
};
1017
1017
1018
-
static struct meson_pmx_func meson8_cbus_functions[] = {
1018
+
static const struct meson_pmx_func meson8_cbus_functions[] = {
1019
1019
FUNCTION(gpio_periphs),
1020
1020
FUNCTION(sd_a),
1021
1021
FUNCTION(sdxc_a),
···
1051
1051
FUNCTION(spdif),
1052
1052
};
1053
1053
1054
-
static struct meson_pmx_func meson8_aobus_functions[] = {
1054
+
static const struct meson_pmx_func meson8_aobus_functions[] = {
1055
1055
FUNCTION(gpio_aobus),
1056
1056
FUNCTION(uart_ao),
1057
1057
FUNCTION(remote),
···
1063
1063
FUNCTION(hdmi_cec_ao),
1064
1064
};
1065
1065
1066
-
static struct meson_bank meson8_cbus_banks[] = {
1066
+
static const struct meson_bank meson8_cbus_banks[] = {
1067
1067
/* name first last irq pullen pull dir out in */
1068
1068
BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1069
1069
BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
···
1074
1074
BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
1075
1075
};
1076
1076
1077
-
static struct meson_bank meson8_aobus_banks[] = {
1077
+
static const struct meson_bank meson8_aobus_banks[] = {
1078
1078
/* name first last irq pullen pull dir out in */
1079
1079
BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
1080
1080
};
1081
1081
1082
-
static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
1082
+
static const struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
1083
1083
.name = "cbus-banks",
1084
1084
.pins = meson8_cbus_pins,
1085
1085
.groups = meson8_cbus_groups,
···
1092
1092
.pmx_ops = &meson8_pmx_ops,
1093
1093
};
1094
1094
1095
-
static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
1095
+
static const struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
1096
1096
.name = "ao-bank",
1097
1097
.pins = meson8_aobus_pins,
1098
1098
.groups = meson8_aobus_groups,
+8
-8
drivers/pinctrl/meson/pinctrl-meson8b.c
+8
-8
drivers/pinctrl/meson/pinctrl-meson8b.c
···
349
349
static const unsigned int eth_mdc_pins[] = { DIF_4_P };
350
350
static const unsigned int eth_mdio_en_pins[] = { DIF_4_N };
351
351
352
-
static struct meson_pmx_group meson8b_cbus_groups[] = {
352
+
static const struct meson_pmx_group meson8b_cbus_groups[] = {
353
353
GPIO_GROUP(GPIOX_0),
354
354
GPIO_GROUP(GPIOX_1),
355
355
GPIO_GROUP(GPIOX_2),
···
603
603
GROUP(eth_rxd2, 7, 23),
604
604
};
605
605
606
-
static struct meson_pmx_group meson8b_aobus_groups[] = {
606
+
static const struct meson_pmx_group meson8b_aobus_groups[] = {
607
607
GPIO_GROUP(GPIOAO_0),
608
608
GPIO_GROUP(GPIOAO_1),
609
609
GPIO_GROUP(GPIOAO_2),
···
869
869
"tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
870
870
};
871
871
872
-
static struct meson_pmx_func meson8b_cbus_functions[] = {
872
+
static const struct meson_pmx_func meson8b_cbus_functions[] = {
873
873
FUNCTION(gpio_periphs),
874
874
FUNCTION(sd_a),
875
875
FUNCTION(sdxc_a),
···
903
903
FUNCTION(clk_24m),
904
904
};
905
905
906
-
static struct meson_pmx_func meson8b_aobus_functions[] = {
906
+
static const struct meson_pmx_func meson8b_aobus_functions[] = {
907
907
FUNCTION(gpio_aobus),
908
908
FUNCTION(uart_ao),
909
909
FUNCTION(uart_ao_b),
···
917
917
FUNCTION(hdmi_cec),
918
918
};
919
919
920
-
static struct meson_bank meson8b_cbus_banks[] = {
920
+
static const struct meson_bank meson8b_cbus_banks[] = {
921
921
/* name first last irq pullen pull dir out in */
922
922
BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
923
923
BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16),
···
938
938
BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
939
939
};
940
940
941
-
static struct meson_bank meson8b_aobus_banks[] = {
941
+
static const struct meson_bank meson8b_aobus_banks[] = {
942
942
/* name first lastc irq pullen pull dir out in */
943
943
BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
944
944
};
945
945
946
-
static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
946
+
static const struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
947
947
.name = "cbus-banks",
948
948
.pins = meson8b_cbus_pins,
949
949
.groups = meson8b_cbus_groups,
···
956
956
.pmx_ops = &meson8_pmx_ops,
957
957
};
958
958
959
-
static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
959
+
static const struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
960
960
.name = "aobus-banks",
961
961
.pins = meson8b_aobus_pins,
962
962
.groups = meson8b_aobus_groups,
+29
-13
drivers/pinctrl/mvebu/pinctrl-dove.c
+29
-13
drivers/pinctrl/mvebu/pinctrl-dove.c
···
767
767
struct resource fb_res;
768
768
struct mvebu_mpp_ctrl_data *mpp_data;
769
769
void __iomem *base;
770
-
int i;
770
+
int i, ret;
771
771
772
772
pdev->dev.platform_data = (void *)device_get_match_data(&pdev->dev);
773
773
···
783
783
clk_prepare_enable(clk);
784
784
785
785
base = devm_platform_get_and_ioremap_resource(pdev, 0, &mpp_res);
786
-
if (IS_ERR(base))
787
-
return PTR_ERR(base);
786
+
if (IS_ERR(base)) {
787
+
ret = PTR_ERR(base);
788
+
goto err_probe;
789
+
}
788
790
789
791
mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
790
792
sizeof(*mpp_data), GFP_KERNEL);
791
-
if (!mpp_data)
792
-
return -ENOMEM;
793
+
if (!mpp_data) {
794
+
ret = -ENOMEM;
795
+
goto err_probe;
796
+
}
793
797
794
798
dove_pinctrl_info.control_data = mpp_data;
795
799
for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
···
812
808
}
813
809
814
810
mpp4_base = devm_ioremap_resource(&pdev->dev, res);
815
-
if (IS_ERR(mpp4_base))
816
-
return PTR_ERR(mpp4_base);
811
+
if (IS_ERR(mpp4_base)) {
812
+
ret = PTR_ERR(mpp4_base);
813
+
goto err_probe;
814
+
}
817
815
818
816
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
819
817
if (!res) {
···
826
820
}
827
821
828
822
pmu_base = devm_ioremap_resource(&pdev->dev, res);
829
-
if (IS_ERR(pmu_base))
830
-
return PTR_ERR(pmu_base);
823
+
if (IS_ERR(pmu_base)) {
824
+
ret = PTR_ERR(pmu_base);
825
+
goto err_probe;
826
+
}
831
827
832
828
gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
833
829
if (IS_ERR(gconfmap)) {
···
839
831
adjust_resource(&fb_res,
840
832
(mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
841
833
gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
842
-
if (IS_ERR(gc_base))
843
-
return PTR_ERR(gc_base);
834
+
if (IS_ERR(gc_base)) {
835
+
ret = PTR_ERR(gc_base);
836
+
goto err_probe;
837
+
}
838
+
844
839
gconfmap = devm_regmap_init_mmio(&pdev->dev,
845
840
gc_base, &gc_regmap_config);
846
-
if (IS_ERR(gconfmap))
847
-
return PTR_ERR(gconfmap);
841
+
if (IS_ERR(gconfmap)) {
842
+
ret = PTR_ERR(gconfmap);
843
+
goto err_probe;
844
+
}
848
845
}
849
846
850
847
/* Warn on any missing DT resource */
···
857
844
dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
858
845
859
846
return mvebu_pinctrl_probe(pdev);
847
+
err_probe:
848
+
clk_disable_unprepare(clk);
849
+
return ret;
860
850
}
861
851
862
852
static struct platform_driver dove_pinctrl_driver = {
+1
-2
drivers/pinctrl/nomadik/pinctrl-abx500.c
+1
-2
drivers/pinctrl/nomadik/pinctrl-abx500.c
···
716
716
if (*num_maps == *reserved_maps)
717
717
return -ENOSPC;
718
718
719
-
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
720
-
GFP_KERNEL);
719
+
dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs), GFP_KERNEL);
721
720
if (!dup_configs)
722
721
return -ENOMEM;
723
722
+1
-2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
+1
-2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
···
601
601
if (*num_maps == *reserved_maps)
602
602
return -ENOSPC;
603
603
604
-
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
605
-
GFP_KERNEL);
604
+
dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs), GFP_KERNEL);
606
605
if (!dup_configs)
607
606
return -ENOMEM;
608
607
+31
-33
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+31
-33
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
···
241
241
npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
242
242
break;
243
243
case IRQ_TYPE_EDGE_BOTH:
244
+
npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
244
245
npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
245
246
break;
246
247
case IRQ_TYPE_LEVEL_LOW:
···
316
315
GPIOCHIP_IRQ_RESOURCE_HELPERS,
317
316
};
318
317
319
-
static const int gpi36_pins[] = { 58 };
320
-
static const int gpi35_pins[] = { 58 };
318
+
static const int gpi36_pins[] = { 36 };
319
+
static const int gpi35_pins[] = { 35 };
321
320
322
321
static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
323
322
static const int tp_uart_pins[] = { 50, 51 };
···
438
437
static const int smb4b_pins[] = { 18, 19 };
439
438
static const int smb4c_pins[] = { 20, 21 };
440
439
static const int smb4d_pins[] = { 22, 23 };
441
-
static const int smb4den_pins[] = { 17 };
442
440
static const int smb5_pins[] = { 26, 27 };
443
441
static const int smb5b_pins[] = { 13, 12 };
444
442
static const int smb5c_pins[] = { 15, 14 };
···
515
515
static const int rg2mdio_pins[] = { 216, 217 };
516
516
517
517
static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
518
-
213, 214, 215, 216, 217 };
518
+
213, 214, 215, 216, 217, 250 };
519
519
520
520
static const int iox1_pins[] = { 0, 1, 2, 3 };
521
521
static const int iox2_pins[] = { 4, 5, 6, 7 };
···
570
570
static const int ddc_pins[] = { 204, 205, 206, 207 };
571
571
572
572
static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
573
-
static const int lpcclk_pins[] = { 168 };
574
573
static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
575
574
576
575
static const int lkgpo0_pins[] = { 16 };
···
698
699
NPCM8XX_GRP(smb4b), \
699
700
NPCM8XX_GRP(smb4c), \
700
701
NPCM8XX_GRP(smb4d), \
701
-
NPCM8XX_GRP(smb4den), \
702
702
NPCM8XX_GRP(smb5), \
703
703
NPCM8XX_GRP(smb5b), \
704
704
NPCM8XX_GRP(smb5c), \
···
806
808
NPCM8XX_GRP(spi3cs3), \
807
809
NPCM8XX_GRP(spi0cs1), \
808
810
NPCM8XX_GRP(lpc), \
809
-
NPCM8XX_GRP(lpcclk), \
810
811
NPCM8XX_GRP(espi), \
811
812
NPCM8XX_GRP(lkgpo0), \
812
813
NPCM8XX_GRP(lkgpo1), \
···
945
948
NPCM8XX_SFUNC(smb4b);
946
949
NPCM8XX_SFUNC(smb4c);
947
950
NPCM8XX_SFUNC(smb4d);
948
-
NPCM8XX_SFUNC(smb4den);
949
951
NPCM8XX_SFUNC(smb5);
950
952
NPCM8XX_SFUNC(smb5b);
951
953
NPCM8XX_SFUNC(smb5c);
···
1052
1056
NPCM8XX_SFUNC(spi3cs3);
1053
1057
NPCM8XX_SFUNC(spi0cs1);
1054
1058
NPCM8XX_SFUNC(lpc);
1055
-
NPCM8XX_SFUNC(lpcclk);
1056
1059
NPCM8XX_SFUNC(espi);
1057
1060
NPCM8XX_SFUNC(lkgpo0);
1058
1061
NPCM8XX_SFUNC(lkgpo1);
···
1167
1172
NPCM8XX_MKFUNC(smb4b),
1168
1173
NPCM8XX_MKFUNC(smb4c),
1169
1174
NPCM8XX_MKFUNC(smb4d),
1170
-
NPCM8XX_MKFUNC(smb4den),
1171
1175
NPCM8XX_MKFUNC(smb5),
1172
1176
NPCM8XX_MKFUNC(smb5b),
1173
1177
NPCM8XX_MKFUNC(smb5c),
···
1274
1280
NPCM8XX_MKFUNC(spi3cs3),
1275
1281
NPCM8XX_MKFUNC(spi0cs1),
1276
1282
NPCM8XX_MKFUNC(lpc),
1277
-
NPCM8XX_MKFUNC(lpcclk),
1278
1283
NPCM8XX_MKFUNC(espi),
1279
1284
NPCM8XX_MKFUNC(lkgpo0),
1280
1285
NPCM8XX_MKFUNC(lkgpo1),
···
1340
1347
NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1341
1348
NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1342
1349
NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2b, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW),
1343
-
NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, smb4den, I2CSEGSEL, 23, none, NONE, 0, none, NONE, 0, SLEW),
1350
+
NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1344
1351
NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1345
1352
NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1346
1353
NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW),
···
1358
1365
NPCM8XX_PINCFG(32, spi0cs1, MFSEL1, 3, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1359
1366
NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1360
1367
NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1368
+
NPCM8XX_PINCFG(35, gpi35, MFSEL5, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1369
+
NPCM8XX_PINCFG(36, gpi36, MFSEL5, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1361
1370
NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1362
1371
NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1363
1372
NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
···
1433
1438
NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1434
1439
NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1435
1440
NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1436
-
NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
1437
-
NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0),
1438
-
NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1439
-
NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1441
+
NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW),
1442
+
NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW),
1443
+
NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1444
+
NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1440
1445
NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1441
1446
NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1442
1447
NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
···
1485
1490
NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1486
1491
NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1487
1492
NPCM8XX_PINCFG(161, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1488
-
NPCM8XX_PINCFG(162, serirq, MFSEL1, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1493
+
NPCM8XX_PINCFG(162, clkrun, MFSEL3, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1489
1494
NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1490
1495
NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1491
1496
NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1492
1497
NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1493
1498
NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1494
-
NPCM8XX_PINCFG(168, lpcclk, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1499
+
NPCM8XX_PINCFG(168, serirq, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1495
1500
NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1496
1501
NPCM8XX_PINCFG(170, smi, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1497
1502
NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
···
1510
1515
NPCM8XX_PINCFG(184, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1511
1516
NPCM8XX_PINCFG(185, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1512
1517
NPCM8XX_PINCFG(186, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1513
-
NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, 0),
1518
+
NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, SLEW),
1514
1519
NPCM8XX_PINCFG(188, gpio1889, MFSEL7, 25, spi3cs2, MFSEL4, 18, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1515
1520
NPCM8XX_PINCFG(189, gpio1889, MFSEL7, 25, spi3cs3, MFSEL4, 19, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1516
1521
NPCM8XX_PINCFG(190, nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)),
1517
-
NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */
1518
-
NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */
1522
+
NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, SLEW), /* XX */
1523
+
NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, SLEW), /* XX */
1519
1524
NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1520
-
NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1521
-
NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1522
-
NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1523
-
NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1524
-
NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1525
-
NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1525
+
NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1526
+
NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1527
+
NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1528
+
NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1529
+
NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1530
+
NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1526
1531
NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1527
1532
NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO),
1528
-
NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)),
1533
+
NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1529
1534
NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)),
1530
1535
NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */
1531
1536
NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */
···
1548
1553
NPCM8XX_PINCFG(226, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
1549
1554
NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1550
1555
NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1551
-
NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1552
-
NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1556
+
NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
1557
+
NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW),
1553
1558
NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 12) | SLEW),
1554
-
NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEWLPC), /* slewlpc ? */
1559
+
NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), /* slewlpc ? */
1555
1560
NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1556
1561
NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1557
1562
NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
···
1562
1567
NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1563
1568
NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1564
1569
NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1565
-
NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
1570
+
NPCM8XX_PINCFG(250, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW),
1571
+
NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0),
1566
1572
NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
1567
1573
NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
1568
1574
NPCM8XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
···
1606
1610
PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
1607
1611
PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
1608
1612
PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
1613
+
PINCTRL_PIN(35, "MCBPCK/GPI35_AHB2PCI_DIS"),
1614
+
PINCTRL_PIN(36, "SYSBPCK/GPI36"),
1609
1615
PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
1610
1616
PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
1611
1617
PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
···
2042
2044
const unsigned int *pin = &offset;
2043
2045
int mode = fn_gpio;
2044
2046
2045
-
if (pin[0] >= 183 && pin[0] <= 189)
2047
+
if ((pin[0] >= 183 && pin[0] <= 189) || pin[0] == 35 || pin[0] == 36)
2046
2048
mode = pincfg[pin[0]].fn0;
2047
2049
2048
2050
npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);
+35
-16
drivers/pinctrl/nxp/pinctrl-s32cc.c
+35
-16
drivers/pinctrl/nxp/pinctrl-s32cc.c
···
2
2
/*
3
3
* Core driver for the S32 CC (Common Chassis) pin controller
4
4
*
5
-
* Copyright 2017-2022 NXP
5
+
* Copyright 2017-2022,2024 NXP
6
6
* Copyright (C) 2022 SUSE LLC
7
7
* Copyright 2015-2016 Freescale Semiconductor, Inc.
8
8
*/
···
38
38
#define S32_MSCR_IBE BIT(19)
39
39
#define S32_MSCR_ODE BIT(20)
40
40
#define S32_MSCR_OBE BIT(21)
41
+
42
+
enum s32_write_type {
43
+
S32_PINCONF_UPDATE_ONLY,
44
+
S32_PINCONF_OVERWRITE,
45
+
};
41
46
42
47
static struct regmap_config s32_regmap_config = {
43
48
.reg_bits = 32,
···
436
431
unsigned int offset,
437
432
bool input)
438
433
{
439
-
unsigned int config;
434
+
/* Always enable IBE for GPIOs. This allows us to read the
435
+
* actual line value and compare it with the one set.
436
+
*/
437
+
unsigned int config = S32_MSCR_IBE;
440
438
unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE;
441
439
442
-
if (input) {
443
-
/* Disable output buffer and enable input buffer */
444
-
config = S32_MSCR_IBE;
445
-
} else {
446
-
/* Disable input buffer and enable output buffer */
447
-
config = S32_MSCR_OBE;
448
-
}
440
+
/* Enable output buffer */
441
+
if (!input)
442
+
config |= S32_MSCR_OBE;
449
443
450
444
return s32_regmap_update(pctldev, offset, mask, config);
451
445
}
···
515
511
*config |= S32_MSCR_ODE;
516
512
*mask |= S32_MSCR_ODE;
517
513
break;
514
+
case PIN_CONFIG_DRIVE_PUSH_PULL:
515
+
*config &= ~S32_MSCR_ODE;
516
+
*mask |= S32_MSCR_ODE;
517
+
break;
518
518
case PIN_CONFIG_OUTPUT_ENABLE:
519
519
if (arg)
520
520
*config |= S32_MSCR_OBE;
···
557
549
return 0;
558
550
}
559
551
560
-
static int s32_pinconf_mscr_update(struct pinctrl_dev *pctldev,
552
+
static int s32_pinconf_mscr_write(struct pinctrl_dev *pctldev,
561
553
unsigned int pin_id,
562
554
unsigned long *configs,
563
-
unsigned int num_configs)
555
+
unsigned int num_configs,
556
+
enum s32_write_type write_type)
564
557
{
565
558
struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
566
559
unsigned int config = 0, mask = 0;
···
580
571
return ret;
581
572
}
582
573
574
+
/* If the MSCR configuration has to be written,
575
+
* the SSS field should not be touched.
576
+
*/
577
+
if (write_type == S32_PINCONF_OVERWRITE)
578
+
mask = (unsigned int)~S32_MSCR_SSS_MASK;
579
+
583
580
if (!config && !mask)
584
581
return 0;
585
582
586
-
dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id, config);
583
+
if (write_type == S32_PINCONF_OVERWRITE)
584
+
dev_dbg(ipctl->dev, "set: pin %u cfg 0x%x\n", pin_id, config);
585
+
else
586
+
dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id,
587
+
config);
587
588
588
589
return s32_regmap_update(pctldev, pin_id, mask, config);
589
590
}
···
609
590
unsigned int pin_id, unsigned long *configs,
610
591
unsigned int num_configs)
611
592
{
612
-
return s32_pinconf_mscr_update(pctldev, pin_id, configs,
613
-
num_configs);
593
+
return s32_pinconf_mscr_write(pctldev, pin_id, configs,
594
+
num_configs, S32_PINCONF_UPDATE_ONLY);
614
595
}
615
596
616
597
static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector,
···
623
604
624
605
grp = &info->groups[selector];
625
606
for (i = 0; i < grp->data.npins; i++) {
626
-
ret = s32_pinconf_mscr_update(pctldev, grp->data.pins[i],
627
-
configs, num_configs);
607
+
ret = s32_pinconf_mscr_write(pctldev, grp->data.pins[i],
608
+
configs, num_configs, S32_PINCONF_OVERWRITE);
628
609
if (ret)
629
610
return ret;
630
611
}
+2
drivers/pinctrl/pinconf-generic.c
+2
drivers/pinctrl/pinconf-generic.c
···
44
44
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
45
45
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
46
46
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
47
+
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_UV, "input schmitt threshold", "uV", true),
47
48
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
48
49
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
49
50
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
···
178
177
{ "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
179
178
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
180
179
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
180
+
{ "input-schmitt-microvolts", PIN_CONFIG_INPUT_SCHMITT_UV, 0 },
181
181
{ "low-power-disable", PIN_CONFIG_MODE_LOW_POWER, 0 },
182
182
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
183
183
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
+575
drivers/pinctrl/pinctrl-eyeq5.c
+575
drivers/pinctrl/pinctrl-eyeq5.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Pinctrl driver for the Mobileye EyeQ5 platform.
4
+
*
5
+
* The registers are located in a syscon region called OLB. There are two pin
6
+
* banks, each being controlled by 5 registers (see enum eq5p_regs) for
7
+
* pull-down, pull-up, drive strength and muxing.
8
+
*
9
+
* For each pin, muxing is between two functions: (0) GPIO or (1) another one
10
+
* that is pin-dependent. Functions are declared statically in this driver.
11
+
*
12
+
* We create pinctrl groups that are 1:1 equivalent to pins: each group has a
13
+
* single pin, and its index/selector is the pin number.
14
+
*
15
+
* We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
16
+
*
17
+
* Copyright (C) 2024 Mobileye Vision Technologies Ltd.
18
+
*/
19
+
20
+
#include <linux/array_size.h>
21
+
#include <linux/auxiliary_bus.h>
22
+
#include <linux/bits.h>
23
+
#include <linux/bug.h>
24
+
#include <linux/device.h>
25
+
#include <linux/err.h>
26
+
#include <linux/errno.h>
27
+
#include <linux/io.h>
28
+
#include <linux/mod_devicetable.h>
29
+
#include <linux/seq_file.h>
30
+
#include <linux/slab.h>
31
+
#include <linux/types.h>
32
+
33
+
#include <linux/pinctrl/pinconf-generic.h>
34
+
#include <linux/pinctrl/pinconf.h>
35
+
#include <linux/pinctrl/pinctrl.h>
36
+
#include <linux/pinctrl/pinmux.h>
37
+
38
+
#include "core.h"
39
+
#include "pinctrl-utils.h"
40
+
41
+
struct eq5p_pinctrl {
42
+
struct pinctrl_desc desc;
43
+
void __iomem *base;
44
+
};
45
+
46
+
enum eq5p_bank {
47
+
EQ5P_BANK_A,
48
+
EQ5P_BANK_B,
49
+
50
+
EQ5P_BANK_COUNT,
51
+
};
52
+
53
+
enum eq5p_regs {
54
+
EQ5P_PD,
55
+
EQ5P_PU,
56
+
EQ5P_DS_LOW,
57
+
EQ5P_DS_HIGH,
58
+
EQ5P_IOCR,
59
+
60
+
EQ5P_REG_COUNT,
61
+
};
62
+
63
+
static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {
64
+
[EQ5P_BANK_A] = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
65
+
[EQ5P_BANK_B] = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},
66
+
};
67
+
68
+
/*
69
+
* Drive strength; two bits per pin.
70
+
*/
71
+
#define EQ5P_DS_MASK GENMASK(1, 0)
72
+
73
+
/*
74
+
* Comments to the right of each pin are the "signal name" in the datasheet.
75
+
*/
76
+
static const struct pinctrl_pin_desc eq5p_pins[] = {
77
+
/* Bank A */
78
+
PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */
79
+
PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */
80
+
PINCTRL_PIN(2, "PA2"), /* A2_TIMER1_CK */
81
+
PINCTRL_PIN(3, "PA3"), /* A3_TIMER1_EOC */
82
+
PINCTRL_PIN(4, "PA4"), /* A4_TIMER2_CK */
83
+
PINCTRL_PIN(5, "PA5"), /* A5_TIMER2_EOC */
84
+
PINCTRL_PIN(6, "PA6"), /* A6_TIMER5_EXT_INCAP1 */
85
+
PINCTRL_PIN(7, "PA7"), /* A7_TIMER5_EXT_INCAP2 */
86
+
PINCTRL_PIN(8, "PA8"), /* A8_TIMER5_EXT_OUTCMP1 */
87
+
PINCTRL_PIN(9, "PA9"), /* A9_TIMER5_EXT_OUTCMP2 */
88
+
PINCTRL_PIN(10, "PA10"), /* A10_UART_0_TX */
89
+
PINCTRL_PIN(11, "PA11"), /* A11_UART_0_RX */
90
+
PINCTRL_PIN(12, "PA12"), /* A12_UART_1_TX */
91
+
PINCTRL_PIN(13, "PA13"), /* A13_UART_1_RX */
92
+
PINCTRL_PIN(14, "PA14"), /* A14_CAN_0_TX */
93
+
PINCTRL_PIN(15, "PA15"), /* A15_CAN_0_RX */
94
+
PINCTRL_PIN(16, "PA16"), /* A16_CAN_1_TX */
95
+
PINCTRL_PIN(17, "PA17"), /* A17_CAN_1_RX */
96
+
PINCTRL_PIN(18, "PA18"), /* A18_SPI_0_DO */
97
+
PINCTRL_PIN(19, "PA19"), /* A19_SPI_0_DI */
98
+
PINCTRL_PIN(20, "PA20"), /* A20_SPI_0_CK */
99
+
PINCTRL_PIN(21, "PA21"), /* A21_SPI_0_CS0 */
100
+
PINCTRL_PIN(22, "PA22"), /* A22_SPI_0_CS1 */
101
+
PINCTRL_PIN(23, "PA23"), /* A23_SPI_1_DO */
102
+
PINCTRL_PIN(24, "PA24"), /* A24_SPI_1_DI */
103
+
PINCTRL_PIN(25, "PA25"), /* A25_SPI_1_CK */
104
+
PINCTRL_PIN(26, "PA26"), /* A26_SPI_1_CS0 */
105
+
PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */
106
+
PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */
107
+
108
+
#define EQ5P_PIN_OFFSET_BANK_B 29
109
+
110
+
/* Bank B */
111
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */
112
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */
113
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */
114
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */
115
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */
116
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */
117
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */
118
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */
119
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */
120
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */
121
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
122
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
123
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
124
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
125
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
126
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
127
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
128
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
129
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */
130
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */
131
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */
132
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */
133
+
PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */
134
+
};
135
+
136
+
static const char * const gpio_groups[] = {
137
+
/* Bank A */
138
+
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
139
+
"PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
140
+
"PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23",
141
+
"PA24", "PA25", "PA26", "PA27", "PA28",
142
+
143
+
/* Bank B */
144
+
"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
145
+
"PB8", "PB9", "PB10", "PB11", "PB12", "PB13", "PB14", "PB15",
146
+
"PB16", "PB17", "PB18", "PB19", "PB20", "PB21", "PB22",
147
+
};
148
+
149
+
/* Groups of functions on bank A */
150
+
static const char * const timer0_groups[] = { "PA0", "PA1" };
151
+
static const char * const timer1_groups[] = { "PA2", "PA3" };
152
+
static const char * const timer2_groups[] = { "PA4", "PA5" };
153
+
static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" };
154
+
static const char * const uart0_groups[] = { "PA10", "PA11" };
155
+
static const char * const uart1_groups[] = { "PA12", "PA13" };
156
+
static const char * const can0_groups[] = { "PA14", "PA15" };
157
+
static const char * const can1_groups[] = { "PA16", "PA17" };
158
+
static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" };
159
+
static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" };
160
+
static const char * const refclk0_groups[] = { "PA28" };
161
+
162
+
/* Groups of functions on bank B */
163
+
static const char * const timer3_groups[] = { "PB0", "PB1" };
164
+
static const char * const timer4_groups[] = { "PB2", "PB3" };
165
+
static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" };
166
+
static const char * const uart2_groups[] = { "PB8", "PB9" };
167
+
static const char * const can2_groups[] = { "PB10", "PB11" };
168
+
static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" };
169
+
static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" };
170
+
static const char * const mclk0_groups[] = { "PB22" };
171
+
172
+
static const struct pinfunction eq5p_functions[] = {
173
+
/* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */
174
+
PINCTRL_PINFUNCTION("gpio", gpio_groups, ARRAY_SIZE(gpio_groups)),
175
+
#define GPIO_FUNC_SELECTOR 0
176
+
177
+
/* Bank A functions */
178
+
PINCTRL_PINFUNCTION("timer0", timer0_groups, ARRAY_SIZE(timer0_groups)),
179
+
PINCTRL_PINFUNCTION("timer1", timer1_groups, ARRAY_SIZE(timer1_groups)),
180
+
PINCTRL_PINFUNCTION("timer2", timer2_groups, ARRAY_SIZE(timer2_groups)),
181
+
PINCTRL_PINFUNCTION("timer5", timer5_groups, ARRAY_SIZE(timer5_groups)),
182
+
PINCTRL_PINFUNCTION("uart0", uart0_groups, ARRAY_SIZE(uart0_groups)),
183
+
PINCTRL_PINFUNCTION("uart1", uart1_groups, ARRAY_SIZE(uart1_groups)),
184
+
PINCTRL_PINFUNCTION("can0", can0_groups, ARRAY_SIZE(can0_groups)),
185
+
PINCTRL_PINFUNCTION("can1", can1_groups, ARRAY_SIZE(can1_groups)),
186
+
PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
187
+
PINCTRL_PINFUNCTION("spi1", spi1_groups, ARRAY_SIZE(spi1_groups)),
188
+
PINCTRL_PINFUNCTION("refclk0", refclk0_groups, ARRAY_SIZE(refclk0_groups)),
189
+
190
+
/* Bank B functions */
191
+
PINCTRL_PINFUNCTION("timer3", timer3_groups, ARRAY_SIZE(timer3_groups)),
192
+
PINCTRL_PINFUNCTION("timer4", timer4_groups, ARRAY_SIZE(timer4_groups)),
193
+
PINCTRL_PINFUNCTION("timer6", timer6_groups, ARRAY_SIZE(timer6_groups)),
194
+
PINCTRL_PINFUNCTION("uart2", uart2_groups, ARRAY_SIZE(uart2_groups)),
195
+
PINCTRL_PINFUNCTION("can2", can2_groups, ARRAY_SIZE(can2_groups)),
196
+
PINCTRL_PINFUNCTION("spi2", spi2_groups, ARRAY_SIZE(spi2_groups)),
197
+
PINCTRL_PINFUNCTION("spi3", spi3_groups, ARRAY_SIZE(spi3_groups)),
198
+
PINCTRL_PINFUNCTION("mclk0", mclk0_groups, ARRAY_SIZE(mclk0_groups)),
199
+
};
200
+
201
+
static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
202
+
enum eq5p_bank bank, enum eq5p_regs reg,
203
+
u32 mask, u32 val)
204
+
{
205
+
void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];
206
+
207
+
writel((readl(ptr) & ~mask) | (val & mask), ptr);
208
+
}
209
+
210
+
static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,
211
+
enum eq5p_bank bank, enum eq5p_regs reg, int offset)
212
+
{
213
+
u32 val = readl(pctrl->base + eq5p_regs[bank][reg]);
214
+
215
+
if (WARN_ON(offset > 31))
216
+
return false;
217
+
218
+
return (val & BIT(offset)) != 0;
219
+
}
220
+
221
+
static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin)
222
+
{
223
+
if (pin < EQ5P_PIN_OFFSET_BANK_B)
224
+
return EQ5P_BANK_A;
225
+
else
226
+
return EQ5P_BANK_B;
227
+
}
228
+
229
+
static unsigned int eq5p_pin_to_offset(unsigned int pin)
230
+
{
231
+
if (pin < EQ5P_PIN_OFFSET_BANK_B)
232
+
return pin;
233
+
else
234
+
return pin - EQ5P_PIN_OFFSET_BANK_B;
235
+
}
236
+
237
+
static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
238
+
{
239
+
return ARRAY_SIZE(eq5p_pins);
240
+
}
241
+
242
+
static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
243
+
unsigned int selector)
244
+
{
245
+
return pctldev->desc->pins[selector].name;
246
+
}
247
+
248
+
static int eq5p_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
249
+
unsigned int selector,
250
+
const unsigned int **pins,
251
+
unsigned int *num_pins)
252
+
{
253
+
*pins = &pctldev->desc->pins[selector].number;
254
+
*num_pins = 1;
255
+
return 0;
256
+
}
257
+
258
+
static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
259
+
unsigned long *config)
260
+
{
261
+
enum pin_config_param param = pinconf_to_config_param(*config);
262
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
263
+
unsigned int offset = eq5p_pin_to_offset(pin);
264
+
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
265
+
u32 val_ds, arg;
266
+
bool pd, pu;
267
+
268
+
pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);
269
+
pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);
270
+
271
+
switch (param) {
272
+
case PIN_CONFIG_BIAS_DISABLE:
273
+
arg = !(pd || pu);
274
+
break;
275
+
case PIN_CONFIG_BIAS_PULL_DOWN:
276
+
arg = pd;
277
+
break;
278
+
case PIN_CONFIG_BIAS_PULL_UP:
279
+
arg = pu;
280
+
break;
281
+
case PIN_CONFIG_DRIVE_STRENGTH:
282
+
offset *= 2; /* two bits per pin */
283
+
if (offset >= 32) {
284
+
val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);
285
+
offset -= 32;
286
+
} else {
287
+
val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);
288
+
}
289
+
arg = (val_ds >> offset) & EQ5P_DS_MASK;
290
+
break;
291
+
default:
292
+
return -ENOTSUPP;
293
+
}
294
+
295
+
*config = pinconf_to_config_packed(param, arg);
296
+
return 0;
297
+
}
298
+
299
+
static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
300
+
struct seq_file *s,
301
+
unsigned int pin)
302
+
{
303
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
304
+
const char *pin_name = pctrl->desc.pins[pin].name;
305
+
unsigned int offset = eq5p_pin_to_offset(pin);
306
+
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
307
+
const char *func_name, *bias;
308
+
unsigned long ds_config;
309
+
u32 drive_strength;
310
+
bool pd, pu;
311
+
int i, j;
312
+
313
+
/*
314
+
* First, let's get the function name. All pins have only two functions:
315
+
* GPIO (IOCR == 0) and something else (IOCR == 1).
316
+
*/
317
+
if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {
318
+
func_name = NULL;
319
+
for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) {
320
+
if (i == GPIO_FUNC_SELECTOR)
321
+
continue;
322
+
323
+
for (j = 0; j < eq5p_functions[i].ngroups; j++) {
324
+
/* Groups and pins are the same thing for us. */
325
+
const char *x = eq5p_functions[i].groups[j];
326
+
327
+
if (strcmp(x, pin_name) == 0) {
328
+
func_name = eq5p_functions[i].name;
329
+
break;
330
+
}
331
+
}
332
+
333
+
if (func_name)
334
+
break;
335
+
}
336
+
337
+
/*
338
+
* We have not found the function attached to this pin, this
339
+
* should never occur as all pins have exactly two functions.
340
+
*/
341
+
if (!func_name)
342
+
func_name = "unknown";
343
+
} else {
344
+
func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name;
345
+
}
346
+
347
+
/* Second, we retrieve the bias. */
348
+
pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);
349
+
pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);
350
+
if (pd && pu)
351
+
bias = "both";
352
+
else if (pd && !pu)
353
+
bias = "pulldown";
354
+
else if (!pd && pu)
355
+
bias = "pullup";
356
+
else
357
+
bias = "none";
358
+
359
+
/* Third, we get the drive strength. */
360
+
ds_config = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 0);
361
+
eq5p_pinconf_get(pctldev, pin, &ds_config);
362
+
drive_strength = pinconf_to_config_argument(ds_config);
363
+
364
+
seq_printf(s, "function=%s bias=%s drive_strength=%d",
365
+
func_name, bias, drive_strength);
366
+
}
367
+
368
+
static const struct pinctrl_ops eq5p_pinctrl_ops = {
369
+
.get_groups_count = eq5p_pinctrl_get_groups_count,
370
+
.get_group_name = eq5p_pinctrl_get_group_name,
371
+
.get_group_pins = eq5p_pinctrl_get_group_pins,
372
+
.pin_dbg_show = eq5p_pinctrl_pin_dbg_show,
373
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
374
+
.dt_free_map = pinctrl_utils_free_map,
375
+
};
376
+
377
+
static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
378
+
{
379
+
return ARRAY_SIZE(eq5p_functions);
380
+
}
381
+
382
+
static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev,
383
+
unsigned int selector)
384
+
{
385
+
return eq5p_functions[selector].name;
386
+
}
387
+
388
+
static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
389
+
unsigned int selector,
390
+
const char * const **groups,
391
+
unsigned int *num_groups)
392
+
{
393
+
*groups = eq5p_functions[selector].groups;
394
+
*num_groups = eq5p_functions[selector].ngroups;
395
+
return 0;
396
+
}
397
+
398
+
static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev,
399
+
unsigned int func_selector, unsigned int pin)
400
+
{
401
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
402
+
const char *func_name = eq5p_functions[func_selector].name;
403
+
const char *group_name = pctldev->desc->pins[pin].name;
404
+
bool is_gpio = func_selector == GPIO_FUNC_SELECTOR;
405
+
unsigned int offset = eq5p_pin_to_offset(pin);
406
+
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
407
+
u32 mask, val;
408
+
409
+
dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name);
410
+
411
+
mask = BIT(offset);
412
+
val = is_gpio ? 0 : mask;
413
+
eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val);
414
+
return 0;
415
+
}
416
+
417
+
static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
418
+
struct pinctrl_gpio_range *range,
419
+
unsigned int pin)
420
+
{
421
+
/* Pin numbers and group selectors are the same thing in our case. */
422
+
return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin);
423
+
}
424
+
425
+
static const struct pinmux_ops eq5p_pinmux_ops = {
426
+
.get_functions_count = eq5p_pinmux_get_functions_count,
427
+
.get_function_name = eq5p_pinmux_get_function_name,
428
+
.get_function_groups = eq5p_pinmux_get_function_groups,
429
+
.set_mux = eq5p_pinmux_set_mux,
430
+
.gpio_request_enable = eq5p_pinmux_gpio_request_enable,
431
+
.strict = true,
432
+
};
433
+
434
+
static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev,
435
+
unsigned int pin, u32 arg)
436
+
{
437
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
438
+
unsigned int offset = eq5p_pin_to_offset(pin);
439
+
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
440
+
unsigned int reg;
441
+
u32 mask, val;
442
+
443
+
if (arg & ~EQ5P_DS_MASK) {
444
+
dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg);
445
+
return -EINVAL;
446
+
}
447
+
448
+
offset *= 2; /* two bits per pin */
449
+
450
+
if (offset >= 32) {
451
+
reg = EQ5P_DS_HIGH;
452
+
offset -= 32;
453
+
} else {
454
+
reg = EQ5P_DS_LOW;
455
+
}
456
+
457
+
mask = EQ5P_DS_MASK << offset;
458
+
val = arg << offset;
459
+
eq5p_update_bits(pctrl, bank, reg, mask, val);
460
+
return 0;
461
+
}
462
+
463
+
static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
464
+
unsigned long *configs, unsigned int num_configs)
465
+
{
466
+
struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
467
+
const char *pin_name = pctldev->desc->pins[pin].name;
468
+
unsigned int offset = eq5p_pin_to_offset(pin);
469
+
enum eq5p_bank bank = eq5p_pin_to_bank(pin);
470
+
struct device *dev = pctldev->dev;
471
+
u32 val = BIT(offset);
472
+
unsigned int i;
473
+
474
+
for (i = 0; i < num_configs; i++) {
475
+
enum pin_config_param param = pinconf_to_config_param(configs[i]);
476
+
u32 arg = pinconf_to_config_argument(configs[i]);
477
+
478
+
switch (param) {
479
+
case PIN_CONFIG_BIAS_DISABLE:
480
+
dev_dbg(dev, "pin=%s bias_disable\n", pin_name);
481
+
482
+
eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);
483
+
eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);
484
+
break;
485
+
486
+
case PIN_CONFIG_BIAS_PULL_DOWN:
487
+
dev_dbg(dev, "pin=%s bias_pull_down arg=%u\n",
488
+
pin_name, arg);
489
+
490
+
if (arg == 0) /* cannot connect to GND */
491
+
return -ENOTSUPP;
492
+
493
+
eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val);
494
+
eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);
495
+
break;
496
+
497
+
case PIN_CONFIG_BIAS_PULL_UP:
498
+
dev_dbg(dev, "pin=%s bias_pull_up arg=%u\n",
499
+
pin_name, arg);
500
+
501
+
if (arg == 0) /* cannot connect to VDD */
502
+
return -ENOTSUPP;
503
+
504
+
eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);
505
+
eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val);
506
+
break;
507
+
508
+
case PIN_CONFIG_DRIVE_STRENGTH:
509
+
dev_dbg(dev, "pin=%s drive_strength arg=%u\n",
510
+
pin_name, arg);
511
+
512
+
eq5p_pinconf_set_drive_strength(pctldev, pin, arg);
513
+
break;
514
+
515
+
default:
516
+
dev_err(dev, "Unsupported pinconf %u\n", param);
517
+
return -ENOTSUPP;
518
+
}
519
+
}
520
+
521
+
return 0;
522
+
}
523
+
524
+
static const struct pinconf_ops eq5p_pinconf_ops = {
525
+
.is_generic = true,
526
+
.pin_config_get = eq5p_pinconf_get,
527
+
.pin_config_set = eq5p_pinconf_set,
528
+
/* Pins and groups are equivalent in this driver. */
529
+
.pin_config_group_get = eq5p_pinconf_get,
530
+
.pin_config_group_set = eq5p_pinconf_set,
531
+
};
532
+
533
+
static int eq5p_probe(struct auxiliary_device *adev,
534
+
const struct auxiliary_device_id *id)
535
+
{
536
+
struct device *dev = &adev->dev;
537
+
struct pinctrl_dev *pctldev;
538
+
struct eq5p_pinctrl *pctrl;
539
+
int ret;
540
+
541
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
542
+
if (!pctrl)
543
+
return -ENOMEM;
544
+
545
+
pctrl->base = (void __iomem *)dev_get_platdata(dev);
546
+
pctrl->desc.name = dev_name(dev);
547
+
pctrl->desc.pins = eq5p_pins;
548
+
pctrl->desc.npins = ARRAY_SIZE(eq5p_pins);
549
+
pctrl->desc.pctlops = &eq5p_pinctrl_ops;
550
+
pctrl->desc.pmxops = &eq5p_pinmux_ops;
551
+
pctrl->desc.confops = &eq5p_pinconf_ops;
552
+
pctrl->desc.owner = THIS_MODULE;
553
+
554
+
ret = devm_pinctrl_register_and_init(dev, &pctrl->desc, pctrl, &pctldev);
555
+
if (ret)
556
+
return dev_err_probe(dev, ret, "failed registering pinctrl device\n");
557
+
558
+
ret = pinctrl_enable(pctldev);
559
+
if (ret)
560
+
return dev_err_probe(dev, ret, "failed enabling pinctrl device\n");
561
+
562
+
return 0;
563
+
}
564
+
565
+
static const struct auxiliary_device_id eq5p_id_table[] = {
566
+
{ .name = "clk_eyeq.pinctrl" },
567
+
{}
568
+
};
569
+
MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table);
570
+
571
+
static struct auxiliary_driver eq5p_driver = {
572
+
.probe = eq5p_probe,
573
+
.id_table = eq5p_id_table,
574
+
};
575
+
module_auxiliary_driver(eq5p_driver);
+8
-27
drivers/pinctrl/pinctrl-k210.c
+8
-27
drivers/pinctrl/pinctrl-k210.c
···
925
925
struct device *dev = &pdev->dev;
926
926
struct device_node *np = dev->of_node;
927
927
struct k210_fpioa_data *pdata;
928
-
int ret;
929
928
930
929
dev_info(dev, "K210 FPIOA pin controller\n");
931
930
···
939
940
if (IS_ERR(pdata->fpioa))
940
941
return PTR_ERR(pdata->fpioa);
941
942
942
-
pdata->clk = devm_clk_get(dev, "ref");
943
+
pdata->clk = devm_clk_get_enabled(dev, "ref");
943
944
if (IS_ERR(pdata->clk))
944
945
return PTR_ERR(pdata->clk);
945
946
946
-
ret = clk_prepare_enable(pdata->clk);
947
-
if (ret)
948
-
return ret;
949
-
950
-
pdata->pclk = devm_clk_get_optional(dev, "pclk");
951
-
if (!IS_ERR(pdata->pclk)) {
952
-
ret = clk_prepare_enable(pdata->pclk);
953
-
if (ret)
954
-
goto disable_clk;
955
-
}
947
+
pdata->pclk = devm_clk_get_optional_enabled(dev, "pclk");
948
+
if (IS_ERR(pdata->pclk))
949
+
return PTR_ERR(pdata->pclk);
956
950
957
951
pdata->sysctl_map =
958
952
syscon_regmap_lookup_by_phandle_args(np,
959
953
"canaan,k210-sysctl-power",
960
954
1, &pdata->power_offset);
961
-
if (IS_ERR(pdata->sysctl_map)) {
962
-
ret = PTR_ERR(pdata->sysctl_map);
963
-
goto disable_pclk;
964
-
}
955
+
if (IS_ERR(pdata->sysctl_map))
956
+
return PTR_ERR(pdata->sysctl_map);
965
957
966
958
k210_fpioa_init_ties(pdata);
967
959
968
960
pdata->pctl = pinctrl_register(&k210_pinctrl_desc, dev, (void *)pdata);
969
-
if (IS_ERR(pdata->pctl)) {
970
-
ret = PTR_ERR(pdata->pctl);
971
-
goto disable_pclk;
972
-
}
961
+
if (IS_ERR(pdata->pctl))
962
+
return PTR_ERR(pdata->pctl);
973
963
974
964
return 0;
975
-
976
-
disable_pclk:
977
-
clk_disable_unprepare(pdata->pclk);
978
-
disable_clk:
979
-
clk_disable_unprepare(pdata->clk);
980
-
981
-
return ret;
982
965
}
983
966
984
967
static const struct of_device_id k210_fpioa_dt_ids[] = {
+207
drivers/pinctrl/pinctrl-rockchip.c
+207
drivers/pinctrl/pinctrl-rockchip.c
···
84
84
}, \
85
85
}
86
86
87
+
#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
88
+
iom1, iom2, iom3, \
89
+
offset0, offset1, \
90
+
offset2, offset3, pull0, \
91
+
pull1, pull2, pull3) \
92
+
{ \
93
+
.bank_num = id, \
94
+
.nr_pins = pins, \
95
+
.name = label, \
96
+
.iomux = { \
97
+
{ .type = iom0, .offset = offset0 }, \
98
+
{ .type = iom1, .offset = offset1 }, \
99
+
{ .type = iom2, .offset = offset2 }, \
100
+
{ .type = iom3, .offset = offset3 }, \
101
+
}, \
102
+
.pull_type[0] = pull0, \
103
+
.pull_type[1] = pull1, \
104
+
.pull_type[2] = pull2, \
105
+
.pull_type[3] = pull3, \
106
+
}
107
+
87
108
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
88
109
{ \
89
110
.bank_num = id, \
···
1141
1120
if (bank->recalced_mask & BIT(pin))
1142
1121
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1143
1122
1123
+
if (ctrl->type == RK3576) {
1124
+
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1125
+
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1126
+
}
1127
+
1144
1128
if (ctrl->type == RK3588) {
1145
1129
if (bank->bank_num == 0) {
1146
1130
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
···
1259
1233
1260
1234
if (bank->recalced_mask & BIT(pin))
1261
1235
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1236
+
1237
+
if (ctrl->type == RK3576) {
1238
+
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1239
+
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1240
+
}
1262
1241
1263
1242
if (ctrl->type == RK3588) {
1264
1243
if (bank->bank_num == 0) {
···
2069
2038
return 0;
2070
2039
}
2071
2040
2041
+
#define RK3576_DRV_BITS_PER_PIN 4
2042
+
#define RK3576_DRV_PINS_PER_REG 4
2043
+
#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
2044
+
#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
2045
+
#define RK3576_DRV_GPIO1_OFFSET 0x6020
2046
+
#define RK3576_DRV_GPIO2_OFFSET 0x6040
2047
+
#define RK3576_DRV_GPIO3_OFFSET 0x6060
2048
+
#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
2049
+
#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
2050
+
#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
2051
+
2052
+
static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2053
+
int pin_num, struct regmap **regmap,
2054
+
int *reg, u8 *bit)
2055
+
{
2056
+
struct rockchip_pinctrl *info = bank->drvdata;
2057
+
2058
+
*regmap = info->regmap_base;
2059
+
2060
+
if (bank->bank_num == 0 && pin_num < 12)
2061
+
*reg = RK3576_DRV_GPIO0_AL_OFFSET;
2062
+
else if (bank->bank_num == 0)
2063
+
*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2064
+
else if (bank->bank_num == 1)
2065
+
*reg = RK3576_DRV_GPIO1_OFFSET;
2066
+
else if (bank->bank_num == 2)
2067
+
*reg = RK3576_DRV_GPIO2_OFFSET;
2068
+
else if (bank->bank_num == 3)
2069
+
*reg = RK3576_DRV_GPIO3_OFFSET;
2070
+
else if (bank->bank_num == 4 && pin_num < 16)
2071
+
*reg = RK3576_DRV_GPIO4_AL_OFFSET;
2072
+
else if (bank->bank_num == 4 && pin_num < 24)
2073
+
*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2074
+
else if (bank->bank_num == 4)
2075
+
*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2076
+
else
2077
+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2078
+
2079
+
*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
2080
+
*bit = pin_num % RK3576_DRV_PINS_PER_REG;
2081
+
*bit *= RK3576_DRV_BITS_PER_PIN;
2082
+
2083
+
return 0;
2084
+
}
2085
+
2086
+
#define RK3576_PULL_BITS_PER_PIN 2
2087
+
#define RK3576_PULL_PINS_PER_REG 8
2088
+
#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
2089
+
#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
2090
+
#define RK3576_PULL_GPIO1_OFFSET 0x6110
2091
+
#define RK3576_PULL_GPIO2_OFFSET 0x6120
2092
+
#define RK3576_PULL_GPIO3_OFFSET 0x6130
2093
+
#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
2094
+
#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
2095
+
#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
2096
+
2097
+
static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2098
+
int pin_num, struct regmap **regmap,
2099
+
int *reg, u8 *bit)
2100
+
{
2101
+
struct rockchip_pinctrl *info = bank->drvdata;
2102
+
2103
+
*regmap = info->regmap_base;
2104
+
2105
+
if (bank->bank_num == 0 && pin_num < 12)
2106
+
*reg = RK3576_PULL_GPIO0_AL_OFFSET;
2107
+
else if (bank->bank_num == 0)
2108
+
*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2109
+
else if (bank->bank_num == 1)
2110
+
*reg = RK3576_PULL_GPIO1_OFFSET;
2111
+
else if (bank->bank_num == 2)
2112
+
*reg = RK3576_PULL_GPIO2_OFFSET;
2113
+
else if (bank->bank_num == 3)
2114
+
*reg = RK3576_PULL_GPIO3_OFFSET;
2115
+
else if (bank->bank_num == 4 && pin_num < 16)
2116
+
*reg = RK3576_PULL_GPIO4_AL_OFFSET;
2117
+
else if (bank->bank_num == 4 && pin_num < 24)
2118
+
*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2119
+
else if (bank->bank_num == 4)
2120
+
*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2121
+
else
2122
+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2123
+
2124
+
*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
2125
+
*bit = pin_num % RK3576_PULL_PINS_PER_REG;
2126
+
*bit *= RK3576_PULL_BITS_PER_PIN;
2127
+
2128
+
return 0;
2129
+
}
2130
+
2131
+
#define RK3576_SMT_BITS_PER_PIN 1
2132
+
#define RK3576_SMT_PINS_PER_REG 8
2133
+
#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
2134
+
#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
2135
+
#define RK3576_SMT_GPIO1_OFFSET 0x6210
2136
+
#define RK3576_SMT_GPIO2_OFFSET 0x6220
2137
+
#define RK3576_SMT_GPIO3_OFFSET 0x6230
2138
+
#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
2139
+
#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
2140
+
#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
2141
+
2142
+
static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2143
+
int pin_num,
2144
+
struct regmap **regmap,
2145
+
int *reg, u8 *bit)
2146
+
{
2147
+
struct rockchip_pinctrl *info = bank->drvdata;
2148
+
2149
+
*regmap = info->regmap_base;
2150
+
2151
+
if (bank->bank_num == 0 && pin_num < 12)
2152
+
*reg = RK3576_SMT_GPIO0_AL_OFFSET;
2153
+
else if (bank->bank_num == 0)
2154
+
*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2155
+
else if (bank->bank_num == 1)
2156
+
*reg = RK3576_SMT_GPIO1_OFFSET;
2157
+
else if (bank->bank_num == 2)
2158
+
*reg = RK3576_SMT_GPIO2_OFFSET;
2159
+
else if (bank->bank_num == 3)
2160
+
*reg = RK3576_SMT_GPIO3_OFFSET;
2161
+
else if (bank->bank_num == 4 && pin_num < 16)
2162
+
*reg = RK3576_SMT_GPIO4_AL_OFFSET;
2163
+
else if (bank->bank_num == 4 && pin_num < 24)
2164
+
*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
2165
+
else if (bank->bank_num == 4)
2166
+
*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
2167
+
else
2168
+
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2169
+
2170
+
*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
2171
+
*bit = pin_num % RK3576_SMT_PINS_PER_REG;
2172
+
*bit *= RK3576_SMT_BITS_PER_PIN;
2173
+
2174
+
return 0;
2175
+
}
2176
+
2072
2177
#define RK3588_PMU1_IOC_REG (0x0000)
2073
2178
#define RK3588_PMU2_IOC_REG (0x4000)
2074
2179
#define RK3588_BUS_IOC_REG (0x8000)
···
2499
2332
rmask_bits = RK3568_DRV_BITS_PER_PIN;
2500
2333
ret = (1 << (strength + 1)) - 1;
2501
2334
goto config;
2335
+
} else if (ctrl->type == RK3576) {
2336
+
rmask_bits = RK3576_DRV_BITS_PER_PIN;
2337
+
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
2338
+
goto config;
2502
2339
}
2503
2340
2504
2341
if (ctrl->type == RV1126) {
···
2640
2469
case RK3368:
2641
2470
case RK3399:
2642
2471
case RK3568:
2472
+
case RK3576:
2643
2473
case RK3588:
2644
2474
pull_type = bank->pull_type[pin_num / 8];
2645
2475
data >>= bit;
···
2700
2528
case RK3368:
2701
2529
case RK3399:
2702
2530
case RK3568:
2531
+
case RK3576:
2703
2532
case RK3588:
2704
2533
pull_type = bank->pull_type[pin_num / 8];
2705
2534
ret = -EINVAL;
···
2966
2793
case RK3368:
2967
2794
case RK3399:
2968
2795
case RK3568:
2796
+
case RK3576:
2969
2797
case RK3588:
2970
2798
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2971
2799
}
···
4123
3949
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4124
3950
};
4125
3951
3952
+
#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
3953
+
PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
3954
+
IOMUX_WIDTH_4BIT, \
3955
+
IOMUX_WIDTH_4BIT, \
3956
+
IOMUX_WIDTH_4BIT, \
3957
+
IOMUX_WIDTH_4BIT, \
3958
+
OFFSET0, OFFSET1, \
3959
+
OFFSET2, OFFSET3, \
3960
+
PULL_TYPE_IO_1V8_ONLY, \
3961
+
PULL_TYPE_IO_1V8_ONLY, \
3962
+
PULL_TYPE_IO_1V8_ONLY, \
3963
+
PULL_TYPE_IO_1V8_ONLY)
3964
+
3965
+
static struct rockchip_pin_bank rk3576_pin_banks[] = {
3966
+
RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
3967
+
RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
3968
+
RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
3969
+
RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
3970
+
RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
3971
+
};
3972
+
3973
+
static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
3974
+
.pin_banks = rk3576_pin_banks,
3975
+
.nr_banks = ARRAY_SIZE(rk3576_pin_banks),
3976
+
.label = "RK3576-GPIO",
3977
+
.type = RK3576,
3978
+
.pull_calc_reg = rk3576_calc_pull_reg_and_bit,
3979
+
.drv_calc_reg = rk3576_calc_drv_reg_and_bit,
3980
+
.schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
3981
+
};
3982
+
4126
3983
static struct rockchip_pin_bank rk3588_pin_banks[] = {
4127
3984
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
4128
3985
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
···
4210
4005
.data = &rk3399_pin_ctrl },
4211
4006
{ .compatible = "rockchip,rk3568-pinctrl",
4212
4007
.data = &rk3568_pin_ctrl },
4008
+
{ .compatible = "rockchip,rk3576-pinctrl",
4009
+
.data = &rk3576_pin_ctrl },
4213
4010
{ .compatible = "rockchip,rk3588-pinctrl",
4214
4011
.data = &rk3588_pin_ctrl },
4215
4012
{},
+1
drivers/pinctrl/pinctrl-rockchip.h
+1
drivers/pinctrl/pinctrl-rockchip.h
+2
-1
drivers/pinctrl/pinctrl-single.c
+2
-1
drivers/pinctrl/pinctrl-single.c
+3
-2
drivers/pinctrl/pinctrl-stmfx.c
+3
-2
drivers/pinctrl/pinctrl-stmfx.c
···
11
11
#include <linux/module.h>
12
12
#include <linux/platform_device.h>
13
13
#include <linux/seq_file.h>
14
+
#include <linux/string_choices.h>
14
15
15
16
#include <linux/pinctrl/pinconf.h>
16
17
#include <linux/pinctrl/pinmux.h>
···
370
369
return;
371
370
372
371
if (dir == GPIO_LINE_DIRECTION_OUT) {
373
-
seq_printf(s, "output %s ", val ? "high" : "low");
372
+
seq_printf(s, "output %s ", str_high_low(val));
374
373
if (type)
375
374
seq_printf(s, "open drain %s internal pull-up ",
376
375
pupd ? "with" : "without");
377
376
else
378
377
seq_puts(s, "push pull no pull ");
379
378
} else {
380
-
seq_printf(s, "input %s ", val ? "high" : "low");
379
+
seq_printf(s, "input %s ", str_high_low(val));
381
380
if (type)
382
381
seq_printf(s, "with internal pull-%s ",
383
382
pupd ? "up" : "down");
+2
-2
drivers/pinctrl/pinctrl-utils.c
+2
-2
drivers/pinctrl/pinctrl-utils.c
···
70
70
if (WARN_ON(*num_maps == *reserved_maps))
71
71
return -ENOSPC;
72
72
73
-
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
74
-
GFP_KERNEL);
73
+
dup_configs = kmemdup_array(configs, num_configs,
74
+
sizeof(*dup_configs), GFP_KERNEL);
75
75
if (!dup_configs)
76
76
return -ENOMEM;
77
77
+1
drivers/pinctrl/pinctrl-zynq.c
+1
drivers/pinctrl/pinctrl-zynq.c
+2
-5
drivers/pinctrl/pinmux.c
+2
-5
drivers/pinctrl/pinmux.c
···
442
442
gname = pctlops->get_group_name(pctldev,
443
443
setting->data.mux.group);
444
444
dev_err_probe(pctldev->dev, ret,
445
-
"could not request pin %d (%s) from group %s "
446
-
" on device %s\n",
445
+
"could not request pin %d (%s) from group %s on device %s\n",
447
446
pins[i], pname, gname,
448
447
pinctrl_dev_get_name(pctldev));
449
448
goto err_pin_request;
···
525
526
gname = pctlops->get_group_name(pctldev,
526
527
setting->data.mux.group);
527
528
dev_warn(pctldev->dev,
528
-
"not freeing pin %d (%s) as part of "
529
-
"deactivating group %s - it is already "
530
-
"used for some other setting",
529
+
"not freeing pin %d (%s) as part of deactivating group %s - it is already used for some other setting",
531
530
pins[i], desc->name, gname);
532
531
}
533
532
}
+1
-1
drivers/pinctrl/realtek/pinctrl-rtd.c
+1
-1
drivers/pinctrl/realtek/pinctrl-rtd.c
+45
-72
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+45
-72
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
16
16
#include <linux/of.h>
17
17
#include <linux/of_irq.h>
18
18
#include <linux/platform_device.h>
19
+
#include <linux/property.h>
19
20
#include <linux/seq_file.h>
20
21
#include <linux/spinlock.h>
21
22
···
52
51
#define PIN_CFG_IO_VMC_QSPI BIT(7)
53
52
#define PIN_CFG_IO_VMC_ETH0 BIT(8)
54
53
#define PIN_CFG_IO_VMC_ETH1 BIT(9)
55
-
#define PIN_CFG_FILONOFF BIT(10)
56
-
#define PIN_CFG_FILNUM BIT(11)
57
-
#define PIN_CFG_FILCLKSEL BIT(12)
58
-
#define PIN_CFG_IOLH_C BIT(13)
59
-
#define PIN_CFG_SOFT_PS BIT(14)
60
-
#define PIN_CFG_OEN BIT(15)
61
-
#define PIN_CFG_NOGPIO_INT BIT(16)
62
-
#define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */
63
-
#define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */
64
-
#define PIN_CFG_ELC BIT(19)
65
-
#define PIN_CFG_IOLH_RZV2H BIT(20)
54
+
#define PIN_CFG_NF BIT(10) /* Digital noise filter */
55
+
#define PIN_CFG_IOLH_C BIT(11)
56
+
#define PIN_CFG_SOFT_PS BIT(12)
57
+
#define PIN_CFG_OEN BIT(13)
58
+
#define PIN_CFG_NOGPIO_INT BIT(14)
59
+
#define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
60
+
#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
61
+
#define PIN_CFG_ELC BIT(17)
62
+
#define PIN_CFG_IOLH_RZV2H BIT(18)
66
63
67
64
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
68
65
#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
···
68
69
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
69
70
(PIN_CFG_IOLH_##group | \
70
71
PIN_CFG_PUPD | \
71
-
PIN_CFG_FILONOFF | \
72
-
PIN_CFG_FILNUM | \
73
-
PIN_CFG_FILCLKSEL)
72
+
PIN_CFG_NF)
74
73
75
74
#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
76
75
PIN_CFG_SR)
···
81
84
PIN_CFG_SR | \
82
85
PIN_CFG_SMT)
83
86
84
-
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
85
-
PIN_CFG_FILONOFF | \
86
-
PIN_CFG_FILNUM | \
87
-
PIN_CFG_FILCLKSEL)
87
+
#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
88
88
89
89
#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
90
90
#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
···
388
394
#ifdef CONFIG_RISCV
389
395
static const u64 r9a07g043f_variable_pin_cfg[] = {
390
396
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
391
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
397
+
PIN_CFG_NF |
392
398
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
393
399
RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
394
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
400
+
PIN_CFG_NF |
395
401
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
396
402
RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
397
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
403
+
PIN_CFG_NF |
398
404
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
399
405
RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
400
406
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
···
425
431
RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
426
432
PIN_CFG_NOGPIO_INT),
427
433
RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
428
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
434
+
PIN_CFG_NF |
429
435
PIN_CFG_NOGPIO_INT),
430
436
};
431
437
#endif
···
522
528
{
523
529
unsigned long *cfgs;
524
530
525
-
cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
526
-
GFP_KERNEL);
531
+
cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
527
532
if (!cfgs)
528
533
return -ENOMEM;
529
534
···
1254
1261
break;
1255
1262
1256
1263
case PIN_CONFIG_OUTPUT_ENABLE:
1257
-
if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
1264
+
if (!(cfg & PIN_CFG_OEN))
1265
+
return -EINVAL;
1266
+
if (!pctrl->data->oen_read)
1258
1267
return -EOPNOTSUPP;
1259
1268
arg = pctrl->data->oen_read(pctrl, _pin);
1260
1269
if (!arg)
···
1385
1390
1386
1391
for (i = 0; i < num_configs; i++) {
1387
1392
param = pinconf_to_config_param(_configs[i]);
1393
+
arg = pinconf_to_config_argument(_configs[i]);
1388
1394
switch (param) {
1389
1395
case PIN_CONFIG_INPUT_ENABLE:
1390
-
arg = pinconf_to_config_argument(_configs[i]);
1391
1396
1392
1397
if (!(cfg & PIN_CFG_IEN))
1393
1398
return -EINVAL;
···
1396
1401
break;
1397
1402
1398
1403
case PIN_CONFIG_OUTPUT_ENABLE:
1399
-
arg = pinconf_to_config_argument(_configs[i]);
1400
-
if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
1404
+
if (!(cfg & PIN_CFG_OEN))
1405
+
return -EINVAL;
1406
+
if (!pctrl->data->oen_write)
1401
1407
return -EOPNOTSUPP;
1402
1408
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
1403
1409
if (ret)
···
1406
1410
break;
1407
1411
1408
1412
case PIN_CONFIG_POWER_SOURCE:
1409
-
settings.power_source = pinconf_to_config_argument(_configs[i]);
1413
+
settings.power_source = arg;
1410
1414
break;
1411
1415
1412
1416
case PIN_CONFIG_SLEW_RATE:
1413
-
arg = pinconf_to_config_argument(_configs[i]);
1414
-
1415
1417
if (!(cfg & PIN_CFG_SR) || arg > 1)
1416
1418
return -EINVAL;
1417
1419
···
1430
1436
break;
1431
1437
1432
1438
case PIN_CONFIG_DRIVE_STRENGTH:
1433
-
arg = pinconf_to_config_argument(_configs[i]);
1434
-
1435
1439
if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1436
1440
return -EINVAL;
1437
1441
···
1449
1457
!hwcfg->drive_strength_ua)
1450
1458
return -EINVAL;
1451
1459
1452
-
settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]);
1460
+
settings.drive_strength_ua = arg;
1453
1461
break;
1454
1462
1455
1463
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
1456
-
arg = pinconf_to_config_argument(_configs[i]);
1457
-
1458
1464
if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1459
1465
return -EINVAL;
1460
1466
···
1470
1480
if (!(cfg & PIN_CFG_IOLH_RZV2H))
1471
1481
return -EINVAL;
1472
1482
1473
-
arg = pinconf_to_config_argument(_configs[i]);
1474
1483
if (arg > 3)
1475
1484
return -EINVAL;
1476
1485
rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
···
1872
1883
#ifdef CONFIG_RISCV
1873
1884
/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
1874
1885
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1875
-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
1876
-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1886
+
PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1877
1887
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
1878
1888
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1879
1889
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
···
1880
1892
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
1881
1893
RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
1882
1894
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
1883
-
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
1884
-
PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
1895
+
RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
1885
1896
PIN_CFG_NOGPIO_INT), /* P25 */
1886
1897
0x0, /* P26 */
1887
1898
0x0, /* P27 */
···
1958
1971
struct rzg2l_dedicated_configs rzg2l_pins[7];
1959
1972
} rzg2l_dedicated_pins = {
1960
1973
.common = {
1961
-
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
1962
-
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
1974
+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
1963
1975
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
1964
1976
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1965
1977
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
···
2039
2053
};
2040
2054
2041
2055
static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
2042
-
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
2043
-
PIN_CFG_FILCLKSEL)) },
2056
+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },
2044
2057
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
2045
2058
PIN_CFG_SOFT_PS)) },
2046
2059
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
···
2078
2093
};
2079
2094
2080
2095
static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
2081
-
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
2082
-
PIN_CFG_FILCLKSEL)) },
2096
+
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2083
2097
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2084
2098
PIN_CFG_IEN)) },
2085
2099
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
···
2580
2596
return -EPROBE_DEFER;
2581
2597
2582
2598
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
2583
-
if (ret) {
2584
-
dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
2585
-
return ret;
2586
-
}
2599
+
if (ret)
2600
+
return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n");
2587
2601
2588
2602
if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
2589
-
of_args.args[2] != pctrl->data->n_port_pins) {
2590
-
dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
2591
-
return -EINVAL;
2592
-
}
2603
+
of_args.args[2] != pctrl->data->n_port_pins)
2604
+
return dev_err_probe(pctrl->dev, -EINVAL,
2605
+
"gpio-ranges does not match selected SOC\n");
2593
2606
2594
2607
chip->names = pctrl->data->port_pins;
2595
2608
chip->request = rzg2l_gpio_request;
···
2604
2623
2605
2624
girq = &chip->irq;
2606
2625
gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
2607
-
girq->fwnode = of_node_to_fwnode(np);
2626
+
girq->fwnode = dev_fwnode(pctrl->dev);
2608
2627
girq->parent_domain = parent_domain;
2609
2628
girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
2610
2629
girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
···
2618
2637
pctrl->gpio_range.name = chip->label;
2619
2638
pctrl->gpio_range.gc = chip;
2620
2639
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
2621
-
if (ret) {
2622
-
dev_err(pctrl->dev, "failed to add GPIO controller\n");
2623
-
return ret;
2624
-
}
2640
+
if (ret)
2641
+
return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n");
2625
2642
2626
2643
dev_dbg(pctrl->dev, "Registered gpio controller\n");
2627
2644
···
2705
2726
2706
2727
ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
2707
2728
&pctrl->pctl);
2708
-
if (ret) {
2709
-
dev_err(pctrl->dev, "pinctrl registration failed\n");
2710
-
return ret;
2711
-
}
2729
+
if (ret)
2730
+
return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n");
2712
2731
2713
2732
ret = pinctrl_enable(pctrl->pctl);
2714
-
if (ret) {
2715
-
dev_err(pctrl->dev, "pinctrl enable failed\n");
2716
-
return ret;
2717
-
}
2733
+
if (ret)
2734
+
dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
2718
2735
2719
2736
ret = rzg2l_gpio_register(pctrl);
2720
-
if (ret) {
2721
-
dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
2722
-
return ret;
2723
-
}
2737
+
if (ret)
2738
+
return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n");
2724
2739
2725
2740
return 0;
2726
2741
}
+1
-2
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+1
-2
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+1
-2
drivers/pinctrl/renesas/pinctrl.c
+1
-2
drivers/pinctrl/renesas/pinctrl.c
+14
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+14
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
···
40
40
#define S5P_OTHERS_RET_MMC (1 << 29)
41
41
#define S5P_OTHERS_RET_UART (1 << 28)
42
42
43
+
#define S5P_PIN_PULL_DISABLE 0
44
+
#define S5P_PIN_PULL_DOWN 1
45
+
#define S5P_PIN_PULL_UP 2
46
+
47
+
static void s5pv210_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
48
+
{
49
+
unsigned int *pud_val = drvdata->pud_val;
50
+
51
+
pud_val[PUD_PULL_DISABLE] = S5P_PIN_PULL_DISABLE;
52
+
pud_val[PUD_PULL_DOWN] = S5P_PIN_PULL_DOWN;
53
+
pud_val[PUD_PULL_UP] = S5P_PIN_PULL_UP;
54
+
}
55
+
43
56
static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
44
57
{
45
58
void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
···
146
133
.nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
147
134
.eint_gpio_init = exynos_eint_gpio_init,
148
135
.eint_wkup_init = exynos_eint_wkup_init,
136
+
.pud_value_init = s5pv210_pud_value_init,
149
137
.suspend = exynos_pinctrl_suspend,
150
138
.resume = exynos_pinctrl_resume,
151
139
.retention_data = &s5pv210_retention_data,
+4
-12
drivers/pinctrl/samsung/pinctrl-exynos.c
+4
-12
drivers/pinctrl/samsung/pinctrl-exynos.c
···
662
662
__init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
663
663
{
664
664
struct device *dev = d->dev;
665
-
struct device_node *wkup_np = NULL;
665
+
struct device_node *wkup_np __free(device_node) = NULL;
666
666
struct device_node *np;
667
667
struct samsung_pin_bank *bank;
668
668
struct exynos_weint_data *weint_data;
···
692
692
693
693
bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
694
694
GFP_KERNEL);
695
-
if (!bank->irq_chip) {
696
-
of_node_put(wkup_np);
695
+
if (!bank->irq_chip)
697
696
return -ENOMEM;
698
-
}
699
697
bank->irq_chip->chip.name = bank->name;
700
698
701
699
bank->irq_domain = irq_domain_create_linear(bank->fwnode,
702
700
bank->nr_pins, &exynos_eint_irqd_ops, bank);
703
701
if (!bank->irq_domain) {
704
702
dev_err(dev, "wkup irq domain add failed\n");
705
-
of_node_put(wkup_np);
706
703
return -ENXIO;
707
704
}
708
705
···
712
715
weint_data = devm_kcalloc(dev,
713
716
bank->nr_pins, sizeof(*weint_data),
714
717
GFP_KERNEL);
715
-
if (!weint_data) {
716
-
of_node_put(wkup_np);
718
+
if (!weint_data)
717
719
return -ENOMEM;
718
-
}
719
720
720
721
for (idx = 0; idx < bank->nr_pins; ++idx) {
721
722
irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
···
730
735
}
731
736
}
732
737
733
-
if (!muxed_banks) {
734
-
of_node_put(wkup_np);
738
+
if (!muxed_banks)
735
739
return 0;
736
-
}
737
740
738
741
irq = irq_of_parse_and_map(wkup_np, 0);
739
-
of_node_put(wkup_np);
740
742
if (!irq) {
741
743
dev_err(dev, "irq number for muxed EINTs not found\n");
742
744
return 0;
+14
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+14
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
···
63
63
#define EINT_CON_MASK 0xF
64
64
#define EINT_CON_LEN 4
65
65
66
+
#define S3C_PIN_PULL_DISABLE 0
67
+
#define S3C_PIN_PULL_DOWN 1
68
+
#define S3C_PIN_PULL_UP 2
69
+
66
70
static const struct samsung_pin_bank_type bank_type_4bit_off = {
67
71
.fld_width = { 4, 1, 2, 0, 2, 2, },
68
72
.reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
···
257
253
}
258
254
259
255
return trigger;
256
+
}
257
+
258
+
static void s3c64xx_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
259
+
{
260
+
unsigned int *pud_val = drvdata->pud_val;
261
+
262
+
pud_val[PUD_PULL_DISABLE] = S3C_PIN_PULL_DISABLE;
263
+
pud_val[PUD_PULL_DOWN] = S3C_PIN_PULL_DOWN;
264
+
pud_val[PUD_PULL_UP] = S3C_PIN_PULL_UP;
260
265
}
261
266
262
267
static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
···
810
797
.nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
811
798
.eint_gpio_init = s3c64xx_eint_gpio_init,
812
799
.eint_wkup_init = s3c64xx_eint_eint0_init,
800
+
.pud_value_init = s3c64xx_pud_value_init,
813
801
},
814
802
};
815
803
+88
-20
drivers/pinctrl/samsung/pinctrl-samsung.c
+88
-20
drivers/pinctrl/samsung/pinctrl-samsung.c
···
122
122
if (WARN_ON(*num_maps == *reserved_maps))
123
123
return -ENOSPC;
124
124
125
-
dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
126
-
GFP_KERNEL);
125
+
dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs),
126
+
GFP_KERNEL);
127
127
if (!dup_configs)
128
128
return -ENOMEM;
129
129
···
251
251
{
252
252
struct samsung_pinctrl_drv_data *drvdata;
253
253
unsigned reserved_maps;
254
-
struct device_node *np;
255
254
int ret;
256
255
257
256
drvdata = pinctrl_dev_get_drvdata(pctldev);
···
265
266
&reserved_maps,
266
267
num_maps);
267
268
268
-
for_each_child_of_node(np_config, np) {
269
+
for_each_child_of_node_scoped(np_config, np) {
269
270
ret = samsung_dt_subnode_to_map(drvdata, pctldev->dev, np, map,
270
271
&reserved_maps, num_maps);
271
272
if (ret < 0) {
272
273
samsung_dt_free_map(pctldev, *map, *num_maps);
273
-
of_node_put(np);
274
274
return ret;
275
275
}
276
276
}
···
821
823
struct device_node *func_np;
822
824
823
825
if (!of_get_child_count(cfg_np)) {
824
-
if (!of_find_property(cfg_np,
825
-
"samsung,pin-function", NULL))
826
+
if (!of_property_present(cfg_np,
827
+
"samsung,pin-function"))
826
828
continue;
827
829
++func_cnt;
828
830
continue;
829
831
}
830
832
831
833
for_each_child_of_node(cfg_np, func_np) {
832
-
if (!of_find_property(func_np,
833
-
"samsung,pin-function", NULL))
834
+
if (!of_property_present(func_np,
835
+
"samsung,pin-function"))
834
836
continue;
835
837
++func_cnt;
836
838
}
···
847
849
* and create pin groups and pin function lists.
848
850
*/
849
851
func_cnt = 0;
850
-
for_each_child_of_node(dev_np, cfg_np) {
851
-
struct device_node *func_np;
852
-
852
+
for_each_child_of_node_scoped(dev_np, cfg_np) {
853
853
if (!of_get_child_count(cfg_np)) {
854
854
ret = samsung_pinctrl_create_function(dev, drvdata,
855
855
cfg_np, func);
856
-
if (ret < 0) {
857
-
of_node_put(cfg_np);
856
+
if (ret < 0)
858
857
return ERR_PTR(ret);
859
-
}
860
858
if (ret > 0) {
861
859
++func;
862
860
++func_cnt;
···
860
866
continue;
861
867
}
862
868
863
-
for_each_child_of_node(cfg_np, func_np) {
869
+
for_each_child_of_node_scoped(cfg_np, func_np) {
864
870
ret = samsung_pinctrl_create_function(dev, drvdata,
865
871
func_np, func);
866
-
if (ret < 0) {
867
-
of_node_put(func_np);
868
-
of_node_put(cfg_np);
872
+
if (ret < 0)
869
873
return ERR_PTR(ret);
870
-
}
871
874
if (ret > 0) {
872
875
++func;
873
876
++func_cnt;
···
988
997
return 0;
989
998
}
990
999
1000
+
static void samsung_pud_value_init(struct samsung_pinctrl_drv_data *drvdata)
1001
+
{
1002
+
unsigned int *pud_val = drvdata->pud_val;
1003
+
1004
+
pud_val[PUD_PULL_DISABLE] = EXYNOS_PIN_PUD_PULL_DISABLE;
1005
+
pud_val[PUD_PULL_DOWN] = EXYNOS_PIN_PID_PULL_DOWN;
1006
+
pud_val[PUD_PULL_UP] = EXYNOS_PIN_PID_PULL_UP;
1007
+
}
1008
+
1009
+
/*
1010
+
* Enable or Disable the pull-down and pull-up for the gpio pins in the
1011
+
* PUD register.
1012
+
*/
1013
+
static void samsung_gpio_set_pud(struct gpio_chip *gc, unsigned int offset,
1014
+
unsigned int value)
1015
+
{
1016
+
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
1017
+
const struct samsung_pin_bank_type *type = bank->type;
1018
+
void __iomem *reg;
1019
+
unsigned int data, mask;
1020
+
1021
+
reg = bank->pctl_base + bank->pctl_offset;
1022
+
data = readl(reg + type->reg_offset[PINCFG_TYPE_PUD]);
1023
+
mask = (1 << type->fld_width[PINCFG_TYPE_PUD]) - 1;
1024
+
data &= ~(mask << (offset * type->fld_width[PINCFG_TYPE_PUD]));
1025
+
data |= value << (offset * type->fld_width[PINCFG_TYPE_PUD]);
1026
+
writel(data, reg + type->reg_offset[PINCFG_TYPE_PUD]);
1027
+
}
1028
+
1029
+
/*
1030
+
* Identify the type of PUD config based on the gpiolib request to enable
1031
+
* or disable the PUD config.
1032
+
*/
1033
+
static int samsung_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
1034
+
unsigned long config)
1035
+
{
1036
+
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
1037
+
struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
1038
+
unsigned int value;
1039
+
int ret = 0;
1040
+
unsigned long flags;
1041
+
1042
+
switch (pinconf_to_config_param(config)) {
1043
+
case PIN_CONFIG_BIAS_DISABLE:
1044
+
value = drvdata->pud_val[PUD_PULL_DISABLE];
1045
+
break;
1046
+
case PIN_CONFIG_BIAS_PULL_DOWN:
1047
+
value = drvdata->pud_val[PUD_PULL_DOWN];
1048
+
break;
1049
+
case PIN_CONFIG_BIAS_PULL_UP:
1050
+
value = drvdata->pud_val[PUD_PULL_UP];
1051
+
break;
1052
+
default:
1053
+
return -ENOTSUPP;
1054
+
}
1055
+
1056
+
ret = clk_enable(drvdata->pclk);
1057
+
if (ret) {
1058
+
dev_err(drvdata->dev, "failed to enable clock\n");
1059
+
return ret;
1060
+
}
1061
+
1062
+
raw_spin_lock_irqsave(&bank->slock, flags);
1063
+
samsung_gpio_set_pud(gc, offset, value);
1064
+
raw_spin_unlock_irqrestore(&bank->slock, flags);
1065
+
1066
+
clk_disable(drvdata->pclk);
1067
+
1068
+
return ret;
1069
+
}
1070
+
991
1071
static const struct gpio_chip samsung_gpiolib_chip = {
992
1072
.request = gpiochip_generic_request,
993
1073
.free = gpiochip_generic_free,
···
1068
1006
.direction_output = samsung_gpio_direction_output,
1069
1007
.to_irq = samsung_gpio_to_irq,
1070
1008
.add_pin_ranges = samsung_add_pin_ranges,
1009
+
.set_config = samsung_gpio_set_config,
1071
1010
.owner = THIS_MODULE,
1072
1011
};
1073
1012
···
1299
1236
ctrl->eint_gpio_init(drvdata);
1300
1237
if (ctrl->eint_wkup_init)
1301
1238
ctrl->eint_wkup_init(drvdata);
1239
+
1240
+
if (ctrl->pud_value_init)
1241
+
ctrl->pud_value_init(drvdata);
1242
+
else
1243
+
samsung_pud_value_init(drvdata);
1302
1244
1303
1245
ret = samsung_gpiolib_register(pdev, drvdata);
1304
1246
if (ret)
+21
drivers/pinctrl/samsung/pinctrl-samsung.h
+21
drivers/pinctrl/samsung/pinctrl-samsung.h
···
61
61
#define PIN_CON_FUNC_INPUT 0x0
62
62
#define PIN_CON_FUNC_OUTPUT 0x1
63
63
64
+
/* Values for the pin PUD register */
65
+
#define EXYNOS_PIN_PUD_PULL_DISABLE 0x0
66
+
#define EXYNOS_PIN_PID_PULL_DOWN 0x1
67
+
#define EXYNOS_PIN_PID_PULL_UP 0x3
68
+
69
+
/*
70
+
* enum pud_index - Possible index values to access the pud_val array.
71
+
* @PUD_PULL_DISABLE: Index for the value of pud disable
72
+
* @PUD_PULL_DOWN: Index for the value of pull down enable
73
+
* @PUD_PULL_UP: Index for the value of pull up enable
74
+
* @PUD_MAX: Maximum value of the index
75
+
*/
76
+
enum pud_index {
77
+
PUD_PULL_DISABLE,
78
+
PUD_PULL_DOWN,
79
+
PUD_PULL_UP,
80
+
PUD_MAX,
81
+
};
82
+
64
83
/**
65
84
* enum eint_type - possible external interrupt types.
66
85
* @EINT_TYPE_NONE: bank does not support external interrupts
···
280
261
281
262
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
282
263
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
264
+
void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata);
283
265
void (*suspend)(struct samsung_pinctrl_drv_data *);
284
266
void (*resume)(struct samsung_pinctrl_drv_data *);
285
267
};
···
327
307
struct samsung_pin_bank *pin_banks;
328
308
unsigned int nr_banks;
329
309
unsigned int nr_pins;
310
+
unsigned int pud_val[PUD_MAX];
330
311
331
312
struct samsung_retention_ctrl *retention_ctrl;
332
313
+54
drivers/pinctrl/sophgo/Kconfig
+54
drivers/pinctrl/sophgo/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
#
3
+
# Sophgo SoC PINCTRL drivers
4
+
#
5
+
6
+
config PINCTRL_SOPHGO_CV18XX
7
+
bool
8
+
select GENERIC_PINCTRL_GROUPS
9
+
select GENERIC_PINMUX_FUNCTIONS
10
+
select GENERIC_PINCONF
11
+
12
+
config PINCTRL_SOPHGO_CV1800B
13
+
tristate "Sophgo CV1800B SoC Pinctrl driver"
14
+
depends on ARCH_SOPHGO || COMPILE_TEST
15
+
depends on OF
16
+
select PINCTRL_SOPHGO_CV18XX
17
+
help
18
+
Say Y to select the pinctrl driver for CV1800B SoC.
19
+
This pin controller allows selecting the mux function for
20
+
each pin. This driver can also be built as a module called
21
+
pinctrl-cv1800b.
22
+
23
+
config PINCTRL_SOPHGO_CV1812H
24
+
tristate "Sophgo CV1812H SoC Pinctrl driver"
25
+
depends on ARCH_SOPHGO || COMPILE_TEST
26
+
depends on OF
27
+
select PINCTRL_SOPHGO_CV18XX
28
+
help
29
+
Say Y to select the pinctrl driver for CV1812H SoC.
30
+
This pin controller allows selecting the mux function for
31
+
each pin. This driver can also be built as a module called
32
+
pinctrl-cv1812h.
33
+
34
+
config PINCTRL_SOPHGO_SG2000
35
+
tristate "Sophgo SG2000 SoC Pinctrl driver"
36
+
depends on ARCH_SOPHGO || COMPILE_TEST
37
+
depends on OF
38
+
select PINCTRL_SOPHGO_CV18XX
39
+
help
40
+
Say Y to select the pinctrl driver for SG2000 SoC.
41
+
This pin controller allows selecting the mux function for
42
+
each pin. This driver can also be built as a module called
43
+
pinctrl-sg2000.
44
+
45
+
config PINCTRL_SOPHGO_SG2002
46
+
tristate "Sophgo SG2000 SoC Pinctrl driver"
47
+
depends on ARCH_SOPHGO || COMPILE_TEST
48
+
depends on OF
49
+
select PINCTRL_SOPHGO_CV18XX
50
+
help
51
+
Say Y to select the pinctrl driver for SG2002 SoC.
52
+
This pin controller allows selecting the mux function for
53
+
each pin. This driver can also be built as a module called
54
+
pinctrl-sg2002.
+7
drivers/pinctrl/sophgo/Makefile
+7
drivers/pinctrl/sophgo/Makefile
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
3
+
obj-$(CONFIG_PINCTRL_SOPHGO_CV18XX) += pinctrl-cv18xx.o
4
+
obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o
5
+
obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o
6
+
obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o
7
+
obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o
+462
drivers/pinctrl/sophgo/pinctrl-cv1800b.c
+462
drivers/pinctrl/sophgo/pinctrl-cv1800b.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo CV1800B SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
* This file is generated from vendor pinout definition.
8
+
*/
9
+
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/of.h>
13
+
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/pinctrl/pinmux.h>
16
+
17
+
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
18
+
19
+
#include "pinctrl-cv18xx.h"
20
+
21
+
enum CV1800B_POWER_DOMAIN {
22
+
VDD18A_AUD = 0,
23
+
VDD18A_USB_PLL_ETH_CSI = 1,
24
+
VDD33A_ETH_USB_SD1 = 2,
25
+
VDDIO_RTC = 3,
26
+
VDDIO_SD0_SPI = 4
27
+
};
28
+
29
+
static const char *const cv1800b_power_domain_desc[] = {
30
+
[VDD18A_AUD] = "VDD18A_AUD",
31
+
[VDD18A_USB_PLL_ETH_CSI] = "VDD18A_USB_PLL_ETH_CSI",
32
+
[VDD33A_ETH_USB_SD1] = "VDD33A_ETH_USB_SD1",
33
+
[VDDIO_RTC] = "VDDIO_RTC",
34
+
[VDDIO_SD0_SPI] = "VDDIO_SD0_SPI",
35
+
};
36
+
37
+
static int cv1800b_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
38
+
{
39
+
u32 pstate = psmap[pin->power_domain];
40
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
41
+
42
+
if (type == IO_TYPE_1V8_ONLY)
43
+
return 79000;
44
+
45
+
if (type == IO_TYPE_1V8_OR_3V3) {
46
+
if (pstate == PIN_POWER_STATE_1V8)
47
+
return 60000;
48
+
if (pstate == PIN_POWER_STATE_3V3)
49
+
return 60000;
50
+
51
+
return -EINVAL;
52
+
}
53
+
54
+
return -ENOTSUPP;
55
+
}
56
+
57
+
static int cv1800b_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
58
+
{
59
+
u32 pstate = psmap[pin->power_domain];
60
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
61
+
62
+
if (type == IO_TYPE_1V8_ONLY)
63
+
return 87000;
64
+
65
+
if (type == IO_TYPE_1V8_OR_3V3) {
66
+
if (pstate == PIN_POWER_STATE_1V8)
67
+
return 61000;
68
+
if (pstate == PIN_POWER_STATE_3V3)
69
+
return 62000;
70
+
71
+
return -EINVAL;
72
+
}
73
+
74
+
return -ENOTSUPP;
75
+
}
76
+
77
+
static const u32 cv1800b_1v8_oc_map[] = {
78
+
12800,
79
+
25300,
80
+
37400,
81
+
49000
82
+
};
83
+
84
+
static const u32 cv1800b_18od33_1v8_oc_map[] = {
85
+
7800,
86
+
11700,
87
+
15500,
88
+
19200,
89
+
23000,
90
+
26600,
91
+
30200,
92
+
33700
93
+
};
94
+
95
+
static const u32 cv1800b_18od33_3v3_oc_map[] = {
96
+
5500,
97
+
8200,
98
+
10800,
99
+
13400,
100
+
16100,
101
+
18700,
102
+
21200,
103
+
23700
104
+
};
105
+
106
+
static const u32 cv1800b_eth_oc_map[] = {
107
+
15700,
108
+
17800
109
+
};
110
+
111
+
static int cv1800b_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
112
+
const u32 **map)
113
+
{
114
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
115
+
u32 pstate = psmap[pin->power_domain];
116
+
117
+
if (type == IO_TYPE_1V8_ONLY) {
118
+
*map = cv1800b_1v8_oc_map;
119
+
return ARRAY_SIZE(cv1800b_1v8_oc_map);
120
+
}
121
+
122
+
if (type == IO_TYPE_1V8_OR_3V3) {
123
+
if (pstate == PIN_POWER_STATE_1V8) {
124
+
*map = cv1800b_18od33_1v8_oc_map;
125
+
return ARRAY_SIZE(cv1800b_18od33_1v8_oc_map);
126
+
} else if (pstate == PIN_POWER_STATE_3V3) {
127
+
*map = cv1800b_18od33_3v3_oc_map;
128
+
return ARRAY_SIZE(cv1800b_18od33_3v3_oc_map);
129
+
}
130
+
}
131
+
132
+
if (type == IO_TYPE_ETH) {
133
+
*map = cv1800b_eth_oc_map;
134
+
return ARRAY_SIZE(cv1800b_eth_oc_map);
135
+
}
136
+
137
+
return -ENOTSUPP;
138
+
}
139
+
140
+
static const u32 cv1800b_1v8_schmitt_map[] = {
141
+
0,
142
+
970000,
143
+
1040000
144
+
};
145
+
146
+
static const u32 cv1800b_18od33_1v8_schmitt_map[] = {
147
+
0,
148
+
1070000
149
+
};
150
+
151
+
static const u32 cv1800b_18od33_3v3_schmitt_map[] = {
152
+
0,
153
+
1100000
154
+
};
155
+
156
+
static int cv1800b_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
157
+
const u32 **map)
158
+
{
159
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
160
+
u32 pstate = psmap[pin->power_domain];
161
+
162
+
if (type == IO_TYPE_1V8_ONLY) {
163
+
*map = cv1800b_1v8_schmitt_map;
164
+
return ARRAY_SIZE(cv1800b_1v8_schmitt_map);
165
+
}
166
+
167
+
if (type == IO_TYPE_1V8_OR_3V3) {
168
+
if (pstate == PIN_POWER_STATE_1V8) {
169
+
*map = cv1800b_18od33_1v8_schmitt_map;
170
+
return ARRAY_SIZE(cv1800b_18od33_1v8_schmitt_map);
171
+
} else if (pstate == PIN_POWER_STATE_3V3) {
172
+
*map = cv1800b_18od33_3v3_schmitt_map;
173
+
return ARRAY_SIZE(cv1800b_18od33_3v3_schmitt_map);
174
+
}
175
+
}
176
+
177
+
return -ENOTSUPP;
178
+
}
179
+
180
+
static const struct cv1800_vddio_cfg_ops cv1800b_vddio_cfg_ops = {
181
+
.get_pull_up = cv1800b_get_pull_up,
182
+
.get_pull_down = cv1800b_get_pull_down,
183
+
.get_oc_map = cv1800b_get_oc_map,
184
+
.get_schmitt_map = cv1800b_get_schmitt_map,
185
+
};
186
+
187
+
static const struct pinctrl_pin_desc cv1800b_pins[] = {
188
+
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
189
+
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
190
+
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
191
+
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
192
+
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
193
+
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
194
+
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
195
+
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
196
+
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
197
+
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
198
+
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
199
+
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
200
+
PINCTRL_PIN(PIN_SPINOR_HOLD_X, "SPINOR_HOLD_X"),
201
+
PINCTRL_PIN(PIN_SPINOR_SCK, "SPINOR_SCK"),
202
+
PINCTRL_PIN(PIN_SPINOR_MOSI, "SPINOR_MOSI"),
203
+
PINCTRL_PIN(PIN_SPINOR_WP_X, "SPINOR_WP_X"),
204
+
PINCTRL_PIN(PIN_SPINOR_MISO, "SPINOR_MISO"),
205
+
PINCTRL_PIN(PIN_SPINOR_CS_X, "SPINOR_CS_X"),
206
+
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
207
+
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
208
+
PINCTRL_PIN(PIN_AUX0, "AUX0"),
209
+
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
210
+
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
211
+
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
212
+
PINCTRL_PIN(PIN_SD1_GPIO0, "SD1_GPIO0"),
213
+
PINCTRL_PIN(PIN_SD1_GPIO1, "SD1_GPIO1"),
214
+
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
215
+
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
216
+
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
217
+
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
218
+
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
219
+
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
220
+
PINCTRL_PIN(PIN_ADC1, "ADC1"),
221
+
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
222
+
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
223
+
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
224
+
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
225
+
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
226
+
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
227
+
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
228
+
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
229
+
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
230
+
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
231
+
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
232
+
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
233
+
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
234
+
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
235
+
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
236
+
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
237
+
};
238
+
239
+
static const struct cv1800_pin cv1800b_pin_data[ARRAY_SIZE(cv1800b_pins)] = {
240
+
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_AUD,
241
+
IO_TYPE_AUDIO,
242
+
CV1800_PINCONF_AREA_SYS, 0x12c, 6),
243
+
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_SPI,
244
+
IO_TYPE_1V8_OR_3V3,
245
+
CV1800_PINCONF_AREA_SYS, 0x000, 7,
246
+
CV1800_PINCONF_AREA_SYS, 0xa00),
247
+
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_SPI,
248
+
IO_TYPE_1V8_OR_3V3,
249
+
CV1800_PINCONF_AREA_SYS, 0x004, 7,
250
+
CV1800_PINCONF_AREA_SYS, 0xa04),
251
+
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_SPI,
252
+
IO_TYPE_1V8_OR_3V3,
253
+
CV1800_PINCONF_AREA_SYS, 0x008, 7,
254
+
CV1800_PINCONF_AREA_SYS, 0xa08),
255
+
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_SPI,
256
+
IO_TYPE_1V8_OR_3V3,
257
+
CV1800_PINCONF_AREA_SYS, 0x00c, 7,
258
+
CV1800_PINCONF_AREA_SYS, 0xa0c),
259
+
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_SPI,
260
+
IO_TYPE_1V8_OR_3V3,
261
+
CV1800_PINCONF_AREA_SYS, 0x010, 7,
262
+
CV1800_PINCONF_AREA_SYS, 0xa10),
263
+
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_SPI,
264
+
IO_TYPE_1V8_OR_3V3,
265
+
CV1800_PINCONF_AREA_SYS, 0x014, 7,
266
+
CV1800_PINCONF_AREA_SYS, 0xa14),
267
+
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_SPI,
268
+
IO_TYPE_1V8_OR_3V3,
269
+
CV1800_PINCONF_AREA_SYS, 0x018, 3,
270
+
CV1800_PINCONF_AREA_SYS, 0x900),
271
+
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_SPI,
272
+
IO_TYPE_1V8_OR_3V3,
273
+
CV1800_PINCONF_AREA_SYS, 0x01c, 3,
274
+
CV1800_PINCONF_AREA_SYS, 0x904),
275
+
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_SPI,
276
+
IO_TYPE_1V8_OR_3V3,
277
+
CV1800_PINCONF_AREA_SYS, 0x020, 3,
278
+
CV1800_PINCONF_AREA_SYS, 0x908),
279
+
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_SPI,
280
+
IO_TYPE_1V8_OR_3V3,
281
+
CV1800_PINCONF_AREA_SYS, 0x024, 7,
282
+
CV1800_PINCONF_AREA_SYS, 0x90c),
283
+
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_SPI,
284
+
IO_TYPE_1V8_OR_3V3,
285
+
CV1800_PINCONF_AREA_SYS, 0x028, 7,
286
+
CV1800_PINCONF_AREA_SYS, 0x910),
287
+
CV1800_GENERAL_PIN(PIN_SPINOR_HOLD_X, VDDIO_SD0_SPI,
288
+
IO_TYPE_1V8_OR_3V3,
289
+
CV1800_PINCONF_AREA_SYS, 0x02c, 3,
290
+
CV1800_PINCONF_AREA_SYS, 0x914),
291
+
CV1800_GENERAL_PIN(PIN_SPINOR_SCK, VDDIO_SD0_SPI,
292
+
IO_TYPE_1V8_OR_3V3,
293
+
CV1800_PINCONF_AREA_SYS, 0x030, 3,
294
+
CV1800_PINCONF_AREA_SYS, 0x918),
295
+
CV1800_GENERAL_PIN(PIN_SPINOR_MOSI, VDDIO_SD0_SPI,
296
+
IO_TYPE_1V8_OR_3V3,
297
+
CV1800_PINCONF_AREA_SYS, 0x034, 3,
298
+
CV1800_PINCONF_AREA_SYS, 0x91c),
299
+
CV1800_GENERAL_PIN(PIN_SPINOR_WP_X, VDDIO_SD0_SPI,
300
+
IO_TYPE_1V8_OR_3V3,
301
+
CV1800_PINCONF_AREA_SYS, 0x038, 3,
302
+
CV1800_PINCONF_AREA_SYS, 0x920),
303
+
CV1800_GENERAL_PIN(PIN_SPINOR_MISO, VDDIO_SD0_SPI,
304
+
IO_TYPE_1V8_OR_3V3,
305
+
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
306
+
CV1800_PINCONF_AREA_SYS, 0x924),
307
+
CV1800_GENERAL_PIN(PIN_SPINOR_CS_X, VDDIO_SD0_SPI,
308
+
IO_TYPE_1V8_OR_3V3,
309
+
CV1800_PINCONF_AREA_SYS, 0x040, 3,
310
+
CV1800_PINCONF_AREA_SYS, 0x928),
311
+
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_SPI,
312
+
IO_TYPE_1V8_OR_3V3,
313
+
CV1800_PINCONF_AREA_SYS, 0x04c, 7,
314
+
CV1800_PINCONF_AREA_SYS, 0x934),
315
+
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_SPI,
316
+
IO_TYPE_1V8_OR_3V3,
317
+
CV1800_PINCONF_AREA_SYS, 0x050, 7,
318
+
CV1800_PINCONF_AREA_SYS, 0x938),
319
+
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_SPI,
320
+
IO_TYPE_1V8_OR_3V3,
321
+
CV1800_PINCONF_AREA_SYS, 0x054, 7,
322
+
CV1800_PINCONF_AREA_SYS, 0x93c),
323
+
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
324
+
IO_TYPE_1V8_ONLY,
325
+
CV1800_PINCONF_AREA_SYS, 0x05c, 0,
326
+
CV1800_PINCONF_AREA_RTC, 0x004),
327
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
328
+
IO_TYPE_1V8_ONLY,
329
+
CV1800_PINCONF_AREA_SYS, 0x068, 3,
330
+
CV1800_PINCONF_AREA_RTC, 0x010),
331
+
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
332
+
IO_TYPE_1V8_ONLY,
333
+
CV1800_PINCONF_AREA_SYS, 0x074, 0,
334
+
CV1800_PINCONF_AREA_RTC, 0x020),
335
+
CV1800_GENERAL_PIN(PIN_SD1_GPIO0, VDD33A_ETH_USB_SD1,
336
+
IO_TYPE_1V8_OR_3V3,
337
+
CV1800_PINCONF_AREA_SYS, 0x088, 7,
338
+
CV1800_PINCONF_AREA_RTC, 0x034),
339
+
CV1800_GENERAL_PIN(PIN_SD1_GPIO1, VDD33A_ETH_USB_SD1,
340
+
IO_TYPE_1V8_OR_3V3,
341
+
CV1800_PINCONF_AREA_SYS, 0x084, 7,
342
+
CV1800_PINCONF_AREA_RTC, 0x030),
343
+
CV1800_GENERAL_PIN(PIN_SD1_D3, VDD33A_ETH_USB_SD1,
344
+
IO_TYPE_1V8_OR_3V3,
345
+
CV1800_PINCONF_AREA_SYS, 0x08c, 7,
346
+
CV1800_PINCONF_AREA_RTC, 0x038),
347
+
CV1800_GENERAL_PIN(PIN_SD1_D2, VDD33A_ETH_USB_SD1,
348
+
IO_TYPE_1V8_OR_3V3,
349
+
CV1800_PINCONF_AREA_SYS, 0x090, 7,
350
+
CV1800_PINCONF_AREA_RTC, 0x03c),
351
+
CV1800_GENERAL_PIN(PIN_SD1_D1, VDD33A_ETH_USB_SD1,
352
+
IO_TYPE_1V8_OR_3V3,
353
+
CV1800_PINCONF_AREA_SYS, 0x094, 7,
354
+
CV1800_PINCONF_AREA_RTC, 0x040),
355
+
CV1800_GENERAL_PIN(PIN_SD1_D0, VDD33A_ETH_USB_SD1,
356
+
IO_TYPE_1V8_OR_3V3,
357
+
CV1800_PINCONF_AREA_SYS, 0x098, 7,
358
+
CV1800_PINCONF_AREA_RTC, 0x044),
359
+
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDD33A_ETH_USB_SD1,
360
+
IO_TYPE_1V8_OR_3V3,
361
+
CV1800_PINCONF_AREA_SYS, 0x09c, 7,
362
+
CV1800_PINCONF_AREA_RTC, 0x048),
363
+
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDD33A_ETH_USB_SD1,
364
+
IO_TYPE_1V8_OR_3V3,
365
+
CV1800_PINCONF_AREA_SYS, 0x0a0, 7,
366
+
CV1800_PINCONF_AREA_RTC, 0x04c),
367
+
CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH_CSI,
368
+
IO_TYPE_1V8_ONLY,
369
+
CV1800_PINCONF_AREA_SYS, 0x0a8, 6,
370
+
CV1800_PINCONF_AREA_SYS, 0x804),
371
+
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH_CSI,
372
+
IO_TYPE_1V8_ONLY,
373
+
CV1800_PINCONF_AREA_SYS, 0x0ac, 6,
374
+
CV1800_PINCONF_AREA_SYS, 0x808),
375
+
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH_CSI,
376
+
IO_TYPE_ETH,
377
+
CV1800_PINCONF_AREA_SYS, 0x0c0, 7),
378
+
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH_CSI,
379
+
IO_TYPE_ETH,
380
+
CV1800_PINCONF_AREA_SYS, 0x0c4, 7),
381
+
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH_CSI,
382
+
IO_TYPE_ETH,
383
+
CV1800_PINCONF_AREA_SYS, 0x0c8, 7),
384
+
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH_CSI,
385
+
IO_TYPE_ETH,
386
+
CV1800_PINCONF_AREA_SYS, 0x0cc, 7),
387
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_USB_PLL_ETH_CSI,
388
+
IO_TYPE_1V8_ONLY,
389
+
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
390
+
CV1800_PINCONF_AREA_SYS, 0x0bc, 7,
391
+
CV1800_PINCONF_AREA_SYS, 0xc04),
392
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_USB_PLL_ETH_CSI,
393
+
IO_TYPE_1V8_ONLY,
394
+
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
395
+
CV1800_PINCONF_AREA_SYS, 0x0b8, 7,
396
+
CV1800_PINCONF_AREA_SYS, 0xc08),
397
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_USB_PLL_ETH_CSI,
398
+
IO_TYPE_1V8_ONLY,
399
+
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
400
+
CV1800_PINCONF_AREA_SYS, 0x0b0, 7,
401
+
CV1800_PINCONF_AREA_SYS, 0xc0c),
402
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_USB_PLL_ETH_CSI,
403
+
IO_TYPE_1V8_ONLY,
404
+
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
405
+
CV1800_PINCONF_AREA_SYS, 0x0b4, 7,
406
+
CV1800_PINCONF_AREA_SYS, 0xc10),
407
+
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_USB_PLL_ETH_CSI,
408
+
IO_TYPE_1V8_ONLY,
409
+
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
410
+
CV1800_PINCONF_AREA_SYS, 0xc14),
411
+
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_USB_PLL_ETH_CSI,
412
+
IO_TYPE_1V8_ONLY,
413
+
CV1800_PINCONF_AREA_SYS, 0x0e8, 7,
414
+
CV1800_PINCONF_AREA_SYS, 0xc18),
415
+
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_USB_PLL_ETH_CSI,
416
+
IO_TYPE_1V8_ONLY,
417
+
CV1800_PINCONF_AREA_SYS, 0x0ec, 7,
418
+
CV1800_PINCONF_AREA_SYS, 0xc1c),
419
+
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_USB_PLL_ETH_CSI,
420
+
IO_TYPE_1V8_ONLY,
421
+
CV1800_PINCONF_AREA_SYS, 0x0f0, 7,
422
+
CV1800_PINCONF_AREA_SYS, 0xc20),
423
+
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_USB_PLL_ETH_CSI,
424
+
IO_TYPE_1V8_ONLY,
425
+
CV1800_PINCONF_AREA_SYS, 0x0f4, 7,
426
+
CV1800_PINCONF_AREA_SYS, 0xc24),
427
+
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_USB_PLL_ETH_CSI,
428
+
IO_TYPE_1V8_ONLY,
429
+
CV1800_PINCONF_AREA_SYS, 0x0f8, 7,
430
+
CV1800_PINCONF_AREA_SYS, 0xc28),
431
+
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_AUD,
432
+
IO_TYPE_AUDIO,
433
+
CV1800_PINCONF_AREA_SYS, 0x120, 5),
434
+
};
435
+
436
+
static const struct cv1800_pinctrl_data cv1800b_pindata = {
437
+
.pins = cv1800b_pins,
438
+
.pindata = cv1800b_pin_data,
439
+
.pdnames = cv1800b_power_domain_desc,
440
+
.vddio_ops = &cv1800b_vddio_cfg_ops,
441
+
.npins = ARRAY_SIZE(cv1800b_pins),
442
+
.npd = ARRAY_SIZE(cv1800b_power_domain_desc),
443
+
};
444
+
445
+
static const struct of_device_id cv1800b_pinctrl_ids[] = {
446
+
{ .compatible = "sophgo,cv1800b-pinctrl", .data = &cv1800b_pindata },
447
+
{ }
448
+
};
449
+
MODULE_DEVICE_TABLE(of, cv1800b_pinctrl_ids);
450
+
451
+
static struct platform_driver cv1800b_pinctrl_driver = {
452
+
.probe = cv1800_pinctrl_probe,
453
+
.driver = {
454
+
.name = "cv1800b-pinctrl",
455
+
.suppress_bind_attrs = true,
456
+
.of_match_table = cv1800b_pinctrl_ids,
457
+
},
458
+
};
459
+
module_platform_driver(cv1800b_pinctrl_driver);
460
+
461
+
MODULE_DESCRIPTION("Pinctrl driver for the CV1800B series SoC");
462
+
MODULE_LICENSE("GPL");
+771
drivers/pinctrl/sophgo/pinctrl-cv1812h.c
+771
drivers/pinctrl/sophgo/pinctrl-cv1812h.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo CV1812H SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
* This file is generated from vendor pinout definition.
8
+
*/
9
+
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/of.h>
13
+
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/pinctrl/pinmux.h>
16
+
17
+
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
18
+
19
+
#include "pinctrl-cv18xx.h"
20
+
21
+
enum CV1812H_POWER_DOMAIN {
22
+
VDD18A_EPHY = 0,
23
+
VDD18A_MIPI = 1,
24
+
VDDIO18_1 = 2,
25
+
VDDIO_EMMC = 3,
26
+
VDDIO_RTC = 4,
27
+
VDDIO_SD0 = 5,
28
+
VDDIO_SD1 = 6,
29
+
VDDIO_VIVO = 7
30
+
};
31
+
32
+
static const char *const cv1812h_power_domain_desc[] = {
33
+
[VDD18A_EPHY] = "VDD18A_EPHY",
34
+
[VDD18A_MIPI] = "VDD18A_MIPI",
35
+
[VDDIO18_1] = "VDDIO18_1",
36
+
[VDDIO_EMMC] = "VDDIO_EMMC",
37
+
[VDDIO_RTC] = "VDDIO_RTC",
38
+
[VDDIO_SD0] = "VDDIO_SD0",
39
+
[VDDIO_SD1] = "VDDIO_SD1",
40
+
[VDDIO_VIVO] = "VDDIO_VIVO",
41
+
};
42
+
43
+
static int cv1812h_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
44
+
{
45
+
u32 pstate = psmap[pin->power_domain];
46
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
47
+
48
+
if (type == IO_TYPE_1V8_ONLY)
49
+
return 79000;
50
+
51
+
if (type == IO_TYPE_1V8_OR_3V3) {
52
+
if (pstate == PIN_POWER_STATE_1V8)
53
+
return 60000;
54
+
if (pstate == PIN_POWER_STATE_3V3)
55
+
return 60000;
56
+
57
+
return -EINVAL;
58
+
}
59
+
60
+
return -ENOTSUPP;
61
+
}
62
+
63
+
static int cv1812h_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
64
+
{
65
+
u32 pstate = psmap[pin->power_domain];
66
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
67
+
68
+
if (type == IO_TYPE_1V8_ONLY)
69
+
return 87000;
70
+
71
+
if (type == IO_TYPE_1V8_OR_3V3) {
72
+
if (pstate == PIN_POWER_STATE_1V8)
73
+
return 61000;
74
+
if (pstate == PIN_POWER_STATE_3V3)
75
+
return 62000;
76
+
77
+
return -EINVAL;
78
+
}
79
+
80
+
return -ENOTSUPP;
81
+
}
82
+
83
+
static const u32 cv1812h_1v8_oc_map[] = {
84
+
12800,
85
+
25300,
86
+
37400,
87
+
49000
88
+
};
89
+
90
+
static const u32 cv1812h_18od33_1v8_oc_map[] = {
91
+
7800,
92
+
11700,
93
+
15500,
94
+
19200,
95
+
23000,
96
+
26600,
97
+
30200,
98
+
33700
99
+
};
100
+
101
+
static const u32 cv1812h_18od33_3v3_oc_map[] = {
102
+
5500,
103
+
8200,
104
+
10800,
105
+
13400,
106
+
16100,
107
+
18700,
108
+
21200,
109
+
23700
110
+
};
111
+
112
+
static const u32 cv1812h_eth_oc_map[] = {
113
+
15700,
114
+
17800
115
+
};
116
+
117
+
static int cv1812h_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
118
+
const u32 **map)
119
+
{
120
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
121
+
u32 pstate = psmap[pin->power_domain];
122
+
123
+
if (type == IO_TYPE_1V8_ONLY) {
124
+
*map = cv1812h_1v8_oc_map;
125
+
return ARRAY_SIZE(cv1812h_1v8_oc_map);
126
+
}
127
+
128
+
if (type == IO_TYPE_1V8_OR_3V3) {
129
+
if (pstate == PIN_POWER_STATE_1V8) {
130
+
*map = cv1812h_18od33_1v8_oc_map;
131
+
return ARRAY_SIZE(cv1812h_18od33_1v8_oc_map);
132
+
} else if (pstate == PIN_POWER_STATE_3V3) {
133
+
*map = cv1812h_18od33_3v3_oc_map;
134
+
return ARRAY_SIZE(cv1812h_18od33_3v3_oc_map);
135
+
}
136
+
}
137
+
138
+
if (type == IO_TYPE_ETH) {
139
+
*map = cv1812h_eth_oc_map;
140
+
return ARRAY_SIZE(cv1812h_eth_oc_map);
141
+
}
142
+
143
+
return -ENOTSUPP;
144
+
}
145
+
146
+
static const u32 cv1812h_1v8_schmitt_map[] = {
147
+
0,
148
+
970000,
149
+
1040000
150
+
};
151
+
152
+
static const u32 cv1812h_18od33_1v8_schmitt_map[] = {
153
+
0,
154
+
1070000
155
+
};
156
+
157
+
static const u32 cv1812h_18od33_3v3_schmitt_map[] = {
158
+
0,
159
+
1100000
160
+
};
161
+
162
+
static int cv1812h_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
163
+
const u32 **map)
164
+
{
165
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
166
+
u32 pstate = psmap[pin->power_domain];
167
+
168
+
if (type == IO_TYPE_1V8_ONLY) {
169
+
*map = cv1812h_1v8_schmitt_map;
170
+
return ARRAY_SIZE(cv1812h_1v8_schmitt_map);
171
+
}
172
+
173
+
if (type == IO_TYPE_1V8_OR_3V3) {
174
+
if (pstate == PIN_POWER_STATE_1V8) {
175
+
*map = cv1812h_18od33_1v8_schmitt_map;
176
+
return ARRAY_SIZE(cv1812h_18od33_1v8_schmitt_map);
177
+
} else if (pstate == PIN_POWER_STATE_3V3) {
178
+
*map = cv1812h_18od33_3v3_schmitt_map;
179
+
return ARRAY_SIZE(cv1812h_18od33_3v3_schmitt_map);
180
+
}
181
+
}
182
+
183
+
return -ENOTSUPP;
184
+
}
185
+
186
+
static const struct cv1800_vddio_cfg_ops cv1812h_vddio_cfg_ops = {
187
+
.get_pull_up = cv1812h_get_pull_up,
188
+
.get_pull_down = cv1812h_get_pull_down,
189
+
.get_oc_map = cv1812h_get_oc_map,
190
+
.get_schmitt_map = cv1812h_get_schmitt_map,
191
+
};
192
+
193
+
static const struct pinctrl_pin_desc cv1812h_pins[] = {
194
+
PINCTRL_PIN(PIN_MIPI_TXM4, "MIPI_TXM4"),
195
+
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
196
+
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
197
+
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
198
+
PINCTRL_PIN(PIN_VIVO_D2, "VIVO_D2"),
199
+
PINCTRL_PIN(PIN_VIVO_D3, "VIVO_D3"),
200
+
PINCTRL_PIN(PIN_VIVO_D10, "VIVO_D10"),
201
+
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
202
+
PINCTRL_PIN(PIN_MIPI_TXP3, "MIPI_TXP3"),
203
+
PINCTRL_PIN(PIN_MIPI_TXM3, "MIPI_TXM3"),
204
+
PINCTRL_PIN(PIN_MIPI_TXP4, "MIPI_TXP4"),
205
+
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
206
+
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
207
+
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
208
+
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
209
+
PINCTRL_PIN(PIN_MIPIRX5N, "MIPIRX5N"),
210
+
PINCTRL_PIN(PIN_VIVO_D1, "VIVO_D1"),
211
+
PINCTRL_PIN(PIN_VIVO_D5, "VIVO_D5"),
212
+
PINCTRL_PIN(PIN_VIVO_D7, "VIVO_D7"),
213
+
PINCTRL_PIN(PIN_VIVO_D9, "VIVO_D9"),
214
+
PINCTRL_PIN(PIN_USB_ID, "USB_ID"),
215
+
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
216
+
PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
217
+
PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
218
+
PINCTRL_PIN(PIN_CAM_PD0, "CAM_PD0"),
219
+
PINCTRL_PIN(PIN_CAM_MCLK0, "CAM_MCLK0"),
220
+
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
221
+
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
222
+
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
223
+
PINCTRL_PIN(PIN_MIPIRX5P, "MIPIRX5P"),
224
+
PINCTRL_PIN(PIN_VIVO_CLK, "VIVO_CLK"),
225
+
PINCTRL_PIN(PIN_VIVO_D6, "VIVO_D6"),
226
+
PINCTRL_PIN(PIN_VIVO_D8, "VIVO_D8"),
227
+
PINCTRL_PIN(PIN_USB_VBUS_EN, "USB_VBUS_EN"),
228
+
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
229
+
PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
230
+
PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
231
+
PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
232
+
PINCTRL_PIN(PIN_CAM_MCLK1, "CAM_MCLK1"),
233
+
PINCTRL_PIN(PIN_IIC3_SCL, "IIC3_SCL"),
234
+
PINCTRL_PIN(PIN_VIVO_D4, "VIVO_D4"),
235
+
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
236
+
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
237
+
PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
238
+
PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
239
+
PINCTRL_PIN(PIN_CAM_PD1, "CAM_PD1"),
240
+
PINCTRL_PIN(PIN_CAM_RST0, "CAM_RST0"),
241
+
PINCTRL_PIN(PIN_VIVO_D0, "VIVO_D0"),
242
+
PINCTRL_PIN(PIN_ADC1, "ADC1"),
243
+
PINCTRL_PIN(PIN_ADC2, "ADC2"),
244
+
PINCTRL_PIN(PIN_ADC3, "ADC3"),
245
+
PINCTRL_PIN(PIN_AUD_AOUTL, "AUD_AOUTL"),
246
+
PINCTRL_PIN(PIN_IIC3_SDA, "IIC3_SDA"),
247
+
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
248
+
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
249
+
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
250
+
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
251
+
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
252
+
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
253
+
PINCTRL_PIN(PIN_RSTN, "RSTN"),
254
+
PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
255
+
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
256
+
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
257
+
PINCTRL_PIN(PIN_AUD_AINR_MIC, "AUD_AINR_MIC"),
258
+
PINCTRL_PIN(PIN_IIC2_SCL, "IIC2_SCL"),
259
+
PINCTRL_PIN(PIN_IIC2_SDA, "IIC2_SDA"),
260
+
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
261
+
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
262
+
PINCTRL_PIN(PIN_UART2_RX, "UART2_RX"),
263
+
PINCTRL_PIN(PIN_UART2_CTS, "UART2_CTS"),
264
+
PINCTRL_PIN(PIN_UART2_TX, "UART2_TX"),
265
+
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
266
+
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
267
+
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
268
+
PINCTRL_PIN(PIN_CLK32K, "CLK32K"),
269
+
PINCTRL_PIN(PIN_UART2_RTS, "UART2_RTS"),
270
+
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
271
+
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
272
+
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
273
+
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
274
+
PINCTRL_PIN(PIN_JTAG_CPU_TRST, "JTAG_CPU_TRST"),
275
+
PINCTRL_PIN(PIN_PWR_ON, "PWR_ON"),
276
+
PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
277
+
PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
278
+
PINCTRL_PIN(PIN_CLK25M, "CLK25M"),
279
+
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
280
+
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
281
+
PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
282
+
PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
283
+
PINCTRL_PIN(PIN_PWR_WAKEUP1, "PWR_WAKEUP1"),
284
+
PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
285
+
PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
286
+
PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
287
+
PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
288
+
PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
289
+
PINCTRL_PIN(PIN_EMMC_RSTN, "EMMC_RSTN"),
290
+
PINCTRL_PIN(PIN_AUX0, "AUX0"),
291
+
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
292
+
PINCTRL_PIN(PIN_PWR_SEQ3, "PWR_SEQ3"),
293
+
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
294
+
PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
295
+
PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
296
+
PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
297
+
PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
298
+
PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
299
+
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
300
+
PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
301
+
PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
302
+
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
303
+
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
304
+
};
305
+
306
+
static const struct cv1800_pin cv1812h_pin_data[ARRAY_SIZE(cv1812h_pins)] = {
307
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM4, VDD18A_MIPI,
308
+
IO_TYPE_1V8_ONLY,
309
+
CV1800_PINCONF_AREA_SYS, 0x194, 7,
310
+
CV1800_PINCONF_AREA_SYS, 0xc60),
311
+
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
312
+
IO_TYPE_1V8_ONLY,
313
+
CV1800_PINCONF_AREA_SYS, 0x18c, 7,
314
+
CV1800_PINCONF_AREA_SYS, 0xc58),
315
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
316
+
IO_TYPE_1V8_ONLY,
317
+
CV1800_PINCONF_AREA_SYS, 0x178, 7,
318
+
CV1800_PINCONF_AREA_SYS, 0x118, 7,
319
+
CV1800_PINCONF_AREA_SYS, 0xc44),
320
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
321
+
IO_TYPE_1V8_ONLY,
322
+
CV1800_PINCONF_AREA_SYS, 0x170, 7,
323
+
CV1800_PINCONF_AREA_SYS, 0x11c, 7,
324
+
CV1800_PINCONF_AREA_SYS, 0xc3c),
325
+
CV1800_GENERAL_PIN(PIN_VIVO_D2, VDDIO_VIVO,
326
+
IO_TYPE_1V8_OR_3V3,
327
+
CV1800_PINCONF_AREA_SYS, 0x154, 7,
328
+
CV1800_PINCONF_AREA_SYS, 0xc20),
329
+
CV1800_GENERAL_PIN(PIN_VIVO_D3, VDDIO_VIVO,
330
+
IO_TYPE_1V8_OR_3V3,
331
+
CV1800_PINCONF_AREA_SYS, 0x150, 7,
332
+
CV1800_PINCONF_AREA_SYS, 0xc1c),
333
+
CV1800_GENERAL_PIN(PIN_VIVO_D10, VDDIO_VIVO,
334
+
IO_TYPE_1V8_OR_3V3,
335
+
CV1800_PINCONF_AREA_SYS, 0x134, 7,
336
+
CV1800_PINCONF_AREA_SYS, 0xc00),
337
+
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDDIO18_1,
338
+
IO_TYPE_1V8_ONLY,
339
+
CV1800_PINCONF_AREA_SYS, 0x108, 5,
340
+
CV1800_PINCONF_AREA_SYS, 0x820),
341
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP3, VDD18A_MIPI,
342
+
IO_TYPE_1V8_ONLY,
343
+
CV1800_PINCONF_AREA_SYS, 0x1a0, 7,
344
+
CV1800_PINCONF_AREA_SYS, 0xc6c),
345
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM3, VDD18A_MIPI,
346
+
IO_TYPE_1V8_ONLY,
347
+
CV1800_PINCONF_AREA_SYS, 0x19c, 7,
348
+
CV1800_PINCONF_AREA_SYS, 0xc68),
349
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP4, VDD18A_MIPI,
350
+
IO_TYPE_1V8_ONLY,
351
+
CV1800_PINCONF_AREA_SYS, 0x198, 7,
352
+
CV1800_PINCONF_AREA_SYS, 0xc64),
353
+
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
354
+
IO_TYPE_1V8_ONLY,
355
+
CV1800_PINCONF_AREA_SYS, 0x190, 7,
356
+
CV1800_PINCONF_AREA_SYS, 0xc5c),
357
+
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
358
+
IO_TYPE_1V8_ONLY,
359
+
CV1800_PINCONF_AREA_SYS, 0x184, 7,
360
+
CV1800_PINCONF_AREA_SYS, 0xc50),
361
+
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
362
+
IO_TYPE_1V8_ONLY,
363
+
CV1800_PINCONF_AREA_SYS, 0x17c, 7,
364
+
CV1800_PINCONF_AREA_SYS, 0xc48),
365
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
366
+
IO_TYPE_1V8_ONLY,
367
+
CV1800_PINCONF_AREA_SYS, 0x16c, 7,
368
+
CV1800_PINCONF_AREA_SYS, 0x120, 7,
369
+
CV1800_PINCONF_AREA_SYS, 0xc38),
370
+
CV1800_GENERAL_PIN(PIN_MIPIRX5N, VDD18A_MIPI,
371
+
IO_TYPE_1V8_ONLY,
372
+
CV1800_PINCONF_AREA_SYS, 0x164, 7,
373
+
CV1800_PINCONF_AREA_SYS, 0xc30),
374
+
CV1800_GENERAL_PIN(PIN_VIVO_D1, VDDIO_VIVO,
375
+
IO_TYPE_1V8_OR_3V3,
376
+
CV1800_PINCONF_AREA_SYS, 0x158, 7,
377
+
CV1800_PINCONF_AREA_SYS, 0xc24),
378
+
CV1800_GENERAL_PIN(PIN_VIVO_D5, VDDIO_VIVO,
379
+
IO_TYPE_1V8_OR_3V3,
380
+
CV1800_PINCONF_AREA_SYS, 0x148, 7,
381
+
CV1800_PINCONF_AREA_SYS, 0xc14),
382
+
CV1800_GENERAL_PIN(PIN_VIVO_D7, VDDIO_VIVO,
383
+
IO_TYPE_1V8_OR_3V3,
384
+
CV1800_PINCONF_AREA_SYS, 0x140, 7,
385
+
CV1800_PINCONF_AREA_SYS, 0xc0c),
386
+
CV1800_GENERAL_PIN(PIN_VIVO_D9, VDDIO_VIVO,
387
+
IO_TYPE_1V8_OR_3V3,
388
+
CV1800_PINCONF_AREA_SYS, 0x138, 7,
389
+
CV1800_PINCONF_AREA_SYS, 0xc04),
390
+
CV1800_GENERAL_PIN(PIN_USB_ID, VDDIO18_1,
391
+
IO_TYPE_1V8_ONLY,
392
+
CV1800_PINCONF_AREA_SYS, 0x0fc, 3,
393
+
CV1800_PINCONF_AREA_SYS, 0x814),
394
+
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_EPHY,
395
+
IO_TYPE_ETH,
396
+
CV1800_PINCONF_AREA_SYS, 0x130, 7),
397
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
398
+
IO_TYPE_1V8_ONLY,
399
+
CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
400
+
CV1800_PINCONF_AREA_SYS, 0xc74),
401
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
402
+
IO_TYPE_1V8_ONLY,
403
+
CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
404
+
CV1800_PINCONF_AREA_SYS, 0xc70),
405
+
CV1800_GENERAL_PIN(PIN_CAM_PD0, VDD18A_MIPI,
406
+
IO_TYPE_1V8_ONLY,
407
+
CV1800_PINCONF_AREA_SYS, 0x004, 4,
408
+
CV1800_PINCONF_AREA_SYS, 0xb04),
409
+
CV1800_GENERAL_PIN(PIN_CAM_MCLK0, VDD18A_MIPI,
410
+
IO_TYPE_1V8_ONLY,
411
+
CV1800_PINCONF_AREA_SYS, 0x000, 3,
412
+
CV1800_PINCONF_AREA_SYS, 0xb00),
413
+
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
414
+
IO_TYPE_1V8_ONLY,
415
+
CV1800_PINCONF_AREA_SYS, 0x188, 7,
416
+
CV1800_PINCONF_AREA_SYS, 0xc54),
417
+
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
418
+
IO_TYPE_1V8_ONLY,
419
+
CV1800_PINCONF_AREA_SYS, 0x180, 7,
420
+
CV1800_PINCONF_AREA_SYS, 0xc4c),
421
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
422
+
IO_TYPE_1V8_ONLY,
423
+
CV1800_PINCONF_AREA_SYS, 0x174, 7,
424
+
CV1800_PINCONF_AREA_SYS, 0x114, 7,
425
+
CV1800_PINCONF_AREA_SYS, 0xc40),
426
+
CV1800_GENERAL_PIN(PIN_MIPIRX5P, VDD18A_MIPI,
427
+
IO_TYPE_1V8_ONLY,
428
+
CV1800_PINCONF_AREA_SYS, 0x168, 7,
429
+
CV1800_PINCONF_AREA_SYS, 0xc34),
430
+
CV1800_GENERAL_PIN(PIN_VIVO_CLK, VDDIO_VIVO,
431
+
IO_TYPE_1V8_OR_3V3,
432
+
CV1800_PINCONF_AREA_SYS, 0x160, 7,
433
+
CV1800_PINCONF_AREA_SYS, 0xc2c),
434
+
CV1800_GENERAL_PIN(PIN_VIVO_D6, VDDIO_VIVO,
435
+
IO_TYPE_1V8_OR_3V3,
436
+
CV1800_PINCONF_AREA_SYS, 0x144, 7,
437
+
CV1800_PINCONF_AREA_SYS, 0xc10),
438
+
CV1800_GENERAL_PIN(PIN_VIVO_D8, VDDIO_VIVO,
439
+
IO_TYPE_1V8_OR_3V3,
440
+
CV1800_PINCONF_AREA_SYS, 0x13c, 7,
441
+
CV1800_PINCONF_AREA_SYS, 0xc08),
442
+
CV1800_GENERAL_PIN(PIN_USB_VBUS_EN, VDDIO18_1,
443
+
IO_TYPE_1V8_ONLY,
444
+
CV1800_PINCONF_AREA_SYS, 0x100, 3,
445
+
CV1800_PINCONF_AREA_SYS, 0x818),
446
+
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_EPHY,
447
+
IO_TYPE_ETH,
448
+
CV1800_PINCONF_AREA_SYS, 0x12c, 7),
449
+
CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDDIO18_1,
450
+
IO_TYPE_1V8_ONLY,
451
+
CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
452
+
CV1800_PINCONF_AREA_SYS, 0xc8c),
453
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
454
+
IO_TYPE_1V8_ONLY,
455
+
CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
456
+
CV1800_PINCONF_AREA_SYS, 0xc7c),
457
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
458
+
IO_TYPE_1V8_ONLY,
459
+
CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
460
+
CV1800_PINCONF_AREA_SYS, 0xc78),
461
+
CV1800_GENERAL_PIN(PIN_CAM_MCLK1, VDD18A_MIPI,
462
+
IO_TYPE_1V8_ONLY,
463
+
CV1800_PINCONF_AREA_SYS, 0x00c, 4,
464
+
CV1800_PINCONF_AREA_SYS, 0xb0c),
465
+
CV1800_GENERAL_PIN(PIN_IIC3_SCL, VDD18A_MIPI,
466
+
IO_TYPE_1V8_ONLY,
467
+
CV1800_PINCONF_AREA_SYS, 0x014, 3,
468
+
CV1800_PINCONF_AREA_SYS, 0xb14),
469
+
CV1800_GENERAL_PIN(PIN_VIVO_D4, VDDIO_VIVO,
470
+
IO_TYPE_1V8_OR_3V3,
471
+
CV1800_PINCONF_AREA_SYS, 0x14c, 7,
472
+
CV1800_PINCONF_AREA_SYS, 0xc18),
473
+
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_EPHY,
474
+
IO_TYPE_ETH,
475
+
CV1800_PINCONF_AREA_SYS, 0x128, 7),
476
+
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_EPHY,
477
+
IO_TYPE_ETH,
478
+
CV1800_PINCONF_AREA_SYS, 0x124, 7),
479
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
480
+
IO_TYPE_1V8_ONLY,
481
+
CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
482
+
CV1800_PINCONF_AREA_SYS, 0xc84),
483
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
484
+
IO_TYPE_1V8_ONLY,
485
+
CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
486
+
CV1800_PINCONF_AREA_SYS, 0xc80),
487
+
CV1800_GENERAL_PIN(PIN_CAM_PD1, VDD18A_MIPI,
488
+
IO_TYPE_1V8_ONLY,
489
+
CV1800_PINCONF_AREA_SYS, 0x010, 6,
490
+
CV1800_PINCONF_AREA_SYS, 0xb10),
491
+
CV1800_GENERAL_PIN(PIN_CAM_RST0, VDD18A_MIPI,
492
+
IO_TYPE_1V8_ONLY,
493
+
CV1800_PINCONF_AREA_SYS, 0x008, 6,
494
+
CV1800_PINCONF_AREA_SYS, 0xb08),
495
+
CV1800_GENERAL_PIN(PIN_VIVO_D0, VDDIO_VIVO,
496
+
IO_TYPE_1V8_OR_3V3,
497
+
CV1800_PINCONF_AREA_SYS, 0x15c, 7,
498
+
CV1800_PINCONF_AREA_SYS, 0xc28),
499
+
CV1800_GENERAL_PIN(PIN_ADC1, VDDIO18_1,
500
+
IO_TYPE_1V8_ONLY,
501
+
CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
502
+
CV1800_PINCONF_AREA_SYS, 0x810),
503
+
CV1800_GENERAL_PIN(PIN_ADC2, VDDIO18_1,
504
+
IO_TYPE_1V8_ONLY,
505
+
CV1800_PINCONF_AREA_SYS, 0x0f4, 7,
506
+
CV1800_PINCONF_AREA_SYS, 0x80c),
507
+
CV1800_GENERAL_PIN(PIN_ADC3, VDDIO18_1,
508
+
IO_TYPE_1V8_ONLY,
509
+
CV1800_PINCONF_AREA_SYS, 0x0f0, 7,
510
+
CV1800_PINCONF_AREA_SYS, 0x808),
511
+
CV1800_FUNC_PIN(PIN_AUD_AOUTL, VDD18A_MIPI,
512
+
IO_TYPE_AUDIO,
513
+
CV1800_PINCONF_AREA_SYS, 0x1c4, 5),
514
+
CV1800_GENERAL_PIN(PIN_IIC3_SDA, VDD18A_MIPI,
515
+
IO_TYPE_1V8_ONLY,
516
+
CV1800_PINCONF_AREA_SYS, 0x018, 3,
517
+
CV1800_PINCONF_AREA_SYS, 0xb18),
518
+
CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
519
+
IO_TYPE_1V8_OR_3V3,
520
+
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
521
+
CV1800_PINCONF_AREA_RTC, 0x05c),
522
+
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
523
+
IO_TYPE_AUDIO,
524
+
CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
525
+
CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
526
+
IO_TYPE_1V8_OR_3V3,
527
+
CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
528
+
CV1800_PINCONF_AREA_RTC, 0x058),
529
+
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
530
+
IO_TYPE_1V8_OR_3V3,
531
+
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
532
+
CV1800_PINCONF_AREA_RTC, 0x06c),
533
+
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
534
+
IO_TYPE_1V8_OR_3V3,
535
+
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
536
+
CV1800_PINCONF_AREA_RTC, 0x068),
537
+
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
538
+
IO_TYPE_AUDIO,
539
+
CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
540
+
CV1800_GENERAL_PIN(PIN_RSTN, VDDIO18_1,
541
+
IO_TYPE_1V8_ONLY,
542
+
CV1800_PINCONF_AREA_SYS, 0x0e8, 0,
543
+
CV1800_PINCONF_AREA_SYS, 0x800),
544
+
CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDDIO18_1,
545
+
IO_TYPE_1V8_ONLY,
546
+
CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
547
+
CV1800_PINCONF_AREA_SYS, 0x804),
548
+
CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
549
+
IO_TYPE_1V8_OR_3V3,
550
+
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
551
+
CV1800_PINCONF_AREA_RTC, 0x060),
552
+
CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
553
+
IO_TYPE_1V8_OR_3V3,
554
+
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
555
+
CV1800_PINCONF_AREA_RTC, 0x064),
556
+
CV1800_FUNC_PIN(PIN_AUD_AINR_MIC, VDD18A_MIPI,
557
+
IO_TYPE_AUDIO,
558
+
CV1800_PINCONF_AREA_SYS, 0x1c0, 6),
559
+
CV1800_GENERAL_PIN(PIN_IIC2_SCL, VDDIO_RTC,
560
+
IO_TYPE_1V8_ONLY,
561
+
CV1800_PINCONF_AREA_SYS, 0x0b8, 7,
562
+
CV1800_PINCONF_AREA_RTC, 0x040),
563
+
CV1800_GENERAL_PIN(PIN_IIC2_SDA, VDDIO_RTC,
564
+
IO_TYPE_1V8_ONLY,
565
+
CV1800_PINCONF_AREA_SYS, 0x0bc, 7,
566
+
CV1800_PINCONF_AREA_RTC, 0x044),
567
+
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_EMMC,
568
+
IO_TYPE_1V8_OR_3V3,
569
+
CV1800_PINCONF_AREA_SYS, 0x034, 3,
570
+
CV1800_PINCONF_AREA_SYS, 0x900),
571
+
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0,
572
+
IO_TYPE_1V8_OR_3V3,
573
+
CV1800_PINCONF_AREA_SYS, 0x028, 7,
574
+
CV1800_PINCONF_AREA_SYS, 0xa0c),
575
+
CV1800_GENERAL_PIN(PIN_UART2_RX, VDDIO_RTC,
576
+
IO_TYPE_1V8_ONLY,
577
+
CV1800_PINCONF_AREA_SYS, 0x0c8, 7,
578
+
CV1800_PINCONF_AREA_RTC, 0x050),
579
+
CV1800_GENERAL_PIN(PIN_UART2_CTS, VDDIO_RTC,
580
+
IO_TYPE_1V8_ONLY,
581
+
CV1800_PINCONF_AREA_SYS, 0x0cc, 7,
582
+
CV1800_PINCONF_AREA_RTC, 0x054),
583
+
CV1800_GENERAL_PIN(PIN_UART2_TX, VDDIO_RTC,
584
+
IO_TYPE_1V8_ONLY,
585
+
CV1800_PINCONF_AREA_SYS, 0x0c0, 7,
586
+
CV1800_PINCONF_AREA_RTC, 0x048),
587
+
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0,
588
+
IO_TYPE_1V8_OR_3V3,
589
+
CV1800_PINCONF_AREA_SYS, 0x01c, 7,
590
+
CV1800_PINCONF_AREA_SYS, 0xa00),
591
+
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0,
592
+
IO_TYPE_1V8_OR_3V3,
593
+
CV1800_PINCONF_AREA_SYS, 0x024, 7,
594
+
CV1800_PINCONF_AREA_SYS, 0xa08),
595
+
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0,
596
+
IO_TYPE_1V8_OR_3V3,
597
+
CV1800_PINCONF_AREA_SYS, 0x020, 7,
598
+
CV1800_PINCONF_AREA_SYS, 0xa04),
599
+
CV1800_GENERAL_PIN(PIN_CLK32K, VDDIO_RTC,
600
+
IO_TYPE_1V8_ONLY,
601
+
CV1800_PINCONF_AREA_SYS, 0x0b0, 7,
602
+
CV1800_PINCONF_AREA_RTC, 0x038),
603
+
CV1800_GENERAL_PIN(PIN_UART2_RTS, VDDIO_RTC,
604
+
IO_TYPE_1V8_ONLY,
605
+
CV1800_PINCONF_AREA_SYS, 0x0c4, 7,
606
+
CV1800_PINCONF_AREA_RTC, 0x04c),
607
+
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0,
608
+
IO_TYPE_1V8_OR_3V3,
609
+
CV1800_PINCONF_AREA_SYS, 0x030, 7,
610
+
CV1800_PINCONF_AREA_SYS, 0xa14),
611
+
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0,
612
+
IO_TYPE_1V8_OR_3V3,
613
+
CV1800_PINCONF_AREA_SYS, 0x02c, 7,
614
+
CV1800_PINCONF_AREA_SYS, 0xa10),
615
+
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_EMMC,
616
+
IO_TYPE_1V8_OR_3V3,
617
+
CV1800_PINCONF_AREA_SYS, 0x044, 7,
618
+
CV1800_PINCONF_AREA_SYS, 0x910),
619
+
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_EMMC,
620
+
IO_TYPE_1V8_OR_3V3,
621
+
CV1800_PINCONF_AREA_SYS, 0x040, 7,
622
+
CV1800_PINCONF_AREA_SYS, 0x90c),
623
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TRST, VDDIO_EMMC,
624
+
IO_TYPE_1V8_OR_3V3,
625
+
CV1800_PINCONF_AREA_SYS, 0x06c, 6,
626
+
CV1800_PINCONF_AREA_SYS, 0x938),
627
+
CV1800_GENERAL_PIN(PIN_PWR_ON, VDDIO_RTC,
628
+
IO_TYPE_1V8_ONLY,
629
+
CV1800_PINCONF_AREA_SYS, 0x09c, 7,
630
+
CV1800_PINCONF_AREA_RTC, 0x024),
631
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
632
+
IO_TYPE_1V8_ONLY,
633
+
CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
634
+
CV1800_PINCONF_AREA_RTC, 0x034),
635
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
636
+
IO_TYPE_1V8_ONLY,
637
+
CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
638
+
CV1800_PINCONF_AREA_RTC, 0x02c),
639
+
CV1800_GENERAL_PIN(PIN_CLK25M, VDDIO_RTC,
640
+
IO_TYPE_1V8_ONLY,
641
+
CV1800_PINCONF_AREA_SYS, 0x0b4, 7,
642
+
CV1800_PINCONF_AREA_RTC, 0x03c),
643
+
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_EMMC,
644
+
IO_TYPE_1V8_OR_3V3,
645
+
CV1800_PINCONF_AREA_SYS, 0x038, 3,
646
+
CV1800_PINCONF_AREA_SYS, 0x904),
647
+
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_EMMC,
648
+
IO_TYPE_1V8_OR_3V3,
649
+
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
650
+
CV1800_PINCONF_AREA_SYS, 0x908),
651
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_EMMC,
652
+
IO_TYPE_1V8_OR_3V3,
653
+
CV1800_PINCONF_AREA_SYS, 0x068, 7,
654
+
CV1800_PINCONF_AREA_SYS, 0x934),
655
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_EMMC,
656
+
IO_TYPE_1V8_OR_3V3,
657
+
CV1800_PINCONF_AREA_SYS, 0x064, 7,
658
+
CV1800_PINCONF_AREA_SYS, 0x930),
659
+
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP1, VDDIO_RTC,
660
+
IO_TYPE_1V8_ONLY,
661
+
CV1800_PINCONF_AREA_SYS, 0x094, 7,
662
+
CV1800_PINCONF_AREA_RTC, 0x01c),
663
+
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
664
+
IO_TYPE_1V8_ONLY,
665
+
CV1800_PINCONF_AREA_SYS, 0x090, 7,
666
+
CV1800_PINCONF_AREA_RTC, 0x018),
667
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
668
+
IO_TYPE_1V8_ONLY,
669
+
CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
670
+
CV1800_PINCONF_AREA_RTC, 0x030),
671
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_EMMC,
672
+
IO_TYPE_1V8_OR_3V3,
673
+
CV1800_PINCONF_AREA_SYS, 0x058, 3,
674
+
CV1800_PINCONF_AREA_SYS, 0x924),
675
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_EMMC,
676
+
IO_TYPE_1V8_OR_3V3,
677
+
CV1800_PINCONF_AREA_SYS, 0x054, 3,
678
+
CV1800_PINCONF_AREA_SYS, 0x920),
679
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_EMMC,
680
+
IO_TYPE_1V8_OR_3V3,
681
+
CV1800_PINCONF_AREA_SYS, 0x04c, 3,
682
+
CV1800_PINCONF_AREA_SYS, 0x918),
683
+
CV1800_GENERAL_PIN(PIN_EMMC_RSTN, VDDIO_EMMC,
684
+
IO_TYPE_1V8_OR_3V3,
685
+
CV1800_PINCONF_AREA_SYS, 0x048, 4,
686
+
CV1800_PINCONF_AREA_SYS, 0x914),
687
+
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_EMMC,
688
+
IO_TYPE_1V8_OR_3V3,
689
+
CV1800_PINCONF_AREA_SYS, 0x078, 7,
690
+
CV1800_PINCONF_AREA_SYS, 0x944),
691
+
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_EMMC,
692
+
IO_TYPE_1V8_OR_3V3,
693
+
CV1800_PINCONF_AREA_SYS, 0x074, 7,
694
+
CV1800_PINCONF_AREA_SYS, 0x940),
695
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ3, VDDIO_RTC,
696
+
IO_TYPE_1V8_ONLY,
697
+
CV1800_PINCONF_AREA_SYS, 0x08c, 3,
698
+
CV1800_PINCONF_AREA_RTC, 0x010),
699
+
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
700
+
IO_TYPE_1V8_ONLY,
701
+
CV1800_PINCONF_AREA_SYS, 0x07c, 0,
702
+
CV1800_PINCONF_AREA_RTC, 0x000),
703
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
704
+
IO_TYPE_1V8_ONLY,
705
+
CV1800_PINCONF_AREA_SYS, 0x084, 3,
706
+
CV1800_PINCONF_AREA_RTC, 0x008),
707
+
CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
708
+
IO_TYPE_1V8_ONLY,
709
+
CV1800_PINCONF_AREA_SYS, 0x098, 7,
710
+
CV1800_PINCONF_AREA_RTC, 0x020),
711
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_EMMC,
712
+
IO_TYPE_1V8_OR_3V3,
713
+
CV1800_PINCONF_AREA_SYS, 0x060, 3,
714
+
CV1800_PINCONF_AREA_SYS, 0x92c),
715
+
CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_EMMC,
716
+
IO_TYPE_1V8_OR_3V3,
717
+
CV1800_PINCONF_AREA_SYS, 0x05c, 3,
718
+
CV1800_PINCONF_AREA_SYS, 0x928),
719
+
CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_EMMC,
720
+
IO_TYPE_1V8_OR_3V3,
721
+
CV1800_PINCONF_AREA_SYS, 0x050, 3,
722
+
CV1800_PINCONF_AREA_SYS, 0x91c),
723
+
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_EMMC,
724
+
IO_TYPE_1V8_OR_3V3,
725
+
CV1800_PINCONF_AREA_SYS, 0x070, 7,
726
+
CV1800_PINCONF_AREA_SYS, 0x93c),
727
+
CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
728
+
IO_TYPE_1V8_ONLY,
729
+
CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
730
+
CV1800_PINCONF_AREA_RTC, 0x0e0),
731
+
CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
732
+
IO_TYPE_1V8_ONLY,
733
+
CV1800_PINCONF_AREA_SYS, 0x080, 0,
734
+
CV1800_PINCONF_AREA_RTC, 0x004),
735
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
736
+
IO_TYPE_1V8_ONLY,
737
+
CV1800_PINCONF_AREA_SYS, 0x088, 3,
738
+
CV1800_PINCONF_AREA_RTC, 0x00c),
739
+
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
740
+
IO_TYPE_1V8_ONLY,
741
+
CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
742
+
CV1800_PINCONF_AREA_RTC, 0x028),
743
+
};
744
+
745
+
static const struct cv1800_pinctrl_data cv1812h_pindata = {
746
+
.pins = cv1812h_pins,
747
+
.pindata = cv1812h_pin_data,
748
+
.pdnames = cv1812h_power_domain_desc,
749
+
.vddio_ops = &cv1812h_vddio_cfg_ops,
750
+
.npins = ARRAY_SIZE(cv1812h_pins),
751
+
.npd = ARRAY_SIZE(cv1812h_power_domain_desc),
752
+
};
753
+
754
+
static const struct of_device_id cv1812h_pinctrl_ids[] = {
755
+
{ .compatible = "sophgo,cv1812h-pinctrl", .data = &cv1812h_pindata },
756
+
{ }
757
+
};
758
+
MODULE_DEVICE_TABLE(of, cv1812h_pinctrl_ids);
759
+
760
+
static struct platform_driver cv1812h_pinctrl_driver = {
761
+
.probe = cv1800_pinctrl_probe,
762
+
.driver = {
763
+
.name = "cv1812h-pinctrl",
764
+
.suppress_bind_attrs = true,
765
+
.of_match_table = cv1812h_pinctrl_ids,
766
+
},
767
+
};
768
+
module_platform_driver(cv1812h_pinctrl_driver);
769
+
770
+
MODULE_DESCRIPTION("Pinctrl driver for the CV1812H series SoC");
771
+
MODULE_LICENSE("GPL");
+765
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
+765
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo CV18XX SoCs pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
*/
8
+
9
+
#include <linux/bitfield.h>
10
+
#include <linux/export.h>
11
+
#include <linux/io.h>
12
+
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/bsearch.h>
15
+
#include <linux/seq_file.h>
16
+
#include <linux/spinlock.h>
17
+
18
+
#include <linux/pinctrl/consumer.h>
19
+
#include <linux/pinctrl/machine.h>
20
+
#include <linux/pinctrl/pinconf-generic.h>
21
+
#include <linux/pinctrl/pinconf.h>
22
+
#include <linux/pinctrl/pinctrl.h>
23
+
#include <linux/pinctrl/pinmux.h>
24
+
25
+
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
26
+
27
+
#include "../core.h"
28
+
#include "../pinctrl-utils.h"
29
+
#include "../pinconf.h"
30
+
#include "../pinmux.h"
31
+
#include "pinctrl-cv18xx.h"
32
+
33
+
struct cv1800_pinctrl {
34
+
struct device *dev;
35
+
struct pinctrl_dev *pctl_dev;
36
+
const struct cv1800_pinctrl_data *data;
37
+
struct pinctrl_desc pdesc;
38
+
u32 *power_cfg;
39
+
40
+
struct mutex mutex;
41
+
raw_spinlock_t lock;
42
+
43
+
void __iomem *regs[2];
44
+
};
45
+
46
+
struct cv1800_pin_mux_config {
47
+
struct cv1800_pin *pin;
48
+
u32 config;
49
+
};
50
+
51
+
static unsigned int cv1800_dt_get_pin(u32 value)
52
+
{
53
+
return value & GENMASK(15, 0);
54
+
}
55
+
56
+
static unsigned int cv1800_dt_get_pin_mux(u32 value)
57
+
{
58
+
return (value >> 16) & GENMASK(7, 0);
59
+
}
60
+
61
+
static unsigned int cv1800_dt_get_pin_mux2(u32 value)
62
+
{
63
+
return (value >> 24) & GENMASK(7, 0);
64
+
}
65
+
66
+
#define cv1800_pinctrl_get_component_addr(pctrl, _comp) \
67
+
((pctrl)->regs[(_comp)->area] + (_comp)->offset)
68
+
69
+
static int cv1800_cmp_pin(const void *key, const void *pivot)
70
+
{
71
+
const struct cv1800_pin *pin = pivot;
72
+
int pin_id = (long)key;
73
+
int pivid = pin->pin;
74
+
75
+
return pin_id - pivid;
76
+
}
77
+
78
+
static int cv1800_set_power_cfg(struct cv1800_pinctrl *pctrl,
79
+
u8 domain, u32 cfg)
80
+
{
81
+
if (domain >= pctrl->data->npd)
82
+
return -ENOTSUPP;
83
+
84
+
if (pctrl->power_cfg[domain] && pctrl->power_cfg[domain] != cfg)
85
+
return -EINVAL;
86
+
87
+
pctrl->power_cfg[domain] = cfg;
88
+
89
+
return 0;
90
+
}
91
+
92
+
static int cv1800_get_power_cfg(struct cv1800_pinctrl *pctrl,
93
+
u8 domain)
94
+
{
95
+
return pctrl->power_cfg[domain];
96
+
}
97
+
98
+
static struct cv1800_pin *cv1800_get_pin(struct cv1800_pinctrl *pctrl,
99
+
unsigned long pin)
100
+
{
101
+
return bsearch((void *)pin, pctrl->data->pindata, pctrl->data->npins,
102
+
sizeof(struct cv1800_pin), cv1800_cmp_pin);
103
+
}
104
+
105
+
#define PIN_BGA_ID_OFFSET 8
106
+
#define PIN_BGA_ID_MASK 0xff
107
+
108
+
static const char *const io_type_desc[] = {
109
+
"1V8",
110
+
"18OD33",
111
+
"AUDIO",
112
+
"ETH"
113
+
};
114
+
115
+
static const char *cv1800_get_power_cfg_desc(struct cv1800_pinctrl *pctrl,
116
+
u8 domain)
117
+
{
118
+
return pctrl->data->pdnames[domain];
119
+
}
120
+
121
+
static void cv1800_pctrl_dbg_show(struct pinctrl_dev *pctldev,
122
+
struct seq_file *seq, unsigned int pin_id)
123
+
{
124
+
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
125
+
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
126
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
127
+
u32 value;
128
+
void __iomem *reg;
129
+
130
+
if (pin->pin >> PIN_BGA_ID_OFFSET)
131
+
seq_printf(seq, "pos: %c%u ",
132
+
'A' + (pin->pin >> PIN_BGA_ID_OFFSET) - 1,
133
+
pin->pin & PIN_BGA_ID_MASK);
134
+
else
135
+
seq_printf(seq, "pos: %u ", pin->pin);
136
+
137
+
seq_printf(seq, "power-domain: %s ",
138
+
cv1800_get_power_cfg_desc(pctrl, pin->power_domain));
139
+
seq_printf(seq, "type: %s ", io_type_desc[type]);
140
+
141
+
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux);
142
+
value = readl(reg);
143
+
seq_printf(seq, "mux: 0x%08x ", value);
144
+
145
+
if (pin->flags & CV1800_PIN_HAVE_MUX2) {
146
+
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2);
147
+
value = readl(reg);
148
+
seq_printf(seq, "mux2: 0x%08x ", value);
149
+
}
150
+
151
+
if (type == IO_TYPE_1V8_ONLY || type == IO_TYPE_1V8_OR_3V3) {
152
+
reg = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf);
153
+
value = readl(reg);
154
+
seq_printf(seq, "conf: 0x%08x ", value);
155
+
}
156
+
}
157
+
158
+
static int cv1800_verify_pinmux_config(const struct cv1800_pin_mux_config *config)
159
+
{
160
+
unsigned int mux = cv1800_dt_get_pin_mux(config->config);
161
+
unsigned int mux2 = cv1800_dt_get_pin_mux2(config->config);
162
+
163
+
if (mux > config->pin->mux.max)
164
+
return -EINVAL;
165
+
166
+
if (config->pin->flags & CV1800_PIN_HAVE_MUX2) {
167
+
if (mux != config->pin->mux2.pfunc)
168
+
return -EINVAL;
169
+
170
+
if (mux2 > config->pin->mux2.max)
171
+
return -EINVAL;
172
+
} else {
173
+
if (mux2 != PIN_MUX_INVALD)
174
+
return -ENOTSUPP;
175
+
}
176
+
177
+
return 0;
178
+
}
179
+
180
+
static int cv1800_verify_pin_group(const struct cv1800_pin_mux_config *mux,
181
+
unsigned long npins)
182
+
{
183
+
enum cv1800_pin_io_type type;
184
+
u8 power_domain;
185
+
int i;
186
+
187
+
if (npins == 1)
188
+
return 0;
189
+
190
+
type = cv1800_pin_io_type(mux[0].pin);
191
+
power_domain = mux[0].pin->power_domain;
192
+
193
+
for (i = 0; i < npins; i++) {
194
+
if (type != cv1800_pin_io_type(mux[i].pin) ||
195
+
power_domain != mux[i].pin->power_domain)
196
+
return -ENOTSUPP;
197
+
}
198
+
199
+
return 0;
200
+
}
201
+
202
+
static int cv1800_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
203
+
struct device_node *np,
204
+
struct pinctrl_map **maps,
205
+
unsigned int *num_maps)
206
+
{
207
+
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
208
+
struct device *dev = pctrl->dev;
209
+
struct device_node *child;
210
+
struct pinctrl_map *map;
211
+
const char **grpnames;
212
+
const char *grpname;
213
+
int ngroups = 0;
214
+
int nmaps = 0;
215
+
int ret;
216
+
217
+
for_each_available_child_of_node(np, child)
218
+
ngroups += 1;
219
+
220
+
grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL);
221
+
if (!grpnames)
222
+
return -ENOMEM;
223
+
224
+
map = devm_kcalloc(dev, ngroups * 2, sizeof(*map), GFP_KERNEL);
225
+
if (!map)
226
+
return -ENOMEM;
227
+
228
+
ngroups = 0;
229
+
mutex_lock(&pctrl->mutex);
230
+
for_each_available_child_of_node(np, child) {
231
+
int npins = of_property_count_u32_elems(child, "pinmux");
232
+
unsigned int *pins;
233
+
struct cv1800_pin_mux_config *pinmuxs;
234
+
u32 config, power;
235
+
int i;
236
+
237
+
if (npins < 1) {
238
+
dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n",
239
+
np, child);
240
+
ret = -EINVAL;
241
+
goto dt_failed;
242
+
}
243
+
244
+
grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn",
245
+
np, child);
246
+
if (!grpname) {
247
+
ret = -ENOMEM;
248
+
goto dt_failed;
249
+
}
250
+
251
+
grpnames[ngroups++] = grpname;
252
+
253
+
pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
254
+
if (!pins) {
255
+
ret = -ENOMEM;
256
+
goto dt_failed;
257
+
}
258
+
259
+
pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL);
260
+
if (!pinmuxs) {
261
+
ret = -ENOMEM;
262
+
goto dt_failed;
263
+
}
264
+
265
+
for (i = 0; i < npins; i++) {
266
+
ret = of_property_read_u32_index(child, "pinmux",
267
+
i, &config);
268
+
if (ret)
269
+
goto dt_failed;
270
+
271
+
pins[i] = cv1800_dt_get_pin(config);
272
+
pinmuxs[i].config = config;
273
+
pinmuxs[i].pin = cv1800_get_pin(pctrl, pins[i]);
274
+
275
+
if (!pinmuxs[i].pin) {
276
+
dev_err(dev, "failed to get pin %d\n", pins[i]);
277
+
ret = -ENODEV;
278
+
goto dt_failed;
279
+
}
280
+
281
+
ret = cv1800_verify_pinmux_config(&pinmuxs[i]);
282
+
if (ret) {
283
+
dev_err(dev, "group %s pin %d is invalid\n",
284
+
grpname, i);
285
+
goto dt_failed;
286
+
}
287
+
}
288
+
289
+
ret = cv1800_verify_pin_group(pinmuxs, npins);
290
+
if (ret) {
291
+
dev_err(dev, "group %s is invalid\n", grpname);
292
+
goto dt_failed;
293
+
}
294
+
295
+
ret = of_property_read_u32(child, "power-source", &power);
296
+
if (ret)
297
+
goto dt_failed;
298
+
299
+
if (!(power == PIN_POWER_STATE_3V3 || power == PIN_POWER_STATE_1V8)) {
300
+
dev_err(dev, "group %s have unsupported power: %u\n",
301
+
grpname, power);
302
+
ret = -ENOTSUPP;
303
+
goto dt_failed;
304
+
}
305
+
306
+
ret = cv1800_set_power_cfg(pctrl, pinmuxs[0].pin->power_domain,
307
+
power);
308
+
if (ret)
309
+
goto dt_failed;
310
+
311
+
map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
312
+
map[nmaps].data.mux.function = np->name;
313
+
map[nmaps].data.mux.group = grpname;
314
+
nmaps += 1;
315
+
316
+
ret = pinconf_generic_parse_dt_config(child, pctldev,
317
+
&map[nmaps].data.configs.configs,
318
+
&map[nmaps].data.configs.num_configs);
319
+
if (ret) {
320
+
dev_err(dev, "failed to parse pin config of group %s: %d\n",
321
+
grpname, ret);
322
+
goto dt_failed;
323
+
}
324
+
325
+
ret = pinctrl_generic_add_group(pctldev, grpname,
326
+
pins, npins, pinmuxs);
327
+
if (ret < 0) {
328
+
dev_err(dev, "failed to add group %s: %d\n", grpname, ret);
329
+
goto dt_failed;
330
+
}
331
+
332
+
/* don't create a map if there are no pinconf settings */
333
+
if (map[nmaps].data.configs.num_configs == 0)
334
+
continue;
335
+
336
+
map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
337
+
map[nmaps].data.configs.group_or_pin = grpname;
338
+
nmaps += 1;
339
+
}
340
+
341
+
ret = pinmux_generic_add_function(pctldev, np->name,
342
+
grpnames, ngroups, NULL);
343
+
if (ret < 0) {
344
+
dev_err(dev, "error adding function %s: %d\n", np->name, ret);
345
+
goto function_failed;
346
+
}
347
+
348
+
*maps = map;
349
+
*num_maps = nmaps;
350
+
mutex_unlock(&pctrl->mutex);
351
+
352
+
return 0;
353
+
354
+
dt_failed:
355
+
of_node_put(child);
356
+
function_failed:
357
+
pinctrl_utils_free_map(pctldev, map, nmaps);
358
+
mutex_unlock(&pctrl->mutex);
359
+
return ret;
360
+
}
361
+
362
+
static const struct pinctrl_ops cv1800_pctrl_ops = {
363
+
.get_groups_count = pinctrl_generic_get_group_count,
364
+
.get_group_name = pinctrl_generic_get_group_name,
365
+
.get_group_pins = pinctrl_generic_get_group_pins,
366
+
.pin_dbg_show = cv1800_pctrl_dbg_show,
367
+
.dt_node_to_map = cv1800_pctrl_dt_node_to_map,
368
+
.dt_free_map = pinctrl_utils_free_map,
369
+
};
370
+
371
+
static int cv1800_pmx_set_mux(struct pinctrl_dev *pctldev,
372
+
unsigned int fsel, unsigned int gsel)
373
+
{
374
+
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
375
+
const struct group_desc *group;
376
+
const struct cv1800_pin_mux_config *configs;
377
+
unsigned int i;
378
+
379
+
group = pinctrl_generic_get_group(pctldev, gsel);
380
+
if (!group)
381
+
return -EINVAL;
382
+
383
+
configs = group->data;
384
+
385
+
for (i = 0; i < group->grp.npins; i++) {
386
+
const struct cv1800_pin *pin = configs[i].pin;
387
+
u32 value = configs[i].config;
388
+
void __iomem *reg_mux;
389
+
void __iomem *reg_mux2;
390
+
unsigned long flags;
391
+
u32 mux;
392
+
u32 mux2;
393
+
394
+
reg_mux = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux);
395
+
reg_mux2 = cv1800_pinctrl_get_component_addr(pctrl, &pin->mux2);
396
+
mux = cv1800_dt_get_pin_mux(value);
397
+
mux2 = cv1800_dt_get_pin_mux2(value);
398
+
399
+
raw_spin_lock_irqsave(&pctrl->lock, flags);
400
+
writel_relaxed(mux, reg_mux);
401
+
if (mux2 != PIN_MUX_INVALD)
402
+
writel_relaxed(mux2, reg_mux2);
403
+
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
404
+
}
405
+
406
+
return 0;
407
+
}
408
+
409
+
static const struct pinmux_ops cv1800_pmx_ops = {
410
+
.get_functions_count = pinmux_generic_get_function_count,
411
+
.get_function_name = pinmux_generic_get_function_name,
412
+
.get_function_groups = pinmux_generic_get_function_groups,
413
+
.set_mux = cv1800_pmx_set_mux,
414
+
.strict = true,
415
+
};
416
+
417
+
#define PIN_IO_PULLUP BIT(2)
418
+
#define PIN_IO_PULLDOWN BIT(3)
419
+
#define PIN_IO_DRIVE GENMASK(7, 5)
420
+
#define PIN_IO_SCHMITT GENMASK(9, 8)
421
+
#define PIN_IO_BUS_HOLD BIT(10)
422
+
#define PIN_IO_OUT_FAST_SLEW BIT(11)
423
+
424
+
static u32 cv1800_pull_down_typical_resistor(struct cv1800_pinctrl *pctrl,
425
+
struct cv1800_pin *pin)
426
+
{
427
+
return pctrl->data->vddio_ops->get_pull_down(pin, pctrl->power_cfg);
428
+
}
429
+
430
+
static u32 cv1800_pull_up_typical_resistor(struct cv1800_pinctrl *pctrl,
431
+
struct cv1800_pin *pin)
432
+
{
433
+
return pctrl->data->vddio_ops->get_pull_up(pin, pctrl->power_cfg);
434
+
}
435
+
436
+
static int cv1800_pinctrl_oc2reg(struct cv1800_pinctrl *pctrl,
437
+
struct cv1800_pin *pin, u32 target)
438
+
{
439
+
const u32 *map;
440
+
int i, len;
441
+
442
+
len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map);
443
+
if (len < 0)
444
+
return len;
445
+
446
+
for (i = 0; i < len; i++) {
447
+
if (map[i] >= target)
448
+
return i;
449
+
}
450
+
451
+
return -EINVAL;
452
+
}
453
+
454
+
static int cv1800_pinctrl_reg2oc(struct cv1800_pinctrl *pctrl,
455
+
struct cv1800_pin *pin, u32 reg)
456
+
{
457
+
const u32 *map;
458
+
int len;
459
+
460
+
len = pctrl->data->vddio_ops->get_oc_map(pin, pctrl->power_cfg, &map);
461
+
if (len < 0)
462
+
return len;
463
+
464
+
if (reg >= len)
465
+
return -EINVAL;
466
+
467
+
return map[reg];
468
+
}
469
+
470
+
static int cv1800_pinctrl_schmitt2reg(struct cv1800_pinctrl *pctrl,
471
+
struct cv1800_pin *pin, u32 target)
472
+
{
473
+
const u32 *map;
474
+
int i, len;
475
+
476
+
len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg,
477
+
&map);
478
+
if (len < 0)
479
+
return len;
480
+
481
+
for (i = 0; i < len; i++) {
482
+
if (map[i] == target)
483
+
return i;
484
+
}
485
+
486
+
return -EINVAL;
487
+
}
488
+
489
+
static int cv1800_pinctrl_reg2schmitt(struct cv1800_pinctrl *pctrl,
490
+
struct cv1800_pin *pin, u32 reg)
491
+
{
492
+
const u32 *map;
493
+
int len;
494
+
495
+
len = pctrl->data->vddio_ops->get_schmitt_map(pin, pctrl->power_cfg,
496
+
&map);
497
+
if (len < 0)
498
+
return len;
499
+
500
+
if (reg >= len)
501
+
return -EINVAL;
502
+
503
+
return map[reg];
504
+
}
505
+
506
+
static int cv1800_pconf_get(struct pinctrl_dev *pctldev,
507
+
unsigned int pin_id, unsigned long *config)
508
+
{
509
+
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
510
+
int param = pinconf_to_config_param(*config);
511
+
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
512
+
enum cv1800_pin_io_type type;
513
+
u32 value;
514
+
u32 arg;
515
+
bool enabled;
516
+
int ret;
517
+
518
+
if (!pin)
519
+
return -EINVAL;
520
+
521
+
type = cv1800_pin_io_type(pin);
522
+
if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO)
523
+
return -ENOTSUPP;
524
+
525
+
value = readl(cv1800_pinctrl_get_component_addr(pctrl, &pin->conf));
526
+
527
+
switch (param) {
528
+
case PIN_CONFIG_BIAS_PULL_DOWN:
529
+
enabled = FIELD_GET(PIN_IO_PULLDOWN, value);
530
+
arg = cv1800_pull_down_typical_resistor(pctrl, pin);
531
+
break;
532
+
case PIN_CONFIG_BIAS_PULL_UP:
533
+
enabled = FIELD_GET(PIN_IO_PULLUP, value);
534
+
arg = cv1800_pull_up_typical_resistor(pctrl, pin);
535
+
break;
536
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
537
+
enabled = true;
538
+
arg = FIELD_GET(PIN_IO_DRIVE, value);
539
+
ret = cv1800_pinctrl_reg2oc(pctrl, pin, arg);
540
+
if (ret < 0)
541
+
return ret;
542
+
arg = ret;
543
+
break;
544
+
case PIN_CONFIG_INPUT_SCHMITT_UV:
545
+
arg = FIELD_GET(PIN_IO_SCHMITT, value);
546
+
ret = cv1800_pinctrl_reg2schmitt(pctrl, pin, arg);
547
+
if (ret < 0)
548
+
return ret;
549
+
arg = ret;
550
+
enabled = arg != 0;
551
+
break;
552
+
case PIN_CONFIG_POWER_SOURCE:
553
+
enabled = true;
554
+
arg = cv1800_get_power_cfg(pctrl, pin->power_domain);
555
+
break;
556
+
case PIN_CONFIG_SLEW_RATE:
557
+
enabled = true;
558
+
arg = FIELD_GET(PIN_IO_OUT_FAST_SLEW, value);
559
+
break;
560
+
case PIN_CONFIG_BIAS_BUS_HOLD:
561
+
arg = FIELD_GET(PIN_IO_BUS_HOLD, value);
562
+
enabled = arg != 0;
563
+
break;
564
+
default:
565
+
return -ENOTSUPP;
566
+
}
567
+
568
+
*config = pinconf_to_config_packed(param, arg);
569
+
570
+
return enabled ? 0 : -EINVAL;
571
+
}
572
+
573
+
static int cv1800_pinconf_compute_config(struct cv1800_pinctrl *pctrl,
574
+
struct cv1800_pin *pin,
575
+
unsigned long *configs,
576
+
unsigned int num_configs,
577
+
u32 *value)
578
+
{
579
+
int i;
580
+
u32 v = 0;
581
+
enum cv1800_pin_io_type type;
582
+
int ret;
583
+
584
+
if (!pin)
585
+
return -EINVAL;
586
+
587
+
type = cv1800_pin_io_type(pin);
588
+
if (type == IO_TYPE_ETH || type == IO_TYPE_AUDIO)
589
+
return -ENOTSUPP;
590
+
591
+
for (i = 0; i < num_configs; i++) {
592
+
int param = pinconf_to_config_param(configs[i]);
593
+
u32 arg = pinconf_to_config_argument(configs[i]);
594
+
595
+
switch (param) {
596
+
case PIN_CONFIG_BIAS_PULL_DOWN:
597
+
v &= ~PIN_IO_PULLDOWN;
598
+
v |= FIELD_PREP(PIN_IO_PULLDOWN, arg);
599
+
break;
600
+
case PIN_CONFIG_BIAS_PULL_UP:
601
+
v &= ~PIN_IO_PULLUP;
602
+
v |= FIELD_PREP(PIN_IO_PULLUP, arg);
603
+
break;
604
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
605
+
ret = cv1800_pinctrl_oc2reg(pctrl, pin, arg);
606
+
if (ret < 0)
607
+
return ret;
608
+
v &= ~PIN_IO_DRIVE;
609
+
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
610
+
break;
611
+
case PIN_CONFIG_INPUT_SCHMITT_UV:
612
+
ret = cv1800_pinctrl_schmitt2reg(pctrl, pin, arg);
613
+
if (ret < 0)
614
+
return ret;
615
+
v &= ~PIN_IO_SCHMITT;
616
+
v |= FIELD_PREP(PIN_IO_SCHMITT, ret);
617
+
break;
618
+
case PIN_CONFIG_POWER_SOURCE:
619
+
/* Ignore power source as it is always fixed */
620
+
break;
621
+
case PIN_CONFIG_SLEW_RATE:
622
+
v &= ~PIN_IO_OUT_FAST_SLEW;
623
+
v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg);
624
+
break;
625
+
case PIN_CONFIG_BIAS_BUS_HOLD:
626
+
v &= ~PIN_IO_BUS_HOLD;
627
+
v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg);
628
+
break;
629
+
default:
630
+
return -ENOTSUPP;
631
+
}
632
+
}
633
+
634
+
*value = v;
635
+
636
+
return 0;
637
+
}
638
+
639
+
static int cv1800_pin_set_config(struct cv1800_pinctrl *pctrl,
640
+
unsigned int pin_id,
641
+
u32 value)
642
+
{
643
+
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
644
+
unsigned long flags;
645
+
void __iomem *addr;
646
+
647
+
if (!pin)
648
+
return -EINVAL;
649
+
650
+
addr = cv1800_pinctrl_get_component_addr(pctrl, &pin->conf);
651
+
652
+
raw_spin_lock_irqsave(&pctrl->lock, flags);
653
+
writel(value, addr);
654
+
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
655
+
656
+
return 0;
657
+
}
658
+
659
+
static int cv1800_pconf_set(struct pinctrl_dev *pctldev,
660
+
unsigned int pin_id, unsigned long *configs,
661
+
unsigned int num_configs)
662
+
{
663
+
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
664
+
struct cv1800_pin *pin = cv1800_get_pin(pctrl, pin_id);
665
+
u32 value;
666
+
667
+
if (!pin)
668
+
return -ENODEV;
669
+
670
+
if (cv1800_pinconf_compute_config(pctrl, pin,
671
+
configs, num_configs, &value))
672
+
return -ENOTSUPP;
673
+
674
+
return cv1800_pin_set_config(pctrl, pin_id, value);
675
+
}
676
+
677
+
static int cv1800_pconf_group_set(struct pinctrl_dev *pctldev,
678
+
unsigned int gsel,
679
+
unsigned long *configs,
680
+
unsigned int num_configs)
681
+
{
682
+
struct cv1800_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
683
+
const struct group_desc *group;
684
+
const struct cv1800_pin_mux_config *pinmuxs;
685
+
u32 value;
686
+
int i;
687
+
688
+
group = pinctrl_generic_get_group(pctldev, gsel);
689
+
if (!group)
690
+
return -EINVAL;
691
+
692
+
pinmuxs = group->data;
693
+
694
+
if (cv1800_pinconf_compute_config(pctrl, pinmuxs[0].pin,
695
+
configs, num_configs, &value))
696
+
return -ENOTSUPP;
697
+
698
+
for (i = 0; i < group->grp.npins; i++)
699
+
cv1800_pin_set_config(pctrl, group->grp.pins[i], value);
700
+
701
+
return 0;
702
+
}
703
+
704
+
static const struct pinconf_ops cv1800_pconf_ops = {
705
+
.pin_config_get = cv1800_pconf_get,
706
+
.pin_config_set = cv1800_pconf_set,
707
+
.pin_config_group_set = cv1800_pconf_group_set,
708
+
.is_generic = true,
709
+
};
710
+
711
+
int cv1800_pinctrl_probe(struct platform_device *pdev)
712
+
{
713
+
struct device *dev = &pdev->dev;
714
+
struct cv1800_pinctrl *pctrl;
715
+
const struct cv1800_pinctrl_data *pctrl_data;
716
+
int ret;
717
+
718
+
pctrl_data = device_get_match_data(dev);
719
+
if (!pctrl_data)
720
+
return -ENODEV;
721
+
722
+
if (pctrl_data->npins == 0 || pctrl_data->npd == 0)
723
+
return dev_err_probe(dev, -EINVAL, "invalid pin data\n");
724
+
725
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
726
+
if (!pctrl)
727
+
return -ENOMEM;
728
+
729
+
pctrl->power_cfg = devm_kcalloc(dev, pctrl_data->npd,
730
+
sizeof(u32), GFP_KERNEL);
731
+
if (!pctrl->power_cfg)
732
+
return -ENOMEM;
733
+
734
+
pctrl->regs[0] = devm_platform_ioremap_resource_byname(pdev, "sys");
735
+
if (IS_ERR(pctrl->regs[0]))
736
+
return PTR_ERR(pctrl->regs[0]);
737
+
738
+
pctrl->regs[1] = devm_platform_ioremap_resource_byname(pdev, "rtc");
739
+
if (IS_ERR(pctrl->regs[1]))
740
+
return PTR_ERR(pctrl->regs[1]);
741
+
742
+
pctrl->pdesc.name = dev_name(dev);
743
+
pctrl->pdesc.pins = pctrl_data->pins;
744
+
pctrl->pdesc.npins = pctrl_data->npins;
745
+
pctrl->pdesc.pctlops = &cv1800_pctrl_ops;
746
+
pctrl->pdesc.pmxops = &cv1800_pmx_ops;
747
+
pctrl->pdesc.confops = &cv1800_pconf_ops;
748
+
pctrl->pdesc.owner = THIS_MODULE;
749
+
750
+
pctrl->data = pctrl_data;
751
+
pctrl->dev = dev;
752
+
raw_spin_lock_init(&pctrl->lock);
753
+
mutex_init(&pctrl->mutex);
754
+
755
+
platform_set_drvdata(pdev, pctrl);
756
+
757
+
ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc,
758
+
pctrl, &pctrl->pctl_dev);
759
+
if (ret)
760
+
return dev_err_probe(dev, ret,
761
+
"fail to register pinctrl driver\n");
762
+
763
+
return pinctrl_enable(pctrl->pctl_dev);
764
+
}
765
+
EXPORT_SYMBOL_GPL(cv1800_pinctrl_probe);
+155
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
+155
drivers/pinctrl/sophgo/pinctrl-cv18xx.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _PINCTRL_SOPHGO_CV18XX_H
7
+
#define _PINCTRL_SOPHGO_CV18XX_H
8
+
9
+
#include <linux/bits.h>
10
+
#include <linux/bitfield.h>
11
+
#include <linux/device.h>
12
+
#include <linux/mutex.h>
13
+
#include <linux/spinlock.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include <linux/pinctrl/pinconf.h>
17
+
18
+
enum cv1800_pin_io_type {
19
+
IO_TYPE_1V8_ONLY = 0,
20
+
IO_TYPE_1V8_OR_3V3 = 1,
21
+
IO_TYPE_AUDIO = 2,
22
+
IO_TYPE_ETH = 3
23
+
};
24
+
25
+
#define CV1800_PINCONF_AREA_SYS 0
26
+
#define CV1800_PINCONF_AREA_RTC 1
27
+
28
+
struct cv1800_pinmux {
29
+
u16 offset;
30
+
u8 area;
31
+
u8 max;
32
+
};
33
+
34
+
struct cv1800_pinmux2 {
35
+
u16 offset;
36
+
u8 area;
37
+
u8 max;
38
+
u8 pfunc;
39
+
};
40
+
41
+
struct cv1800_pinconf {
42
+
u16 offset;
43
+
u8 area;
44
+
};
45
+
46
+
#define CV1800_PIN_HAVE_MUX2 BIT(0)
47
+
#define CV1800_PIN_IO_TYPE GENMASK(2, 1)
48
+
49
+
#define CV1800_PIN_FLAG_IO_TYPE(type) \
50
+
FIELD_PREP_CONST(CV1800_PIN_IO_TYPE, type)
51
+
struct cv1800_pin {
52
+
u16 pin;
53
+
u16 flags;
54
+
u8 power_domain;
55
+
struct cv1800_pinmux mux;
56
+
struct cv1800_pinmux2 mux2;
57
+
struct cv1800_pinconf conf;
58
+
};
59
+
60
+
#define PIN_POWER_STATE_1V8 1800
61
+
#define PIN_POWER_STATE_3V3 3300
62
+
63
+
/**
64
+
* struct cv1800_vddio_cfg_ops - pin vddio operations
65
+
*
66
+
* @get_pull_up: get resistor for pull up;
67
+
* @get_pull_down: get resistor for pull down.
68
+
* @get_oc_map: get mapping for typical low level output current value to
69
+
* register value map.
70
+
* @get_schmitt_map: get mapping for register value to typical schmitt
71
+
* threshold.
72
+
*/
73
+
struct cv1800_vddio_cfg_ops {
74
+
int (*get_pull_up)(struct cv1800_pin *pin, const u32 *psmap);
75
+
int (*get_pull_down)(struct cv1800_pin *pin, const u32 *psmap);
76
+
int (*get_oc_map)(struct cv1800_pin *pin, const u32 *psmap,
77
+
const u32 **map);
78
+
int (*get_schmitt_map)(struct cv1800_pin *pin, const u32 *psmap,
79
+
const u32 **map);
80
+
};
81
+
82
+
struct cv1800_pinctrl_data {
83
+
const struct pinctrl_pin_desc *pins;
84
+
const struct cv1800_pin *pindata;
85
+
const char * const *pdnames;
86
+
const struct cv1800_vddio_cfg_ops *vddio_ops;
87
+
u16 npins;
88
+
u16 npd;
89
+
};
90
+
91
+
static inline enum cv1800_pin_io_type cv1800_pin_io_type(struct cv1800_pin *pin)
92
+
{
93
+
return FIELD_GET(CV1800_PIN_IO_TYPE, pin->flags);
94
+
};
95
+
96
+
int cv1800_pinctrl_probe(struct platform_device *pdev);
97
+
98
+
#define CV1800_FUNC_PIN(_id, _power_domain, _type, \
99
+
_mux_area, _mux_offset, _mux_func_max) \
100
+
{ \
101
+
.pin = (_id), \
102
+
.power_domain = (_power_domain), \
103
+
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
104
+
.mux = { \
105
+
.area = (_mux_area), \
106
+
.offset = (_mux_offset), \
107
+
.max = (_mux_func_max), \
108
+
}, \
109
+
}
110
+
111
+
#define CV1800_GENERAL_PIN(_id, _power_domain, _type, \
112
+
_mux_area, _mux_offset, _mux_func_max, \
113
+
_conf_area, _conf_offset) \
114
+
{ \
115
+
.pin = (_id), \
116
+
.power_domain = (_power_domain), \
117
+
.flags = CV1800_PIN_FLAG_IO_TYPE(_type), \
118
+
.mux = { \
119
+
.area = (_mux_area), \
120
+
.offset = (_mux_offset), \
121
+
.max = (_mux_func_max), \
122
+
}, \
123
+
.conf = { \
124
+
.area = (_conf_area), \
125
+
.offset = (_conf_offset), \
126
+
}, \
127
+
}
128
+
129
+
#define CV1800_GENERATE_PIN_MUX2(_id, _power_domain, _type, \
130
+
_mux_area, _mux_offset, _mux_func_max, \
131
+
_mux2_area, _mux2_offset, \
132
+
_mux2_func_max, \
133
+
_conf_area, _conf_offset) \
134
+
{ \
135
+
.pin = (_id), \
136
+
.power_domain = (_power_domain), \
137
+
.flags = CV1800_PIN_FLAG_IO_TYPE(_type) | \
138
+
CV1800_PIN_HAVE_MUX2, \
139
+
.mux = { \
140
+
.area = (_mux_area), \
141
+
.offset = (_mux_offset), \
142
+
.max = (_mux_func_max), \
143
+
}, \
144
+
.mux2 = { \
145
+
.area = (_mux2_area), \
146
+
.offset = (_mux2_offset), \
147
+
.max = (_mux2_func_max), \
148
+
}, \
149
+
.conf = { \
150
+
.area = (_conf_area), \
151
+
.offset = (_conf_offset), \
152
+
}, \
153
+
}
154
+
155
+
#endif
+771
drivers/pinctrl/sophgo/pinctrl-sg2000.c
+771
drivers/pinctrl/sophgo/pinctrl-sg2000.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2000 SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
* This file is generated from vendor pinout definition.
8
+
*/
9
+
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/of.h>
13
+
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/pinctrl/pinmux.h>
16
+
17
+
#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
18
+
19
+
#include "pinctrl-cv18xx.h"
20
+
21
+
enum SG2000_POWER_DOMAIN {
22
+
VDD18A_EPHY = 0,
23
+
VDD18A_MIPI = 1,
24
+
VDDIO18_1 = 2,
25
+
VDDIO_EMMC = 3,
26
+
VDDIO_RTC = 4,
27
+
VDDIO_SD0 = 5,
28
+
VDDIO_SD1 = 6,
29
+
VDDIO_VIVO = 7
30
+
};
31
+
32
+
static const char *const sg2000_power_domain_desc[] = {
33
+
[VDD18A_EPHY] = "VDD18A_EPHY",
34
+
[VDD18A_MIPI] = "VDD18A_MIPI",
35
+
[VDDIO18_1] = "VDDIO18_1",
36
+
[VDDIO_EMMC] = "VDDIO_EMMC",
37
+
[VDDIO_RTC] = "VDDIO_RTC",
38
+
[VDDIO_SD0] = "VDDIO_SD0",
39
+
[VDDIO_SD1] = "VDDIO_SD1",
40
+
[VDDIO_VIVO] = "VDDIO_VIVO",
41
+
};
42
+
43
+
static int sg2000_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
44
+
{
45
+
u32 pstate = psmap[pin->power_domain];
46
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
47
+
48
+
if (type == IO_TYPE_1V8_ONLY)
49
+
return 79000;
50
+
51
+
if (type == IO_TYPE_1V8_OR_3V3) {
52
+
if (pstate == PIN_POWER_STATE_1V8)
53
+
return 60000;
54
+
if (pstate == PIN_POWER_STATE_3V3)
55
+
return 60000;
56
+
57
+
return -EINVAL;
58
+
}
59
+
60
+
return -ENOTSUPP;
61
+
}
62
+
63
+
static int sg2000_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
64
+
{
65
+
u32 pstate = psmap[pin->power_domain];
66
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
67
+
68
+
if (type == IO_TYPE_1V8_ONLY)
69
+
return 87000;
70
+
71
+
if (type == IO_TYPE_1V8_OR_3V3) {
72
+
if (pstate == PIN_POWER_STATE_1V8)
73
+
return 61000;
74
+
if (pstate == PIN_POWER_STATE_3V3)
75
+
return 62000;
76
+
77
+
return -EINVAL;
78
+
}
79
+
80
+
return -ENOTSUPP;
81
+
}
82
+
83
+
static const u32 sg2000_1v8_oc_map[] = {
84
+
12800,
85
+
25300,
86
+
37400,
87
+
49000
88
+
};
89
+
90
+
static const u32 sg2000_18od33_1v8_oc_map[] = {
91
+
7800,
92
+
11700,
93
+
15500,
94
+
19200,
95
+
23000,
96
+
26600,
97
+
30200,
98
+
33700
99
+
};
100
+
101
+
static const u32 sg2000_18od33_3v3_oc_map[] = {
102
+
5500,
103
+
8200,
104
+
10800,
105
+
13400,
106
+
16100,
107
+
18700,
108
+
21200,
109
+
23700
110
+
};
111
+
112
+
static const u32 sg2000_eth_oc_map[] = {
113
+
15700,
114
+
17800
115
+
};
116
+
117
+
static int sg2000_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
118
+
const u32 **map)
119
+
{
120
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
121
+
u32 pstate = psmap[pin->power_domain];
122
+
123
+
if (type == IO_TYPE_1V8_ONLY) {
124
+
*map = sg2000_1v8_oc_map;
125
+
return ARRAY_SIZE(sg2000_1v8_oc_map);
126
+
}
127
+
128
+
if (type == IO_TYPE_1V8_OR_3V3) {
129
+
if (pstate == PIN_POWER_STATE_1V8) {
130
+
*map = sg2000_18od33_1v8_oc_map;
131
+
return ARRAY_SIZE(sg2000_18od33_1v8_oc_map);
132
+
} else if (pstate == PIN_POWER_STATE_3V3) {
133
+
*map = sg2000_18od33_3v3_oc_map;
134
+
return ARRAY_SIZE(sg2000_18od33_3v3_oc_map);
135
+
}
136
+
}
137
+
138
+
if (type == IO_TYPE_ETH) {
139
+
*map = sg2000_eth_oc_map;
140
+
return ARRAY_SIZE(sg2000_eth_oc_map);
141
+
}
142
+
143
+
return -ENOTSUPP;
144
+
}
145
+
146
+
static const u32 sg2000_1v8_schmitt_map[] = {
147
+
0,
148
+
970000,
149
+
1040000
150
+
};
151
+
152
+
static const u32 sg2000_18od33_1v8_schmitt_map[] = {
153
+
0,
154
+
1070000
155
+
};
156
+
157
+
static const u32 sg2000_18od33_3v3_schmitt_map[] = {
158
+
0,
159
+
1100000
160
+
};
161
+
162
+
static int sg2000_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
163
+
const u32 **map)
164
+
{
165
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
166
+
u32 pstate = psmap[pin->power_domain];
167
+
168
+
if (type == IO_TYPE_1V8_ONLY) {
169
+
*map = sg2000_1v8_schmitt_map;
170
+
return ARRAY_SIZE(sg2000_1v8_schmitt_map);
171
+
}
172
+
173
+
if (type == IO_TYPE_1V8_OR_3V3) {
174
+
if (pstate == PIN_POWER_STATE_1V8) {
175
+
*map = sg2000_18od33_1v8_schmitt_map;
176
+
return ARRAY_SIZE(sg2000_18od33_1v8_schmitt_map);
177
+
} else if (pstate == PIN_POWER_STATE_3V3) {
178
+
*map = sg2000_18od33_3v3_schmitt_map;
179
+
return ARRAY_SIZE(sg2000_18od33_3v3_schmitt_map);
180
+
}
181
+
}
182
+
183
+
return -ENOTSUPP;
184
+
}
185
+
186
+
static const struct cv1800_vddio_cfg_ops sg2000_vddio_cfg_ops = {
187
+
.get_pull_up = sg2000_get_pull_up,
188
+
.get_pull_down = sg2000_get_pull_down,
189
+
.get_oc_map = sg2000_get_oc_map,
190
+
.get_schmitt_map = sg2000_get_schmitt_map,
191
+
};
192
+
193
+
static const struct pinctrl_pin_desc sg2000_pins[] = {
194
+
PINCTRL_PIN(PIN_MIPI_TXM4, "MIPI_TXM4"),
195
+
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
196
+
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
197
+
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
198
+
PINCTRL_PIN(PIN_VIVO_D2, "VIVO_D2"),
199
+
PINCTRL_PIN(PIN_VIVO_D3, "VIVO_D3"),
200
+
PINCTRL_PIN(PIN_VIVO_D10, "VIVO_D10"),
201
+
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
202
+
PINCTRL_PIN(PIN_MIPI_TXP3, "MIPI_TXP3"),
203
+
PINCTRL_PIN(PIN_MIPI_TXM3, "MIPI_TXM3"),
204
+
PINCTRL_PIN(PIN_MIPI_TXP4, "MIPI_TXP4"),
205
+
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
206
+
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
207
+
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
208
+
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
209
+
PINCTRL_PIN(PIN_MIPIRX5N, "MIPIRX5N"),
210
+
PINCTRL_PIN(PIN_VIVO_D1, "VIVO_D1"),
211
+
PINCTRL_PIN(PIN_VIVO_D5, "VIVO_D5"),
212
+
PINCTRL_PIN(PIN_VIVO_D7, "VIVO_D7"),
213
+
PINCTRL_PIN(PIN_VIVO_D9, "VIVO_D9"),
214
+
PINCTRL_PIN(PIN_USB_ID, "USB_ID"),
215
+
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
216
+
PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
217
+
PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
218
+
PINCTRL_PIN(PIN_CAM_PD0, "CAM_PD0"),
219
+
PINCTRL_PIN(PIN_CAM_MCLK0, "CAM_MCLK0"),
220
+
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
221
+
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
222
+
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
223
+
PINCTRL_PIN(PIN_MIPIRX5P, "MIPIRX5P"),
224
+
PINCTRL_PIN(PIN_VIVO_CLK, "VIVO_CLK"),
225
+
PINCTRL_PIN(PIN_VIVO_D6, "VIVO_D6"),
226
+
PINCTRL_PIN(PIN_VIVO_D8, "VIVO_D8"),
227
+
PINCTRL_PIN(PIN_USB_VBUS_EN, "USB_VBUS_EN"),
228
+
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
229
+
PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
230
+
PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
231
+
PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
232
+
PINCTRL_PIN(PIN_CAM_MCLK1, "CAM_MCLK1"),
233
+
PINCTRL_PIN(PIN_IIC3_SCL, "IIC3_SCL"),
234
+
PINCTRL_PIN(PIN_VIVO_D4, "VIVO_D4"),
235
+
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
236
+
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
237
+
PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
238
+
PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
239
+
PINCTRL_PIN(PIN_CAM_PD1, "CAM_PD1"),
240
+
PINCTRL_PIN(PIN_CAM_RST0, "CAM_RST0"),
241
+
PINCTRL_PIN(PIN_VIVO_D0, "VIVO_D0"),
242
+
PINCTRL_PIN(PIN_ADC1, "ADC1"),
243
+
PINCTRL_PIN(PIN_ADC2, "ADC2"),
244
+
PINCTRL_PIN(PIN_ADC3, "ADC3"),
245
+
PINCTRL_PIN(PIN_AUD_AOUTL, "AUD_AOUTL"),
246
+
PINCTRL_PIN(PIN_IIC3_SDA, "IIC3_SDA"),
247
+
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
248
+
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
249
+
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
250
+
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
251
+
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
252
+
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
253
+
PINCTRL_PIN(PIN_RSTN, "RSTN"),
254
+
PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
255
+
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
256
+
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
257
+
PINCTRL_PIN(PIN_AUD_AINR_MIC, "AUD_AINR_MIC"),
258
+
PINCTRL_PIN(PIN_IIC2_SCL, "IIC2_SCL"),
259
+
PINCTRL_PIN(PIN_IIC2_SDA, "IIC2_SDA"),
260
+
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
261
+
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
262
+
PINCTRL_PIN(PIN_UART2_RX, "UART2_RX"),
263
+
PINCTRL_PIN(PIN_UART2_CTS, "UART2_CTS"),
264
+
PINCTRL_PIN(PIN_UART2_TX, "UART2_TX"),
265
+
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
266
+
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
267
+
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
268
+
PINCTRL_PIN(PIN_CLK32K, "CLK32K"),
269
+
PINCTRL_PIN(PIN_UART2_RTS, "UART2_RTS"),
270
+
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
271
+
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
272
+
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
273
+
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
274
+
PINCTRL_PIN(PIN_JTAG_CPU_TRST, "JTAG_CPU_TRST"),
275
+
PINCTRL_PIN(PIN_PWR_ON, "PWR_ON"),
276
+
PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
277
+
PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
278
+
PINCTRL_PIN(PIN_CLK25M, "CLK25M"),
279
+
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
280
+
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
281
+
PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
282
+
PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
283
+
PINCTRL_PIN(PIN_PWR_WAKEUP1, "PWR_WAKEUP1"),
284
+
PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
285
+
PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
286
+
PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
287
+
PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
288
+
PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
289
+
PINCTRL_PIN(PIN_EMMC_RSTN, "EMMC_RSTN"),
290
+
PINCTRL_PIN(PIN_AUX0, "AUX0"),
291
+
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
292
+
PINCTRL_PIN(PIN_PWR_SEQ3, "PWR_SEQ3"),
293
+
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
294
+
PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
295
+
PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
296
+
PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
297
+
PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
298
+
PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
299
+
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
300
+
PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
301
+
PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
302
+
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
303
+
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
304
+
};
305
+
306
+
static const struct cv1800_pin sg2000_pin_data[ARRAY_SIZE(sg2000_pins)] = {
307
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM4, VDD18A_MIPI,
308
+
IO_TYPE_1V8_ONLY,
309
+
CV1800_PINCONF_AREA_SYS, 0x194, 7,
310
+
CV1800_PINCONF_AREA_SYS, 0xc60),
311
+
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
312
+
IO_TYPE_1V8_ONLY,
313
+
CV1800_PINCONF_AREA_SYS, 0x18c, 7,
314
+
CV1800_PINCONF_AREA_SYS, 0xc58),
315
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
316
+
IO_TYPE_1V8_ONLY,
317
+
CV1800_PINCONF_AREA_SYS, 0x178, 7,
318
+
CV1800_PINCONF_AREA_SYS, 0x118, 7,
319
+
CV1800_PINCONF_AREA_SYS, 0xc44),
320
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
321
+
IO_TYPE_1V8_ONLY,
322
+
CV1800_PINCONF_AREA_SYS, 0x170, 7,
323
+
CV1800_PINCONF_AREA_SYS, 0x11c, 7,
324
+
CV1800_PINCONF_AREA_SYS, 0xc3c),
325
+
CV1800_GENERAL_PIN(PIN_VIVO_D2, VDDIO_VIVO,
326
+
IO_TYPE_1V8_OR_3V3,
327
+
CV1800_PINCONF_AREA_SYS, 0x154, 7,
328
+
CV1800_PINCONF_AREA_SYS, 0xc20),
329
+
CV1800_GENERAL_PIN(PIN_VIVO_D3, VDDIO_VIVO,
330
+
IO_TYPE_1V8_OR_3V3,
331
+
CV1800_PINCONF_AREA_SYS, 0x150, 7,
332
+
CV1800_PINCONF_AREA_SYS, 0xc1c),
333
+
CV1800_GENERAL_PIN(PIN_VIVO_D10, VDDIO_VIVO,
334
+
IO_TYPE_1V8_OR_3V3,
335
+
CV1800_PINCONF_AREA_SYS, 0x134, 7,
336
+
CV1800_PINCONF_AREA_SYS, 0xc00),
337
+
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDDIO18_1,
338
+
IO_TYPE_1V8_ONLY,
339
+
CV1800_PINCONF_AREA_SYS, 0x108, 5,
340
+
CV1800_PINCONF_AREA_SYS, 0x820),
341
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP3, VDD18A_MIPI,
342
+
IO_TYPE_1V8_ONLY,
343
+
CV1800_PINCONF_AREA_SYS, 0x1a0, 7,
344
+
CV1800_PINCONF_AREA_SYS, 0xc6c),
345
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM3, VDD18A_MIPI,
346
+
IO_TYPE_1V8_ONLY,
347
+
CV1800_PINCONF_AREA_SYS, 0x19c, 7,
348
+
CV1800_PINCONF_AREA_SYS, 0xc68),
349
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP4, VDD18A_MIPI,
350
+
IO_TYPE_1V8_ONLY,
351
+
CV1800_PINCONF_AREA_SYS, 0x198, 7,
352
+
CV1800_PINCONF_AREA_SYS, 0xc64),
353
+
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
354
+
IO_TYPE_1V8_ONLY,
355
+
CV1800_PINCONF_AREA_SYS, 0x190, 7,
356
+
CV1800_PINCONF_AREA_SYS, 0xc5c),
357
+
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
358
+
IO_TYPE_1V8_ONLY,
359
+
CV1800_PINCONF_AREA_SYS, 0x184, 7,
360
+
CV1800_PINCONF_AREA_SYS, 0xc50),
361
+
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
362
+
IO_TYPE_1V8_ONLY,
363
+
CV1800_PINCONF_AREA_SYS, 0x17c, 7,
364
+
CV1800_PINCONF_AREA_SYS, 0xc48),
365
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
366
+
IO_TYPE_1V8_ONLY,
367
+
CV1800_PINCONF_AREA_SYS, 0x16c, 7,
368
+
CV1800_PINCONF_AREA_SYS, 0x120, 7,
369
+
CV1800_PINCONF_AREA_SYS, 0xc38),
370
+
CV1800_GENERAL_PIN(PIN_MIPIRX5N, VDD18A_MIPI,
371
+
IO_TYPE_1V8_ONLY,
372
+
CV1800_PINCONF_AREA_SYS, 0x164, 7,
373
+
CV1800_PINCONF_AREA_SYS, 0xc30),
374
+
CV1800_GENERAL_PIN(PIN_VIVO_D1, VDDIO_VIVO,
375
+
IO_TYPE_1V8_OR_3V3,
376
+
CV1800_PINCONF_AREA_SYS, 0x158, 7,
377
+
CV1800_PINCONF_AREA_SYS, 0xc24),
378
+
CV1800_GENERAL_PIN(PIN_VIVO_D5, VDDIO_VIVO,
379
+
IO_TYPE_1V8_OR_3V3,
380
+
CV1800_PINCONF_AREA_SYS, 0x148, 7,
381
+
CV1800_PINCONF_AREA_SYS, 0xc14),
382
+
CV1800_GENERAL_PIN(PIN_VIVO_D7, VDDIO_VIVO,
383
+
IO_TYPE_1V8_OR_3V3,
384
+
CV1800_PINCONF_AREA_SYS, 0x140, 7,
385
+
CV1800_PINCONF_AREA_SYS, 0xc0c),
386
+
CV1800_GENERAL_PIN(PIN_VIVO_D9, VDDIO_VIVO,
387
+
IO_TYPE_1V8_OR_3V3,
388
+
CV1800_PINCONF_AREA_SYS, 0x138, 7,
389
+
CV1800_PINCONF_AREA_SYS, 0xc04),
390
+
CV1800_GENERAL_PIN(PIN_USB_ID, VDDIO18_1,
391
+
IO_TYPE_1V8_ONLY,
392
+
CV1800_PINCONF_AREA_SYS, 0x0fc, 3,
393
+
CV1800_PINCONF_AREA_SYS, 0x814),
394
+
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_EPHY,
395
+
IO_TYPE_ETH,
396
+
CV1800_PINCONF_AREA_SYS, 0x130, 7),
397
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
398
+
IO_TYPE_1V8_ONLY,
399
+
CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
400
+
CV1800_PINCONF_AREA_SYS, 0xc74),
401
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
402
+
IO_TYPE_1V8_ONLY,
403
+
CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
404
+
CV1800_PINCONF_AREA_SYS, 0xc70),
405
+
CV1800_GENERAL_PIN(PIN_CAM_PD0, VDD18A_MIPI,
406
+
IO_TYPE_1V8_ONLY,
407
+
CV1800_PINCONF_AREA_SYS, 0x004, 4,
408
+
CV1800_PINCONF_AREA_SYS, 0xb04),
409
+
CV1800_GENERAL_PIN(PIN_CAM_MCLK0, VDD18A_MIPI,
410
+
IO_TYPE_1V8_ONLY,
411
+
CV1800_PINCONF_AREA_SYS, 0x000, 3,
412
+
CV1800_PINCONF_AREA_SYS, 0xb00),
413
+
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
414
+
IO_TYPE_1V8_ONLY,
415
+
CV1800_PINCONF_AREA_SYS, 0x188, 7,
416
+
CV1800_PINCONF_AREA_SYS, 0xc54),
417
+
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
418
+
IO_TYPE_1V8_ONLY,
419
+
CV1800_PINCONF_AREA_SYS, 0x180, 7,
420
+
CV1800_PINCONF_AREA_SYS, 0xc4c),
421
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
422
+
IO_TYPE_1V8_ONLY,
423
+
CV1800_PINCONF_AREA_SYS, 0x174, 7,
424
+
CV1800_PINCONF_AREA_SYS, 0x114, 7,
425
+
CV1800_PINCONF_AREA_SYS, 0xc40),
426
+
CV1800_GENERAL_PIN(PIN_MIPIRX5P, VDD18A_MIPI,
427
+
IO_TYPE_1V8_ONLY,
428
+
CV1800_PINCONF_AREA_SYS, 0x168, 7,
429
+
CV1800_PINCONF_AREA_SYS, 0xc34),
430
+
CV1800_GENERAL_PIN(PIN_VIVO_CLK, VDDIO_VIVO,
431
+
IO_TYPE_1V8_OR_3V3,
432
+
CV1800_PINCONF_AREA_SYS, 0x160, 7,
433
+
CV1800_PINCONF_AREA_SYS, 0xc2c),
434
+
CV1800_GENERAL_PIN(PIN_VIVO_D6, VDDIO_VIVO,
435
+
IO_TYPE_1V8_OR_3V3,
436
+
CV1800_PINCONF_AREA_SYS, 0x144, 7,
437
+
CV1800_PINCONF_AREA_SYS, 0xc10),
438
+
CV1800_GENERAL_PIN(PIN_VIVO_D8, VDDIO_VIVO,
439
+
IO_TYPE_1V8_OR_3V3,
440
+
CV1800_PINCONF_AREA_SYS, 0x13c, 7,
441
+
CV1800_PINCONF_AREA_SYS, 0xc08),
442
+
CV1800_GENERAL_PIN(PIN_USB_VBUS_EN, VDDIO18_1,
443
+
IO_TYPE_1V8_ONLY,
444
+
CV1800_PINCONF_AREA_SYS, 0x100, 3,
445
+
CV1800_PINCONF_AREA_SYS, 0x818),
446
+
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_EPHY,
447
+
IO_TYPE_ETH,
448
+
CV1800_PINCONF_AREA_SYS, 0x12c, 7),
449
+
CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDDIO18_1,
450
+
IO_TYPE_1V8_ONLY,
451
+
CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
452
+
CV1800_PINCONF_AREA_SYS, 0xc8c),
453
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
454
+
IO_TYPE_1V8_ONLY,
455
+
CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
456
+
CV1800_PINCONF_AREA_SYS, 0xc7c),
457
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
458
+
IO_TYPE_1V8_ONLY,
459
+
CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
460
+
CV1800_PINCONF_AREA_SYS, 0xc78),
461
+
CV1800_GENERAL_PIN(PIN_CAM_MCLK1, VDD18A_MIPI,
462
+
IO_TYPE_1V8_ONLY,
463
+
CV1800_PINCONF_AREA_SYS, 0x00c, 4,
464
+
CV1800_PINCONF_AREA_SYS, 0xb0c),
465
+
CV1800_GENERAL_PIN(PIN_IIC3_SCL, VDD18A_MIPI,
466
+
IO_TYPE_1V8_ONLY,
467
+
CV1800_PINCONF_AREA_SYS, 0x014, 3,
468
+
CV1800_PINCONF_AREA_SYS, 0xb14),
469
+
CV1800_GENERAL_PIN(PIN_VIVO_D4, VDDIO_VIVO,
470
+
IO_TYPE_1V8_OR_3V3,
471
+
CV1800_PINCONF_AREA_SYS, 0x14c, 7,
472
+
CV1800_PINCONF_AREA_SYS, 0xc18),
473
+
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_EPHY,
474
+
IO_TYPE_ETH,
475
+
CV1800_PINCONF_AREA_SYS, 0x128, 7),
476
+
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_EPHY,
477
+
IO_TYPE_ETH,
478
+
CV1800_PINCONF_AREA_SYS, 0x124, 7),
479
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
480
+
IO_TYPE_1V8_ONLY,
481
+
CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
482
+
CV1800_PINCONF_AREA_SYS, 0xc84),
483
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
484
+
IO_TYPE_1V8_ONLY,
485
+
CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
486
+
CV1800_PINCONF_AREA_SYS, 0xc80),
487
+
CV1800_GENERAL_PIN(PIN_CAM_PD1, VDD18A_MIPI,
488
+
IO_TYPE_1V8_ONLY,
489
+
CV1800_PINCONF_AREA_SYS, 0x010, 6,
490
+
CV1800_PINCONF_AREA_SYS, 0xb10),
491
+
CV1800_GENERAL_PIN(PIN_CAM_RST0, VDD18A_MIPI,
492
+
IO_TYPE_1V8_ONLY,
493
+
CV1800_PINCONF_AREA_SYS, 0x008, 6,
494
+
CV1800_PINCONF_AREA_SYS, 0xb08),
495
+
CV1800_GENERAL_PIN(PIN_VIVO_D0, VDDIO_VIVO,
496
+
IO_TYPE_1V8_OR_3V3,
497
+
CV1800_PINCONF_AREA_SYS, 0x15c, 7,
498
+
CV1800_PINCONF_AREA_SYS, 0xc28),
499
+
CV1800_GENERAL_PIN(PIN_ADC1, VDDIO18_1,
500
+
IO_TYPE_1V8_ONLY,
501
+
CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
502
+
CV1800_PINCONF_AREA_SYS, 0x810),
503
+
CV1800_GENERAL_PIN(PIN_ADC2, VDDIO18_1,
504
+
IO_TYPE_1V8_ONLY,
505
+
CV1800_PINCONF_AREA_SYS, 0x0f4, 7,
506
+
CV1800_PINCONF_AREA_SYS, 0x80c),
507
+
CV1800_GENERAL_PIN(PIN_ADC3, VDDIO18_1,
508
+
IO_TYPE_1V8_ONLY,
509
+
CV1800_PINCONF_AREA_SYS, 0x0f0, 7,
510
+
CV1800_PINCONF_AREA_SYS, 0x808),
511
+
CV1800_FUNC_PIN(PIN_AUD_AOUTL, VDD18A_MIPI,
512
+
IO_TYPE_AUDIO,
513
+
CV1800_PINCONF_AREA_SYS, 0x1c4, 5),
514
+
CV1800_GENERAL_PIN(PIN_IIC3_SDA, VDD18A_MIPI,
515
+
IO_TYPE_1V8_ONLY,
516
+
CV1800_PINCONF_AREA_SYS, 0x018, 3,
517
+
CV1800_PINCONF_AREA_SYS, 0xb18),
518
+
CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
519
+
IO_TYPE_1V8_OR_3V3,
520
+
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
521
+
CV1800_PINCONF_AREA_RTC, 0x05c),
522
+
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
523
+
IO_TYPE_AUDIO,
524
+
CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
525
+
CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
526
+
IO_TYPE_1V8_OR_3V3,
527
+
CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
528
+
CV1800_PINCONF_AREA_RTC, 0x058),
529
+
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
530
+
IO_TYPE_1V8_OR_3V3,
531
+
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
532
+
CV1800_PINCONF_AREA_RTC, 0x06c),
533
+
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
534
+
IO_TYPE_1V8_OR_3V3,
535
+
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
536
+
CV1800_PINCONF_AREA_RTC, 0x068),
537
+
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
538
+
IO_TYPE_AUDIO,
539
+
CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
540
+
CV1800_GENERAL_PIN(PIN_RSTN, VDDIO18_1,
541
+
IO_TYPE_1V8_ONLY,
542
+
CV1800_PINCONF_AREA_SYS, 0x0e8, 0,
543
+
CV1800_PINCONF_AREA_SYS, 0x800),
544
+
CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDDIO18_1,
545
+
IO_TYPE_1V8_ONLY,
546
+
CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
547
+
CV1800_PINCONF_AREA_SYS, 0x804),
548
+
CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
549
+
IO_TYPE_1V8_OR_3V3,
550
+
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
551
+
CV1800_PINCONF_AREA_RTC, 0x060),
552
+
CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
553
+
IO_TYPE_1V8_OR_3V3,
554
+
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
555
+
CV1800_PINCONF_AREA_RTC, 0x064),
556
+
CV1800_FUNC_PIN(PIN_AUD_AINR_MIC, VDD18A_MIPI,
557
+
IO_TYPE_AUDIO,
558
+
CV1800_PINCONF_AREA_SYS, 0x1c0, 6),
559
+
CV1800_GENERAL_PIN(PIN_IIC2_SCL, VDDIO_RTC,
560
+
IO_TYPE_1V8_ONLY,
561
+
CV1800_PINCONF_AREA_SYS, 0x0b8, 7,
562
+
CV1800_PINCONF_AREA_RTC, 0x040),
563
+
CV1800_GENERAL_PIN(PIN_IIC2_SDA, VDDIO_RTC,
564
+
IO_TYPE_1V8_ONLY,
565
+
CV1800_PINCONF_AREA_SYS, 0x0bc, 7,
566
+
CV1800_PINCONF_AREA_RTC, 0x044),
567
+
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_EMMC,
568
+
IO_TYPE_1V8_OR_3V3,
569
+
CV1800_PINCONF_AREA_SYS, 0x034, 3,
570
+
CV1800_PINCONF_AREA_SYS, 0x900),
571
+
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0,
572
+
IO_TYPE_1V8_OR_3V3,
573
+
CV1800_PINCONF_AREA_SYS, 0x028, 7,
574
+
CV1800_PINCONF_AREA_SYS, 0xa0c),
575
+
CV1800_GENERAL_PIN(PIN_UART2_RX, VDDIO_RTC,
576
+
IO_TYPE_1V8_ONLY,
577
+
CV1800_PINCONF_AREA_SYS, 0x0c8, 7,
578
+
CV1800_PINCONF_AREA_RTC, 0x050),
579
+
CV1800_GENERAL_PIN(PIN_UART2_CTS, VDDIO_RTC,
580
+
IO_TYPE_1V8_ONLY,
581
+
CV1800_PINCONF_AREA_SYS, 0x0cc, 7,
582
+
CV1800_PINCONF_AREA_RTC, 0x054),
583
+
CV1800_GENERAL_PIN(PIN_UART2_TX, VDDIO_RTC,
584
+
IO_TYPE_1V8_ONLY,
585
+
CV1800_PINCONF_AREA_SYS, 0x0c0, 7,
586
+
CV1800_PINCONF_AREA_RTC, 0x048),
587
+
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0,
588
+
IO_TYPE_1V8_OR_3V3,
589
+
CV1800_PINCONF_AREA_SYS, 0x01c, 7,
590
+
CV1800_PINCONF_AREA_SYS, 0xa00),
591
+
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0,
592
+
IO_TYPE_1V8_OR_3V3,
593
+
CV1800_PINCONF_AREA_SYS, 0x024, 7,
594
+
CV1800_PINCONF_AREA_SYS, 0xa08),
595
+
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0,
596
+
IO_TYPE_1V8_OR_3V3,
597
+
CV1800_PINCONF_AREA_SYS, 0x020, 7,
598
+
CV1800_PINCONF_AREA_SYS, 0xa04),
599
+
CV1800_GENERAL_PIN(PIN_CLK32K, VDDIO_RTC,
600
+
IO_TYPE_1V8_ONLY,
601
+
CV1800_PINCONF_AREA_SYS, 0x0b0, 7,
602
+
CV1800_PINCONF_AREA_RTC, 0x038),
603
+
CV1800_GENERAL_PIN(PIN_UART2_RTS, VDDIO_RTC,
604
+
IO_TYPE_1V8_ONLY,
605
+
CV1800_PINCONF_AREA_SYS, 0x0c4, 7,
606
+
CV1800_PINCONF_AREA_RTC, 0x04c),
607
+
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0,
608
+
IO_TYPE_1V8_OR_3V3,
609
+
CV1800_PINCONF_AREA_SYS, 0x030, 7,
610
+
CV1800_PINCONF_AREA_SYS, 0xa14),
611
+
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0,
612
+
IO_TYPE_1V8_OR_3V3,
613
+
CV1800_PINCONF_AREA_SYS, 0x02c, 7,
614
+
CV1800_PINCONF_AREA_SYS, 0xa10),
615
+
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_EMMC,
616
+
IO_TYPE_1V8_OR_3V3,
617
+
CV1800_PINCONF_AREA_SYS, 0x044, 7,
618
+
CV1800_PINCONF_AREA_SYS, 0x910),
619
+
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_EMMC,
620
+
IO_TYPE_1V8_OR_3V3,
621
+
CV1800_PINCONF_AREA_SYS, 0x040, 7,
622
+
CV1800_PINCONF_AREA_SYS, 0x90c),
623
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TRST, VDDIO_EMMC,
624
+
IO_TYPE_1V8_OR_3V3,
625
+
CV1800_PINCONF_AREA_SYS, 0x06c, 6,
626
+
CV1800_PINCONF_AREA_SYS, 0x938),
627
+
CV1800_GENERAL_PIN(PIN_PWR_ON, VDDIO_RTC,
628
+
IO_TYPE_1V8_ONLY,
629
+
CV1800_PINCONF_AREA_SYS, 0x09c, 7,
630
+
CV1800_PINCONF_AREA_RTC, 0x024),
631
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
632
+
IO_TYPE_1V8_ONLY,
633
+
CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
634
+
CV1800_PINCONF_AREA_RTC, 0x034),
635
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
636
+
IO_TYPE_1V8_ONLY,
637
+
CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
638
+
CV1800_PINCONF_AREA_RTC, 0x02c),
639
+
CV1800_GENERAL_PIN(PIN_CLK25M, VDDIO_RTC,
640
+
IO_TYPE_1V8_ONLY,
641
+
CV1800_PINCONF_AREA_SYS, 0x0b4, 7,
642
+
CV1800_PINCONF_AREA_RTC, 0x03c),
643
+
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_EMMC,
644
+
IO_TYPE_1V8_OR_3V3,
645
+
CV1800_PINCONF_AREA_SYS, 0x038, 3,
646
+
CV1800_PINCONF_AREA_SYS, 0x904),
647
+
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_EMMC,
648
+
IO_TYPE_1V8_OR_3V3,
649
+
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
650
+
CV1800_PINCONF_AREA_SYS, 0x908),
651
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_EMMC,
652
+
IO_TYPE_1V8_OR_3V3,
653
+
CV1800_PINCONF_AREA_SYS, 0x068, 7,
654
+
CV1800_PINCONF_AREA_SYS, 0x934),
655
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_EMMC,
656
+
IO_TYPE_1V8_OR_3V3,
657
+
CV1800_PINCONF_AREA_SYS, 0x064, 7,
658
+
CV1800_PINCONF_AREA_SYS, 0x930),
659
+
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP1, VDDIO_RTC,
660
+
IO_TYPE_1V8_ONLY,
661
+
CV1800_PINCONF_AREA_SYS, 0x094, 7,
662
+
CV1800_PINCONF_AREA_RTC, 0x01c),
663
+
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
664
+
IO_TYPE_1V8_ONLY,
665
+
CV1800_PINCONF_AREA_SYS, 0x090, 7,
666
+
CV1800_PINCONF_AREA_RTC, 0x018),
667
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
668
+
IO_TYPE_1V8_ONLY,
669
+
CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
670
+
CV1800_PINCONF_AREA_RTC, 0x030),
671
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_EMMC,
672
+
IO_TYPE_1V8_OR_3V3,
673
+
CV1800_PINCONF_AREA_SYS, 0x058, 3,
674
+
CV1800_PINCONF_AREA_SYS, 0x924),
675
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_EMMC,
676
+
IO_TYPE_1V8_OR_3V3,
677
+
CV1800_PINCONF_AREA_SYS, 0x054, 3,
678
+
CV1800_PINCONF_AREA_SYS, 0x920),
679
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_EMMC,
680
+
IO_TYPE_1V8_OR_3V3,
681
+
CV1800_PINCONF_AREA_SYS, 0x04c, 3,
682
+
CV1800_PINCONF_AREA_SYS, 0x918),
683
+
CV1800_GENERAL_PIN(PIN_EMMC_RSTN, VDDIO_EMMC,
684
+
IO_TYPE_1V8_OR_3V3,
685
+
CV1800_PINCONF_AREA_SYS, 0x048, 4,
686
+
CV1800_PINCONF_AREA_SYS, 0x914),
687
+
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_EMMC,
688
+
IO_TYPE_1V8_OR_3V3,
689
+
CV1800_PINCONF_AREA_SYS, 0x078, 7,
690
+
CV1800_PINCONF_AREA_SYS, 0x944),
691
+
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_EMMC,
692
+
IO_TYPE_1V8_OR_3V3,
693
+
CV1800_PINCONF_AREA_SYS, 0x074, 7,
694
+
CV1800_PINCONF_AREA_SYS, 0x940),
695
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ3, VDDIO_RTC,
696
+
IO_TYPE_1V8_ONLY,
697
+
CV1800_PINCONF_AREA_SYS, 0x08c, 3,
698
+
CV1800_PINCONF_AREA_RTC, 0x010),
699
+
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
700
+
IO_TYPE_1V8_ONLY,
701
+
CV1800_PINCONF_AREA_SYS, 0x07c, 0,
702
+
CV1800_PINCONF_AREA_RTC, 0x000),
703
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
704
+
IO_TYPE_1V8_ONLY,
705
+
CV1800_PINCONF_AREA_SYS, 0x084, 3,
706
+
CV1800_PINCONF_AREA_RTC, 0x008),
707
+
CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
708
+
IO_TYPE_1V8_ONLY,
709
+
CV1800_PINCONF_AREA_SYS, 0x098, 7,
710
+
CV1800_PINCONF_AREA_RTC, 0x020),
711
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_EMMC,
712
+
IO_TYPE_1V8_OR_3V3,
713
+
CV1800_PINCONF_AREA_SYS, 0x060, 3,
714
+
CV1800_PINCONF_AREA_SYS, 0x92c),
715
+
CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_EMMC,
716
+
IO_TYPE_1V8_OR_3V3,
717
+
CV1800_PINCONF_AREA_SYS, 0x05c, 3,
718
+
CV1800_PINCONF_AREA_SYS, 0x928),
719
+
CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_EMMC,
720
+
IO_TYPE_1V8_OR_3V3,
721
+
CV1800_PINCONF_AREA_SYS, 0x050, 3,
722
+
CV1800_PINCONF_AREA_SYS, 0x91c),
723
+
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_EMMC,
724
+
IO_TYPE_1V8_OR_3V3,
725
+
CV1800_PINCONF_AREA_SYS, 0x070, 7,
726
+
CV1800_PINCONF_AREA_SYS, 0x93c),
727
+
CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
728
+
IO_TYPE_1V8_ONLY,
729
+
CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
730
+
CV1800_PINCONF_AREA_RTC, 0x0e0),
731
+
CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
732
+
IO_TYPE_1V8_ONLY,
733
+
CV1800_PINCONF_AREA_SYS, 0x080, 0,
734
+
CV1800_PINCONF_AREA_RTC, 0x004),
735
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
736
+
IO_TYPE_1V8_ONLY,
737
+
CV1800_PINCONF_AREA_SYS, 0x088, 3,
738
+
CV1800_PINCONF_AREA_RTC, 0x00c),
739
+
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
740
+
IO_TYPE_1V8_ONLY,
741
+
CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
742
+
CV1800_PINCONF_AREA_RTC, 0x028),
743
+
};
744
+
745
+
static const struct cv1800_pinctrl_data sg2000_pindata = {
746
+
.pins = sg2000_pins,
747
+
.pindata = sg2000_pin_data,
748
+
.pdnames = sg2000_power_domain_desc,
749
+
.vddio_ops = &sg2000_vddio_cfg_ops,
750
+
.npins = ARRAY_SIZE(sg2000_pins),
751
+
.npd = ARRAY_SIZE(sg2000_power_domain_desc),
752
+
};
753
+
754
+
static const struct of_device_id sg2000_pinctrl_ids[] = {
755
+
{ .compatible = "sophgo,sg2000-pinctrl", .data = &sg2000_pindata },
756
+
{ }
757
+
};
758
+
MODULE_DEVICE_TABLE(of, sg2000_pinctrl_ids);
759
+
760
+
static struct platform_driver sg2000_pinctrl_driver = {
761
+
.probe = cv1800_pinctrl_probe,
762
+
.driver = {
763
+
.name = "sg2000-pinctrl",
764
+
.suppress_bind_attrs = true,
765
+
.of_match_table = sg2000_pinctrl_ids,
766
+
},
767
+
};
768
+
module_platform_driver(sg2000_pinctrl_driver);
769
+
770
+
MODULE_DESCRIPTION("Pinctrl driver for the SG2000 series SoC");
771
+
MODULE_LICENSE("GPL");
+542
drivers/pinctrl/sophgo/pinctrl-sg2002.c
+542
drivers/pinctrl/sophgo/pinctrl-sg2002.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2002 SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
* This file is generated from vendor pinout definition.
8
+
*/
9
+
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/of.h>
13
+
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/pinctrl/pinmux.h>
16
+
17
+
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
18
+
19
+
#include "pinctrl-cv18xx.h"
20
+
21
+
enum SG2002_POWER_DOMAIN {
22
+
VDD18A_MIPI = 0,
23
+
VDD18A_USB_PLL_ETH = 1,
24
+
VDDIO_RTC = 2,
25
+
VDDIO_SD0_EMMC = 3,
26
+
VDDIO_SD1 = 4
27
+
};
28
+
29
+
static const char *const sg2002_power_domain_desc[] = {
30
+
[VDD18A_MIPI] = "VDD18A_MIPI",
31
+
[VDD18A_USB_PLL_ETH] = "VDD18A_USB_PLL_ETH",
32
+
[VDDIO_RTC] = "VDDIO_RTC",
33
+
[VDDIO_SD0_EMMC] = "VDDIO_SD0_EMMC",
34
+
[VDDIO_SD1] = "VDDIO_SD1",
35
+
};
36
+
37
+
static int sg2002_get_pull_up(struct cv1800_pin *pin, const u32 *psmap)
38
+
{
39
+
u32 pstate = psmap[pin->power_domain];
40
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
41
+
42
+
if (type == IO_TYPE_1V8_ONLY)
43
+
return 79000;
44
+
45
+
if (type == IO_TYPE_1V8_OR_3V3) {
46
+
if (pstate == PIN_POWER_STATE_1V8)
47
+
return 60000;
48
+
if (pstate == PIN_POWER_STATE_3V3)
49
+
return 60000;
50
+
51
+
return -EINVAL;
52
+
}
53
+
54
+
return -ENOTSUPP;
55
+
}
56
+
57
+
static int sg2002_get_pull_down(struct cv1800_pin *pin, const u32 *psmap)
58
+
{
59
+
u32 pstate = psmap[pin->power_domain];
60
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
61
+
62
+
if (type == IO_TYPE_1V8_ONLY)
63
+
return 87000;
64
+
65
+
if (type == IO_TYPE_1V8_OR_3V3) {
66
+
if (pstate == PIN_POWER_STATE_1V8)
67
+
return 61000;
68
+
if (pstate == PIN_POWER_STATE_3V3)
69
+
return 62000;
70
+
71
+
return -EINVAL;
72
+
}
73
+
74
+
return -ENOTSUPP;
75
+
}
76
+
77
+
static const u32 sg2002_1v8_oc_map[] = {
78
+
12800,
79
+
25300,
80
+
37400,
81
+
49000
82
+
};
83
+
84
+
static const u32 sg2002_18od33_1v8_oc_map[] = {
85
+
7800,
86
+
11700,
87
+
15500,
88
+
19200,
89
+
23000,
90
+
26600,
91
+
30200,
92
+
33700
93
+
};
94
+
95
+
static const u32 sg2002_18od33_3v3_oc_map[] = {
96
+
5500,
97
+
8200,
98
+
10800,
99
+
13400,
100
+
16100,
101
+
18700,
102
+
21200,
103
+
23700
104
+
};
105
+
106
+
static const u32 sg2002_eth_oc_map[] = {
107
+
15700,
108
+
17800
109
+
};
110
+
111
+
static int sg2002_get_oc_map(struct cv1800_pin *pin, const u32 *psmap,
112
+
const u32 **map)
113
+
{
114
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
115
+
u32 pstate = psmap[pin->power_domain];
116
+
117
+
if (type == IO_TYPE_1V8_ONLY) {
118
+
*map = sg2002_1v8_oc_map;
119
+
return ARRAY_SIZE(sg2002_1v8_oc_map);
120
+
}
121
+
122
+
if (type == IO_TYPE_1V8_OR_3V3) {
123
+
if (pstate == PIN_POWER_STATE_1V8) {
124
+
*map = sg2002_18od33_1v8_oc_map;
125
+
return ARRAY_SIZE(sg2002_18od33_1v8_oc_map);
126
+
} else if (pstate == PIN_POWER_STATE_3V3) {
127
+
*map = sg2002_18od33_3v3_oc_map;
128
+
return ARRAY_SIZE(sg2002_18od33_3v3_oc_map);
129
+
}
130
+
}
131
+
132
+
if (type == IO_TYPE_ETH) {
133
+
*map = sg2002_eth_oc_map;
134
+
return ARRAY_SIZE(sg2002_eth_oc_map);
135
+
}
136
+
137
+
return -ENOTSUPP;
138
+
}
139
+
140
+
static const u32 sg2002_1v8_schmitt_map[] = {
141
+
0,
142
+
970000,
143
+
1040000
144
+
};
145
+
146
+
static const u32 sg2002_18od33_1v8_schmitt_map[] = {
147
+
0,
148
+
1070000
149
+
};
150
+
151
+
static const u32 sg2002_18od33_3v3_schmitt_map[] = {
152
+
0,
153
+
1100000
154
+
};
155
+
156
+
static int sg2002_get_schmitt_map(struct cv1800_pin *pin, const u32 *psmap,
157
+
const u32 **map)
158
+
{
159
+
enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
160
+
u32 pstate = psmap[pin->power_domain];
161
+
162
+
if (type == IO_TYPE_1V8_ONLY) {
163
+
*map = sg2002_1v8_schmitt_map;
164
+
return ARRAY_SIZE(sg2002_1v8_schmitt_map);
165
+
}
166
+
167
+
if (type == IO_TYPE_1V8_OR_3V3) {
168
+
if (pstate == PIN_POWER_STATE_1V8) {
169
+
*map = sg2002_18od33_1v8_schmitt_map;
170
+
return ARRAY_SIZE(sg2002_18od33_1v8_schmitt_map);
171
+
} else if (pstate == PIN_POWER_STATE_3V3) {
172
+
*map = sg2002_18od33_3v3_schmitt_map;
173
+
return ARRAY_SIZE(sg2002_18od33_3v3_schmitt_map);
174
+
}
175
+
}
176
+
177
+
return -ENOTSUPP;
178
+
}
179
+
180
+
static const struct cv1800_vddio_cfg_ops sg2002_vddio_cfg_ops = {
181
+
.get_pull_up = sg2002_get_pull_up,
182
+
.get_pull_down = sg2002_get_pull_down,
183
+
.get_oc_map = sg2002_get_oc_map,
184
+
.get_schmitt_map = sg2002_get_schmitt_map,
185
+
};
186
+
187
+
static const struct pinctrl_pin_desc sg2002_pins[] = {
188
+
PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
189
+
PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
190
+
PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
191
+
PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
192
+
PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
193
+
PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
194
+
PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
195
+
PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
196
+
PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
197
+
PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
198
+
PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
199
+
PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
200
+
PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
201
+
PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
202
+
PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
203
+
PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
204
+
PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
205
+
PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
206
+
PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
207
+
PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
208
+
PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
209
+
PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
210
+
PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
211
+
PINCTRL_PIN(PIN_AUX0, "AUX0"),
212
+
PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
213
+
PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
214
+
PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
215
+
PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
216
+
PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
217
+
PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
218
+
PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
219
+
PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
220
+
PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
221
+
PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
222
+
PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
223
+
PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
224
+
PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
225
+
PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
226
+
PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
227
+
PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
228
+
PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
229
+
PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
230
+
PINCTRL_PIN(PIN_ADC1, "ADC1"),
231
+
PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
232
+
PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
233
+
PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
234
+
PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
235
+
PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
236
+
PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
237
+
PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
238
+
PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
239
+
PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
240
+
PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
241
+
PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
242
+
PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
243
+
PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
244
+
PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
245
+
PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
246
+
PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
247
+
PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
248
+
PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
249
+
PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
250
+
PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
251
+
PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
252
+
PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
253
+
};
254
+
255
+
static const struct cv1800_pin sg2002_pin_data[ARRAY_SIZE(sg2002_pins)] = {
256
+
CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
257
+
IO_TYPE_AUDIO,
258
+
CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
259
+
CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
260
+
IO_TYPE_AUDIO,
261
+
CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
262
+
CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_EMMC,
263
+
IO_TYPE_1V8_OR_3V3,
264
+
CV1800_PINCONF_AREA_SYS, 0x01c, 7,
265
+
CV1800_PINCONF_AREA_SYS, 0xa00),
266
+
CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_EMMC,
267
+
IO_TYPE_1V8_OR_3V3,
268
+
CV1800_PINCONF_AREA_SYS, 0x020, 7,
269
+
CV1800_PINCONF_AREA_SYS, 0xa04),
270
+
CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_EMMC,
271
+
IO_TYPE_1V8_OR_3V3,
272
+
CV1800_PINCONF_AREA_SYS, 0x024, 7,
273
+
CV1800_PINCONF_AREA_SYS, 0xa08),
274
+
CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_EMMC,
275
+
IO_TYPE_1V8_OR_3V3,
276
+
CV1800_PINCONF_AREA_SYS, 0x028, 7,
277
+
CV1800_PINCONF_AREA_SYS, 0xa0c),
278
+
CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_EMMC,
279
+
IO_TYPE_1V8_OR_3V3,
280
+
CV1800_PINCONF_AREA_SYS, 0x02c, 7,
281
+
CV1800_PINCONF_AREA_SYS, 0xa10),
282
+
CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_EMMC,
283
+
IO_TYPE_1V8_OR_3V3,
284
+
CV1800_PINCONF_AREA_SYS, 0x030, 7,
285
+
CV1800_PINCONF_AREA_SYS, 0xa14),
286
+
CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_EMMC,
287
+
IO_TYPE_1V8_OR_3V3,
288
+
CV1800_PINCONF_AREA_SYS, 0x034, 3,
289
+
CV1800_PINCONF_AREA_SYS, 0x900),
290
+
CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_EMMC,
291
+
IO_TYPE_1V8_OR_3V3,
292
+
CV1800_PINCONF_AREA_SYS, 0x038, 3,
293
+
CV1800_PINCONF_AREA_SYS, 0x904),
294
+
CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_EMMC,
295
+
IO_TYPE_1V8_OR_3V3,
296
+
CV1800_PINCONF_AREA_SYS, 0x03c, 3,
297
+
CV1800_PINCONF_AREA_SYS, 0x908),
298
+
CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_EMMC,
299
+
IO_TYPE_1V8_OR_3V3,
300
+
CV1800_PINCONF_AREA_SYS, 0x040, 7,
301
+
CV1800_PINCONF_AREA_SYS, 0x90c),
302
+
CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_EMMC,
303
+
IO_TYPE_1V8_OR_3V3,
304
+
CV1800_PINCONF_AREA_SYS, 0x044, 7,
305
+
CV1800_PINCONF_AREA_SYS, 0x910),
306
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_SD0_EMMC,
307
+
IO_TYPE_1V8_OR_3V3,
308
+
CV1800_PINCONF_AREA_SYS, 0x04c, 3,
309
+
CV1800_PINCONF_AREA_SYS, 0x918),
310
+
CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_SD0_EMMC,
311
+
IO_TYPE_1V8_OR_3V3,
312
+
CV1800_PINCONF_AREA_SYS, 0x050, 3,
313
+
CV1800_PINCONF_AREA_SYS, 0x91c),
314
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_SD0_EMMC,
315
+
IO_TYPE_1V8_OR_3V3,
316
+
CV1800_PINCONF_AREA_SYS, 0x054, 3,
317
+
CV1800_PINCONF_AREA_SYS, 0x920),
318
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_SD0_EMMC,
319
+
IO_TYPE_1V8_OR_3V3,
320
+
CV1800_PINCONF_AREA_SYS, 0x058, 3,
321
+
CV1800_PINCONF_AREA_SYS, 0x924),
322
+
CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_SD0_EMMC,
323
+
IO_TYPE_1V8_OR_3V3,
324
+
CV1800_PINCONF_AREA_SYS, 0x05c, 3,
325
+
CV1800_PINCONF_AREA_SYS, 0x928),
326
+
CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_SD0_EMMC,
327
+
IO_TYPE_1V8_OR_3V3,
328
+
CV1800_PINCONF_AREA_SYS, 0x060, 3,
329
+
CV1800_PINCONF_AREA_SYS, 0x92c),
330
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_SD0_EMMC,
331
+
IO_TYPE_1V8_OR_3V3,
332
+
CV1800_PINCONF_AREA_SYS, 0x064, 7,
333
+
CV1800_PINCONF_AREA_SYS, 0x930),
334
+
CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_SD0_EMMC,
335
+
IO_TYPE_1V8_OR_3V3,
336
+
CV1800_PINCONF_AREA_SYS, 0x068, 7,
337
+
CV1800_PINCONF_AREA_SYS, 0x934),
338
+
CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_EMMC,
339
+
IO_TYPE_1V8_OR_3V3,
340
+
CV1800_PINCONF_AREA_SYS, 0x070, 7,
341
+
CV1800_PINCONF_AREA_SYS, 0x93c),
342
+
CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_EMMC,
343
+
IO_TYPE_1V8_OR_3V3,
344
+
CV1800_PINCONF_AREA_SYS, 0x074, 7,
345
+
CV1800_PINCONF_AREA_SYS, 0x940),
346
+
CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_EMMC,
347
+
IO_TYPE_1V8_OR_3V3,
348
+
CV1800_PINCONF_AREA_SYS, 0x078, 7,
349
+
CV1800_PINCONF_AREA_SYS, 0x944),
350
+
CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
351
+
IO_TYPE_1V8_ONLY,
352
+
CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
353
+
CV1800_PINCONF_AREA_RTC, 0x0e0),
354
+
CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
355
+
IO_TYPE_1V8_ONLY,
356
+
CV1800_PINCONF_AREA_SYS, 0x07c, 0,
357
+
CV1800_PINCONF_AREA_RTC, 0x000),
358
+
CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
359
+
IO_TYPE_1V8_ONLY,
360
+
CV1800_PINCONF_AREA_SYS, 0x080, 0,
361
+
CV1800_PINCONF_AREA_RTC, 0x004),
362
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
363
+
IO_TYPE_1V8_ONLY,
364
+
CV1800_PINCONF_AREA_SYS, 0x084, 3,
365
+
CV1800_PINCONF_AREA_RTC, 0x008),
366
+
CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
367
+
IO_TYPE_1V8_ONLY,
368
+
CV1800_PINCONF_AREA_SYS, 0x088, 3,
369
+
CV1800_PINCONF_AREA_RTC, 0x00c),
370
+
CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
371
+
IO_TYPE_1V8_ONLY,
372
+
CV1800_PINCONF_AREA_SYS, 0x090, 7,
373
+
CV1800_PINCONF_AREA_RTC, 0x018),
374
+
CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
375
+
IO_TYPE_1V8_ONLY,
376
+
CV1800_PINCONF_AREA_SYS, 0x098, 7,
377
+
CV1800_PINCONF_AREA_RTC, 0x020),
378
+
CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
379
+
IO_TYPE_1V8_ONLY,
380
+
CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
381
+
CV1800_PINCONF_AREA_RTC, 0x028),
382
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
383
+
IO_TYPE_1V8_ONLY,
384
+
CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
385
+
CV1800_PINCONF_AREA_RTC, 0x02c),
386
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
387
+
IO_TYPE_1V8_ONLY,
388
+
CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
389
+
CV1800_PINCONF_AREA_RTC, 0x030),
390
+
CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
391
+
IO_TYPE_1V8_ONLY,
392
+
CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
393
+
CV1800_PINCONF_AREA_RTC, 0x034),
394
+
CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
395
+
IO_TYPE_1V8_OR_3V3,
396
+
CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
397
+
CV1800_PINCONF_AREA_RTC, 0x058),
398
+
CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
399
+
IO_TYPE_1V8_OR_3V3,
400
+
CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
401
+
CV1800_PINCONF_AREA_RTC, 0x05c),
402
+
CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
403
+
IO_TYPE_1V8_OR_3V3,
404
+
CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
405
+
CV1800_PINCONF_AREA_RTC, 0x060),
406
+
CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
407
+
IO_TYPE_1V8_OR_3V3,
408
+
CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
409
+
CV1800_PINCONF_AREA_RTC, 0x064),
410
+
CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
411
+
IO_TYPE_1V8_OR_3V3,
412
+
CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
413
+
CV1800_PINCONF_AREA_RTC, 0x068),
414
+
CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
415
+
IO_TYPE_1V8_OR_3V3,
416
+
CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
417
+
CV1800_PINCONF_AREA_RTC, 0x06c),
418
+
CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDD18A_USB_PLL_ETH,
419
+
IO_TYPE_1V8_ONLY,
420
+
CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
421
+
CV1800_PINCONF_AREA_SYS, 0x804),
422
+
CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH,
423
+
IO_TYPE_1V8_ONLY,
424
+
CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
425
+
CV1800_PINCONF_AREA_SYS, 0x810),
426
+
CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH,
427
+
IO_TYPE_1V8_ONLY,
428
+
CV1800_PINCONF_AREA_SYS, 0x108, 5,
429
+
CV1800_PINCONF_AREA_SYS, 0x820),
430
+
CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH,
431
+
IO_TYPE_ETH,
432
+
CV1800_PINCONF_AREA_SYS, 0x124, 7),
433
+
CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH,
434
+
IO_TYPE_ETH,
435
+
CV1800_PINCONF_AREA_SYS, 0x128, 7),
436
+
CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH,
437
+
IO_TYPE_ETH,
438
+
CV1800_PINCONF_AREA_SYS, 0x12c, 7),
439
+
CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH,
440
+
IO_TYPE_ETH,
441
+
CV1800_PINCONF_AREA_SYS, 0x130, 7),
442
+
CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDD18A_USB_PLL_ETH,
443
+
IO_TYPE_1V8_ONLY,
444
+
CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
445
+
CV1800_PINCONF_AREA_SYS, 0xc8c),
446
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
447
+
IO_TYPE_1V8_ONLY,
448
+
CV1800_PINCONF_AREA_SYS, 0x16c, 7,
449
+
CV1800_PINCONF_AREA_SYS, 0x120, 7,
450
+
CV1800_PINCONF_AREA_SYS, 0xc38),
451
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
452
+
IO_TYPE_1V8_ONLY,
453
+
CV1800_PINCONF_AREA_SYS, 0x170, 7,
454
+
CV1800_PINCONF_AREA_SYS, 0x11c, 7,
455
+
CV1800_PINCONF_AREA_SYS, 0xc3c),
456
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
457
+
IO_TYPE_1V8_ONLY,
458
+
CV1800_PINCONF_AREA_SYS, 0x174, 7,
459
+
CV1800_PINCONF_AREA_SYS, 0x114, 7,
460
+
CV1800_PINCONF_AREA_SYS, 0xc40),
461
+
CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
462
+
IO_TYPE_1V8_ONLY,
463
+
CV1800_PINCONF_AREA_SYS, 0x178, 7,
464
+
CV1800_PINCONF_AREA_SYS, 0x118, 7,
465
+
CV1800_PINCONF_AREA_SYS, 0xc44),
466
+
CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
467
+
IO_TYPE_1V8_ONLY,
468
+
CV1800_PINCONF_AREA_SYS, 0x17c, 7,
469
+
CV1800_PINCONF_AREA_SYS, 0xc48),
470
+
CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
471
+
IO_TYPE_1V8_ONLY,
472
+
CV1800_PINCONF_AREA_SYS, 0x180, 7,
473
+
CV1800_PINCONF_AREA_SYS, 0xc4c),
474
+
CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
475
+
IO_TYPE_1V8_ONLY,
476
+
CV1800_PINCONF_AREA_SYS, 0x184, 7,
477
+
CV1800_PINCONF_AREA_SYS, 0xc50),
478
+
CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
479
+
IO_TYPE_1V8_ONLY,
480
+
CV1800_PINCONF_AREA_SYS, 0x188, 7,
481
+
CV1800_PINCONF_AREA_SYS, 0xc54),
482
+
CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
483
+
IO_TYPE_1V8_ONLY,
484
+
CV1800_PINCONF_AREA_SYS, 0x18c, 7,
485
+
CV1800_PINCONF_AREA_SYS, 0xc58),
486
+
CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
487
+
IO_TYPE_1V8_ONLY,
488
+
CV1800_PINCONF_AREA_SYS, 0x190, 7,
489
+
CV1800_PINCONF_AREA_SYS, 0xc5c),
490
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
491
+
IO_TYPE_1V8_ONLY,
492
+
CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
493
+
CV1800_PINCONF_AREA_SYS, 0xc70),
494
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
495
+
IO_TYPE_1V8_ONLY,
496
+
CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
497
+
CV1800_PINCONF_AREA_SYS, 0xc74),
498
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
499
+
IO_TYPE_1V8_ONLY,
500
+
CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
501
+
CV1800_PINCONF_AREA_SYS, 0xc78),
502
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
503
+
IO_TYPE_1V8_ONLY,
504
+
CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
505
+
CV1800_PINCONF_AREA_SYS, 0xc7c),
506
+
CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
507
+
IO_TYPE_1V8_ONLY,
508
+
CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
509
+
CV1800_PINCONF_AREA_SYS, 0xc80),
510
+
CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
511
+
IO_TYPE_1V8_ONLY,
512
+
CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
513
+
CV1800_PINCONF_AREA_SYS, 0xc84),
514
+
};
515
+
516
+
static const struct cv1800_pinctrl_data sg2002_pindata = {
517
+
.pins = sg2002_pins,
518
+
.pindata = sg2002_pin_data,
519
+
.pdnames = sg2002_power_domain_desc,
520
+
.vddio_ops = &sg2002_vddio_cfg_ops,
521
+
.npins = ARRAY_SIZE(sg2002_pins),
522
+
.npd = ARRAY_SIZE(sg2002_power_domain_desc),
523
+
};
524
+
525
+
static const struct of_device_id sg2002_pinctrl_ids[] = {
526
+
{ .compatible = "sophgo,sg2002-pinctrl", .data = &sg2002_pindata },
527
+
{ }
528
+
};
529
+
MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids);
530
+
531
+
static struct platform_driver sg2002_pinctrl_driver = {
532
+
.probe = cv1800_pinctrl_probe,
533
+
.driver = {
534
+
.name = "sg2002-pinctrl",
535
+
.suppress_bind_attrs = true,
536
+
.of_match_table = sg2002_pinctrl_ids,
537
+
},
538
+
};
539
+
module_platform_driver(sg2002_pinctrl_driver);
540
+
541
+
MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
542
+
MODULE_LICENSE("GPL");
+4
-10
drivers/pinctrl/sunxi/pinctrl-sunxi.c
+4
-10
drivers/pinctrl/sunxi/pinctrl-sunxi.c
···
1603
1603
}
1604
1604
1605
1605
ret = of_clk_get_parent_count(node);
1606
-
clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1606
+
clk = devm_clk_get_enabled(&pdev->dev, ret == 1 ? NULL : "apb");
1607
1607
if (IS_ERR(clk)) {
1608
1608
ret = PTR_ERR(clk);
1609
1609
goto gpiochip_error;
1610
1610
}
1611
-
1612
-
ret = clk_prepare_enable(clk);
1613
-
if (ret)
1614
-
goto gpiochip_error;
1615
1611
1616
1612
pctl->irq = devm_kcalloc(&pdev->dev,
1617
1613
pctl->desc->irq_banks,
···
1615
1619
GFP_KERNEL);
1616
1620
if (!pctl->irq) {
1617
1621
ret = -ENOMEM;
1618
-
goto clk_error;
1622
+
goto gpiochip_error;
1619
1623
}
1620
1624
1621
1625
for (i = 0; i < pctl->desc->irq_banks; i++) {
1622
1626
pctl->irq[i] = platform_get_irq(pdev, i);
1623
1627
if (pctl->irq[i] < 0) {
1624
1628
ret = pctl->irq[i];
1625
-
goto clk_error;
1629
+
goto gpiochip_error;
1626
1630
}
1627
1631
}
1628
1632
···
1633
1637
if (!pctl->domain) {
1634
1638
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1635
1639
ret = -ENOMEM;
1636
-
goto clk_error;
1640
+
goto gpiochip_error;
1637
1641
}
1638
1642
1639
1643
for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
···
1665
1669
1666
1670
return 0;
1667
1671
1668
-
clk_error:
1669
-
clk_disable_unprepare(clk);
1670
1672
gpiochip_error:
1671
1673
gpiochip_remove(pctl->chip);
1672
1674
return ret;
+24
-34
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
+24
-34
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
···
82
82
u32 reg_start_offset;
83
83
u32 reg_nr_per_pin;
84
84
85
-
struct regmap_config *regmap_config;
85
+
const struct regmap_config *regmap_config;
86
86
};
87
87
88
88
/**
···
274
274
}
275
275
276
276
/**
277
+
* ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
278
+
* @data: IODelay device
279
+
*
280
+
* Deinitialize the IODelay device (basically just lock the region back up.
281
+
*/
282
+
static void ti_iodelay_pinconf_deinit_dev(void *data)
283
+
{
284
+
struct ti_iodelay_device *iod = data;
285
+
const struct ti_iodelay_reg_data *reg = iod->reg_data;
286
+
287
+
/* lock the iodelay region back again */
288
+
regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
289
+
reg->global_lock_mask, reg->global_lock_val);
290
+
}
291
+
292
+
/**
277
293
* ti_iodelay_pinconf_init_dev() - Initialize IODelay device
278
294
* @iod: iodelay device
279
295
*
···
308
292
/* unlock the iodelay region */
309
293
r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
310
294
reg->global_lock_mask, reg->global_unlock_val);
295
+
if (r)
296
+
return r;
297
+
298
+
r = devm_add_action_or_reset(iod->dev, ti_iodelay_pinconf_deinit_dev,
299
+
iod);
311
300
if (r)
312
301
return r;
313
302
···
372
351
ival->fine_ref_count, ival->fine_delay_count, ival->fdpe);
373
352
374
353
return 0;
375
-
}
376
-
377
-
/**
378
-
* ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device
379
-
* @iod: IODelay device
380
-
*
381
-
* Deinitialize the IODelay device (basically just lock the region back up.
382
-
*/
383
-
static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod)
384
-
{
385
-
const struct ti_iodelay_reg_data *reg = iod->reg_data;
386
-
387
-
/* lock the iodelay region back again */
388
-
regmap_update_bits(iod->regmap, reg->reg_global_lock_offset,
389
-
reg->global_lock_mask, reg->global_lock_val);
390
354
}
391
355
392
356
/**
···
776
770
return 0;
777
771
}
778
772
779
-
static struct regmap_config dra7_iodelay_regmap_config = {
773
+
static const struct regmap_config dra7_iodelay_regmap_config = {
780
774
.reg_bits = 32,
781
775
.reg_stride = 4,
782
776
.val_bits = 32,
783
777
.max_register = 0xd1c,
784
778
};
785
779
786
-
static struct ti_iodelay_reg_data dra7_iodelay_data = {
780
+
static const struct ti_iodelay_reg_data dra7_iodelay_data = {
787
781
.signature_mask = 0x0003f000,
788
782
.signature_value = 0x29,
789
783
.lock_mask = 0x00000400,
···
883
877
return ret;
884
878
}
885
879
886
-
platform_set_drvdata(pdev, iod);
887
-
888
880
return pinctrl_enable(iod->pctl);
889
-
}
890
-
891
-
/**
892
-
* ti_iodelay_remove() - standard remove
893
-
* @pdev: platform device
894
-
*/
895
-
static void ti_iodelay_remove(struct platform_device *pdev)
896
-
{
897
-
struct ti_iodelay_device *iod = platform_get_drvdata(pdev);
898
-
899
-
ti_iodelay_pinconf_deinit_dev(iod);
900
-
901
-
/* Expect other allocations to be freed by devm */
902
881
}
903
882
904
883
static struct platform_driver ti_iodelay_driver = {
905
884
.probe = ti_iodelay_probe,
906
-
.remove_new = ti_iodelay_remove,
907
885
.driver = {
908
886
.name = DRIVER_NAME,
909
887
.of_match_table = ti_iodelay_of_match,
+63
include/dt-bindings/pinctrl/pinctrl-cv1800b.h
+63
include/dt-bindings/pinctrl/pinctrl-cv1800b.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*
5
+
* This file is generated from vendor pinout definition.
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_PINCTRL_CV1800B_H
9
+
#define _DT_BINDINGS_PINCTRL_CV1800B_H
10
+
11
+
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
12
+
13
+
#define PIN_AUD_AOUTR 1
14
+
#define PIN_SD0_CLK 3
15
+
#define PIN_SD0_CMD 4
16
+
#define PIN_SD0_D0 5
17
+
#define PIN_SD0_D1 7
18
+
#define PIN_SD0_D2 8
19
+
#define PIN_SD0_D3 9
20
+
#define PIN_SD0_CD 11
21
+
#define PIN_SD0_PWR_EN 12
22
+
#define PIN_SPK_EN 14
23
+
#define PIN_UART0_TX 15
24
+
#define PIN_UART0_RX 16
25
+
#define PIN_SPINOR_HOLD_X 17
26
+
#define PIN_SPINOR_SCK 18
27
+
#define PIN_SPINOR_MOSI 19
28
+
#define PIN_SPINOR_WP_X 20
29
+
#define PIN_SPINOR_MISO 21
30
+
#define PIN_SPINOR_CS_X 22
31
+
#define PIN_IIC0_SCL 23
32
+
#define PIN_IIC0_SDA 24
33
+
#define PIN_AUX0 25
34
+
#define PIN_PWR_VBAT_DET 30
35
+
#define PIN_PWR_SEQ2 31
36
+
#define PIN_XTAL_XIN 33
37
+
#define PIN_SD1_GPIO0 35
38
+
#define PIN_SD1_GPIO1 36
39
+
#define PIN_SD1_D3 38
40
+
#define PIN_SD1_D2 39
41
+
#define PIN_SD1_D1 40
42
+
#define PIN_SD1_D0 41
43
+
#define PIN_SD1_CMD 42
44
+
#define PIN_SD1_CLK 43
45
+
#define PIN_ADC1 44
46
+
#define PIN_USB_VBUS_DET 45
47
+
#define PIN_ETH_TXP 47
48
+
#define PIN_ETH_TXM 48
49
+
#define PIN_ETH_RXP 49
50
+
#define PIN_ETH_RXM 50
51
+
#define PIN_MIPIRX4N 56
52
+
#define PIN_MIPIRX4P 57
53
+
#define PIN_MIPIRX3N 58
54
+
#define PIN_MIPIRX3P 59
55
+
#define PIN_MIPIRX2N 60
56
+
#define PIN_MIPIRX2P 61
57
+
#define PIN_MIPIRX1N 62
58
+
#define PIN_MIPIRX1P 63
59
+
#define PIN_MIPIRX0N 64
60
+
#define PIN_MIPIRX0P 65
61
+
#define PIN_AUD_AINL_MIC 67
62
+
63
+
#endif /* _DT_BINDINGS_PINCTRL_CV1800B_H */
+127
include/dt-bindings/pinctrl/pinctrl-cv1812h.h
+127
include/dt-bindings/pinctrl/pinctrl-cv1812h.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*
5
+
* This file is generated from vendor pinout definition.
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_PINCTRL_CV1812H_H
9
+
#define _DT_BINDINGS_PINCTRL_CV1812H_H
10
+
11
+
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
12
+
13
+
#define PINPOS(row, col) \
14
+
((((row) - 'A' + 1) << 8) + ((col) - 1))
15
+
16
+
#define PIN_MIPI_TXM4 PINPOS('A', 2)
17
+
#define PIN_MIPIRX0N PINPOS('A', 4)
18
+
#define PIN_MIPIRX3P PINPOS('A', 6)
19
+
#define PIN_MIPIRX4P PINPOS('A', 7)
20
+
#define PIN_VIVO_D2 PINPOS('A', 9)
21
+
#define PIN_VIVO_D3 PINPOS('A', 10)
22
+
#define PIN_VIVO_D10 PINPOS('A', 12)
23
+
#define PIN_USB_VBUS_DET PINPOS('A', 13)
24
+
#define PIN_MIPI_TXP3 PINPOS('B', 1)
25
+
#define PIN_MIPI_TXM3 PINPOS('B', 2)
26
+
#define PIN_MIPI_TXP4 PINPOS('B', 3)
27
+
#define PIN_MIPIRX0P PINPOS('B', 4)
28
+
#define PIN_MIPIRX1N PINPOS('B', 5)
29
+
#define PIN_MIPIRX2N PINPOS('B', 6)
30
+
#define PIN_MIPIRX4N PINPOS('B', 7)
31
+
#define PIN_MIPIRX5N PINPOS('B', 8)
32
+
#define PIN_VIVO_D1 PINPOS('B', 9)
33
+
#define PIN_VIVO_D5 PINPOS('B', 10)
34
+
#define PIN_VIVO_D7 PINPOS('B', 11)
35
+
#define PIN_VIVO_D9 PINPOS('B', 12)
36
+
#define PIN_USB_ID PINPOS('B', 13)
37
+
#define PIN_ETH_RXM PINPOS('B', 15)
38
+
#define PIN_MIPI_TXP2 PINPOS('C', 1)
39
+
#define PIN_MIPI_TXM2 PINPOS('C', 2)
40
+
#define PIN_CAM_PD0 PINPOS('C', 3)
41
+
#define PIN_CAM_MCLK0 PINPOS('C', 4)
42
+
#define PIN_MIPIRX1P PINPOS('C', 5)
43
+
#define PIN_MIPIRX2P PINPOS('C', 6)
44
+
#define PIN_MIPIRX3N PINPOS('C', 7)
45
+
#define PIN_MIPIRX5P PINPOS('C', 8)
46
+
#define PIN_VIVO_CLK PINPOS('C', 9)
47
+
#define PIN_VIVO_D6 PINPOS('C', 10)
48
+
#define PIN_VIVO_D8 PINPOS('C', 11)
49
+
#define PIN_USB_VBUS_EN PINPOS('C', 12)
50
+
#define PIN_ETH_RXP PINPOS('C', 14)
51
+
#define PIN_GPIO_RTX PINPOS('C', 15)
52
+
#define PIN_MIPI_TXP1 PINPOS('D', 1)
53
+
#define PIN_MIPI_TXM1 PINPOS('D', 2)
54
+
#define PIN_CAM_MCLK1 PINPOS('D', 3)
55
+
#define PIN_IIC3_SCL PINPOS('D', 4)
56
+
#define PIN_VIVO_D4 PINPOS('D', 10)
57
+
#define PIN_ETH_TXM PINPOS('D', 14)
58
+
#define PIN_ETH_TXP PINPOS('D', 15)
59
+
#define PIN_MIPI_TXP0 PINPOS('E', 1)
60
+
#define PIN_MIPI_TXM0 PINPOS('E', 2)
61
+
#define PIN_CAM_PD1 PINPOS('E', 4)
62
+
#define PIN_CAM_RST0 PINPOS('E', 5)
63
+
#define PIN_VIVO_D0 PINPOS('E', 10)
64
+
#define PIN_ADC1 PINPOS('E', 13)
65
+
#define PIN_ADC2 PINPOS('E', 14)
66
+
#define PIN_ADC3 PINPOS('E', 15)
67
+
#define PIN_AUD_AOUTL PINPOS('F', 2)
68
+
#define PIN_IIC3_SDA PINPOS('F', 4)
69
+
#define PIN_SD1_D2 PINPOS('F', 14)
70
+
#define PIN_AUD_AOUTR PINPOS('G', 2)
71
+
#define PIN_SD1_D3 PINPOS('G', 13)
72
+
#define PIN_SD1_CLK PINPOS('G', 14)
73
+
#define PIN_SD1_CMD PINPOS('G', 15)
74
+
#define PIN_AUD_AINL_MIC PINPOS('H', 1)
75
+
#define PIN_RSTN PINPOS('H', 12)
76
+
#define PIN_PWM0_BUCK PINPOS('H', 13)
77
+
#define PIN_SD1_D1 PINPOS('H', 14)
78
+
#define PIN_SD1_D0 PINPOS('H', 15)
79
+
#define PIN_AUD_AINR_MIC PINPOS('J', 1)
80
+
#define PIN_IIC2_SCL PINPOS('J', 13)
81
+
#define PIN_IIC2_SDA PINPOS('J', 14)
82
+
#define PIN_SD0_CD PINPOS('K', 2)
83
+
#define PIN_SD0_D1 PINPOS('K', 3)
84
+
#define PIN_UART2_RX PINPOS('K', 13)
85
+
#define PIN_UART2_CTS PINPOS('K', 14)
86
+
#define PIN_UART2_TX PINPOS('K', 15)
87
+
#define PIN_SD0_CLK PINPOS('L', 1)
88
+
#define PIN_SD0_D0 PINPOS('L', 2)
89
+
#define PIN_SD0_CMD PINPOS('L', 3)
90
+
#define PIN_CLK32K PINPOS('L', 14)
91
+
#define PIN_UART2_RTS PINPOS('L', 15)
92
+
#define PIN_SD0_D3 PINPOS('M', 1)
93
+
#define PIN_SD0_D2 PINPOS('M', 2)
94
+
#define PIN_UART0_RX PINPOS('M', 4)
95
+
#define PIN_UART0_TX PINPOS('M', 5)
96
+
#define PIN_JTAG_CPU_TRST PINPOS('M', 6)
97
+
#define PIN_PWR_ON PINPOS('M', 11)
98
+
#define PIN_PWR_GPIO2 PINPOS('M', 12)
99
+
#define PIN_PWR_GPIO0 PINPOS('M', 13)
100
+
#define PIN_CLK25M PINPOS('M', 14)
101
+
#define PIN_SD0_PWR_EN PINPOS('N', 1)
102
+
#define PIN_SPK_EN PINPOS('N', 3)
103
+
#define PIN_JTAG_CPU_TCK PINPOS('N', 4)
104
+
#define PIN_JTAG_CPU_TMS PINPOS('N', 6)
105
+
#define PIN_PWR_WAKEUP1 PINPOS('N', 11)
106
+
#define PIN_PWR_WAKEUP0 PINPOS('N', 12)
107
+
#define PIN_PWR_GPIO1 PINPOS('N', 13)
108
+
#define PIN_EMMC_DAT3 PINPOS('P', 1)
109
+
#define PIN_EMMC_DAT0 PINPOS('P', 2)
110
+
#define PIN_EMMC_DAT2 PINPOS('P', 3)
111
+
#define PIN_EMMC_RSTN PINPOS('P', 4)
112
+
#define PIN_AUX0 PINPOS('P', 5)
113
+
#define PIN_IIC0_SDA PINPOS('P', 6)
114
+
#define PIN_PWR_SEQ3 PINPOS('P', 10)
115
+
#define PIN_PWR_VBAT_DET PINPOS('P', 11)
116
+
#define PIN_PWR_SEQ1 PINPOS('P', 12)
117
+
#define PIN_PWR_BUTTON1 PINPOS('P', 13)
118
+
#define PIN_EMMC_DAT1 PINPOS('R', 2)
119
+
#define PIN_EMMC_CMD PINPOS('R', 3)
120
+
#define PIN_EMMC_CLK PINPOS('R', 4)
121
+
#define PIN_IIC0_SCL PINPOS('R', 6)
122
+
#define PIN_GPIO_ZQ PINPOS('R', 10)
123
+
#define PIN_PWR_RSTN PINPOS('R', 11)
124
+
#define PIN_PWR_SEQ2 PINPOS('R', 12)
125
+
#define PIN_XTAL_XIN PINPOS('R', 13)
126
+
127
+
#endif /* _DT_BINDINGS_PINCTRL_CV1812H_H */
+19
include/dt-bindings/pinctrl/pinctrl-cv18xx.h
+19
include/dt-bindings/pinctrl/pinctrl-cv18xx.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2023 Sophgo Ltd.
4
+
*
5
+
* Author: Inochi Amaoto <inochiama@outlook.com>
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_PINCTRL_CV18XX_H
9
+
#define _DT_BINDINGS_PINCTRL_CV18XX_H
10
+
11
+
#define PIN_MUX_INVALD 0xff
12
+
13
+
#define PINMUX2(pin, mux, mux2) \
14
+
(((pin) & 0xffff) | (((mux) & 0xff) << 16) | (((mux2) & 0xff) << 24))
15
+
16
+
#define PINMUX(pin, mux) \
17
+
PINMUX2(pin, mux, PIN_MUX_INVALD)
18
+
19
+
#endif /* _DT_BINDINGS_PINCTRL_CV18XX_H */
+127
include/dt-bindings/pinctrl/pinctrl-sg2000.h
+127
include/dt-bindings/pinctrl/pinctrl-sg2000.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*
5
+
* This file is generated from vendor pinout definition.
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_PINCTRL_SG2000_H
9
+
#define _DT_BINDINGS_PINCTRL_SG2000_H
10
+
11
+
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
12
+
13
+
#define PINPOS(row, col) \
14
+
((((row) - 'A' + 1) << 8) + ((col) - 1))
15
+
16
+
#define PIN_MIPI_TXM4 PINPOS('A', 2)
17
+
#define PIN_MIPIRX0N PINPOS('A', 4)
18
+
#define PIN_MIPIRX3P PINPOS('A', 6)
19
+
#define PIN_MIPIRX4P PINPOS('A', 7)
20
+
#define PIN_VIVO_D2 PINPOS('A', 9)
21
+
#define PIN_VIVO_D3 PINPOS('A', 10)
22
+
#define PIN_VIVO_D10 PINPOS('A', 12)
23
+
#define PIN_USB_VBUS_DET PINPOS('A', 13)
24
+
#define PIN_MIPI_TXP3 PINPOS('B', 1)
25
+
#define PIN_MIPI_TXM3 PINPOS('B', 2)
26
+
#define PIN_MIPI_TXP4 PINPOS('B', 3)
27
+
#define PIN_MIPIRX0P PINPOS('B', 4)
28
+
#define PIN_MIPIRX1N PINPOS('B', 5)
29
+
#define PIN_MIPIRX2N PINPOS('B', 6)
30
+
#define PIN_MIPIRX4N PINPOS('B', 7)
31
+
#define PIN_MIPIRX5N PINPOS('B', 8)
32
+
#define PIN_VIVO_D1 PINPOS('B', 9)
33
+
#define PIN_VIVO_D5 PINPOS('B', 10)
34
+
#define PIN_VIVO_D7 PINPOS('B', 11)
35
+
#define PIN_VIVO_D9 PINPOS('B', 12)
36
+
#define PIN_USB_ID PINPOS('B', 13)
37
+
#define PIN_ETH_RXM PINPOS('B', 15)
38
+
#define PIN_MIPI_TXP2 PINPOS('C', 1)
39
+
#define PIN_MIPI_TXM2 PINPOS('C', 2)
40
+
#define PIN_CAM_PD0 PINPOS('C', 3)
41
+
#define PIN_CAM_MCLK0 PINPOS('C', 4)
42
+
#define PIN_MIPIRX1P PINPOS('C', 5)
43
+
#define PIN_MIPIRX2P PINPOS('C', 6)
44
+
#define PIN_MIPIRX3N PINPOS('C', 7)
45
+
#define PIN_MIPIRX5P PINPOS('C', 8)
46
+
#define PIN_VIVO_CLK PINPOS('C', 9)
47
+
#define PIN_VIVO_D6 PINPOS('C', 10)
48
+
#define PIN_VIVO_D8 PINPOS('C', 11)
49
+
#define PIN_USB_VBUS_EN PINPOS('C', 12)
50
+
#define PIN_ETH_RXP PINPOS('C', 14)
51
+
#define PIN_GPIO_RTX PINPOS('C', 15)
52
+
#define PIN_MIPI_TXP1 PINPOS('D', 1)
53
+
#define PIN_MIPI_TXM1 PINPOS('D', 2)
54
+
#define PIN_CAM_MCLK1 PINPOS('D', 3)
55
+
#define PIN_IIC3_SCL PINPOS('D', 4)
56
+
#define PIN_VIVO_D4 PINPOS('D', 10)
57
+
#define PIN_ETH_TXM PINPOS('D', 14)
58
+
#define PIN_ETH_TXP PINPOS('D', 15)
59
+
#define PIN_MIPI_TXP0 PINPOS('E', 1)
60
+
#define PIN_MIPI_TXM0 PINPOS('E', 2)
61
+
#define PIN_CAM_PD1 PINPOS('E', 4)
62
+
#define PIN_CAM_RST0 PINPOS('E', 5)
63
+
#define PIN_VIVO_D0 PINPOS('E', 10)
64
+
#define PIN_ADC1 PINPOS('E', 13)
65
+
#define PIN_ADC2 PINPOS('E', 14)
66
+
#define PIN_ADC3 PINPOS('E', 15)
67
+
#define PIN_AUD_AOUTL PINPOS('F', 2)
68
+
#define PIN_IIC3_SDA PINPOS('F', 4)
69
+
#define PIN_SD1_D2 PINPOS('F', 14)
70
+
#define PIN_AUD_AOUTR PINPOS('G', 2)
71
+
#define PIN_SD1_D3 PINPOS('G', 13)
72
+
#define PIN_SD1_CLK PINPOS('G', 14)
73
+
#define PIN_SD1_CMD PINPOS('G', 15)
74
+
#define PIN_AUD_AINL_MIC PINPOS('H', 1)
75
+
#define PIN_RSTN PINPOS('H', 12)
76
+
#define PIN_PWM0_BUCK PINPOS('H', 13)
77
+
#define PIN_SD1_D1 PINPOS('H', 14)
78
+
#define PIN_SD1_D0 PINPOS('H', 15)
79
+
#define PIN_AUD_AINR_MIC PINPOS('J', 1)
80
+
#define PIN_IIC2_SCL PINPOS('J', 13)
81
+
#define PIN_IIC2_SDA PINPOS('J', 14)
82
+
#define PIN_SD0_CD PINPOS('K', 2)
83
+
#define PIN_SD0_D1 PINPOS('K', 3)
84
+
#define PIN_UART2_RX PINPOS('K', 13)
85
+
#define PIN_UART2_CTS PINPOS('K', 14)
86
+
#define PIN_UART2_TX PINPOS('K', 15)
87
+
#define PIN_SD0_CLK PINPOS('L', 1)
88
+
#define PIN_SD0_D0 PINPOS('L', 2)
89
+
#define PIN_SD0_CMD PINPOS('L', 3)
90
+
#define PIN_CLK32K PINPOS('L', 14)
91
+
#define PIN_UART2_RTS PINPOS('L', 15)
92
+
#define PIN_SD0_D3 PINPOS('M', 1)
93
+
#define PIN_SD0_D2 PINPOS('M', 2)
94
+
#define PIN_UART0_RX PINPOS('M', 4)
95
+
#define PIN_UART0_TX PINPOS('M', 5)
96
+
#define PIN_JTAG_CPU_TRST PINPOS('M', 6)
97
+
#define PIN_PWR_ON PINPOS('M', 11)
98
+
#define PIN_PWR_GPIO2 PINPOS('M', 12)
99
+
#define PIN_PWR_GPIO0 PINPOS('M', 13)
100
+
#define PIN_CLK25M PINPOS('M', 14)
101
+
#define PIN_SD0_PWR_EN PINPOS('N', 1)
102
+
#define PIN_SPK_EN PINPOS('N', 3)
103
+
#define PIN_JTAG_CPU_TCK PINPOS('N', 4)
104
+
#define PIN_JTAG_CPU_TMS PINPOS('N', 6)
105
+
#define PIN_PWR_WAKEUP1 PINPOS('N', 11)
106
+
#define PIN_PWR_WAKEUP0 PINPOS('N', 12)
107
+
#define PIN_PWR_GPIO1 PINPOS('N', 13)
108
+
#define PIN_EMMC_DAT3 PINPOS('P', 1)
109
+
#define PIN_EMMC_DAT0 PINPOS('P', 2)
110
+
#define PIN_EMMC_DAT2 PINPOS('P', 3)
111
+
#define PIN_EMMC_RSTN PINPOS('P', 4)
112
+
#define PIN_AUX0 PINPOS('P', 5)
113
+
#define PIN_IIC0_SDA PINPOS('P', 6)
114
+
#define PIN_PWR_SEQ3 PINPOS('P', 10)
115
+
#define PIN_PWR_VBAT_DET PINPOS('P', 11)
116
+
#define PIN_PWR_SEQ1 PINPOS('P', 12)
117
+
#define PIN_PWR_BUTTON1 PINPOS('P', 13)
118
+
#define PIN_EMMC_DAT1 PINPOS('R', 2)
119
+
#define PIN_EMMC_CMD PINPOS('R', 3)
120
+
#define PIN_EMMC_CLK PINPOS('R', 4)
121
+
#define PIN_IIC0_SCL PINPOS('R', 6)
122
+
#define PIN_GPIO_ZQ PINPOS('R', 10)
123
+
#define PIN_PWR_RSTN PINPOS('R', 11)
124
+
#define PIN_PWR_SEQ2 PINPOS('R', 12)
125
+
#define PIN_XTAL_XIN PINPOS('R', 13)
126
+
127
+
#endif /* _DT_BINDINGS_PINCTRL_SG2000_H */
+79
include/dt-bindings/pinctrl/pinctrl-sg2002.h
+79
include/dt-bindings/pinctrl/pinctrl-sg2002.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*
5
+
* This file is generated from vendor pinout definition.
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_PINCTRL_SG2002_H
9
+
#define _DT_BINDINGS_PINCTRL_SG2002_H
10
+
11
+
#include <dt-bindings/pinctrl/pinctrl-cv18xx.h>
12
+
13
+
#define PIN_AUD_AINL_MIC 2
14
+
#define PIN_AUD_AOUTR 4
15
+
#define PIN_SD0_CLK 6
16
+
#define PIN_SD0_CMD 7
17
+
#define PIN_SD0_D0 8
18
+
#define PIN_SD0_D1 10
19
+
#define PIN_SD0_D2 11
20
+
#define PIN_SD0_D3 12
21
+
#define PIN_SD0_CD 14
22
+
#define PIN_SD0_PWR_EN 15
23
+
#define PIN_SPK_EN 17
24
+
#define PIN_UART0_TX 18
25
+
#define PIN_UART0_RX 19
26
+
#define PIN_EMMC_DAT2 20
27
+
#define PIN_EMMC_CLK 21
28
+
#define PIN_EMMC_DAT0 22
29
+
#define PIN_EMMC_DAT3 23
30
+
#define PIN_EMMC_CMD 24
31
+
#define PIN_EMMC_DAT1 25
32
+
#define PIN_JTAG_CPU_TMS 26
33
+
#define PIN_JTAG_CPU_TCK 27
34
+
#define PIN_IIC0_SCL 28
35
+
#define PIN_IIC0_SDA 29
36
+
#define PIN_AUX0 30
37
+
#define PIN_GPIO_ZQ 35
38
+
#define PIN_PWR_VBAT_DET 38
39
+
#define PIN_PWR_RSTN 39
40
+
#define PIN_PWR_SEQ1 40
41
+
#define PIN_PWR_SEQ2 41
42
+
#define PIN_PWR_WAKEUP0 43
43
+
#define PIN_PWR_BUTTON1 44
44
+
#define PIN_XTAL_XIN 45
45
+
#define PIN_PWR_GPIO0 47
46
+
#define PIN_PWR_GPIO1 48
47
+
#define PIN_PWR_GPIO2 49
48
+
#define PIN_SD1_D3 51
49
+
#define PIN_SD1_D2 52
50
+
#define PIN_SD1_D1 53
51
+
#define PIN_SD1_D0 54
52
+
#define PIN_SD1_CMD 55
53
+
#define PIN_SD1_CLK 56
54
+
#define PIN_PWM0_BUCK 58
55
+
#define PIN_ADC1 59
56
+
#define PIN_USB_VBUS_DET 60
57
+
#define PIN_ETH_TXP 62
58
+
#define PIN_ETH_TXM 63
59
+
#define PIN_ETH_RXP 64
60
+
#define PIN_ETH_RXM 65
61
+
#define PIN_GPIO_RTX 67
62
+
#define PIN_MIPIRX4N 72
63
+
#define PIN_MIPIRX4P 73
64
+
#define PIN_MIPIRX3N 74
65
+
#define PIN_MIPIRX3P 75
66
+
#define PIN_MIPIRX2N 76
67
+
#define PIN_MIPIRX2P 77
68
+
#define PIN_MIPIRX1N 78
69
+
#define PIN_MIPIRX1P 79
70
+
#define PIN_MIPIRX0N 80
71
+
#define PIN_MIPIRX0P 81
72
+
#define PIN_MIPI_TXM2 83
73
+
#define PIN_MIPI_TXP2 84
74
+
#define PIN_MIPI_TXM1 85
75
+
#define PIN_MIPI_TXP1 86
76
+
#define PIN_MIPI_TXM0 87
77
+
#define PIN_MIPI_TXP0 88
78
+
79
+
#endif /* _DT_BINDINGS_PINCTRL_SG2002_H */
+3
include/linux/pinctrl/pinconf-generic.h
+3
include/linux/pinctrl/pinconf-generic.h
···
81
81
* @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
82
82
* If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
83
83
* schmitt-trigger mode is disabled.
84
+
* @PIN_CONFIG_INPUT_SCHMITT_UV: this will configure an input pin to run in
85
+
* schmitt-trigger mode. The argument is in uV.
84
86
* @PIN_CONFIG_MODE_LOW_POWER: this will configure the pin for low power
85
87
* operation, if several modes of operation are supported these can be
86
88
* passed in the argument on a custom form, else just use argument 1
···
134
132
PIN_CONFIG_INPUT_ENABLE,
135
133
PIN_CONFIG_INPUT_SCHMITT,
136
134
PIN_CONFIG_INPUT_SCHMITT_ENABLE,
135
+
PIN_CONFIG_INPUT_SCHMITT_UV,
137
136
PIN_CONFIG_MODE_LOW_POWER,
138
137
PIN_CONFIG_MODE_PWM,
139
138
PIN_CONFIG_OUTPUT,