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drm/xe: Fix platform order

Platform order in enum xe_platform started to be used by some parts of
the code, like the GuC/HuC firmware loading logic. The order itself is
not very important, but it's better to follow a convention: as was
documented in the comment above the enum, reorder the platforms by
graphics version. While at it, remove the gen terminology.

v2:
- Use "graphics version" instead of chronological order (Matt Roper)
- Also change pciidlist to follow the same order
- Remove "gen" from comments around enum xe_platform

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230331230902.1603294-1-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

authored by

Lucas De Marchi and committed by
Rodrigo Vivi 96578d10 c33a7219

+11 -9
+2 -2
drivers/gpu/drm/xe/xe_pci.c
··· 281 281 */ 282 282 static const struct pci_device_id pciidlist[] = { 283 283 XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc), 284 + XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 285 + XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 284 286 XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc), 285 287 XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc), 286 288 XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc), 287 - XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc), 288 - XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc), 289 289 XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), 290 290 { } 291 291 };
+7 -5
drivers/gpu/drm/xe/xe_platform_types.h
··· 6 6 #ifndef _XE_PLATFORM_INFO_TYPES_H_ 7 7 #define _XE_PLATFORM_INFO_TYPES_H_ 8 8 9 - /* Keep in gen based order, and chronological order within a gen */ 9 + /* 10 + * Keep this in graphics version based order and chronological order within a 11 + * version 12 + */ 10 13 enum xe_platform { 11 14 XE_PLATFORM_UNINITIALIZED = 0, 12 - /* gen12 */ 13 15 XE_TIGERLAKE, 14 16 XE_ROCKETLAKE, 17 + XE_ALDERLAKE_S, 18 + XE_ALDERLAKE_P, 15 19 XE_DG1, 16 20 XE_DG2, 17 21 XE_PVC, 18 - XE_ALDERLAKE_S, 19 - XE_ALDERLAKE_P, 20 22 XE_METEORLAKE, 21 23 }; 22 24 23 25 enum xe_subplatform { 24 26 XE_SUBPLATFORM_UNINITIALIZED = 0, 25 27 XE_SUBPLATFORM_NONE, 28 + XE_SUBPLATFORM_ADLP_RPLU, 26 29 XE_SUBPLATFORM_DG2_G10, 27 30 XE_SUBPLATFORM_DG2_G11, 28 31 XE_SUBPLATFORM_DG2_G12, 29 - XE_SUBPLATFORM_ADLP_RPLU, 30 32 }; 31 33 32 34 #endif
+2 -2
drivers/gpu/drm/xe/xe_uc_fw.c
··· 43 43 */ 44 44 #define XE_GUC_FIRMWARE_DEFS(fw_def, guc_def) \ 45 45 fw_def(METEORLAKE, guc_def(mtl, 70, 5, 2)) \ 46 - fw_def(ALDERLAKE_P, guc_def(adlp, 70, 5, 2)) \ 47 - fw_def(ALDERLAKE_S, guc_def(tgl, 70, 5, 2)) \ 48 46 fw_def(PVC, guc_def(pvc, 70, 5, 2)) \ 49 47 fw_def(DG2, guc_def(dg2, 70, 5, 2)) \ 50 48 fw_def(DG1, guc_def(dg1, 70, 5, 2)) \ 49 + fw_def(ALDERLAKE_P, guc_def(adlp, 70, 5, 2)) \ 50 + fw_def(ALDERLAKE_S, guc_def(tgl, 70, 5, 2)) \ 51 51 fw_def(TIGERLAKE, guc_def(tgl, 70, 5, 2)) 52 52 53 53 #define XE_HUC_FIRMWARE_DEFS(fw_def, huc_def, huc_ver) \