Merge tag 'drm-fixes-2025-09-12' of https://gitlab.freedesktop.org/drm/kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull drm fixes from Dave Airlie:
"Weekly pull fixes for drm, mostly amdgpu and xe, with a revert for
nouveau and some maintainers updates, and misc bits, doesn't seem too
out of the normal.

MAINTAINERS:
- add rust tree to MAINTAINERS
- fix X entries for nova/nouveau

nova:
- depend on 64-bit

i915:
- Fix size for for_each_set_bit() in abox iteration

xe:
- Don't touch survivability_mode on fini
- Fixes around eviction and suspend
- Extend Wa_13011645652 to PTL-H, WCL

amdgpu:
- PSP 11.x fix
- DPCD quirk handing fix
- DCN 3.5 PG fix
- Audio suspend fix
- OEM i2c clean up fix
- Module unload memory leak fix
- DC delay fix
- ISP firmware fix
- VCN fixes

amdkfd:
- P2P topology fix
- APU mem limit calculation fix

mediatek:
- fix potential OF node use-after-free

panthor:
- out-of-bounds check

nouveau:
- revert waitqueue removal for sched teardown

* tag 'drm-fixes-2025-09-12' of https://gitlab.freedesktop.org/drm/kernel: (25 commits)
MAINTAINERS: drm-misc: fix X: entries for nova/nouveau
drm/mediatek: clean up driver data initialisation
drm/mediatek: fix potential OF node use-after-free
drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time
drm/amdgpu/vcn4: Fix IB parsing with multiple engine info packages
drm/amd/amdgpu: Declare isp firmware binary file
drm/amd/display: use udelay rather than fsleep
drm/amdgpu: fix a memory leak in fence cleanup when unloading
drm/xe: Extend Wa_13011645652 to PTL-H, WCL
drm/xe: Block exec and rebind worker while evicting for suspend / hibernate
drm/xe: Allow the pm notifier to continue on failure
drm/xe: Attempt to bring bos back to VRAM after eviction
drm/xe/configfs: Don't touch survivability_mode on fini
amd/amdkfd: correct mem limit calculation for small APUs
drm/amdkfd: fix p2p links bug in topology
drm/amd/display: remove oem i2c adapter on finish
drm/amd/display: Drop dm_prepare_suspend() and dm_complete()
drm/amd/display: Correct sequences and delays for DCN35 PG & RCG
drm/amd/display: Disable DPCD Probe Quirk
drm/i915/power: fix size for for_each_set_bit() in abox iteration
...

Linus Torvalds 9 months ago 965c995c cb780b79

+364 -347

40 changed files

expand all

MAINTAINERS

drivers

gpu

drm

amd

amdgpu

amdgpu_amdkfd_gpuvm.c

amdgpu_ring.c

isp_v4_1_1.c

psp_v11_0.c

vcn_v3_0.c

vcn_v4_0.c

amdkfd

kfd_topology.c

display

amdgpu_dm

amdgpu_dm.c

amdgpu_dm_mst_types.c

dc.h

dccg

dcn35

dcn35_dccg.c

hwss

dcn20

dcn20_hwseq.c

dcn35

dcn35_hwseq.c

dcn35_init.c

dcn351

dcn351_init.c

inc

pg_cntl.h

dcn35

dcn35_pg_cntl.c

i915

display

intel_display_power.c

mediatek

mtk_drm_drv.c

nouveau

nouveau_fence.c

nouveau_fence.h

nouveau_sched.c

nouveau_sched.h

nouveau_uvmm.c

panthor

panthor_drv.c

tests

xe_bo.c

xe_dma_buf.c

xe_bo.c

xe_bo.h

xe_device_types.h

xe_dma_buf.c

xe_exec.c

xe_pm.c

xe_survivability_mode.c

xe_vm.c

xe_vm.h

xe_vm_types.h

xe_wa_oob.rules

nova-core

Kconfig

+11 -2

MAINTAINERS

··· 8078 8078 F: Documentation/gpu/ 8079 8079 F: drivers/gpu/drm/ 8080 8080 F: drivers/gpu/vga/ 8081 - F: rust/kernel/drm/ 8082 8081 F: include/drm/drm 8083 8082 F: include/linux/vga* 8084 8083 F: include/uapi/drm/ ··· 8089 8090 X: drivers/gpu/drm/kmb/ 8090 8091 X: drivers/gpu/drm/mediatek/ 8091 8092 X: drivers/gpu/drm/msm/ 8092 - X: drivers/gpu/drm/nouveau/ 8093 + X: drivers/gpu/drm/nova/ 8093 8094 X: drivers/gpu/drm/radeon/ 8094 8095 X: drivers/gpu/drm/tegra/ 8095 8096 X: drivers/gpu/drm/xe/ 8097 + 8098 + DRM DRIVERS AND COMMON INFRASTRUCTURE [RUST] 8099 + M: Danilo Krummrich <dakr@kernel.org> 8100 + M: Alice Ryhl <aliceryhl@google.com> 8101 + S: Supported 8102 + W: https://drm.pages.freedesktop.org/maintainer-tools/drm-rust.html 8103 + T: git https://gitlab.freedesktop.org/drm/rust/kernel.git 8104 + F: drivers/gpu/drm/nova/ 8105 + F: drivers/gpu/nova-core/ 8106 + F: rust/kernel/drm/ 8096 8107 8097 8108 DRM DRIVERS FOR ALLWINNER A10 8098 8109 M: Maxime Ripard <mripard@kernel.org>

+32 -12

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

··· 213 213 spin_lock(&kfd_mem_limit.mem_limit_lock); 214 214 215 215 if (kfd_mem_limit.system_mem_used + system_mem_needed > 216 - kfd_mem_limit.max_system_mem_limit) 216 + kfd_mem_limit.max_system_mem_limit) { 217 217 pr_debug("Set no_system_mem_limit=1 if using shared memory\n"); 218 + if (!no_system_mem_limit) { 219 + ret = -ENOMEM; 220 + goto release; 221 + } 222 + } 218 223 219 - if ((kfd_mem_limit.system_mem_used + system_mem_needed > 220 - kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) || 221 - (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 222 - kfd_mem_limit.max_ttm_mem_limit) || 223 - (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed > 224 - vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) { 224 + if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 225 + kfd_mem_limit.max_ttm_mem_limit) { 225 226 ret = -ENOMEM; 226 227 goto release; 228 + } 229 + 230 + /*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with 231 + * carve out < gtt. In that case, VRAM allocation will go to gtt domain, skip 232 + * VRAM check since ttm_mem_limit check already cover this allocation 233 + */ 234 + 235 + if (adev && xcp_id >= 0 && (!adev->apu_prefer_gtt || adev->gmc.is_app_apu)) { 236 + uint64_t vram_available = 237 + vram_size - reserved_for_pt - reserved_for_ras - 238 + atomic64_read(&adev->vram_pin_size); 239 + if (adev->kfd.vram_used[xcp_id] + vram_needed > vram_available) { 240 + ret = -ENOMEM; 241 + goto release; 242 + } 227 243 } 228 244 229 245 /* Update memory accounting by decreasing available system ··· 1642 1626 uint64_t vram_available, system_mem_available, ttm_mem_available; 1643 1627 1644 1628 spin_lock(&kfd_mem_limit.mem_limit_lock); 1645 - vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1646 - - adev->kfd.vram_used_aligned[xcp_id] 1647 - - atomic64_read(&adev->vram_pin_size) 1648 - - reserved_for_pt 1649 - - reserved_for_ras; 1629 + if (adev->apu_prefer_gtt && !adev->gmc.is_app_apu) 1630 + vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1631 + - adev->kfd.vram_used_aligned[xcp_id]; 1632 + else 1633 + vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1634 + - adev->kfd.vram_used_aligned[xcp_id] 1635 + - atomic64_read(&adev->vram_pin_size) 1636 + - reserved_for_pt 1637 + - reserved_for_ras; 1650 1638 1651 1639 if (adev->apu_prefer_gtt) { 1652 1640 system_mem_available = no_system_mem_limit ?

-2

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

··· 421 421 dma_fence_put(ring->vmid_wait); 422 422 ring->vmid_wait = NULL; 423 423 ring->me = 0; 424 - 425 - ring->adev->rings[ring->idx] = NULL; 426 424 } 427 425 428 426 /**

drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c

··· 29 29 #include "amdgpu.h" 30 30 #include "isp_v4_1_1.h" 31 31 32 + MODULE_FIRMWARE("amdgpu/isp_4_1_1.bin"); 33 + 32 34 #define ISP_PERFORMANCE_STATE_LOW 0 33 35 #define ISP_PERFORMANCE_STATE_HIGH 1 34 36

+4 -15

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

··· 149 149 int ret; 150 150 int retry_loop; 151 151 152 - for (retry_loop = 0; retry_loop < 10; retry_loop++) { 152 + for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 153 /* Wait for bootloader to signify that is 154 154 ready having bit 31 of C2PMSG_35 set to 1 */ 155 155 ret = psp_wait_for( 156 156 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 157 - 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 157 + 0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE); 158 158 159 159 if (ret == 0) 160 160 return 0; ··· 396 396 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 397 397 398 398 msleep(500); 399 - 400 - offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 401 - 402 - ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 403 - 0); 404 - 405 - if (ret) { 406 - DRM_INFO("psp mode 1 reset failed!\n"); 407 - return -EINVAL; 408 - } 409 - 410 - DRM_INFO("psp mode1 reset succeed \n"); 411 399 412 400 return 0; 413 401 } ··· 653 665 .ring_get_wptr = psp_v11_0_ring_get_wptr, 654 666 .ring_set_wptr = psp_v11_0_ring_set_wptr, 655 667 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 656 - .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 668 + .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw, 669 + .wait_for_bootloader = psp_v11_0_wait_for_bootloader 657 670 }; 658 671 659 672 void psp_v11_0_set_psp_funcs(struct psp_context *psp)

+8 -4

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

··· 1888 1888 struct amdgpu_job *job) 1889 1889 { 1890 1890 struct drm_gpu_scheduler **scheds; 1891 - 1892 - /* The create msg must be in the first IB submitted */ 1893 - if (atomic_read(&job->base.entity->fence_seq)) 1894 - return -EINVAL; 1891 + struct dma_fence *fence; 1895 1892 1896 1893 /* if VCN0 is harvested, we can't support AV1 */ 1897 1894 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1898 1895 return -EINVAL; 1896 + 1897 + /* wait for all jobs to finish before switching to instance 0 */ 1898 + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull); 1899 + if (fence) { 1900 + dma_fence_wait(fence, false); 1901 + dma_fence_put(fence); 1902 + } 1899 1903 1900 1904 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1901 1905 [AMDGPU_RING_PRIO_DEFAULT].sched;

+27 -33

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

··· 1808 1808 struct amdgpu_job *job) 1809 1809 { 1810 1810 struct drm_gpu_scheduler **scheds; 1811 - 1812 - /* The create msg must be in the first IB submitted */ 1813 - if (atomic_read(&job->base.entity->fence_seq)) 1814 - return -EINVAL; 1811 + struct dma_fence *fence; 1815 1812 1816 1813 /* if VCN0 is harvested, we can't support AV1 */ 1817 1814 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1818 1815 return -EINVAL; 1816 + 1817 + /* wait for all jobs to finish before switching to instance 0 */ 1818 + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull); 1819 + if (fence) { 1820 + dma_fence_wait(fence, false); 1821 + dma_fence_put(fence); 1822 + } 1819 1823 1820 1824 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1821 1825 [AMDGPU_RING_PRIO_0].sched; ··· 1911 1907 1912 1908 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1913 1909 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1914 - 1915 1910 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1916 - #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1917 - 1918 1911 #define RENCODE_ENCODE_STANDARD_AV1 2 1919 1912 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1920 - #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1921 1913 1922 - /* return the offset in ib if id is found, -1 otherwise 1923 - * to speed up the searching we only search upto max_offset 1924 - */ 1925 - static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1914 + /* return the offset in ib if id is found, -1 otherwise */ 1915 + static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int start) 1926 1916 { 1927 1917 int i; 1928 1918 1929 - for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1919 + for (i = start; i < ib->length_dw && ib->ptr[i] >= 8; i += ib->ptr[i] / 4) { 1930 1920 if (ib->ptr[i + 1] == id) 1931 1921 return i; 1932 1922 } ··· 1935 1937 struct amdgpu_vcn_decode_buffer *decode_buffer; 1936 1938 uint64_t addr; 1937 1939 uint32_t val; 1938 - int idx; 1940 + int idx = 0, sidx; 1939 1941 1940 1942 /* The first instance can decode anything */ 1941 1943 if (!ring->me) 1942 1944 return 0; 1943 1945 1944 - /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1945 - idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1946 - RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1947 - if (idx < 0) /* engine info is missing */ 1948 - return 0; 1946 + while ((idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, idx)) >= 0) { 1947 + val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1948 + if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1949 + decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1949 1950 1950 - val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1951 - if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1952 - decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1951 + if (!(decode_buffer->valid_buf_flag & 0x1)) 1952 + return 0; 1953 1953 1954 - if (!(decode_buffer->valid_buf_flag & 0x1)) 1955 - return 0; 1956 - 1957 - addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1958 - decode_buffer->msg_buffer_address_lo; 1959 - return vcn_v4_0_dec_msg(p, job, addr); 1960 - } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1961 - idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1962 - RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1963 - if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1964 - return vcn_v4_0_limit_sched(p, job); 1954 + addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1955 + decode_buffer->msg_buffer_address_lo; 1956 + return vcn_v4_0_dec_msg(p, job, addr); 1957 + } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1958 + sidx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, idx); 1959 + if (sidx >= 0 && ib->ptr[sidx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1960 + return vcn_v4_0_limit_sched(p, job); 1961 + } 1962 + idx += ib->ptr[idx] / 4; 1965 1963 } 1966 1964 return 0; 1967 1965 }

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

··· 1587 1587 break; 1588 1588 if (!dev->gpu || !dev->gpu->adev || 1589 1589 (dev->gpu->kfd->hive_id && 1590 - dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id)) 1590 + dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id && 1591 + amdgpu_xgmi_get_is_sharing_enabled(dev->gpu->adev, new_dev->gpu->adev))) 1591 1592 goto next; 1592 1593 1593 1594 /* check if node(s) is/are peer accessible in one direction or bi-direction */

+12 -22

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 2913 2913 return 0; 2914 2914 } 2915 2915 2916 + static void dm_oem_i2c_hw_fini(struct amdgpu_device *adev) 2917 + { 2918 + struct amdgpu_display_manager *dm = &adev->dm; 2919 + 2920 + if (dm->oem_i2c) { 2921 + i2c_del_adapter(&dm->oem_i2c->base); 2922 + kfree(dm->oem_i2c); 2923 + dm->oem_i2c = NULL; 2924 + } 2925 + } 2926 + 2916 2927 /** 2917 2928 * dm_hw_init() - Initialize DC device 2918 2929 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. ··· 2974 2963 { 2975 2964 struct amdgpu_device *adev = ip_block->adev; 2976 2965 2977 - kfree(adev->dm.oem_i2c); 2966 + dm_oem_i2c_hw_fini(adev); 2978 2967 2979 2968 amdgpu_dm_hpd_fini(adev); 2980 2969 ··· 3136 3125 drm_atomic_helper_resume(ddev, dm->cached_state); 3137 3126 3138 3127 dm->cached_state = NULL; 3139 - } 3140 - 3141 - static void dm_complete(struct amdgpu_ip_block *ip_block) 3142 - { 3143 - struct amdgpu_device *adev = ip_block->adev; 3144 - 3145 - dm_destroy_cached_state(adev); 3146 - } 3147 - 3148 - static int dm_prepare_suspend(struct amdgpu_ip_block *ip_block) 3149 - { 3150 - struct amdgpu_device *adev = ip_block->adev; 3151 - 3152 - if (amdgpu_in_reset(adev)) 3153 - return 0; 3154 - 3155 - WARN_ON(adev->dm.cached_state); 3156 - 3157 - return dm_cache_state(adev); 3158 3128 } 3159 3129 3160 3130 static int dm_suspend(struct amdgpu_ip_block *ip_block) ··· 3563 3571 .early_fini = amdgpu_dm_early_fini, 3564 3572 .hw_init = dm_hw_init, 3565 3573 .hw_fini = dm_hw_fini, 3566 - .prepare_suspend = dm_prepare_suspend, 3567 3574 .suspend = dm_suspend, 3568 3575 .resume = dm_resume, 3569 - .complete = dm_complete, 3570 3576 .is_idle = dm_is_idle, 3571 3577 .wait_for_idle = dm_wait_for_idle, 3572 3578 .check_soft_reset = dm_check_soft_reset,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

··· 809 809 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 810 810 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 811 811 &aconnector->base); 812 + drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false); 812 813 813 814 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 814 815 return;

drivers/gpu/drm/amd/display/dc/dc.h

··· 1145 1145 bool enable_hblank_borrow; 1146 1146 bool force_subvp_df_throttle; 1147 1147 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1148 + bool enable_pg_cntl_debug_logs; 1148 1149 }; 1149 1150 1150 1151

+39 -35

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

··· 133 133 }; 134 134 135 135 136 - static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool enable) 136 + static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) 137 137 { 138 138 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 139 139 140 - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable) 140 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg) 141 141 return; 142 142 143 143 switch (inst) { 144 144 case 0: 145 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1); 145 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 146 146 break; 147 147 case 1: 148 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1); 148 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 149 149 break; 150 150 case 2: 151 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1); 151 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 152 152 break; 153 153 case 3: 154 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1); 154 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 155 155 break; 156 156 default: 157 157 BREAK_TO_DEBUGGER(); 158 158 return; 159 159 } 160 + 161 + /* Wait for clock to ramp */ 162 + if (!allow_rcg) 163 + udelay(10); 160 164 } 161 165 162 166 static void dccg35_set_symclk32_se_rcg( ··· 389 385 } 390 386 } 391 387 392 - static void dccg35_set_dppclk_rcg(struct dccg *dccg, 393 - int inst, bool enable) 388 + static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg) 394 389 { 395 - 396 390 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 397 391 398 - 399 - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable) 392 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg) 400 393 return; 401 394 402 395 switch (inst) { 403 396 case 0: 404 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1); 397 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 405 398 break; 406 399 case 1: 407 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1); 400 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 408 401 break; 409 402 case 2: 410 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1); 403 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 411 404 break; 412 405 case 3: 413 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1); 406 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 414 407 break; 415 408 default: 416 409 BREAK_TO_DEBUGGER(); 417 410 break; 418 411 } 419 - //DC_LOG_DEBUG("%s: inst(%d) DPPCLK rcg_disable: %d\n", __func__, inst, enable ? 0 : 1); 420 412 413 + /* Wait for clock to ramp */ 414 + if (!allow_rcg) 415 + udelay(10); 421 416 } 422 417 423 418 static void dccg35_set_dpstreamclk_rcg( ··· 1180 1177 } 1181 1178 1182 1179 static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg, 1183 - uint32_t dpp_inst, uint32_t enable) 1180 + uint32_t dpp_inst, uint32_t disallow_rcg) 1184 1181 { 1185 1182 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1186 1183 1187 - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) 1184 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg) 1188 1185 return; 1189 1186 1190 1187 1191 1188 switch (dpp_inst) { 1192 1189 case 0: 1193 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable); 1190 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, disallow_rcg); 1194 1191 break; 1195 1192 case 1: 1196 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable); 1193 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, disallow_rcg); 1197 1194 break; 1198 1195 case 2: 1199 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable); 1196 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, disallow_rcg); 1200 1197 break; 1201 1198 case 3: 1202 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable); 1199 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, disallow_rcg); 1203 1200 break; 1204 1201 default: 1205 1202 break; 1206 1203 } 1207 - //DC_LOG_DEBUG("%s: dpp_inst(%d) rcg: %d\n", __func__, dpp_inst, enable); 1208 1204 1205 + /* Wait for clock to ramp */ 1206 + if (disallow_rcg) 1207 + udelay(10); 1209 1208 } 1210 1209 1211 1210 static void dccg35_get_pixel_rate_div( ··· 1787 1782 //Disable DTO 1788 1783 switch (inst) { 1789 1784 case 0: 1790 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1791 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1); 1785 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1); 1792 1786 1793 1787 REG_UPDATE_2(DSCCLK0_DTO_PARAM, 1794 1788 DSCCLK0_DTO_PHASE, 0, ··· 1795 1791 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1); 1796 1792 break; 1797 1793 case 1: 1798 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1799 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1); 1794 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1); 1800 1795 1801 1796 REG_UPDATE_2(DSCCLK1_DTO_PARAM, 1802 1797 DSCCLK1_DTO_PHASE, 0, ··· 1803 1800 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1); 1804 1801 break; 1805 1802 case 2: 1806 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1807 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1); 1803 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1); 1808 1804 1809 1805 REG_UPDATE_2(DSCCLK2_DTO_PARAM, 1810 1806 DSCCLK2_DTO_PHASE, 0, ··· 1811 1809 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1); 1812 1810 break; 1813 1811 case 3: 1814 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1815 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1); 1812 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1); 1816 1813 1817 1814 REG_UPDATE_2(DSCCLK3_DTO_PARAM, 1818 1815 DSCCLK3_DTO_PHASE, 0, ··· 1822 1821 BREAK_TO_DEBUGGER(); 1823 1822 return; 1824 1823 } 1824 + 1825 + /* Wait for clock to ramp */ 1826 + udelay(10); 1825 1827 } 1826 1828 1827 1829 static void dccg35_disable_dscclk(struct dccg *dccg, ··· 1868 1864 default: 1869 1865 return; 1870 1866 } 1867 + 1868 + /* Wait for clock ramp */ 1869 + udelay(10); 1871 1870 } 1872 1871 1873 1872 static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) ··· 2356 2349 2357 2350 void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating) 2358 2351 { 2359 - 2360 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) { 2361 - dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); 2362 - } 2352 + dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); 2363 2353 } 2364 2354 2365 2355 static const struct dccg_funcs dccg35_funcs_new = {

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

··· 955 955 return DC_ERROR_UNEXPECTED; 956 956 } 957 957 958 - fsleep(stream->timing.v_total * (stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz)); 958 + udelay(stream->timing.v_total * (stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz)); 959 959 960 960 params.vertical_total_min = stream->adjust.v_total_min; 961 961 params.vertical_total_max = stream->adjust.v_total_max;

+20 -95

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

··· 113 113 } 114 114 #endif 115 115 116 + static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log) 117 + { 118 + if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) { 119 + if (dc->res_pool->pg_cntl->funcs->print_pg_status) 120 + dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log); 121 + } 122 + } 123 + 116 124 void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable) 117 125 { 118 126 REG_UPDATE_3(DMU_CLK_CNTL, ··· 144 136 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 145 137 uint32_t user_level = MAX_BACKLIGHT_LEVEL; 146 138 int i; 139 + 140 + print_pg_status(dc, __func__, ": start"); 147 141 148 142 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 149 143 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); ··· 210 200 211 201 /* we want to turn off all dp displays before doing detection */ 212 202 dc->link_srv->blank_all_dp_displays(dc); 213 - /* 214 - if (hws->funcs.enable_power_gating_plane) 215 - hws->funcs.enable_power_gating_plane(dc->hwseq, true); 216 - */ 203 + 217 204 if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init) 218 205 res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub); 219 206 /* If taking control over from VBIOS, we may want to optimize our first ··· 243 236 } 244 237 245 238 hws->funcs.init_pipes(dc, dc->current_state); 239 + print_pg_status(dc, __func__, ": after init_pipes"); 240 + 246 241 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control && 247 242 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter) 248 243 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, ··· 321 312 if (dc->res_pool->pg_cntl->funcs->init_pg_status) 322 313 dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl); 323 314 } 315 + print_pg_status(dc, __func__, ": after init_pg_status"); 324 316 } 325 317 326 318 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) ··· 508 498 hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating( 509 499 hws->ctx->dc->res_pool->dccg, phy_inst, clock_on); 510 500 } 511 - } 512 - 513 - void dcn35_dsc_pg_control( 514 - struct dce_hwseq *hws, 515 - unsigned int dsc_inst, 516 - bool power_on) 517 - { 518 - uint32_t power_gate = power_on ? 0 : 1; 519 - uint32_t pwr_status = power_on ? 0 : 2; 520 - uint32_t org_ip_request_cntl = 0; 521 - 522 - if (hws->ctx->dc->debug.disable_dsc_power_gate) 523 - return; 524 - if (hws->ctx->dc->debug.ignore_pg) 525 - return; 526 - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 527 - if (org_ip_request_cntl == 0) 528 - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 529 - 530 - switch (dsc_inst) { 531 - case 0: /* DSC0 */ 532 - REG_UPDATE(DOMAIN16_PG_CONFIG, 533 - DOMAIN_POWER_GATE, power_gate); 534 - 535 - REG_WAIT(DOMAIN16_PG_STATUS, 536 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 537 - 1, 1000); 538 - break; 539 - case 1: /* DSC1 */ 540 - REG_UPDATE(DOMAIN17_PG_CONFIG, 541 - DOMAIN_POWER_GATE, power_gate); 542 - 543 - REG_WAIT(DOMAIN17_PG_STATUS, 544 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 545 - 1, 1000); 546 - break; 547 - case 2: /* DSC2 */ 548 - REG_UPDATE(DOMAIN18_PG_CONFIG, 549 - DOMAIN_POWER_GATE, power_gate); 550 - 551 - REG_WAIT(DOMAIN18_PG_STATUS, 552 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 553 - 1, 1000); 554 - break; 555 - case 3: /* DSC3 */ 556 - REG_UPDATE(DOMAIN19_PG_CONFIG, 557 - DOMAIN_POWER_GATE, power_gate); 558 - 559 - REG_WAIT(DOMAIN19_PG_STATUS, 560 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 561 - 1, 1000); 562 - break; 563 - default: 564 - BREAK_TO_DEBUGGER(); 565 - break; 566 - } 567 - 568 - if (org_ip_request_cntl == 0) 569 - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 570 - } 571 - 572 - void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) 573 - { 574 - bool force_on = true; /* disable power gating */ 575 - uint32_t org_ip_request_cntl = 0; 576 - 577 - if (hws->ctx->dc->debug.disable_hubp_power_gate) 578 - return; 579 - if (hws->ctx->dc->debug.ignore_pg) 580 - return; 581 - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 582 - if (org_ip_request_cntl == 0) 583 - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 584 - /* DCHUBP0/1/2/3/4/5 */ 585 - REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 586 - REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 587 - /* DPP0/1/2/3/4/5 */ 588 - REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 589 - REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 590 - 591 - force_on = true; /* disable power gating */ 592 - if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 593 - force_on = false; 594 - 595 - /* DCS0/1/2/3/4 */ 596 - REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 597 - REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 598 - REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 599 - REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 600 - 601 - 602 501 } 603 502 604 503 /* In headless boot cases, DIG may be turned ··· 1372 1453 } 1373 1454 1374 1455 dcn20_prepare_bandwidth(dc, context); 1456 + 1457 + print_pg_status(dc, __func__, ": after rcg and power up"); 1375 1458 } 1376 1459 1377 1460 void dcn35_optimize_bandwidth( ··· 1381 1460 struct dc_state *context) 1382 1461 { 1383 1462 struct pg_block_update pg_update_state; 1463 + 1464 + print_pg_status(dc, __func__, ": before rcg and power up"); 1384 1465 1385 1466 dcn20_optimize_bandwidth(dc, context); 1386 1467 ··· 1395 1472 if (dc->hwss.root_clock_control) 1396 1473 dc->hwss.root_clock_control(dc, &pg_update_state, false); 1397 1474 } 1475 + 1476 + print_pg_status(dc, __func__, ": after rcg and power up"); 1398 1477 } 1399 1478 1400 1479 void dcn35_set_drr(struct pipe_ctx **pipe_ctx,

-3

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

··· 115 115 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, 116 116 .update_visual_confirm_color = dcn10_update_visual_confirm_color, 117 117 .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, 118 - .update_dsc_pg = dcn32_update_dsc_pg, 119 118 .calc_blocks_to_gate = dcn35_calc_blocks_to_gate, 120 119 .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate, 121 120 .hw_block_power_up = dcn35_hw_block_power_up, ··· 149 150 .plane_atomic_disable = dcn35_plane_atomic_disable, 150 151 //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/ 151 152 //.hubp_pg_control = dcn35_hubp_pg_control, 152 - .enable_power_gating_plane = dcn35_enable_power_gating_plane, 153 153 .dpp_root_clock_control = dcn35_dpp_root_clock_control, 154 154 .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, 155 155 .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, ··· 163 165 .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, 164 166 .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, 165 167 .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy, 166 - .dsc_pg_control = dcn35_dsc_pg_control, 167 168 .dsc_pg_status = dcn32_dsc_pg_status, 168 169 .enable_plane = dcn35_enable_plane, 169 170 .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,

-3

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

··· 114 114 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, 115 115 .update_visual_confirm_color = dcn10_update_visual_confirm_color, 116 116 .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, 117 - .update_dsc_pg = dcn32_update_dsc_pg, 118 117 .calc_blocks_to_gate = dcn351_calc_blocks_to_gate, 119 118 .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate, 120 119 .hw_block_power_up = dcn351_hw_block_power_up, ··· 144 145 .plane_atomic_disable = dcn35_plane_atomic_disable, 145 146 //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/ 146 147 //.hubp_pg_control = dcn35_hubp_pg_control, 147 - .enable_power_gating_plane = dcn35_enable_power_gating_plane, 148 148 .dpp_root_clock_control = dcn35_dpp_root_clock_control, 149 149 .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, 150 150 .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, ··· 157 159 .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, 158 160 .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, 159 161 .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy, 160 - .dsc_pg_control = dcn35_dsc_pg_control, 161 162 .dsc_pg_status = dcn32_dsc_pg_status, 162 163 .enable_plane = dcn35_enable_plane, 163 164 .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h

··· 49 49 void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on); 50 50 void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on); 51 51 void (*init_pg_status)(struct pg_cntl *pg_cntl); 52 + void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log); 52 53 }; 53 54 54 55 #endif //__DC_PG_CNTL_H__

+50 -28

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

··· 79 79 uint32_t power_gate = power_on ? 0 : 1; 80 80 uint32_t pwr_status = power_on ? 0 : 2; 81 81 uint32_t org_ip_request_cntl = 0; 82 - bool block_enabled; 82 + bool block_enabled = false; 83 + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || 84 + pg_cntl->ctx->dc->debug.disable_dsc_power_gate || 85 + pg_cntl->ctx->dc->idle_optimizations_allowed; 83 86 84 - /*need to enable dscclk regardless DSC_PG*/ 85 - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) 86 - pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( 87 - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); 88 - 89 - if (pg_cntl->ctx->dc->debug.ignore_pg || 90 - pg_cntl->ctx->dc->debug.disable_dsc_power_gate || 91 - pg_cntl->ctx->dc->idle_optimizations_allowed) 87 + if (skip_pg && !power_on) 92 88 return; 93 89 94 90 block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst); ··· 107 111 108 112 REG_WAIT(DOMAIN16_PG_STATUS, 109 113 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 110 - 1, 1000); 114 + 1, 10000); 111 115 break; 112 116 case 1: /* DSC1 */ 113 117 REG_UPDATE(DOMAIN17_PG_CONFIG, ··· 115 119 116 120 REG_WAIT(DOMAIN17_PG_STATUS, 117 121 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 118 - 1, 1000); 122 + 1, 10000); 119 123 break; 120 124 case 2: /* DSC2 */ 121 125 REG_UPDATE(DOMAIN18_PG_CONFIG, ··· 123 127 124 128 REG_WAIT(DOMAIN18_PG_STATUS, 125 129 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 126 - 1, 1000); 130 + 1, 10000); 127 131 break; 128 132 case 3: /* DSC3 */ 129 133 REG_UPDATE(DOMAIN19_PG_CONFIG, ··· 131 135 132 136 REG_WAIT(DOMAIN19_PG_STATUS, 133 137 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 134 - 1, 1000); 138 + 1, 10000); 135 139 break; 136 140 default: 137 141 BREAK_TO_DEBUGGER(); ··· 140 144 141 145 if (dsc_inst < MAX_PIPES) 142 146 pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on; 143 - 144 - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { 145 - /*this is to disable dscclk*/ 146 - pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( 147 - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); 148 - } 149 147 } 150 148 151 149 static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst) ··· 179 189 uint32_t pwr_status = power_on ? 0 : 2; 180 190 uint32_t org_ip_request_cntl; 181 191 bool block_enabled; 192 + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || 193 + pg_cntl->ctx->dc->debug.disable_hubp_power_gate || 194 + pg_cntl->ctx->dc->debug.disable_dpp_power_gate || 195 + pg_cntl->ctx->dc->idle_optimizations_allowed; 182 196 183 - if (pg_cntl->ctx->dc->debug.ignore_pg || 184 - pg_cntl->ctx->dc->debug.disable_hubp_power_gate || 185 - pg_cntl->ctx->dc->debug.disable_dpp_power_gate || 186 - pg_cntl->ctx->dc->idle_optimizations_allowed) 197 + if (skip_pg && !power_on) 187 198 return; 188 199 189 200 block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); ··· 204 213 case 0: 205 214 /* DPP0 & HUBP0 */ 206 215 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 207 - REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 216 + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 208 217 break; 209 218 case 1: 210 219 /* DPP1 & HUBP1 */ 211 220 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 212 - REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 221 + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 213 222 break; 214 223 case 2: 215 224 /* DPP2 & HUBP2 */ 216 225 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 217 - REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 226 + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 218 227 break; 219 228 case 3: 220 229 /* DPP3 & HUBP3 */ 221 230 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 222 - REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 231 + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 223 232 break; 224 233 default: 225 234 BREAK_TO_DEBUGGER(); ··· 492 501 pg_cntl->pg_res_enable[PG_DWB] = block_enabled; 493 502 } 494 503 504 + static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log) 505 + { 506 + int i = 0; 507 + bool block_enabled = false; 508 + 509 + DC_LOG_DEBUG("%s: %s", debug_func, debug_log); 510 + 511 + DC_LOG_DEBUG("PG_CNTL status:\n"); 512 + 513 + block_enabled = pg_cntl35_io_clk_status(pg_cntl); 514 + DC_LOG_DEBUG("ONO0=%d (DCCG, DIO, DCIO)\n", block_enabled ? 1 : 0); 515 + 516 + block_enabled = pg_cntl35_mem_status(pg_cntl); 517 + DC_LOG_DEBUG("ONO1=%d (DCHUBBUB, DCHVM, DCHUBBUBMEM)\n", block_enabled ? 1 : 0); 518 + 519 + block_enabled = pg_cntl35_plane_otg_status(pg_cntl); 520 + DC_LOG_DEBUG("ONO2=%d (MPC, OPP, OPTC, DWB)\n", block_enabled ? 1 : 0); 521 + 522 + block_enabled = pg_cntl35_hpo_pg_status(pg_cntl); 523 + DC_LOG_DEBUG("ONO3=%d (HPO)\n", block_enabled ? 1 : 0); 524 + 525 + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { 526 + block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i); 527 + DC_LOG_DEBUG("ONO%d=%d (DCHUBP%d, DPP%d)\n", 4 + i * 2, block_enabled ? 1 : 0, i, i); 528 + 529 + block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i); 530 + DC_LOG_DEBUG("ONO%d=%d (DSC%d)\n", 5 + i * 2, block_enabled ? 1 : 0, i); 531 + } 532 + } 533 + 495 534 static const struct pg_cntl_funcs pg_cntl35_funcs = { 496 535 .init_pg_status = pg_cntl35_init_pg_status, 497 536 .dsc_pg_control = pg_cntl35_dsc_pg_control, ··· 532 511 .mpcc_pg_control = pg_cntl35_mpcc_pg_control, 533 512 .opp_pg_control = pg_cntl35_opp_pg_control, 534 513 .optc_pg_control = pg_cntl35_optc_pg_control, 535 - .dwb_pg_control = pg_cntl35_dwb_pg_control 514 + .dwb_pg_control = pg_cntl35_dwb_pg_control, 515 + .print_pg_status = pg_cntl35_print_pg_status 536 516 }; 537 517 538 518 struct pg_cntl *pg_cntl35_create(

+3 -3

drivers/gpu/drm/i915/display/intel_display_power.c

··· 1172 1172 if (DISPLAY_VER(display) == 12) 1173 1173 abox_regs |= BIT(0); 1174 1174 1175 - for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1175 + for_each_set_bit(i, &abox_regs, BITS_PER_TYPE(abox_regs)) 1176 1176 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); 1177 1177 } 1178 1178 ··· 1629 1629 if (table[config].page_mask == 0) { 1630 1630 drm_dbg_kms(display->drm, 1631 1631 "Unknown memory configuration; disabling address buddy logic.\n"); 1632 - for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1632 + for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) 1633 1633 intel_de_write(display, BW_BUDDY_CTL(i), 1634 1634 BW_BUDDY_DISABLE); 1635 1635 } else { 1636 - for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1636 + for_each_set_bit(i, &abox_mask, BITS_PER_TYPE(abox_mask)) { 1637 1637 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), 1638 1638 table[config].page_mask); 1639 1639

+9 -14

drivers/gpu/drm/mediatek/mtk_drm_drv.c

··· 387 387 388 388 of_id = of_match_node(mtk_drm_of_ids, node); 389 389 if (!of_id) 390 - goto next_put_node; 390 + continue; 391 391 392 392 pdev = of_find_device_by_node(node); 393 393 if (!pdev) 394 - goto next_put_node; 394 + continue; 395 395 396 396 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 397 + put_device(&pdev->dev); 397 398 if (!drm_dev) 398 - goto next_put_device_pdev_dev; 399 + continue; 399 400 400 401 temp_drm_priv = dev_get_drvdata(drm_dev); 402 + put_device(drm_dev); 401 403 if (!temp_drm_priv) 402 - goto next_put_device_drm_dev; 404 + continue; 403 405 404 406 if (temp_drm_priv->data->main_len) 405 407 all_drm_priv[CRTC_MAIN] = temp_drm_priv; ··· 413 411 if (temp_drm_priv->mtk_drm_bound) 414 412 cnt++; 415 413 416 - next_put_device_drm_dev: 417 - put_device(drm_dev); 418 - 419 - next_put_device_pdev_dev: 420 - put_device(&pdev->dev); 421 - 422 - next_put_node: 423 - of_node_put(node); 424 - 425 - if (cnt == MAX_CRTC) 414 + if (cnt == MAX_CRTC) { 415 + of_node_put(node); 426 416 break; 417 + } 427 418 } 428 419 429 420 if (drm_priv->data->mmsys_dev_num == cnt) {

-15

drivers/gpu/drm/nouveau/nouveau_fence.c

··· 240 240 return ret; 241 241 } 242 242 243 - void 244 - nouveau_fence_cancel(struct nouveau_fence *fence) 245 - { 246 - struct nouveau_fence_chan *fctx = nouveau_fctx(fence); 247 - unsigned long flags; 248 - 249 - spin_lock_irqsave(&fctx->lock, flags); 250 - if (!dma_fence_is_signaled_locked(&fence->base)) { 251 - dma_fence_set_error(&fence->base, -ECANCELED); 252 - if (nouveau_fence_signal(fence)) 253 - nvif_event_block(&fctx->event); 254 - } 255 - spin_unlock_irqrestore(&fctx->lock, flags); 256 - } 257 - 258 243 bool 259 244 nouveau_fence_done(struct nouveau_fence *fence) 260 245 {

-1

drivers/gpu/drm/nouveau/nouveau_fence.h

··· 29 29 30 30 int nouveau_fence_emit(struct nouveau_fence *); 31 31 bool nouveau_fence_done(struct nouveau_fence *); 32 - void nouveau_fence_cancel(struct nouveau_fence *fence); 33 32 int nouveau_fence_wait(struct nouveau_fence *, bool lazy, bool intr); 34 33 int nouveau_fence_sync(struct nouveau_bo *, struct nouveau_channel *, bool exclusive, bool intr); 35 34

+14 -21

drivers/gpu/drm/nouveau/nouveau_sched.c

··· 11 11 #include "nouveau_exec.h" 12 12 #include "nouveau_abi16.h" 13 13 #include "nouveau_sched.h" 14 - #include "nouveau_chan.h" 15 14 16 15 #define NOUVEAU_SCHED_JOB_TIMEOUT_MS 10000 17 16 ··· 121 122 { 122 123 struct nouveau_sched *sched = job->sched; 123 124 124 - spin_lock(&sched->job_list.lock); 125 + spin_lock(&sched->job.list.lock); 125 126 list_del(&job->entry); 126 - spin_unlock(&sched->job_list.lock); 127 + spin_unlock(&sched->job.list.lock); 128 + 129 + wake_up(&sched->job.wq); 127 130 } 128 131 129 132 void ··· 306 305 } 307 306 308 307 /* Submit was successful; add the job to the schedulers job list. */ 309 - spin_lock(&sched->job_list.lock); 310 - list_add(&job->entry, &sched->job_list.head); 311 - spin_unlock(&sched->job_list.lock); 308 + spin_lock(&sched->job.list.lock); 309 + list_add(&job->entry, &sched->job.list.head); 310 + spin_unlock(&sched->job.list.lock); 312 311 313 312 drm_sched_job_arm(&job->base); 314 313 job->done_fence = dma_fence_get(&job->base.s_fence->finished); ··· 393 392 nouveau_job_fini(job); 394 393 } 395 394 396 - static void 397 - nouveau_sched_cancel_job(struct drm_sched_job *sched_job) 398 - { 399 - struct nouveau_fence *fence; 400 - struct nouveau_job *job; 401 - 402 - job = to_nouveau_job(sched_job); 403 - fence = to_nouveau_fence(job->done_fence); 404 - 405 - nouveau_fence_cancel(fence); 406 - } 407 - 408 395 static const struct drm_sched_backend_ops nouveau_sched_ops = { 409 396 .run_job = nouveau_sched_run_job, 410 397 .timedout_job = nouveau_sched_timedout_job, 411 398 .free_job = nouveau_sched_free_job, 412 - .cancel_job = nouveau_sched_cancel_job, 413 399 }; 414 400 415 401 static int ··· 446 458 goto fail_sched; 447 459 448 460 mutex_init(&sched->mutex); 449 - spin_lock_init(&sched->job_list.lock); 450 - INIT_LIST_HEAD(&sched->job_list.head); 461 + spin_lock_init(&sched->job.list.lock); 462 + INIT_LIST_HEAD(&sched->job.list.head); 463 + init_waitqueue_head(&sched->job.wq); 451 464 452 465 return 0; 453 466 ··· 482 493 return 0; 483 494 } 484 495 496 + 485 497 static void 486 498 nouveau_sched_fini(struct nouveau_sched *sched) 487 499 { 488 500 struct drm_gpu_scheduler *drm_sched = &sched->base; 489 501 struct drm_sched_entity *entity = &sched->entity; 502 + 503 + rmb(); /* for list_empty to work without lock */ 504 + wait_event(sched->job.wq, list_empty(&sched->job.list.head)); 490 505 491 506 drm_sched_entity_fini(entity); 492 507 drm_sched_fini(drm_sched);

+6 -3

drivers/gpu/drm/nouveau/nouveau_sched.h

··· 103 103 struct mutex mutex; 104 104 105 105 struct { 106 - struct list_head head; 107 - spinlock_t lock; 108 - } job_list; 106 + struct { 107 + struct list_head head; 108 + spinlock_t lock; 109 + } list; 110 + struct wait_queue_head wq; 111 + } job; 109 112 }; 110 113 111 114 int nouveau_sched_create(struct nouveau_sched **psched, struct nouveau_drm *drm,

+4 -4

drivers/gpu/drm/nouveau/nouveau_uvmm.c

··· 1019 1019 u64 end = addr + range; 1020 1020 1021 1021 again: 1022 - spin_lock(&sched->job_list.lock); 1023 - list_for_each_entry(__job, &sched->job_list.head, entry) { 1022 + spin_lock(&sched->job.list.lock); 1023 + list_for_each_entry(__job, &sched->job.list.head, entry) { 1024 1024 struct nouveau_uvmm_bind_job *bind_job = to_uvmm_bind_job(__job); 1025 1025 1026 1026 list_for_each_op(op, &bind_job->ops) { ··· 1030 1030 1031 1031 if (!(end <= op_addr || addr >= op_end)) { 1032 1032 nouveau_uvmm_bind_job_get(bind_job); 1033 - spin_unlock(&sched->job_list.lock); 1033 + spin_unlock(&sched->job.list.lock); 1034 1034 wait_for_completion(&bind_job->complete); 1035 1035 nouveau_uvmm_bind_job_put(bind_job); 1036 1036 goto again; ··· 1038 1038 } 1039 1039 } 1040 1040 } 1041 - spin_unlock(&sched->job_list.lock); 1041 + spin_unlock(&sched->job.list.lock); 1042 1042 } 1043 1043 1044 1044 static int

+1 -1

drivers/gpu/drm/panthor/panthor_drv.c

··· 1094 1094 struct drm_panthor_queue_create *queue_args; 1095 1095 int ret; 1096 1096 1097 - if (!args->queues.count) 1097 + if (!args->queues.count || args->queues.count > MAX_CS_PER_CSG) 1098 1098 return -EINVAL; 1099 1099 1100 1100 ret = PANTHOR_UOBJ_GET_ARRAY(queue_args, &args->queues);

+1 -1

drivers/gpu/drm/xe/tests/xe_bo.c

··· 236 236 } 237 237 238 238 xe_bo_lock(external, false); 239 - err = xe_bo_pin_external(external); 239 + err = xe_bo_pin_external(external, false); 240 240 xe_bo_unlock(external); 241 241 if (err) { 242 242 KUNIT_FAIL(test, "external bo pin err=%pe\n",

+1 -9

drivers/gpu/drm/xe/tests/xe_dma_buf.c

··· 89 89 return; 90 90 } 91 91 92 - /* 93 - * If on different devices, the exporter is kept in system if 94 - * possible, saving a migration step as the transfer is just 95 - * likely as fast from system memory. 96 - */ 97 - if (params->mem_mask & XE_BO_FLAG_SYSTEM) 98 - KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, XE_PL_TT)); 99 - else 100 - KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, mem_type)); 92 + KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(exported, mem_type)); 101 93 102 94 if (params->force_different_devices) 103 95 KUNIT_EXPECT_TRUE(test, xe_bo_is_mem_type(imported, XE_PL_TT));

+12 -4

drivers/gpu/drm/xe/xe_bo.c

··· 186 186 187 187 bo->placements[*c] = (struct ttm_place) { 188 188 .mem_type = XE_PL_TT, 189 + .flags = (bo_flags & XE_BO_FLAG_VRAM_MASK) ? 190 + TTM_PL_FLAG_FALLBACK : 0, 189 191 }; 190 192 *c += 1; 191 193 } ··· 2271 2269 /** 2272 2270 * xe_bo_pin_external - pin an external BO 2273 2271 * @bo: buffer object to be pinned 2272 + * @in_place: Pin in current placement, don't attempt to migrate. 2274 2273 * 2275 2274 * Pin an external (not tied to a VM, can be exported via dma-buf / prime FD) 2276 2275 * BO. Unique call compared to xe_bo_pin as this function has it own set of ··· 2279 2276 * 2280 2277 * Returns 0 for success, negative error code otherwise. 2281 2278 */ 2282 - int xe_bo_pin_external(struct xe_bo *bo) 2279 + int xe_bo_pin_external(struct xe_bo *bo, bool in_place) 2283 2280 { 2284 2281 struct xe_device *xe = xe_bo_device(bo); 2285 2282 int err; ··· 2288 2285 xe_assert(xe, xe_bo_is_user(bo)); 2289 2286 2290 2287 if (!xe_bo_is_pinned(bo)) { 2291 - err = xe_bo_validate(bo, NULL, false); 2292 - if (err) 2293 - return err; 2288 + if (!in_place) { 2289 + err = xe_bo_validate(bo, NULL, false); 2290 + if (err) 2291 + return err; 2292 + } 2294 2293 2295 2294 spin_lock(&xe->pinned.lock); 2296 2295 list_add_tail(&bo->pinned_link, &xe->pinned.late.external); ··· 2444 2439 .gfp_retry_mayfail = true, 2445 2440 }; 2446 2441 int ret; 2442 + 2443 + if (xe_bo_is_pinned(bo)) 2444 + return 0; 2447 2445 2448 2446 if (vm) { 2449 2447 lockdep_assert_held(&vm->lock);

+1 -1

drivers/gpu/drm/xe/xe_bo.h

··· 198 198 } 199 199 } 200 200 201 - int xe_bo_pin_external(struct xe_bo *bo); 201 + int xe_bo_pin_external(struct xe_bo *bo, bool in_place); 202 202 int xe_bo_pin(struct xe_bo *bo); 203 203 void xe_bo_unpin_external(struct xe_bo *bo); 204 204 void xe_bo_unpin(struct xe_bo *bo);

drivers/gpu/drm/xe/xe_device_types.h

··· 553 553 554 554 /** @pm_notifier: Our PM notifier to perform actions in response to various PM events. */ 555 555 struct notifier_block pm_notifier; 556 + /** @pm_block: Completion to block validating tasks on suspend / hibernate prepare */ 557 + struct completion pm_block; 558 + /** @rebind_resume_list: List of wq items to kick on resume. */ 559 + struct list_head rebind_resume_list; 560 + /** @rebind_resume_lock: Lock to protect the rebind_resume_list */ 561 + struct mutex rebind_resume_lock; 556 562 557 563 /** @pmt: Support the PMT driver callback interface */ 558 564 struct {

+1 -1

drivers/gpu/drm/xe/xe_dma_buf.c

··· 72 72 return ret; 73 73 } 74 74 75 - ret = xe_bo_pin_external(bo); 75 + ret = xe_bo_pin_external(bo, true); 76 76 xe_assert(xe, !ret); 77 77 78 78 return 0;

drivers/gpu/drm/xe/xe_exec.c

··· 237 237 goto err_unlock_list; 238 238 } 239 239 240 + /* 241 + * It's OK to block interruptible here with the vm lock held, since 242 + * on task freezing during suspend / hibernate, the call will 243 + * return -ERESTARTSYS and the IOCTL will be rerun. 244 + */ 245 + err = wait_for_completion_interruptible(&xe->pm_block); 246 + if (err) 247 + goto err_unlock_list; 248 + 240 249 vm_exec.vm = &vm->gpuvm; 241 250 vm_exec.flags = DRM_EXEC_INTERRUPTIBLE_WAIT; 242 251 if (xe_vm_in_lr_mode(vm)) {

+32 -10

drivers/gpu/drm/xe/xe_pm.c

··· 24 24 #include "xe_pcode.h" 25 25 #include "xe_pxp.h" 26 26 #include "xe_trace.h" 27 + #include "xe_vm.h" 27 28 #include "xe_wa.h" 28 29 29 30 /** ··· 291 290 return DEFAULT_VRAM_THRESHOLD; 292 291 } 293 292 293 + static void xe_pm_wake_rebind_workers(struct xe_device *xe) 294 + { 295 + struct xe_vm *vm, *next; 296 + 297 + mutex_lock(&xe->rebind_resume_lock); 298 + list_for_each_entry_safe(vm, next, &xe->rebind_resume_list, 299 + preempt.pm_activate_link) { 300 + list_del_init(&vm->preempt.pm_activate_link); 301 + xe_vm_resume_rebind_worker(vm); 302 + } 303 + mutex_unlock(&xe->rebind_resume_lock); 304 + } 305 + 294 306 static int xe_pm_notifier_callback(struct notifier_block *nb, 295 307 unsigned long action, void *data) 296 308 { ··· 313 299 switch (action) { 314 300 case PM_HIBERNATION_PREPARE: 315 301 case PM_SUSPEND_PREPARE: 302 + reinit_completion(&xe->pm_block); 316 303 xe_pm_runtime_get(xe); 317 304 err = xe_bo_evict_all_user(xe); 318 - if (err) { 305 + if (err) 319 306 drm_dbg(&xe->drm, "Notifier evict user failed (%d)\n", err); 320 - xe_pm_runtime_put(xe); 321 - break; 322 - } 323 307 324 308 err = xe_bo_notifier_prepare_all_pinned(xe); 325 - if (err) { 309 + if (err) 326 310 drm_dbg(&xe->drm, "Notifier prepare pin failed (%d)\n", err); 327 - xe_pm_runtime_put(xe); 328 - } 311 + /* 312 + * Keep the runtime pm reference until post hibernation / post suspend to 313 + * avoid a runtime suspend interfering with evicted objects or backup 314 + * allocations. 315 + */ 329 316 break; 330 317 case PM_POST_HIBERNATION: 331 318 case PM_POST_SUSPEND: 319 + complete_all(&xe->pm_block); 320 + xe_pm_wake_rebind_workers(xe); 332 321 xe_bo_notifier_unprepare_all_pinned(xe); 333 322 xe_pm_runtime_put(xe); 334 323 break; 335 324 } 336 - 337 - if (err) 338 - return NOTIFY_BAD; 339 325 340 326 return NOTIFY_DONE; 341 327 } ··· 357 343 err = register_pm_notifier(&xe->pm_notifier); 358 344 if (err) 359 345 return err; 346 + 347 + err = drmm_mutex_init(&xe->drm, &xe->rebind_resume_lock); 348 + if (err) 349 + goto err_unregister; 350 + 351 + init_completion(&xe->pm_block); 352 + complete_all(&xe->pm_block); 353 + INIT_LIST_HEAD(&xe->rebind_resume_list); 360 354 361 355 /* For now suspend/resume is only allowed with GuC */ 362 356 if (!xe_device_uc_enabled(xe))

+2 -1

drivers/gpu/drm/xe/xe_survivability_mode.c

··· 41 41 * 42 42 * # echo 1 > /sys/kernel/config/xe/0000:03:00.0/survivability_mode 43 43 * 44 + * It is the responsibility of the user to clear the mode once firmware flash is complete. 45 + * 44 46 * Refer :ref:`xe_configfs` for more details on how to use configfs 45 47 * 46 48 * Survivability mode is indicated by the below admin-only readable sysfs which provides additional ··· 149 147 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 150 148 struct device *dev = &pdev->dev; 151 149 152 - xe_configfs_clear_survivability_mode(pdev); 153 150 sysfs_remove_file(&dev->kobj, &dev_attr_survivability_mode.attr); 154 151 } 155 152

+41 -1

drivers/gpu/drm/xe/xe_vm.c

··· 393 393 list_move_tail(&gpuva_to_vma(gpuva)->combined_links.rebind, 394 394 &vm->rebind_list); 395 395 396 + if (!try_wait_for_completion(&vm->xe->pm_block)) 397 + return -EAGAIN; 398 + 396 399 ret = xe_bo_validate(gem_to_xe_bo(vm_bo->obj), vm, false); 397 400 if (ret) 398 401 return ret; ··· 482 479 return xe_vm_validate_rebind(vm, exec, vm->preempt.num_exec_queues); 483 480 } 484 481 482 + static bool vm_suspend_rebind_worker(struct xe_vm *vm) 483 + { 484 + struct xe_device *xe = vm->xe; 485 + bool ret = false; 486 + 487 + mutex_lock(&xe->rebind_resume_lock); 488 + if (!try_wait_for_completion(&vm->xe->pm_block)) { 489 + ret = true; 490 + list_move_tail(&vm->preempt.pm_activate_link, &xe->rebind_resume_list); 491 + } 492 + mutex_unlock(&xe->rebind_resume_lock); 493 + 494 + return ret; 495 + } 496 + 497 + /** 498 + * xe_vm_resume_rebind_worker() - Resume the rebind worker. 499 + * @vm: The vm whose preempt worker to resume. 500 + * 501 + * Resume a preempt worker that was previously suspended by 502 + * vm_suspend_rebind_worker(). 503 + */ 504 + void xe_vm_resume_rebind_worker(struct xe_vm *vm) 505 + { 506 + queue_work(vm->xe->ordered_wq, &vm->preempt.rebind_work); 507 + } 508 + 485 509 static void preempt_rebind_work_func(struct work_struct *w) 486 510 { 487 511 struct xe_vm *vm = container_of(w, struct xe_vm, preempt.rebind_work); ··· 532 502 } 533 503 534 504 retry: 505 + if (!try_wait_for_completion(&vm->xe->pm_block) && vm_suspend_rebind_worker(vm)) { 506 + up_write(&vm->lock); 507 + return; 508 + } 509 + 535 510 if (xe_vm_userptr_check_repin(vm)) { 536 511 err = xe_vm_userptr_pin(vm); 537 512 if (err) ··· 1749 1714 if (flags & XE_VM_FLAG_LR_MODE) { 1750 1715 INIT_WORK(&vm->preempt.rebind_work, preempt_rebind_work_func); 1751 1716 xe_pm_runtime_get_noresume(xe); 1717 + INIT_LIST_HEAD(&vm->preempt.pm_activate_link); 1752 1718 } 1753 1719 1754 1720 if (flags & XE_VM_FLAG_FAULT_MODE) { ··· 1931 1895 xe_assert(xe, !vm->preempt.num_exec_queues); 1932 1896 1933 1897 xe_vm_close(vm); 1934 - if (xe_vm_in_preempt_fence_mode(vm)) 1898 + if (xe_vm_in_preempt_fence_mode(vm)) { 1899 + mutex_lock(&xe->rebind_resume_lock); 1900 + list_del_init(&vm->preempt.pm_activate_link); 1901 + mutex_unlock(&xe->rebind_resume_lock); 1935 1902 flush_work(&vm->preempt.rebind_work); 1903 + } 1936 1904 if (xe_vm_in_fault_mode(vm)) 1937 1905 xe_svm_close(vm); 1938 1906

drivers/gpu/drm/xe/xe_vm.h

··· 273 273 struct xe_exec_queue *q, u64 addr, 274 274 enum xe_cache_level cache_lvl); 275 275 276 + void xe_vm_resume_rebind_worker(struct xe_vm *vm); 277 + 276 278 /** 277 279 * xe_vm_resv() - Return's the vm's reservation object 278 280 * @vm: The vm

drivers/gpu/drm/xe/xe_vm_types.h

··· 293 293 * BOs 294 294 */ 295 295 struct work_struct rebind_work; 296 + /** 297 + * @preempt.pm_activate_link: Link to list of rebind workers to be 298 + * kicked on resume. 299 + */ 300 + struct list_head pm_activate_link; 296 301 } preempt; 297 302 298 303 /** @um: unified memory state */

+2 -1

drivers/gpu/drm/xe/xe_wa_oob.rules

··· 30 30 16022287689 GRAPHICS_VERSION(2001) 31 31 GRAPHICS_VERSION(2004) 32 32 13011645652 GRAPHICS_VERSION(2004) 33 - GRAPHICS_VERSION(3001) 33 + GRAPHICS_VERSION_RANGE(3000, 3001) 34 + GRAPHICS_VERSION(3003) 34 35 14022293748 GRAPHICS_VERSION_RANGE(2001, 2002) 35 36 GRAPHICS_VERSION(2004) 36 37 GRAPHICS_VERSION_RANGE(3000, 3001)

drivers/gpu/nova-core/Kconfig

··· 1 1 config NOVA_CORE 2 2 tristate "Nova Core GPU driver" 3 + depends on 64BIT 3 4 depends on PCI 4 5 depends on RUST 5 6 depends on RUST_FW_LOADER_ABSTRACTIONS

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