+2 -2

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

reviewed

··· 270 270 if (of_machine_is_compatible("fsl,imx8mp") || 271 271 of_machine_is_compatible("fsl,imx91") || 272 272 of_machine_is_compatible("fsl,imx93")) { 273 273 - /* Binding doc describes the propety: 273 273 + /* Binding doc describes the property: 274 274 * is required by i.MX8MP, i.MX91, i.MX93. 275 275 - * is optinoal for i.MX8DXL. 275 275 + * is optional for i.MX8DXL. 276 276 */ 277 277 dwmac->intf_regmap = 278 278 syscon_regmap_lookup_by_phandle_args(np, "intf_mode", 1,

+2 -2

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

reviewed

··· 746 746 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); 747 747 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); 748 748 749 749 - /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) 749 749 + /* The timeout was previously set to 10ms, but some board (OrangePI0) 750 750 * need more if no cable plugged. 100ms seems OK 751 751 */ 752 752 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, ··· 821 821 return ret; 822 822 } 823 823 824 824 - /* Make sure the EPHY is properly reseted, as U-Boot may leave 824 824 + /* Make sure the EPHY is properly reset, as U-Boot may leave 825 825 * it at deasserted state, and thus it may fail to reset EMAC. 826 826 * 827 827 * This assumes the driver has exclusive access to the EPHY reset.

+1 -1

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

reviewed

··· 152 152 153 153 /*--- DMA BLOCK defines ---*/ 154 154 /* DMA Bus Mode register defines */ 155 155 - /* Programmable burst length (passed thorugh platform)*/ 155 155 + /* Programmable burst length (passed through platform)*/ 156 156 #define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */ 157 157 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 158 158

+1 -1

drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

reviewed

··· 108 108 memset(mc_filter, 0, sizeof(mc_filter)); 109 109 netdev_for_each_mc_addr(ha, dev) { 110 110 /* The upper 6 bits of the calculated CRC are used to 111 111 - * index the contens of the hash table 111 111 + * index the contents of the hash table 112 112 */ 113 113 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 114 114 /* The most significant bit determines the register to

+1 -1

drivers/net/ethernet/stmicro/stmmac/enh_desc.c

reviewed

··· 88 88 89 89 /* bits 5 7 0 | Frame status 90 90 * ---------------------------------------------------------- 91 91 - * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects) 91 91 + * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octets) 92 92 * 1 0 0 | IPv4/6 No CSUM errorS. 93 93 * 1 0 1 | IPv4/6 CSUM PAYLOAD error 94 94 * 1 1 0 | IPv4/6 CSUM IP HR error

+2 -2

drivers/net/ethernet/stmicro/stmmac/mmc_core.c

reviewed

··· 252 252 writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK); 253 253 } 254 254 255 255 - /* This reads the MAC core counters (if actaully supported). 255 255 + /* This reads the MAC core counters (if actually supported). 256 256 * by default the MMC core is programmed to reset each 257 257 * counter after a read. So all the field of the mmc struct 258 258 * have to be incremented. ··· 420 420 *dest = *dest + tmp; 421 421 } 422 422 423 423 - /* This reads the MAC core counters (if actaully supported). 423 423 + /* This reads the MAC core counters (if actually supported). 424 424 * by default the MMC core is programmed to reset each 425 425 * counter after a read. So all the field of the mmc struct 426 426 * have to be incremented.

+1 -1

drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c

reviewed

··· 43 43 unsigned long data; 44 44 u32 reg_value; 45 45 46 46 - /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second 46 46 + /* For GMAC3.x, 4.x versions, in "fine adjustment mode" set sub-second 47 47 * increment to twice the number of nanoseconds of a clock cycle. 48 48 * The calculation of the default_addend value by the caller will set it 49 49 * to mid-range = 2^31 when the remainder of this division is zero,

+5 -5

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

reviewed

··· 1130 1130 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 1131 1131 STMMAC_DEFAULT_TWT_LS); 1132 1132 1133 1133 - /* Try to cnfigure the hardware timer. */ 1133 1133 + /* Try to configure the hardware timer. */ 1134 1134 ret = stmmac_set_lpi_mode(priv, priv->hw, STMMAC_LPI_TIMER, 1135 1135 priv->tx_lpi_clk_stop, priv->tx_lpi_timer); 1136 1136 ··· 3511 3511 /** 3512 3512 * stmmac_mtl_configuration - Configure MTL 3513 3513 * @priv: driver private structure 3514 3514 - * Description: It is used for configurring MTL 3514 3514 + * Description: It is used for configuring MTL 3515 3515 */ 3516 3516 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3517 3517 { ··· 4389 4389 4390 4390 /* Always insert VLAN tag to SKB payload for TSO frames. 4391 4391 * 4392 4392 - * Never insert VLAN tag by HW, since segments splited by 4392 4392 + * Never insert VLAN tag by HW, since segments split by 4393 4393 * TSO engine will be un-tagged by mistake. 4394 4394 */ 4395 4395 if (skb_vlan_tag_present(skb)) { ··· 5962 5962 unsigned long flags; 5963 5963 5964 5964 spin_lock_irqsave(&ch->lock, flags); 5965 5965 - /* Both RX and TX work done are compelte, 5965 5965 + /* Both RX and TX work done are complete, 5966 5966 * so enable both RX & TX IRQs. 5967 5967 */ 5968 5968 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); ··· 6294 6294 /** 6295 6295 * stmmac_ioctl - Entry point for the Ioctl 6296 6296 * @dev: Device pointer. 6297 6297 - * @rq: An IOCTL specefic structure, that can contain a pointer to 6297 6297 + * @rq: An IOCTL specific structure, that can contain a pointer to 6298 6298 * a proprietary structure used to pass information to the driver. 6299 6299 * @cmd: IOCTL command 6300 6300 * Description:

+1 -1

drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c

reviewed

··· 483 483 * If a specific clk_csr value is passed from the platform 484 484 * this means that the CSR Clock Range selection cannot be 485 485 * changed at run-time and it is fixed (as reported in the driver 486 486 - * documentation). Viceversa the driver will try to set the MDC 486 486 + * documentation). Vice versa the driver will try to set the MDC 487 487 * clock dynamically according to the actual clock input. 488 488 */ 489 489 static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)

+1 -1

drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c

reviewed

··· 2000 2000 } 2001 2001 2002 2002 /* 2003 2003 - * First tests will always be MAC / PHY loobpack. If any of 2003 2003 + * First tests will always be MAC / PHY loopback. If any of 2004 2004 * them is not supported we abort earlier. 2005 2005 */ 2006 2006 if (ret) {