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ASoC: amd: update ps platform acp header file

Rename Audio buffer and soundwire manager instance registers.
Remove scratch registers as these registers can be accessed
using ACP_SCRATCH_REG_0 register relative offset.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20230201165626.3169041-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Vijendar Mukunda and committed by
Mark Brown 96ebccb2 1c9ded98

+294 -457
+294 -457
include/sound/acp63_chip_offset_byte.h
··· 126 126 #define ACP_PAD_PULLDOWN_CTRL 0x0001448 127 127 #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C 128 128 #define ACP_PAD_SCHMEN_CTRL 0x0001450 129 - #define ACP_SW_PAD_KEEPER_EN 0x0001454 130 - #define ACP_SW_WAKE_EN 0x0001458 129 + #define ACP_SW0_PAD_KEEPER_EN 0x0001454 130 + #define ACP_SW0_WAKE_EN 0x0001458 131 131 #define ACP_I2S_WAKE_EN 0x000145C 132 132 #define ACP_SW1_WAKE_EN 0x0001460 133 133 134 - #define ACP_SW_I2S_ERROR_REASON 0x00018B4 135 - #define ACP_SW_POS_TRACK_I2S_TX_CTRL 0x00018B8 136 - #define ACP_SW_I2S_TX_DMA_POS 0x00018BC 137 - #define ACP_SW_POS_TRACK_BT_TX_CTRL 0x00018C0 138 - #define ACP_SW_BT_TX_DMA_POS 0x00018C4 139 - #define ACP_SW_POS_TRACK_HS_TX_CTRL 0x00018C8 140 - #define ACP_SW_HS_TX_DMA_POS 0x00018CC 141 - #define ACP_SW_POS_TRACK_I2S_RX_CTRL 0x00018D0 142 - #define ACP_SW_I2S_RX_DMA_POS 0x00018D4 143 - #define ACP_SW_POS_TRACK_BT_RX_CTRL 0x00018D8 144 - #define ACP_SW_BT_RX_DMA_POS 0x00018DC 145 - #define ACP_SW_POS_TRACK_HS_RX_CTRL 0x00018E0 146 - #define ACP_SW_HS_RX_DMA_POS 0x00018E4 134 + #define ACP_SW0_I2S_ERROR_REASON 0x00018B4 135 + #define ACP_SW0_POS_TRACK_AUDIO0_TX_CTRL 0x00018B8 136 + #define ACP_SW0_AUDIO0_TX_DMA_POS 0x00018BC 137 + #define ACP_SW0_POS_TRACK_AUDIO1_TX_CTRL 0x00018C0 138 + #define ACP_SW0_AUDIO1_TX_DMA_POS 0x00018C4 139 + #define ACP_SW0_POS_TRACK_AUDIO2_TX_CTRL 0x00018C8 140 + #define ACP_SW0_AUDIO2_TX_DMA_POS 0x00018CC 141 + #define ACP_SW0_POS_TRACK_AUDIO0_RX_CTRL 0x00018D0 142 + #define ACP_SW0_AUDIO0_DMA_POS 0x00018D4 143 + #define ACP_SW0_POS_TRACK_AUDIO1_RX_CTRL 0x00018D8 144 + #define ACP_SW0_AUDIO1_RX_DMA_POS 0x00018DC 145 + #define ACP_SW0_POS_TRACK_AUDIO2_RX_CTRL 0x00018E0 146 + #define ACP_SW0_AUDIO2_RX_DMA_POS 0x00018E4 147 147 #define ACP_ERROR_INTR_MASK1 0X0001974 148 148 #define ACP_ERROR_INTR_MASK2 0X0001978 149 149 #define ACP_ERROR_INTR_MASK3 0X000197C ··· 155 155 #define ACP_EXTERNAL_INTR_STAT 0x0001A0C 156 156 #define ACP_EXTERNAL_INTR_STAT1 0x0001A10 157 157 #define ACP_ERROR_STATUS 0x0001A4C 158 - #define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50 159 - #define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C 160 - #define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70 161 - #define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74 162 - #define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78 158 + #define ACP_SW1_I2S_ERROR_REASON 0x0001A50 159 + #define ACP_SW1_POS_TRACK_AUDIO0_TX_CTRL 0x0001A6C 160 + #define ACP_SW1_AUDIO0_TX_DMA_POS 0x0001A70 161 + #define ACP_SW1_POS_TRACK_AUDIO0_RX_CTRL 0x0001A74 162 + #define ACP_SW1_AUDIO0_RX_DMA_POS 0x0001A78 163 163 #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C 164 164 #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80 165 165 #define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84 166 - #define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88 167 - #define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C 168 - #define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90 169 - #define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94 170 - #define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98 171 - #define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C 172 - #define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0 173 - #define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4 166 + #define ACP_SW1_POS_TRACK_AUDIO1_TX_CTRL 0x0001A88 167 + #define ACP_SW1_AUDIO1_TX_DMA_POS 0x0001A8C 168 + #define ACP_SW1_POS_TRACK_AUDIO2_TX_CTRL 0x0001A90 169 + #define ACP_SW1_AUDIO2_TX_DMA_POS 0x0001A94 170 + #define ACP_SW1_POS_TRACK_AUDIO1_RX_CTRL 0x0001A98 171 + #define ACP_SW1_AUDIO1_RX_DMA_POS 0x0001A9C 172 + #define ACP_SW1_POS_TRACK_AUDIO2_RX_CTRL 0x0001AA0 173 + #define ACP_SW1_AUDIO2_RX_DMA_POS 0x0001AA4 174 174 #define ACP_ERROR_INTR_MASK4 0X0001AEC 175 175 #define ACP_ERROR_INTR_MASK5 0X0001AF0 176 176 177 177 /* Registers from ACP_AUDIO_BUFFERS block */ 178 - #define ACP_I2S_RX_RINGBUFADDR 0x0002000 179 - #define ACP_I2S_RX_RINGBUFSIZE 0x0002004 180 - #define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008 181 - #define ACP_I2S_RX_FIFOADDR 0x000200C 182 - #define ACP_I2S_RX_FIFOSIZE 0x0002010 183 - #define ACP_I2S_RX_DMA_SIZE 0x0002014 184 - #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 185 - #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C 186 - #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020 187 - #define ACP_I2S_TX_RINGBUFADDR 0x0002024 188 - #define ACP_I2S_TX_RINGBUFSIZE 0x0002028 189 - #define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C 190 - #define ACP_I2S_TX_FIFOADDR 0x0002030 191 - #define ACP_I2S_TX_FIFOSIZE 0x0002034 192 - #define ACP_I2S_TX_DMA_SIZE 0x0002038 193 - #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C 194 - #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040 195 - #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044 196 - #define ACP_BT_RX_RINGBUFADDR 0x0002048 197 - #define ACP_BT_RX_RINGBUFSIZE 0x000204C 198 - #define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050 199 - #define ACP_BT_RX_FIFOADDR 0x0002054 200 - #define ACP_BT_RX_FIFOSIZE 0x0002058 201 - #define ACP_BT_RX_DMA_SIZE 0x000205C 202 - #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 203 - #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064 204 - #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068 205 - #define ACP_BT_TX_RINGBUFADDR 0x000206C 206 - #define ACP_BT_TX_RINGBUFSIZE 0x0002070 207 - #define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074 208 - #define ACP_BT_TX_FIFOADDR 0x0002078 209 - #define ACP_BT_TX_FIFOSIZE 0x000207C 210 - #define ACP_BT_TX_DMA_SIZE 0x0002080 211 - #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 212 - #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088 213 - #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C 214 - #define ACP_HS_RX_RINGBUFADDR 0x0002090 215 - #define ACP_HS_RX_RINGBUFSIZE 0x0002094 216 - #define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098 217 - #define ACP_HS_RX_FIFOADDR 0x000209C 218 - #define ACP_HS_RX_FIFOSIZE 0x00020A0 219 - #define ACP_HS_RX_DMA_SIZE 0x00020A4 220 - #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 221 - #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC 222 - #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0 223 - #define ACP_HS_TX_RINGBUFADDR 0x00020B4 224 - #define ACP_HS_TX_RINGBUFSIZE 0x00020B8 225 - #define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC 226 - #define ACP_HS_TX_FIFOADDR 0x00020C0 227 - #define ACP_HS_TX_FIFOSIZE 0x00020C4 228 - #define ACP_HS_TX_DMA_SIZE 0x00020C8 229 - #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC 230 - #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 231 - #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4 232 - #define ACP_AUDIO_RX_RINGBUFADDR ACP_I2S_RX_RINGBUFADDR 233 - #define ACP_AUDIO_RX_RINGBUFSIZE ACP_I2S_RX_RINGBUFSIZE 234 - #define ACP_AUDIO_RX_LINKPOSITIONCNTR ACP_I2S_RX_LINKPOSITIONCNTR 235 - #define ACP_AUDIO_RX_FIFOADDR ACP_I2S_RX_FIFOADDR 236 - #define ACP_AUDIO_RX_FIFOSIZE ACP_I2S_RX_FIFOSIZE 237 - #define ACP_AUDIO_RX_DMA_SIZE ACP_I2S_RX_DMA_SIZE 238 - #define ACP_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 239 - #define ACP_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 240 - #define ACP_AUDIO_RX_INTR_WATERMARK_SIZE ACP_I2S_RX_INTR_WATERMARK_SIZE 241 - #define ACP_AUDIO_TX_RINGBUFADDR ACP_I2S_TX_RINGBUFADDR 242 - #define ACP_AUDIO_TX_RINGBUFSIZE ACP_I2S_TX_RINGBUFSIZE 243 - #define ACP_AUDIO_TX_LINKPOSITIONCNTR ACP_I2S_TX_LINKPOSITIONCNTR 244 - #define ACP_AUDIO_TX_FIFOADDR ACP_I2S_TX_FIFOADDR 245 - #define ACP_AUDIO_TX_FIFOSIZE ACP_I2S_TX_FIFOSIZE 246 - #define ACP_AUDIO_TX_DMA_SIZE ACP_I2S_TX_DMA_SIZE 247 - #define ACP_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 248 - #define ACP_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 249 - #define ACP_AUDIO_TX_INTR_WATERMARK_SIZE ACP_I2S_TX_INTR_WATERMARK_SIZE 178 + #define ACP_AUDIO0_RX_RINGBUFADDR 0x0002000 179 + #define ACP_AUDIO0_RX_RINGBUFSIZE 0x0002004 180 + #define ACP_AUDIO0_RX_LINKPOSITIONCNTR 0x0002008 181 + #define ACP_AUDIO0_RX_FIFOADDR 0x000200C 182 + #define ACP_AUDIO0_RX_FIFOSIZE 0x0002010 183 + #define ACP_AUDIO0_RX_DMA_SIZE 0x0002014 184 + #define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 185 + #define ACP_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x000201C 186 + #define ACP_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0002020 187 + #define ACP_AUDIO0_TX_RINGBUFADDR 0x0002024 188 + #define ACP_AUDIO0_TX_RINGBUFSIZE 0x0002028 189 + #define ACP_AUDIO0_TX_LINKPOSITIONCNTR 0x000202C 190 + #define ACP_AUDIO0_TX_FIFOADDR 0x0002030 191 + #define ACP_AUDIO0_TX_FIFOSIZE 0x0002034 192 + #define ACP_AUDIO0_TX_DMA_SIZE 0x0002038 193 + #define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x000203C 194 + #define ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0002040 195 + #define ACP_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0002044 196 + #define ACP_AUDIO1_RX_RINGBUFADDR 0x0002048 197 + #define ACP_AUDIO1_RX_RINGBUFSIZE 0x000204C 198 + #define ACP_AUDIO1_RX_LINKPOSITIONCNTR 0x0002050 199 + #define ACP_AUDIO1_RX_FIFOADDR 0x0002054 200 + #define ACP_AUDIO1_RX_FIFOSIZE 0x0002058 201 + #define ACP_AUDIO1_RX_DMA_SIZE 0x000205C 202 + #define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 203 + #define ACP_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0002064 204 + #define ACP_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0002068 205 + #define ACP_AUDIO1_TX_RINGBUFADDR 0x000206C 206 + #define ACP_AUDIO1_TX_RINGBUFSIZE 0x0002070 207 + #define ACP_AUDIO1_TX_LINKPOSITIONCNTR 0x0002074 208 + #define ACP_AUDIO1_TX_FIFOADDR 0x0002078 209 + #define ACP_AUDIO1_TX_FIFOSIZE 0x000207C 210 + #define ACP_AUDIO1_TX_DMA_SIZE 0x0002080 211 + #define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 212 + #define ACP_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0002088 213 + #define ACP_AUDIO1_TX_INTR_WATERMARK_SIZE 0x000208C 214 + #define ACP_AUDIO2_RX_RINGBUFADDR 0x0002090 215 + #define ACP_AUDIO2_RX_RINGBUFSIZE 0x0002094 216 + #define ACP_AUDIO2_RX_LINKPOSITIONCNTR 0x0002098 217 + #define ACP_AUDIO2_RX_FIFOADDR 0x000209C 218 + #define ACP_AUDIO2_RX_FIFOSIZE 0x00020A0 219 + #define ACP_AUDIO2_RX_DMA_SIZE 0x00020A4 220 + #define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 221 + #define ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x00020AC 222 + #define ACP_AUDIO2_RX_INTR_WATERMARK_SIZE 0x00020B0 223 + #define ACP_AUDIO2_TX_RINGBUFADDR 0x00020B4 224 + #define ACP_AUDIO2_TX_RINGBUFSIZE 0x00020B8 225 + #define ACP_AUDIO2_TX_LINKPOSITIONCNTR 0x00020BC 226 + #define ACP_AUDIO2_TX_FIFOADDR 0x00020C0 227 + #define ACP_AUDIO2_TX_FIFOSIZE 0x00020C4 228 + #define ACP_AUDIO2_TX_DMA_SIZE 0x00020C8 229 + #define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC 230 + #define ACP_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 231 + #define ACP_AUDIO2_TX_INTR_WATERMARK_SIZE 0x00020D4 250 232 251 233 /* Registers from ACP_I2S_TDM block */ 252 234 #define ACP_I2STDM_IER 0x0002400 ··· 274 292 #define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68 275 293 #define ACP_PDM_CLKDIV 0x0002C6C 276 294 277 - /* Registers from ACP_SW_SWCLK block */ 278 - #define ACP_SW_EN 0x0003000 279 - #define ACP_SW_EN_STATUS 0x0003004 280 - #define ACP_SW_FRAMESIZE 0x0003008 281 - #define ACP_SW_SSP_COUNTER 0x000300C 282 - #define ACP_SW_AUDIO_TX_EN 0x0003010 283 - #define ACP_SW_AUDIO_TX_EN_STATUS 0x0003014 284 - #define ACP_SW_AUDIO_TX_FRAME_FORMAT 0x0003018 285 - #define ACP_SW_AUDIO_TX_SAMPLEINTERVAL 0x000301C 286 - #define ACP_SW_AUDIO_TX_HCTRL_DP0 0x0003020 287 - #define ACP_SW_AUDIO_TX_HCTRL_DP1 0x0003024 288 - #define ACP_SW_AUDIO_TX_HCTRL_DP2 0x0003028 289 - #define ACP_SW_AUDIO_TX_HCTRL_DP3 0x000302C 290 - #define ACP_SW_AUDIO_TX_OFFSET_DP0 0x0003030 291 - #define ACP_SW_AUDIO_TX_OFFSET_DP1 0x0003034 292 - #define ACP_SW_AUDIO_TX_OFFSET_DP2 0x0003038 293 - #define ACP_SW_AUDIO_TX_OFFSET_DP3 0x000303C 294 - #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP0 0x0003040 295 - #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP1 0x0003044 296 - #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP2 0x0003048 297 - #define ACP_SW_AUDIO_TX_CHANNEL_ENABLE_DP3 0x000304C 298 - #define ACP_SW_BT_TX_EN 0x0003050 299 - #define ACP_SW_BT_TX_EN_STATUS 0x0003054 300 - #define ACP_SW_BT_TX_FRAME_FORMAT 0x0003058 301 - #define ACP_SW_BT_TX_SAMPLEINTERVAL 0x000305C 302 - #define ACP_SW_BT_TX_HCTRL 0x0003060 303 - #define ACP_SW_BT_TX_OFFSET 0x0003064 304 - #define ACP_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003068 305 - #define ACP_SW_HEADSET_TX_EN 0x000306C 306 - #define ACP_SW_HEADSET_TX_EN_STATUS 0x0003070 307 - #define ACP_SW_HEADSET_TX_FRAME_FORMAT 0x0003074 308 - #define ACP_SW_HEADSET_TX_SAMPLEINTERVAL 0x0003078 309 - #define ACP_SW_HEADSET_TX_HCTRL 0x000307C 310 - #define ACP_SW_HEADSET_TX_OFFSET 0x0003080 311 - #define ACP_SW_HEADSET_TX_CHANNEL_ENABLE_DP0 0x0003084 312 - #define ACP_SW_AUDIO_RX_EN 0x0003088 313 - #define ACP_SW_AUDIO_RX_EN_STATUS 0x000308C 314 - #define ACP_SW_AUDIO_RX_FRAME_FORMAT 0x0003090 315 - #define ACP_SW_AUDIO_RX_SAMPLEINTERVAL 0x0003094 316 - #define ACP_SW_AUDIO_RX_HCTRL_DP0 0x0003098 317 - #define ACP_SW_AUDIO_RX_HCTRL_DP1 0x000309C 318 - #define ACP_SW_AUDIO_RX_HCTRL_DP2 0x0003100 319 - #define ACP_SW_AUDIO_RX_HCTRL_DP3 0x0003104 320 - #define ACP_SW_AUDIO_RX_OFFSET_DP0 0x0003108 321 - #define ACP_SW_AUDIO_RX_OFFSET_DP1 0x000310C 322 - #define ACP_SW_AUDIO_RX_OFFSET_DP2 0x0003110 323 - #define ACP_SW_AUDIO_RX_OFFSET_DP3 0x0003114 324 - #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP0 0x0003118 325 - #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP1 0x000311C 326 - #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP2 0x0003120 327 - #define ACP_SW_AUDIO_RX_CHANNEL_ENABLE_DP3 0x0003124 328 - #define ACP_SW_BT_RX_EN 0x0003128 329 - #define ACP_SW_BT_RX_EN_STATUS 0x000312C 330 - #define ACP_SW_BT_RX_FRAME_FORMAT 0x0003130 331 - #define ACP_SW_BT_RX_SAMPLEINTERVAL 0x0003134 332 - #define ACP_SW_BT_RX_HCTRL 0x0003138 333 - #define ACP_SW_BT_RX_OFFSET 0x000313C 334 - #define ACP_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003140 335 - #define ACP_SW_HEADSET_RX_EN 0x0003144 336 - #define ACP_SW_HEADSET_RX_EN_STATUS 0x0003148 337 - #define ACP_SW_HEADSET_RX_FRAME_FORMAT 0x000314C 338 - #define ACP_SW_HEADSET_RX_SAMPLEINTERVAL 0x0003150 339 - #define ACP_SW_HEADSET_RX_HCTRL 0x0003154 340 - #define ACP_SW_HEADSET_RX_OFFSET 0x0003158 341 - #define ACP_SW_HEADSET_RX_CHANNEL_ENABLE_DP0 0x000315C 342 - #define ACP_SW_BPT_PORT_EN 0x0003160 343 - #define ACP_SW_BPT_PORT_EN_STATUS 0x0003164 344 - #define ACP_SW_BPT_PORT_FRAME_FORMAT 0x0003168 345 - #define ACP_SW_BPT_PORT_SAMPLEINTERVAL 0x000316C 346 - #define ACP_SW_BPT_PORT_HCTRL 0x0003170 347 - #define ACP_SW_BPT_PORT_OFFSET 0x0003174 348 - #define ACP_SW_BPT_PORT_CHANNEL_ENABLE 0x0003178 349 - #define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR 0x000317C 350 - #define ACP_SW_CLK_RESUME_CTRL 0x0003180 351 - #define ACP_SW_CLK_RESUME_DELAY_CNTR 0x0003184 352 - #define ACP_SW_BUS_RESET_CTRL 0x0003188 353 - #define ACP_SW_PRBS_ERR_STATUS 0x000318C 354 - #define SW_IMM_CMD_UPPER_WORD 0x0003230 355 - #define SW_IMM_CMD_LOWER_QWORD 0x0003234 356 - #define SW_IMM_RESP_UPPER_WORD 0x0003238 357 - #define SW_IMM_RESP_LOWER_QWORD 0x000323C 358 - #define SW_IMM_CMD_STS 0x0003240 359 - #define SW_BRA_BASE_ADDRESS 0x0003244 360 - #define SW_BRA_TRANSFER_SIZE 0x0003248 361 - #define SW_BRA_DMA_BUSY 0x000324C 362 - #define SW_BRA_RESP 0x0003250 363 - #define SW_BRA_RESP_FRAME_ADDR 0x0003254 364 - #define SW_BRA_CURRENT_TRANSFER_SIZE 0x0003258 365 - #define SW_STATE_CHANGE_STATUS_0TO7 0x000325C 366 - #define SW_STATE_CHANGE_STATUS_8TO11 0x0003260 367 - #define SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003264 368 - #define SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003268 369 - #define SW_CLK_FREQUENCY_CTRL 0x000326C 370 - #define SW_ERROR_INTR_MASK 0x0003270 371 - #define SW_PHY_TEST_MODE_DATA_OFF 0x0003274 295 + /* Registers from ACP_SW0_SWCLK block */ 296 + #define ACP_SW0_EN 0x0003000 297 + #define ACP_SW0_EN_STATUS 0x0003004 298 + #define ACP_SW0_FRAMESIZE 0x0003008 299 + #define ACP_SW0_SSP_COUNTER 0x000300C 300 + #define ACP_SW0_AUDIO0_TX_EN 0x0003010 301 + #define ACP_SW0_AUDIO0_TX_EN_STATUS 0x0003014 302 + #define ACP_SW0_AUDIO0_TX_FRAME_FORMAT 0x0003018 303 + #define ACP_SW0_AUDIO0_TX_SAMPLEINTERVAL 0x000301C 304 + #define ACP_SW0_AUDIO0_TX_HCTRL_DP0 0x0003020 305 + #define ACP_SW0_AUDIO0_TX_HCTRL_DP1 0x0003024 306 + #define ACP_SW0_AUDIO0_TX_HCTRL_DP2 0x0003028 307 + #define ACP_SW0_AUDIO0_TX_HCTRL_DP3 0x000302C 308 + #define ACP_SW0_AUDIO0_TX_OFFSET_DP0 0x0003030 309 + #define ACP_SW0_AUDIO0_TX_OFFSET_DP1 0x0003034 310 + #define ACP_SW0_AUDIO0_TX_OFFSET_DP2 0x0003038 311 + #define ACP_SW0_AUDIO0_TX_OFFSET_DP3 0x000303C 312 + #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x0003040 313 + #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x0003044 314 + #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP2 0x0003048 315 + #define ACP_SW0_AUDIO0_TX_CHANNEL_ENABLE_DP3 0x000304C 316 + #define ACP_SW0_AUDIO1_TX_EN 0x0003050 317 + #define ACP_SW0_AUDIO1_TX_EN_STATUS 0x0003054 318 + #define ACP_SW0_AUDIO1_TX_FRAME_FORMAT 0x0003058 319 + #define ACP_SW0_AUDIO1_TX_SAMPLEINTERVAL 0x000305C 320 + #define ACP_SW0_AUDIO1_TX_HCTRL 0x0003060 321 + #define ACP_SW0_AUDIO1_TX_OFFSET 0x0003064 322 + #define ACP_SW0_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003068 323 + #define ACP_SW0_AUDIO2_TX_EN 0x000306C 324 + #define ACP_SW0_AUDIO2_TX_EN_STATUS 0x0003070 325 + #define ACP_SW0_AUDIO2_TX_FRAME_FORMAT 0x0003074 326 + #define ACP_SW0_AUDIO2_TX_SAMPLEINTERVAL 0x0003078 327 + #define ACP_SW0_AUDIO2_TX_HCTRL 0x000307C 328 + #define ACP_SW0_AUDIO2_TX_OFFSET 0x0003080 329 + #define ACP_SW0_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x0003084 330 + #define ACP_SW0_AUDIO0_RX_EN 0x0003088 331 + #define ACP_SW0_AUDIO0_RX_EN_STATUS 0x000308C 332 + #define ACP_SW0_AUDIO0_RX_FRAME_FORMAT 0x0003090 333 + #define ACP_SW0_AUDIO0_RX_SAMPLEINTERVAL 0x0003094 334 + #define ACP_SW0_AUDIO0_RX_HCTRL_DP0 0x0003098 335 + #define ACP_SW0_AUDIO0_RX_HCTRL_DP1 0x000309C 336 + #define ACP_SW0_AUDIO0_RX_HCTRL_DP2 0x0003100 337 + #define ACP_SW0_AUDIO0_RX_HCTRL_DP3 0x0003104 338 + #define ACP_SW0_AUDIO0_RX_OFFSET_DP0 0x0003108 339 + #define ACP_SW0_AUDIO0_RX_OFFSET_DP1 0x000310C 340 + #define ACP_SW0_AUDIO0_RX_OFFSET_DP2 0x0003110 341 + #define ACP_SW0_AUDIO0_RX_OFFSET_DP3 0x0003114 342 + #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x0003118 343 + #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x000311C 344 + #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP2 0x0003120 345 + #define ACP_SW0_AUDIO0_RX_CHANNEL_ENABLE_DP3 0x0003124 346 + #define ACP_SW0_AUDIO1_RX_EN 0x0003128 347 + #define ACP_SW0_AUDIO1_RX_EN_STATUS 0x000312C 348 + #define ACP_SW0_AUDIO1_RX_FRAME_FORMAT 0x0003130 349 + #define ACP_SW0_AUDIO1_RX_SAMPLEINTERVAL 0x0003134 350 + #define ACP_SW0_AUDIO1_RX_HCTRL 0x0003138 351 + #define ACP_SW0_AUDIO1_RX_OFFSET 0x000313C 352 + #define ACP_SW0_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003140 353 + #define ACP_SW0_AUDIO2_RX_EN 0x0003144 354 + #define ACP_SW0_AUDIO2_RX_EN_STATUS 0x0003148 355 + #define ACP_SW0_AUDIO2_RX_FRAME_FORMAT 0x000314C 356 + #define ACP_SW0_AUDIO2_RX_SAMPLEINTERVAL 0x0003150 357 + #define ACP_SW0_AUDIO2_RX_HCTRL 0x0003154 358 + #define ACP_SW0_AUDIO2_RX_OFFSET 0x0003158 359 + #define ACP_SW0_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x000315C 360 + #define ACP_SW0_BPT_PORT_EN 0x0003160 361 + #define ACP_SW0_BPT_PORT_EN_STATUS 0x0003164 362 + #define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0003168 363 + #define ACP_SW0_BPT_PORT_SAMPLEINTERVAL 0x000316C 364 + #define ACP_SW0_BPT_PORT_HCTRL 0x0003170 365 + #define ACP_SW0_BPT_PORT_OFFSET 0x0003174 366 + #define ACP_SW0_BPT_PORT_CHANNEL_ENABLE 0x0003178 367 + #define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x000317C 368 + #define ACP_SW0_CLK_RESUME_CTRL 0x0003180 369 + #define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0003184 370 + #define ACP_SW0_BUS_RESET_CTRL 0x0003188 371 + #define ACP_SW0_PRBS_ERR_STATUS 0x000318C 372 + #define ACP_SW0_IMM_CMD_UPPER_WORD 0x0003230 373 + #define ACP_SW0_IMM_CMD_LOWER_QWORD 0x0003234 374 + #define ACP_SW0_IMM_RESP_UPPER_WORD 0x0003238 375 + #define ACP_SW0_IMM_RESP_LOWER_QWORD 0x000323C 376 + #define ACP_SW0_IMM_CMD_STS 0x0003240 377 + #define ACP_SW0_BRA_BASE_ADDRESS 0x0003244 378 + #define ACP_SW0_BRA_TRANSFER_SIZE 0x0003248 379 + #define ACP_SW0_BRA_DMA_BUSY 0x000324C 380 + #define ACP_SW0_BRA_RESP 0x0003250 381 + #define ACP_SW0_BRA_RESP_FRAME_ADDR 0x0003254 382 + #define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x0003258 383 + #define ACP_SW0_STATECHANGE_STATUS_0TO7 0x000325C 384 + #define ACP_SW0_STATECHANGE_STATUS_8TO11 0x0003260 385 + #define ACP_SW0_STATECHANGE_STATUS_MASK_0TO7 0x0003264 386 + #define ACP_SW0_STATECHANGE_STATUS_MASK_8TO11 0x0003268 387 + #define ACP_SW0_CLK_FREQUENCY_CTRL 0x000326C 388 + #define ACP_SW0_ERROR_INTR_MASK 0x0003270 389 + #define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x0003274 372 390 373 391 /* Registers from ACP_P1_AUDIO_BUFFERS block */ 374 - #define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00 375 - #define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04 376 - #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08 377 - #define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C 378 - #define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10 379 - #define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14 380 - #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 381 - #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C 382 - #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20 383 - #define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24 384 - #define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28 385 - #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C 386 - #define ACP_P1_I2S_TX_FIFOADDR 0x0003A30 387 - #define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34 388 - #define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38 389 - #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C 390 - #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 391 - #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44 392 - #define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48 393 - #define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C 394 - #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50 395 - #define ACP_P1_BT_RX_FIFOADDR 0x0003A54 396 - #define ACP_P1_BT_RX_FIFOSIZE 0x0003A58 397 - #define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C 398 - #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 399 - #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 400 - #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68 401 - #define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C 402 - #define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70 403 - #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74 404 - #define ACP_P1_BT_TX_FIFOADDR 0x0003A78 405 - #define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C 406 - #define ACP_P1_BT_TX_DMA_SIZE 0x0003A80 407 - #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 408 - #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 409 - #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C 410 - #define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90 411 - #define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94 412 - #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98 413 - #define ACP_P1_HS_RX_FIFOADDR 0x0003A9C 414 - #define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0 415 - #define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4 416 - #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 417 - #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC 418 - #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0 419 - #define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4 420 - #define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8 421 - #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC 422 - #define ACP_P1_HS_TX_FIFOADDR 0x0003AC0 423 - #define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4 424 - #define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8 425 - #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC 426 - #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 427 - #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4 428 - #define ACP_P1_AUDIO_RX_RINGBUFADDR ACP_P1_I2S_RX_RINGBUFADDR 429 - #define ACP_P1_AUDIO_RX_RINGBUFSIZE ACP_P1_I2S_RX_RINGBUFSIZE 430 - #define ACP_P1_AUDIO_RX_LINKPOSITIONCNTR ACP_P1_I2S_RX_LINKPOSITIONCNTR 431 - #define ACP_P1_AUDIO_RX_FIFOADDR ACP_P1_I2S_RX_FIFOADDR 432 - #define ACP_P1_AUDIO_RX_FIFOSIZE ACP_P1_I2S_RX_FIFOSIZE 433 - #define ACP_P1_AUDIO_RX_DMA_SIZE ACP_P1_I2S_RX_DMA_SIZE 434 - #define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 435 - #define ACP_P1_AUDIO_RX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 436 - #define ACP_P1_AUDIO_RX_INTR_WATERMARK_SIZE ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 437 - #define ACP_P1_AUDIO_TX_RINGBUFADDR ACP_P1_I2S_TX_RINGBUFADDR 438 - #define ACP_P1_AUDIO_TX_RINGBUFSIZE ACP_P1_I2S_TX_RINGBUFSIZE 439 - #define ACP_P1_AUDIO_TX_LINKPOSITIONCNTR ACP_P1_I2S_TX_LINKPOSITIONCNTR 440 - #define ACP_P1_AUDIO_TX_FIFOADDR ACP_P1_I2S_TX_FIFOADDR 441 - #define ACP_P1_AUDIO_TX_FIFOSIZE ACP_P1_I2S_TX_FIFOSIZE 442 - #define ACP_P1_AUDIO_TX_DMA_SIZE ACP_P1_I2S_TX_DMA_SIZE 443 - #define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_HIGH ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 444 - #define ACP_P1_AUDIO_TX_LINEARPOSITIONCNTR_LOW ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 445 - #define ACP_P1_AUDIO_TX_INTR_WATERMARK_SIZE ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 392 + #define ACP_P1_AUDIO0_RX_RINGBUFADDR 0x0003A00 393 + #define ACP_P1_AUDIO0_RX_RINGBUFSIZE 0x0003A04 394 + #define ACP_P1_AUDIO0_RX_LINKPOSITIONCNTR 0x0003A08 395 + #define ACP_P1_AUDIO0_RX_FIFOADDR 0x0003A0C 396 + #define ACP_P1_AUDIO0_RX_FIFOSIZE 0x0003A10 397 + #define ACP_P1_AUDIO0_RX_DMA_SIZE 0x0003A14 398 + #define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 399 + #define ACP_P1_AUDIO0_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C 400 + #define ACP_P1_AUDIO0_RX_INTR_WATERMARK_SIZE 0x0003A20 401 + #define ACP_P1_AUDIO0_TX_RINGBUFADDR 0x0003A24 402 + #define ACP_P1_AUDIO0_TX_RINGBUFSIZE 0x0003A28 403 + #define ACP_P1_AUDIO0_TX_LINKPOSITIONCNTR 0x0003A2C 404 + #define ACP_P1_AUDIO0_TX_FIFOADDR 0x0003A30 405 + #define ACP_P1_AUDIO0_TX_FIFOSIZE 0x0003A34 406 + #define ACP_P1_AUDIO0_TX_DMA_SIZE 0x0003A38 407 + #define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C 408 + #define ACP_P1_AUDIO0_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 409 + #define ACP_P1_AUDIO0_TX_INTR_WATERMARK_SIZE 0x0003A44 410 + #define ACP_P1_AUDIO1_RX_RINGBUFADDR 0x0003A48 411 + #define ACP_P1_AUDIO1_RX_RINGBUFSIZE 0x0003A4C 412 + #define ACP_P1_AUDIO1_RX_LINKPOSITIONCNTR 0x0003A50 413 + #define ACP_P1_AUDIO1_RX_FIFOADDR 0x0003A54 414 + #define ACP_P1_AUDIO1_RX_FIFOSIZE 0x0003A58 415 + #define ACP_P1_AUDIO1_RX_DMA_SIZE 0x0003A5C 416 + #define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 417 + #define ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 418 + #define ACP_P1_AUDIO1_RX_INTR_WATERMARK_SIZE 0x0003A68 419 + #define ACP_P1_AUDIO1_TX_RINGBUFADDR 0x0003A6C 420 + #define ACP_P1_AUDIO1_TX_RINGBUFSIZE 0x0003A70 421 + #define ACP_P1_AUDIO1_TX_LINKPOSITIONCNTR 0x0003A74 422 + #define ACP_P1_AUDIO1_TX_FIFOADDR 0x0003A78 423 + #define ACP_P1_AUDIO1_TX_FIFOSIZE 0x0003A7C 424 + #define ACP_P1_AUDIO1_TX_DMA_SIZE 0x0003A80 425 + #define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 426 + #define ACP_P1_AUDIO1_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 427 + #define ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE 0x0003A8C 428 + #define ACP_P1_AUDIO2_RX_RINGBUFADDR 0x0003A90 429 + #define ACP_P1_AUDIO2_RX_RINGBUFSIZE 0x0003A94 430 + #define ACP_P1_AUDIO2_RX_LINKPOSITIONCNTR 0x0003A98 431 + #define ACP_P1_AUDIO2_RX_FIFOADDR 0x0003A9C 432 + #define ACP_P1_AUDIO2_RX_FIFOSIZE 0x0003AA0 433 + #define ACP_P1_AUDIO2_RX_DMA_SIZE 0x0003AA4 434 + #define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 435 + #define ACP_P1_AUDIO2_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC 436 + #define ACP_P1_AUDIO2_RX_INTR_WATERMARK_SIZE 0x0003AB0 437 + #define ACP_P1_AUDIO2_TX_RINGBUFADDR 0x0003AB4 438 + #define ACP_P1_AUDIO2_TX_RINGBUFSIZE 0x0003AB8 439 + #define ACP_P1_AUDIO2_TX_LINKPOSITIONCNTR 0x0003ABC 440 + #define ACP_P1_AUDIO2_TX_FIFOADDR 0x0003AC0 441 + #define ACP_P1_AUDIO2_TX_FIFOSIZE 0x0003AC4 442 + #define ACP_P1_AUDIO2_TX_DMA_SIZE 0x0003AC8 443 + #define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC 444 + #define ACP_P1_AUDIO2_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 445 + #define ACP_P1_AUDIO2_TX_INTR_WATERMARK_SIZE 0x0003AD4 446 446 447 - /* Registers from ACP_P1_SW_SWCLK block */ 448 - #define ACP_P1_SW_EN 0x0003C00 449 - #define ACP_P1_SW_EN_STATUS 0x0003C04 450 - #define ACP_P1_SW_FRAMESIZE 0x0003C08 451 - #define ACP_P1_SW_SSP_COUNTER 0x0003C0C 452 - #define ACP_P1_SW_BT_TX_EN 0x0003C50 453 - #define ACP_P1_SW_BT_TX_EN_STATUS 0x0003C54 454 - #define ACP_P1_SW_BT_TX_FRAME_FORMAT 0x0003C58 455 - #define ACP_P1_SW_BT_TX_SAMPLEINTERVAL 0x0003C5C 456 - #define ACP_P1_SW_BT_TX_HCTRL 0x0003C60 457 - #define ACP_P1_SW_BT_TX_OFFSET 0x0003C64 458 - #define ACP_P1_SW_BT_TX_CHANNEL_ENABLE_DP0 0x0003C68 459 - #define ACP_P1_SW_BT_RX_EN 0x0003D28 460 - #define ACP_P1_SW_BT_RX_EN_STATUS 0x0003D2C 461 - #define ACP_P1_SW_BT_RX_FRAME_FORMAT 0x0003D30 462 - #define ACP_P1_SW_BT_RX_SAMPLEINTERVAL 0x0003D34 463 - #define ACP_P1_SW_BT_RX_HCTRL 0x0003D38 464 - #define ACP_P1_SW_BT_RX_OFFSET 0x0003D3C 465 - #define ACP_P1_SW_BT_RX_CHANNEL_ENABLE_DP0 0x0003D40 466 - #define ACP_P1_SW_BPT_PORT_EN 0x0003D60 467 - #define ACP_P1_SW_BPT_PORT_EN_STATUS 0x0003D64 468 - #define ACP_P1_SW_BPT_PORT_FRAME_FORMAT 0x0003D68 469 - #define ACP_P1_SW_BPT_PORT_SAMPLEINTERVAL 0x0003D6C 470 - #define ACP_P1_SW_BPT_PORT_HCTRL 0x0003D70 471 - #define ACP_P1_SW_BPT_PORT_OFFSET 0x0003D74 472 - #define ACP_P1_SW_BPT_PORT_CHANNEL_ENABLE 0x0003D78 473 - #define ACP_P1_SW_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C 474 - #define ACP_P1_SW_CLK_RESUME_CTRL 0x0003D80 475 - #define ACP_P1_SW_CLK_RESUME_DELAY_CNTR 0x0003D84 476 - #define ACP_P1_SW_BUS_RESET_CTRL 0x0003D88 477 - #define ACP_P1_SW_PRBS_ERR_STATUS 0x0003D8C 447 + /* Registers from ACP_SW1_SWCLK block */ 448 + #define ACP_SW1_EN 0x0003C00 449 + #define ACP_SW1_EN_STATUS 0x0003C04 450 + #define ACP_SW1_FRAMESIZE 0x0003C08 451 + #define ACP_SW1_SSP_COUNTER 0x0003C0C 452 + #define ACP_SW1_AUDIO1_TX_EN 0x0003C50 453 + #define ACP_SW1_AUDIO1_TX_EN_STATUS 0x0003C54 454 + #define ACP_SW1_AUDIO1_TX_FRAME_FORMAT 0x0003C58 455 + #define ACP_SW1_AUDIO1_TX_SAMPLEINTERVAL 0x0003C5C 456 + #define ACP_SW1_AUDIO1_TX_HCTRL 0x0003C60 457 + #define ACP_SW1_AUDIO1_TX_OFFSET 0x0003C64 458 + #define ACP_SW1_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x0003C68 459 + #define ACP_SW1_AUDIO1_RX_EN 0x0003D28 460 + #define ACP_SW1_AUDIO1_RX_EN_STATUS 0x0003D2C 461 + #define ACP_SW1_AUDIO1_RX_FRAME_FORMAT 0x0003D30 462 + #define ACP_SW1_AUDIO1_RX_SAMPLEINTERVAL 0x0003D34 463 + #define ACP_SW1_AUDIO1_RX_HCTRL 0x0003D38 464 + #define ACP_SW1_AUDIO1_RX_OFFSET 0x0003D3C 465 + #define ACP_SW1_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x0003D40 466 + #define ACP_SW1_BPT_PORT_EN 0x0003D60 467 + #define ACP_SW1_BPT_PORT_EN_STATUS 0x0003D64 468 + #define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0003D68 469 + #define ACP_SW1_BPT_PORT_SAMPLEINTERVAL 0x0003D6C 470 + #define ACP_SW1_BPT_PORT_HCTRL 0x0003D70 471 + #define ACP_SW1_BPT_PORT_OFFSET 0x0003D74 472 + #define ACP_SW1_BPT_PORT_CHANNEL_ENABLE 0x0003D78 473 + #define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0003D7C 474 + #define ACP_SW1_CLK_RESUME_CTRL 0x0003D80 475 + #define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0003D84 476 + #define ACP_SW1_BUS_RESET_CTRL 0x0003D88 477 + #define ACP_SW1_PRBS_ERR_STATUS 0x0003D8C 478 478 479 - /* Registers from ACP_P1_SW_ACLK block */ 480 - #define P1_SW_CORB_BASE_ADDRESS 0x0003E00 481 - #define P1_SW_CORB_WRITE_POINTER 0x0003E04 482 - #define P1_SW_CORB_READ_POINTER 0x0003E08 483 - #define P1_SW_CORB_CONTROL 0x0003E0C 484 - #define P1_SW_CORB_SIZE 0x0003E14 485 - #define P1_SW_RIRB_BASE_ADDRESS 0x0003E18 486 - #define P1_SW_RIRB_WRITE_POINTER 0x0003E1C 487 - #define P1_SW_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20 488 - #define P1_SW_RIRB_CONTROL 0x0003E24 489 - #define P1_SW_RIRB_SIZE 0x0003E28 490 - #define P1_SW_RIRB_FIFO_MIN_THDL 0x0003E2C 491 - #define P1_SW_IMM_CMD_UPPER_WORD 0x0003E30 492 - #define P1_SW_IMM_CMD_LOWER_QWORD 0x0003E34 493 - #define P1_SW_IMM_RESP_UPPER_WORD 0x0003E38 494 - #define P1_SW_IMM_RESP_LOWER_QWORD 0x0003E3C 495 - #define P1_SW_IMM_CMD_STS 0x0003E40 496 - #define P1_SW_BRA_BASE_ADDRESS 0x0003E44 497 - #define P1_SW_BRA_TRANSFER_SIZE 0x0003E48 498 - #define P1_SW_BRA_DMA_BUSY 0x0003E4C 499 - #define P1_SW_BRA_RESP 0x0003E50 500 - #define P1_SW_BRA_RESP_FRAME_ADDR 0x0003E54 501 - #define P1_SW_BRA_CURRENT_TRANSFER_SIZE 0x0003E58 502 - #define P1_SW_STATE_CHANGE_STATUS_0TO7 0x0003E5C 503 - #define P1_SW_STATE_CHANGE_STATUS_8TO11 0x0003E60 504 - #define P1_SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003E64 505 - #define P1_SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003E68 506 - #define P1_SW_CLK_FREQUENCY_CTRL 0x0003E6C 507 - #define P1_SW_ERROR_INTR_MASK 0x0003E70 508 - #define P1_SW_PHY_TEST_MODE_DATA_OFF 0x0003E74 479 + /* Registers from ACP_SW1_ACLK block */ 480 + #define ACP_SW1_CORB_BASE_ADDRESS 0x0003E00 481 + #define ACP_SW1_CORB_WRITE_POINTER 0x0003E04 482 + #define ACP_SW1_CORB_READ_POINTER 0x0003E08 483 + #define ACP_SW1_CORB_CONTROL 0x0003E0C 484 + #define ACP_SW1_CORB_SIZE 0x0003E14 485 + #define ACP_SW1_RIRB_BASE_ADDRESS 0x0003E18 486 + #define ACP_SW1_RIRB_WRITE_POINTER 0x0003E1C 487 + #define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x0003E20 488 + #define ACP_SW1_RIRB_CONTROL 0x0003E24 489 + #define ACP_SW1_RIRB_SIZE 0x0003E28 490 + #define ACP_SW1_RIRB_FIFO_MIN_THDL 0x0003E2C 491 + #define ACP_SW1_IMM_CMD_UPPER_WORD 0x0003E30 492 + #define ACP_SW1_IMM_CMD_LOWER_QWORD 0x0003E34 493 + #define ACP_SW1_IMM_RESP_UPPER_WORD 0x0003E38 494 + #define ACP_SW1_IMM_RESP_LOWER_QWORD 0x0003E3C 495 + #define ACP_SW1_IMM_CMD_STS 0x0003E40 496 + #define ACP_SW1_BRA_BASE_ADDRESS 0x0003E44 497 + #define ACP_SW1_BRA_TRANSFER_SIZE 0x0003E48 498 + #define ACP_SW1_BRA_DMA_BUSY 0x0003E4C 499 + #define ACP_SW1_BRA_RESP 0x0003E50 500 + #define ACP_SW1_BRA_RESP_FRAME_ADDR 0x0003E54 501 + #define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x0003E58 502 + #define ACP_SW1_STATECHANGE_STATUS_0TO7 0x0003E5C 503 + #define ACP_SW1_STATECHANGE_STATUS_8TO11 0x0003E60 504 + #define ACP_SW1_STATECHANGE_STATUS_MASK_0TO7 0x0003E64 505 + #define ACP_SW1_STATECHANGE_STATUS_MASK_8TO11 0x0003E68 506 + #define ACP_SW1_CLK_FREQUENCY_CTRL 0x0003E6C 507 + #define ACP_SW1_ERROR_INTR_MASK 0x0003E70 508 + #define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x0003E74 509 509 510 510 /* Registers from ACP_SCRATCH block */ 511 - #define ACP_SCRATCH_REG_0 0x0010000 512 - #define ACP_SCRATCH_REG_1 0x0010004 513 - #define ACP_SCRATCH_REG_2 0x0010008 514 - #define ACP_SCRATCH_REG_3 0x001000C 515 - #define ACP_SCRATCH_REG_4 0x0010010 516 - #define ACP_SCRATCH_REG_5 0x0010014 517 - #define ACP_SCRATCH_REG_6 0x0010018 518 - #define ACP_SCRATCH_REG_7 0x001001C 519 - #define ACP_SCRATCH_REG_8 0x0010020 520 - #define ACP_SCRATCH_REG_9 0x0010024 521 - #define ACP_SCRATCH_REG_10 0x0010028 522 - #define ACP_SCRATCH_REG_11 0x001002C 523 - #define ACP_SCRATCH_REG_12 0x0010030 524 - #define ACP_SCRATCH_REG_13 0x0010034 525 - #define ACP_SCRATCH_REG_14 0x0010038 526 - #define ACP_SCRATCH_REG_15 0x001003C 527 - #define ACP_SCRATCH_REG_16 0x0010040 528 - #define ACP_SCRATCH_REG_17 0x0010044 529 - #define ACP_SCRATCH_REG_18 0x0010048 530 - #define ACP_SCRATCH_REG_19 0x001004C 531 - #define ACP_SCRATCH_REG_20 0x0010050 532 - #define ACP_SCRATCH_REG_21 0x0010054 533 - #define ACP_SCRATCH_REG_22 0x0010058 534 - #define ACP_SCRATCH_REG_23 0x001005C 535 - #define ACP_SCRATCH_REG_24 0x0010060 536 - #define ACP_SCRATCH_REG_25 0x0010064 537 - #define ACP_SCRATCH_REG_26 0x0010068 538 - #define ACP_SCRATCH_REG_27 0x001006C 539 - #define ACP_SCRATCH_REG_28 0x0010070 540 - #define ACP_SCRATCH_REG_29 0x0010074 541 - #define ACP_SCRATCH_REG_30 0x0010078 542 - #define ACP_SCRATCH_REG_31 0x001007C 543 - #define ACP_SCRATCH_REG_32 0x0010080 544 - #define ACP_SCRATCH_REG_33 0x0010084 545 - #define ACP_SCRATCH_REG_34 0x0010088 546 - #define ACP_SCRATCH_REG_35 0x001008C 547 - #define ACP_SCRATCH_REG_36 0x0010090 548 - #define ACP_SCRATCH_REG_37 0x0010094 549 - #define ACP_SCRATCH_REG_38 0x0010098 550 - #define ACP_SCRATCH_REG_39 0x001009C 551 - #define ACP_SCRATCH_REG_40 0x00100A0 552 - #define ACP_SCRATCH_REG_41 0x00100A4 553 - #define ACP_SCRATCH_REG_42 0x00100A8 554 - #define ACP_SCRATCH_REG_43 0x00100AC 555 - #define ACP_SCRATCH_REG_44 0x00100B0 556 - #define ACP_SCRATCH_REG_45 0x00100B4 557 - #define ACP_SCRATCH_REG_46 0x00100B8 558 - #define ACP_SCRATCH_REG_47 0x00100BC 559 - #define ACP_SCRATCH_REG_48 0x00100C0 560 - #define ACP_SCRATCH_REG_49 0x00100C4 561 - #define ACP_SCRATCH_REG_50 0x00100C8 562 - #define ACP_SCRATCH_REG_51 0x00100CC 563 - #define ACP_SCRATCH_REG_52 0x00100D0 564 - #define ACP_SCRATCH_REG_53 0x00100D4 565 - #define ACP_SCRATCH_REG_54 0x00100D8 566 - #define ACP_SCRATCH_REG_55 0x00100DC 567 - #define ACP_SCRATCH_REG_56 0x00100E0 568 - #define ACP_SCRATCH_REG_57 0x00100E4 569 - #define ACP_SCRATCH_REG_58 0x00100E8 570 - #define ACP_SCRATCH_REG_59 0x00100EC 571 - #define ACP_SCRATCH_REG_60 0x00100F0 572 - #define ACP_SCRATCH_REG_61 0x00100F4 573 - #define ACP_SCRATCH_REG_62 0x00100F8 574 - #define ACP_SCRATCH_REG_63 0x00100FC 575 - #define ACP_SCRATCH_REG_64 0x0010100 576 - #define ACP_SCRATCH_REG_65 0x0010104 577 - #define ACP_SCRATCH_REG_66 0x0010108 578 - #define ACP_SCRATCH_REG_67 0x001010C 579 - #define ACP_SCRATCH_REG_68 0x0010110 580 - #define ACP_SCRATCH_REG_69 0x0010114 581 - #define ACP_SCRATCH_REG_70 0x0010118 582 - #define ACP_SCRATCH_REG_71 0x001011C 583 - #define ACP_SCRATCH_REG_72 0x0010120 584 - #define ACP_SCRATCH_REG_73 0x0010124 585 - #define ACP_SCRATCH_REG_74 0x0010128 586 - #define ACP_SCRATCH_REG_75 0x001012C 587 - #define ACP_SCRATCH_REG_76 0x0010130 588 - #define ACP_SCRATCH_REG_77 0x0010134 589 - #define ACP_SCRATCH_REG_78 0x0010138 590 - #define ACP_SCRATCH_REG_79 0x001013C 591 - #define ACP_SCRATCH_REG_80 0x0010140 592 - #define ACP_SCRATCH_REG_81 0x0010144 593 - #define ACP_SCRATCH_REG_82 0x0010148 594 - #define ACP_SCRATCH_REG_83 0x001014C 595 - #define ACP_SCRATCH_REG_84 0x0010150 596 - #define ACP_SCRATCH_REG_85 0x0010154 597 - #define ACP_SCRATCH_REG_86 0x0010158 598 - #define ACP_SCRATCH_REG_87 0x001015C 599 - #define ACP_SCRATCH_REG_88 0x0010160 600 - #define ACP_SCRATCH_REG_89 0x0010164 601 - #define ACP_SCRATCH_REG_90 0x0010168 602 - #define ACP_SCRATCH_REG_91 0x001016C 603 - #define ACP_SCRATCH_REG_92 0x0010170 604 - #define ACP_SCRATCH_REG_93 0x0010174 605 - #define ACP_SCRATCH_REG_94 0x0010178 606 - #define ACP_SCRATCH_REG_95 0x001017C 607 - #define ACP_SCRATCH_REG_96 0x0010180 608 - #define ACP_SCRATCH_REG_97 0x0010184 609 - #define ACP_SCRATCH_REG_98 0x0010188 610 - #define ACP_SCRATCH_REG_99 0x001018C 611 - #define ACP_SCRATCH_REG_100 0x0010190 612 - #define ACP_SCRATCH_REG_101 0x0010194 613 - #define ACP_SCRATCH_REG_102 0x0010198 614 - #define ACP_SCRATCH_REG_103 0x001019C 615 - #define ACP_SCRATCH_REG_104 0x00101A0 616 - #define ACP_SCRATCH_REG_105 0x00101A4 617 - #define ACP_SCRATCH_REG_106 0x00101A8 618 - #define ACP_SCRATCH_REG_107 0x00101AC 619 - #define ACP_SCRATCH_REG_108 0x00101B0 620 - #define ACP_SCRATCH_REG_109 0x00101B4 621 - #define ACP_SCRATCH_REG_110 0x00101B8 622 - #define ACP_SCRATCH_REG_111 0x00101BC 623 - #define ACP_SCRATCH_REG_112 0x00101C0 624 - #define ACP_SCRATCH_REG_113 0x00101C4 625 - #define ACP_SCRATCH_REG_114 0x00101C8 626 - #define ACP_SCRATCH_REG_115 0x00101CC 627 - #define ACP_SCRATCH_REG_116 0x00101D0 628 - #define ACP_SCRATCH_REG_117 0x00101D4 629 - #define ACP_SCRATCH_REG_118 0x00101D8 630 - #define ACP_SCRATCH_REG_119 0x00101DC 631 - #define ACP_SCRATCH_REG_120 0x00101E0 632 - #define ACP_SCRATCH_REG_121 0x00101E4 633 - #define ACP_SCRATCH_REG_122 0x00101E8 634 - #define ACP_SCRATCH_REG_123 0x00101EC 635 - #define ACP_SCRATCH_REG_124 0x00101F0 636 - #define ACP_SCRATCH_REG_125 0x00101F4 637 - #define ACP_SCRATCH_REG_126 0x00101F8 638 - #define ACP_SCRATCH_REG_127 0x00101FC 639 - #define ACP_SCRATCH_REG_128 0x0010200 511 + #define ACP_SCRATCH_REG_0 0x0010000 512 + 640 513 #endif