Merge tag 'pwm/duty_offset-for-6.13-rc1' into togreg

+705 -152

drivers/pwm/core.c

··· 31 31 32 32 static DEFINE_IDR(pwm_chips); 33 33 34 + static void pwmchip_lock(struct pwm_chip *chip) 35 + { 36 + if (chip->atomic) 37 + spin_lock(&chip->atomic_lock); 38 + else 39 + mutex_lock(&chip->nonatomic_lock); 40 + } 41 + 42 + static void pwmchip_unlock(struct pwm_chip *chip) 43 + { 44 + if (chip->atomic) 45 + spin_unlock(&chip->atomic_lock); 46 + else 47 + mutex_unlock(&chip->nonatomic_lock); 48 + } 49 + 50 + DEFINE_GUARD(pwmchip, struct pwm_chip *, pwmchip_lock(_T), pwmchip_unlock(_T)) 51 + 52 + static bool pwm_wf_valid(const struct pwm_waveform *wf) 53 + { 54 + /* 55 + * For now restrict waveforms to period_length_ns <= S64_MAX to provide 56 + * some space for future extensions. One possibility is to simplify 57 + * representing waveforms with inverted polarity using negative values 58 + * somehow. 59 + */ 60 + if (wf->period_length_ns > S64_MAX) 61 + return false; 62 + 63 + if (wf->duty_length_ns > wf->period_length_ns) 64 + return false; 65 + 66 + /* 67 + * .duty_offset_ns is supposed to be smaller than .period_length_ns, apart 68 + * from the corner case .duty_offset_ns == 0 && .period_length_ns == 0. 69 + */ 70 + if (wf->duty_offset_ns && wf->duty_offset_ns >= wf->period_length_ns) 71 + return false; 72 + 73 + return true; 74 + } 75 + 76 + static void pwm_wf2state(const struct pwm_waveform *wf, struct pwm_state *state) 77 + { 78 + if (wf->period_length_ns) { 79 + if (wf->duty_length_ns + wf->duty_offset_ns < wf->period_length_ns) 80 + *state = (struct pwm_state){ 81 + .enabled = true, 82 + .polarity = PWM_POLARITY_NORMAL, 83 + .period = wf->period_length_ns, 84 + .duty_cycle = wf->duty_length_ns, 85 + }; 86 + else 87 + *state = (struct pwm_state){ 88 + .enabled = true, 89 + .polarity = PWM_POLARITY_INVERSED, 90 + .period = wf->period_length_ns, 91 + .duty_cycle = wf->period_length_ns - wf->duty_length_ns, 92 + }; 93 + } else { 94 + *state = (struct pwm_state){ 95 + .enabled = false, 96 + }; 97 + } 98 + } 99 + 100 + static void pwm_state2wf(const struct pwm_state *state, struct pwm_waveform *wf) 101 + { 102 + if (state->enabled) { 103 + if (state->polarity == PWM_POLARITY_NORMAL) 104 + *wf = (struct pwm_waveform){ 105 + .period_length_ns = state->period, 106 + .duty_length_ns = state->duty_cycle, 107 + .duty_offset_ns = 0, 108 + }; 109 + else 110 + *wf = (struct pwm_waveform){ 111 + .period_length_ns = state->period, 112 + .duty_length_ns = state->period - state->duty_cycle, 113 + .duty_offset_ns = state->duty_cycle, 114 + }; 115 + } else { 116 + *wf = (struct pwm_waveform){ 117 + .period_length_ns = 0, 118 + }; 119 + } 120 + } 121 + 122 + static int pwmwfcmp(const struct pwm_waveform *a, const struct pwm_waveform *b) 123 + { 124 + if (a->period_length_ns > b->period_length_ns) 125 + return 1; 126 + 127 + if (a->period_length_ns < b->period_length_ns) 128 + return -1; 129 + 130 + if (a->duty_length_ns > b->duty_length_ns) 131 + return 1; 132 + 133 + if (a->duty_length_ns < b->duty_length_ns) 134 + return -1; 135 + 136 + if (a->duty_offset_ns > b->duty_offset_ns) 137 + return 1; 138 + 139 + if (a->duty_offset_ns < b->duty_offset_ns) 140 + return -1; 141 + 142 + return 0; 143 + } 144 + 145 + static bool pwm_check_rounding(const struct pwm_waveform *wf, 146 + const struct pwm_waveform *wf_rounded) 147 + { 148 + if (!wf->period_length_ns) 149 + return true; 150 + 151 + if (wf->period_length_ns < wf_rounded->period_length_ns) 152 + return false; 153 + 154 + if (wf->duty_length_ns < wf_rounded->duty_length_ns) 155 + return false; 156 + 157 + if (wf->duty_offset_ns < wf_rounded->duty_offset_ns) 158 + return false; 159 + 160 + return true; 161 + } 162 + 163 + static int __pwm_round_waveform_tohw(struct pwm_chip *chip, struct pwm_device *pwm, 164 + const struct pwm_waveform *wf, void *wfhw) 165 + { 166 + const struct pwm_ops *ops = chip->ops; 167 + int ret; 168 + 169 + ret = ops->round_waveform_tohw(chip, pwm, wf, wfhw); 170 + trace_pwm_round_waveform_tohw(pwm, wf, wfhw, ret); 171 + 172 + return ret; 173 + } 174 + 175 + static int __pwm_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm, 176 + const void *wfhw, struct pwm_waveform *wf) 177 + { 178 + const struct pwm_ops *ops = chip->ops; 179 + int ret; 180 + 181 + ret = ops->round_waveform_fromhw(chip, pwm, wfhw, wf); 182 + trace_pwm_round_waveform_fromhw(pwm, wfhw, wf, ret); 183 + 184 + return ret; 185 + } 186 + 187 + static int __pwm_read_waveform(struct pwm_chip *chip, struct pwm_device *pwm, void *wfhw) 188 + { 189 + const struct pwm_ops *ops = chip->ops; 190 + int ret; 191 + 192 + ret = ops->read_waveform(chip, pwm, wfhw); 193 + trace_pwm_read_waveform(pwm, wfhw, ret); 194 + 195 + return ret; 196 + } 197 + 198 + static int __pwm_write_waveform(struct pwm_chip *chip, struct pwm_device *pwm, const void *wfhw) 199 + { 200 + const struct pwm_ops *ops = chip->ops; 201 + int ret; 202 + 203 + ret = ops->write_waveform(chip, pwm, wfhw); 204 + trace_pwm_write_waveform(pwm, wfhw, ret); 205 + 206 + return ret; 207 + } 208 + 209 + #define WFHWSIZE 20 210 + 211 + /** 212 + * pwm_round_waveform_might_sleep - Query hardware capabilities 213 + * Cannot be used in atomic context. 214 + * @pwm: PWM device 215 + * @wf: waveform to round and output parameter 216 + * 217 + * Typically a given waveform cannot be implemented exactly by hardware, e.g. 218 + * because hardware only supports coarse period resolution or no duty_offset. 219 + * This function returns the actually implemented waveform if you pass wf to 220 + * pwm_set_waveform_might_sleep now. 221 + * 222 + * Note however that the world doesn't stop turning when you call it, so when 223 + * doing 224 + * 225 + * pwm_round_waveform_might_sleep(mypwm, &wf); 226 + * pwm_set_waveform_might_sleep(mypwm, &wf, true); 227 + * 228 + * the latter might fail, e.g. because an input clock changed its rate between 229 + * these two calls and the waveform determined by 230 + * pwm_round_waveform_might_sleep() cannot be implemented any more. 231 + * 232 + * Returns 0 on success, 1 if there is no valid hardware configuration matching 233 + * the input waveform under the PWM rounding rules or a negative errno. 234 + */ 235 + int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf) 236 + { 237 + struct pwm_chip *chip = pwm->chip; 238 + const struct pwm_ops *ops = chip->ops; 239 + struct pwm_waveform wf_req = *wf; 240 + char wfhw[WFHWSIZE]; 241 + int ret_tohw, ret_fromhw; 242 + 243 + BUG_ON(WFHWSIZE < ops->sizeof_wfhw); 244 + 245 + if (!pwm_wf_valid(wf)) 246 + return -EINVAL; 247 + 248 + guard(pwmchip)(chip); 249 + 250 + if (!chip->operational) 251 + return -ENODEV; 252 + 253 + ret_tohw = __pwm_round_waveform_tohw(chip, pwm, wf, wfhw); 254 + if (ret_tohw < 0) 255 + return ret_tohw; 256 + 257 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && ret_tohw > 1) 258 + dev_err(&chip->dev, "Unexpected return value from __pwm_round_waveform_tohw: requested %llu/%llu [+%llu], return value %d\n", 259 + wf_req.duty_length_ns, wf_req.period_length_ns, wf_req.duty_offset_ns, ret_tohw); 260 + 261 + ret_fromhw = __pwm_round_waveform_fromhw(chip, pwm, wfhw, wf); 262 + if (ret_fromhw < 0) 263 + return ret_fromhw; 264 + 265 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && ret_fromhw > 0) 266 + dev_err(&chip->dev, "Unexpected return value from __pwm_round_waveform_fromhw: requested %llu/%llu [+%llu], return value %d\n", 267 + wf_req.duty_length_ns, wf_req.period_length_ns, wf_req.duty_offset_ns, ret_tohw); 268 + 269 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && 270 + ret_tohw == 0 && !pwm_check_rounding(&wf_req, wf)) 271 + dev_err(&chip->dev, "Wrong rounding: requested %llu/%llu [+%llu], result %llu/%llu [+%llu]\n", 272 + wf_req.duty_length_ns, wf_req.period_length_ns, wf_req.duty_offset_ns, 273 + wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns); 274 + 275 + return ret_tohw; 276 + } 277 + EXPORT_SYMBOL_GPL(pwm_round_waveform_might_sleep); 278 + 279 + /** 280 + * pwm_get_waveform_might_sleep - Query hardware about current configuration 281 + * Cannot be used in atomic context. 282 + * @pwm: PWM device 283 + * @wf: output parameter 284 + * 285 + * Stores the current configuration of the PWM in @wf. Note this is the 286 + * equivalent of pwm_get_state_hw() (and not pwm_get_state()) for pwm_waveform. 287 + */ 288 + int pwm_get_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf) 289 + { 290 + struct pwm_chip *chip = pwm->chip; 291 + const struct pwm_ops *ops = chip->ops; 292 + char wfhw[WFHWSIZE]; 293 + int err; 294 + 295 + BUG_ON(WFHWSIZE < ops->sizeof_wfhw); 296 + 297 + guard(pwmchip)(chip); 298 + 299 + if (!chip->operational) 300 + return -ENODEV; 301 + 302 + err = __pwm_read_waveform(chip, pwm, &wfhw); 303 + if (err) 304 + return err; 305 + 306 + return __pwm_round_waveform_fromhw(chip, pwm, &wfhw, wf); 307 + } 308 + EXPORT_SYMBOL_GPL(pwm_get_waveform_might_sleep); 309 + 310 + /* Called with the pwmchip lock held */ 311 + static int __pwm_set_waveform(struct pwm_device *pwm, 312 + const struct pwm_waveform *wf, 313 + bool exact) 314 + { 315 + struct pwm_chip *chip = pwm->chip; 316 + const struct pwm_ops *ops = chip->ops; 317 + char wfhw[WFHWSIZE]; 318 + struct pwm_waveform wf_rounded; 319 + int err; 320 + 321 + BUG_ON(WFHWSIZE < ops->sizeof_wfhw); 322 + 323 + if (!pwm_wf_valid(wf)) 324 + return -EINVAL; 325 + 326 + err = __pwm_round_waveform_tohw(chip, pwm, wf, &wfhw); 327 + if (err) 328 + return err; 329 + 330 + if ((IS_ENABLED(CONFIG_PWM_DEBUG) || exact) && wf->period_length_ns) { 331 + err = __pwm_round_waveform_fromhw(chip, pwm, &wfhw, &wf_rounded); 332 + if (err) 333 + return err; 334 + 335 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && !pwm_check_rounding(wf, &wf_rounded)) 336 + dev_err(&chip->dev, "Wrong rounding: requested %llu/%llu [+%llu], result %llu/%llu [+%llu]\n", 337 + wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, 338 + wf_rounded.duty_length_ns, wf_rounded.period_length_ns, wf_rounded.duty_offset_ns); 339 + 340 + if (exact && pwmwfcmp(wf, &wf_rounded)) { 341 + dev_dbg(&chip->dev, "Requested no rounding, but %llu/%llu [+%llu] -> %llu/%llu [+%llu]\n", 342 + wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, 343 + wf_rounded.duty_length_ns, wf_rounded.period_length_ns, wf_rounded.duty_offset_ns); 344 + 345 + return 1; 346 + } 347 + } 348 + 349 + err = __pwm_write_waveform(chip, pwm, &wfhw); 350 + if (err) 351 + return err; 352 + 353 + /* update .state */ 354 + pwm_wf2state(wf, &pwm->state); 355 + 356 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && ops->read_waveform && wf->period_length_ns) { 357 + struct pwm_waveform wf_set; 358 + 359 + err = __pwm_read_waveform(chip, pwm, &wfhw); 360 + if (err) 361 + /* maybe ignore? */ 362 + return err; 363 + 364 + err = __pwm_round_waveform_fromhw(chip, pwm, &wfhw, &wf_set); 365 + if (err) 366 + /* maybe ignore? */ 367 + return err; 368 + 369 + if (pwmwfcmp(&wf_set, &wf_rounded) != 0) 370 + dev_err(&chip->dev, 371 + "Unexpected setting: requested %llu/%llu [+%llu], expected %llu/%llu [+%llu], set %llu/%llu [+%llu]\n", 372 + wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, 373 + wf_rounded.duty_length_ns, wf_rounded.period_length_ns, wf_rounded.duty_offset_ns, 374 + wf_set.duty_length_ns, wf_set.period_length_ns, wf_set.duty_offset_ns); 375 + } 376 + return 0; 377 + } 378 + 379 + /** 380 + * pwm_set_waveform_might_sleep - Apply a new waveform 381 + * Cannot be used in atomic context. 382 + * @pwm: PWM device 383 + * @wf: The waveform to apply 384 + * @exact: If true no rounding is allowed 385 + * 386 + * Typically a requested waveform cannot be implemented exactly, e.g. because 387 + * you requested .period_length_ns = 100 ns, but the hardware can only set 388 + * periods that are a multiple of 8.5 ns. With that hardware passing exact = 389 + * true results in pwm_set_waveform_might_sleep() failing and returning 1. If 390 + * exact = false you get a period of 93.5 ns (i.e. the biggest period not bigger 391 + * than the requested value). 392 + * Note that even with exact = true, some rounding by less than 1 is 393 + * possible/needed. In the above example requesting .period_length_ns = 94 and 394 + * exact = true, you get the hardware configured with period = 93.5 ns. 395 + */ 396 + int pwm_set_waveform_might_sleep(struct pwm_device *pwm, 397 + const struct pwm_waveform *wf, bool exact) 398 + { 399 + struct pwm_chip *chip = pwm->chip; 400 + int err; 401 + 402 + might_sleep(); 403 + 404 + guard(pwmchip)(chip); 405 + 406 + if (!chip->operational) 407 + return -ENODEV; 408 + 409 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && chip->atomic) { 410 + /* 411 + * Catch any drivers that have been marked as atomic but 412 + * that will sleep anyway. 413 + */ 414 + non_block_start(); 415 + err = __pwm_set_waveform(pwm, wf, exact); 416 + non_block_end(); 417 + } else { 418 + err = __pwm_set_waveform(pwm, wf, exact); 419 + } 420 + 421 + return err; 422 + } 423 + EXPORT_SYMBOL_GPL(pwm_set_waveform_might_sleep); 424 + 34 425 static void pwm_apply_debug(struct pwm_device *pwm, 35 426 const struct pwm_state *state) 36 427 { ··· 555 164 static int __pwm_apply(struct pwm_device *pwm, const struct pwm_state *state) 556 165 { 557 166 struct pwm_chip *chip; 167 + const struct pwm_ops *ops; 558 168 int err; 559 169 560 170 if (!pwm || !state) ··· 579 187 } 580 188 581 189 chip = pwm->chip; 190 + ops = chip->ops; 582 191 583 192 if (state->period == pwm->state.period && 584 193 state->duty_cycle == pwm->state.duty_cycle && ··· 588 195 state->usage_power == pwm->state.usage_power) 589 196 return 0; 590 197 591 - err = chip->ops->apply(chip, pwm, state); 592 - trace_pwm_apply(pwm, state, err); 593 - if (err) 594 - return err; 198 + if (ops->write_waveform) { 199 + struct pwm_waveform wf; 200 + char wfhw[WFHWSIZE]; 595 201 596 - pwm->state = *state; 202 + BUG_ON(WFHWSIZE < ops->sizeof_wfhw); 597 203 598 - /* 599 - * only do this after pwm->state was applied as some 600 - * implementations of .get_state depend on this 601 - */ 602 - pwm_apply_debug(pwm, state); 204 + pwm_state2wf(state, &wf); 205 + 206 + /* 207 + * The rounding is wrong here for states with inverted polarity. 208 + * While .apply() rounds down duty_cycle (which represents the 209 + * time from the start of the period to the inner edge), 210 + * .round_waveform_tohw() rounds down the time the PWM is high. 211 + * Can be fixed if the need arises, until reported otherwise 212 + * let's assume that consumers don't care. 213 + */ 214 + 215 + err = __pwm_round_waveform_tohw(chip, pwm, &wf, &wfhw); 216 + if (err) { 217 + if (err > 0) 218 + /* 219 + * This signals an invalid request, typically 220 + * the requested period (or duty_offset) is 221 + * smaller than possible with the hardware. 222 + */ 223 + return -EINVAL; 224 + 225 + return err; 226 + } 227 + 228 + if (IS_ENABLED(CONFIG_PWM_DEBUG)) { 229 + struct pwm_waveform wf_rounded; 230 + 231 + err = __pwm_round_waveform_fromhw(chip, pwm, &wfhw, &wf_rounded); 232 + if (err) 233 + return err; 234 + 235 + if (!pwm_check_rounding(&wf, &wf_rounded)) 236 + dev_err(&chip->dev, "Wrong rounding: requested %llu/%llu [+%llu], result %llu/%llu [+%llu]\n", 237 + wf.duty_length_ns, wf.period_length_ns, wf.duty_offset_ns, 238 + wf_rounded.duty_length_ns, wf_rounded.period_length_ns, wf_rounded.duty_offset_ns); 239 + } 240 + 241 + err = __pwm_write_waveform(chip, pwm, &wfhw); 242 + if (err) 243 + return err; 244 + 245 + pwm->state = *state; 246 + 247 + } else { 248 + err = ops->apply(chip, pwm, state); 249 + trace_pwm_apply(pwm, state, err); 250 + if (err) 251 + return err; 252 + 253 + pwm->state = *state; 254 + 255 + /* 256 + * only do this after pwm->state was applied as some 257 + * implementations of .get_state() depend on this 258 + */ 259 + pwm_apply_debug(pwm, state); 260 + } 603 261 604 262 return 0; 605 263 } ··· 664 220 int pwm_apply_might_sleep(struct pwm_device *pwm, const struct pwm_state *state) 665 221 { 666 222 int err; 223 + struct pwm_chip *chip = pwm->chip; 667 224 668 225 /* 669 226 * Some lowlevel driver's implementations of .apply() make use of ··· 675 230 */ 676 231 might_sleep(); 677 232 678 - if (IS_ENABLED(CONFIG_PWM_DEBUG) && pwm->chip->atomic) { 233 + guard(pwmchip)(chip); 234 + 235 + if (!chip->operational) 236 + return -ENODEV; 237 + 238 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && chip->atomic) { 679 239 /* 680 240 * Catch any drivers that have been marked as atomic but 681 241 * that will sleep anyway. ··· 704 254 */ 705 255 int pwm_apply_atomic(struct pwm_device *pwm, const struct pwm_state *state) 706 256 { 707 - WARN_ONCE(!pwm->chip->atomic, 257 + struct pwm_chip *chip = pwm->chip; 258 + 259 + WARN_ONCE(!chip->atomic, 708 260 "sleeping PWM driver used in atomic context\n"); 261 + 262 + guard(pwmchip)(chip); 263 + 264 + if (!chip->operational) 265 + return -ENODEV; 709 266 710 267 return __pwm_apply(pwm, state); 711 268 } 712 269 EXPORT_SYMBOL_GPL(pwm_apply_atomic); 270 + 271 + static int pwm_get_state_hw(struct pwm_device *pwm, struct pwm_state *state) 272 + { 273 + struct pwm_chip *chip = pwm->chip; 274 + const struct pwm_ops *ops = chip->ops; 275 + int ret = -EOPNOTSUPP; 276 + 277 + if (ops->read_waveform) { 278 + char wfhw[WFHWSIZE]; 279 + struct pwm_waveform wf; 280 + 281 + BUG_ON(WFHWSIZE < ops->sizeof_wfhw); 282 + 283 + scoped_guard(pwmchip, chip) { 284 + 285 + ret = __pwm_read_waveform(chip, pwm, &wfhw); 286 + if (ret) 287 + return ret; 288 + 289 + ret = __pwm_round_waveform_fromhw(chip, pwm, &wfhw, &wf); 290 + if (ret) 291 + return ret; 292 + } 293 + 294 + pwm_wf2state(&wf, state); 295 + 296 + } else if (ops->get_state) { 297 + scoped_guard(pwmchip, chip) 298 + ret = ops->get_state(chip, pwm, state); 299 + 300 + trace_pwm_get(pwm, state, ret); 301 + } 302 + 303 + return ret; 304 + } 713 305 714 306 /** 715 307 * pwm_adjust_config() - adjust the current PWM config to the PWM arguments ··· 826 334 if (!ops->capture) 827 335 return -ENOSYS; 828 336 337 + /* 338 + * Holding the pwm_lock is probably not needed. If you use pwm_capture() 339 + * and you're interested to speed it up, please convince yourself it's 340 + * really not needed, test and then suggest a patch on the mailing list. 341 + */ 829 342 guard(mutex)(&pwm_lock); 343 + 344 + guard(pwmchip)(chip); 345 + 346 + if (!chip->operational) 347 + return -ENODEV; 830 348 831 349 return ops->capture(chip, pwm, result, timeout); 832 350 } ··· 870 368 if (test_bit(PWMF_REQUESTED, &pwm->flags)) 871 369 return -EBUSY; 872 370 371 + /* 372 + * This function is called while holding pwm_lock. As .operational only 373 + * changes while holding this lock, checking it here without holding the 374 + * chip lock is fine. 375 + */ 376 + if (!chip->operational) 377 + return -ENODEV; 378 + 873 379 if (!try_module_get(chip->owner)) 874 380 return -ENODEV; 875 381 ··· 896 386 } 897 387 } 898 388 899 - if (ops->get_state) { 389 + if (ops->read_waveform || ops->get_state) { 900 390 /* 901 391 * Zero-initialize state because most drivers are unaware of 902 392 * .usage_power. The other members of state are supposed to be ··· 906 396 */ 907 397 struct pwm_state state = { 0, }; 908 398 909 - err = ops->get_state(chip, pwm, &state); 910 - trace_pwm_get(pwm, &state, err); 911 - 399 + err = pwm_get_state_hw(pwm, &state); 912 400 if (!err) 913 401 pwm->state = state; 914 402 ··· 1528 1020 1529 1021 chip->npwm = npwm; 1530 1022 chip->uses_pwmchip_alloc = true; 1023 + chip->operational = false; 1531 1024 1532 1025 pwmchip_dev = &chip->dev; 1533 1026 device_initialize(pwmchip_dev); ··· 1593 1084 { 1594 1085 const struct pwm_ops *ops = chip->ops; 1595 1086 1596 - if (!ops->apply) 1597 - return false; 1087 + if (ops->write_waveform) { 1088 + if (!ops->round_waveform_tohw || 1089 + !ops->round_waveform_fromhw || 1090 + !ops->write_waveform) 1091 + return false; 1598 1092 1599 - if (IS_ENABLED(CONFIG_PWM_DEBUG) && !ops->get_state) 1600 - dev_warn(pwmchip_parent(chip), 1601 - "Please implement the .get_state() callback\n"); 1093 + if (WFHWSIZE < ops->sizeof_wfhw) { 1094 + dev_warn(pwmchip_parent(chip), "WFHWSIZE < %zu\n", ops->sizeof_wfhw); 1095 + return false; 1096 + } 1097 + } else { 1098 + if (!ops->apply) 1099 + return false; 1100 + 1101 + if (IS_ENABLED(CONFIG_PWM_DEBUG) && !ops->get_state) 1102 + dev_warn(pwmchip_parent(chip), 1103 + "Please implement the .get_state() callback\n"); 1104 + } 1602 1105 1603 1106 return true; 1604 1107 } 1605 - 1606 - /** 1607 - * __pwmchip_add() - register a new PWM chip 1608 - * @chip: the PWM chip to add 1609 - * @owner: reference to the module providing the chip. 1610 - * 1611 - * Register a new PWM chip. @owner is supposed to be THIS_MODULE, use the 1612 - * pwmchip_add wrapper to do this right. 1613 - * 1614 - * Returns: 0 on success or a negative error code on failure. 1615 - */ 1616 - int __pwmchip_add(struct pwm_chip *chip, struct module *owner) 1617 - { 1618 - int ret; 1619 - 1620 - if (!chip || !pwmchip_parent(chip) || !chip->ops || !chip->npwm) 1621 - return -EINVAL; 1622 - 1623 - /* 1624 - * a struct pwm_chip must be allocated using (devm_)pwmchip_alloc, 1625 - * otherwise the embedded struct device might disappear too early 1626 - * resulting in memory corruption. 1627 - * Catch drivers that were not converted appropriately. 1628 - */ 1629 - if (!chip->uses_pwmchip_alloc) 1630 - return -EINVAL; 1631 - 1632 - if (!pwm_ops_check(chip)) 1633 - return -EINVAL; 1634 - 1635 - chip->owner = owner; 1636 - 1637 - guard(mutex)(&pwm_lock); 1638 - 1639 - ret = idr_alloc(&pwm_chips, chip, 0, 0, GFP_KERNEL); 1640 - if (ret < 0) 1641 - return ret; 1642 - 1643 - chip->id = ret; 1644 - 1645 - dev_set_name(&chip->dev, "pwmchip%u", chip->id); 1646 - 1647 - if (IS_ENABLED(CONFIG_OF)) 1648 - of_pwmchip_add(chip); 1649 - 1650 - ret = device_add(&chip->dev); 1651 - if (ret) 1652 - goto err_device_add; 1653 - 1654 - return 0; 1655 - 1656 - err_device_add: 1657 - if (IS_ENABLED(CONFIG_OF)) 1658 - of_pwmchip_remove(chip); 1659 - 1660 - idr_remove(&pwm_chips, chip->id); 1661 - 1662 - return ret; 1663 - } 1664 - EXPORT_SYMBOL_GPL(__pwmchip_add); 1665 - 1666 - /** 1667 - * pwmchip_remove() - remove a PWM chip 1668 - * @chip: the PWM chip to remove 1669 - * 1670 - * Removes a PWM chip. 1671 - */ 1672 - void pwmchip_remove(struct pwm_chip *chip) 1673 - { 1674 - pwmchip_sysfs_unexport(chip); 1675 - 1676 - if (IS_ENABLED(CONFIG_OF)) 1677 - of_pwmchip_remove(chip); 1678 - 1679 - scoped_guard(mutex, &pwm_lock) 1680 - idr_remove(&pwm_chips, chip->id); 1681 - 1682 - device_del(&chip->dev); 1683 - } 1684 - EXPORT_SYMBOL_GPL(pwmchip_remove); 1685 - 1686 - static void devm_pwmchip_remove(void *data) 1687 - { 1688 - struct pwm_chip *chip = data; 1689 - 1690 - pwmchip_remove(chip); 1691 - } 1692 - 1693 - int __devm_pwmchip_add(struct device *dev, struct pwm_chip *chip, struct module *owner) 1694 - { 1695 - int ret; 1696 - 1697 - ret = __pwmchip_add(chip, owner); 1698 - if (ret) 1699 - return ret; 1700 - 1701 - return devm_add_action_or_reset(dev, devm_pwmchip_remove, chip); 1702 - } 1703 - EXPORT_SYMBOL_GPL(__devm_pwmchip_add); 1704 1108 1705 1109 static struct device_link *pwm_device_link_add(struct device *dev, 1706 1110 struct pwm_device *pwm) ··· 1793 1371 static LIST_HEAD(pwm_lookup_list); 1794 1372 1795 1373 /** 1796 - * pwm_add_table() - register PWM device consumers 1797 - * @table: array of consumers to register 1798 - * @num: number of consumers in table 1799 - */ 1800 - void pwm_add_table(struct pwm_lookup *table, size_t num) 1801 - { 1802 - guard(mutex)(&pwm_lookup_lock); 1803 - 1804 - while (num--) { 1805 - list_add_tail(&table->list, &pwm_lookup_list); 1806 - table++; 1807 - } 1808 - } 1809 - 1810 - /** 1811 - * pwm_remove_table() - unregister PWM device consumers 1812 - * @table: array of consumers to unregister 1813 - * @num: number of consumers in table 1814 - */ 1815 - void pwm_remove_table(struct pwm_lookup *table, size_t num) 1816 - { 1817 - guard(mutex)(&pwm_lookup_lock); 1818 - 1819 - while (num--) { 1820 - list_del(&table->list); 1821 - table++; 1822 - } 1823 - } 1824 - 1825 - /** 1826 1374 * pwm_get() - look up and request a PWM device 1827 1375 * @dev: device for PWM consumer 1828 1376 * @con_id: consumer name ··· 1930 1538 1931 1539 guard(mutex)(&pwm_lock); 1932 1540 1933 - if (!test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) { 1541 + /* 1542 + * Trigger a warning if a consumer called pwm_put() twice. 1543 + * If the chip isn't operational, PWMF_REQUESTED was already cleared in 1544 + * pwmchip_remove(). So don't warn in this case. 1545 + */ 1546 + if (chip->operational && !test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) { 1934 1547 pr_warn("PWM device already freed\n"); 1935 1548 return; 1936 1549 } 1937 1550 1938 - if (chip->ops->free) 1551 + if (chip->operational && chip->ops->free) 1939 1552 pwm->chip->ops->free(pwm->chip, pwm); 1940 1553 1941 1554 pwm->label = NULL; ··· 2017 1620 return pwm; 2018 1621 } 2019 1622 EXPORT_SYMBOL_GPL(devm_fwnode_pwm_get); 1623 + 1624 + /** 1625 + * __pwmchip_add() - register a new PWM chip 1626 + * @chip: the PWM chip to add 1627 + * @owner: reference to the module providing the chip. 1628 + * 1629 + * Register a new PWM chip. @owner is supposed to be THIS_MODULE, use the 1630 + * pwmchip_add wrapper to do this right. 1631 + * 1632 + * Returns: 0 on success or a negative error code on failure. 1633 + */ 1634 + int __pwmchip_add(struct pwm_chip *chip, struct module *owner) 1635 + { 1636 + int ret; 1637 + 1638 + if (!chip || !pwmchip_parent(chip) || !chip->ops || !chip->npwm) 1639 + return -EINVAL; 1640 + 1641 + /* 1642 + * a struct pwm_chip must be allocated using (devm_)pwmchip_alloc, 1643 + * otherwise the embedded struct device might disappear too early 1644 + * resulting in memory corruption. 1645 + * Catch drivers that were not converted appropriately. 1646 + */ 1647 + if (!chip->uses_pwmchip_alloc) 1648 + return -EINVAL; 1649 + 1650 + if (!pwm_ops_check(chip)) 1651 + return -EINVAL; 1652 + 1653 + chip->owner = owner; 1654 + 1655 + if (chip->atomic) 1656 + spin_lock_init(&chip->atomic_lock); 1657 + else 1658 + mutex_init(&chip->nonatomic_lock); 1659 + 1660 + guard(mutex)(&pwm_lock); 1661 + 1662 + ret = idr_alloc(&pwm_chips, chip, 0, 0, GFP_KERNEL); 1663 + if (ret < 0) 1664 + return ret; 1665 + 1666 + chip->id = ret; 1667 + 1668 + dev_set_name(&chip->dev, "pwmchip%u", chip->id); 1669 + 1670 + if (IS_ENABLED(CONFIG_OF)) 1671 + of_pwmchip_add(chip); 1672 + 1673 + scoped_guard(pwmchip, chip) 1674 + chip->operational = true; 1675 + 1676 + ret = device_add(&chip->dev); 1677 + if (ret) 1678 + goto err_device_add; 1679 + 1680 + return 0; 1681 + 1682 + err_device_add: 1683 + scoped_guard(pwmchip, chip) 1684 + chip->operational = false; 1685 + 1686 + if (IS_ENABLED(CONFIG_OF)) 1687 + of_pwmchip_remove(chip); 1688 + 1689 + idr_remove(&pwm_chips, chip->id); 1690 + 1691 + return ret; 1692 + } 1693 + EXPORT_SYMBOL_GPL(__pwmchip_add); 1694 + 1695 + /** 1696 + * pwmchip_remove() - remove a PWM chip 1697 + * @chip: the PWM chip to remove 1698 + * 1699 + * Removes a PWM chip. 1700 + */ 1701 + void pwmchip_remove(struct pwm_chip *chip) 1702 + { 1703 + pwmchip_sysfs_unexport(chip); 1704 + 1705 + scoped_guard(mutex, &pwm_lock) { 1706 + unsigned int i; 1707 + 1708 + scoped_guard(pwmchip, chip) 1709 + chip->operational = false; 1710 + 1711 + for (i = 0; i < chip->npwm; ++i) { 1712 + struct pwm_device *pwm = &chip->pwms[i]; 1713 + 1714 + if (test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) { 1715 + dev_warn(&chip->dev, "Freeing requested PWM #%u\n", i); 1716 + if (pwm->chip->ops->free) 1717 + pwm->chip->ops->free(pwm->chip, pwm); 1718 + } 1719 + } 1720 + 1721 + if (IS_ENABLED(CONFIG_OF)) 1722 + of_pwmchip_remove(chip); 1723 + 1724 + idr_remove(&pwm_chips, chip->id); 1725 + } 1726 + 1727 + device_del(&chip->dev); 1728 + } 1729 + EXPORT_SYMBOL_GPL(pwmchip_remove); 1730 + 1731 + static void devm_pwmchip_remove(void *data) 1732 + { 1733 + struct pwm_chip *chip = data; 1734 + 1735 + pwmchip_remove(chip); 1736 + } 1737 + 1738 + int __devm_pwmchip_add(struct device *dev, struct pwm_chip *chip, struct module *owner) 1739 + { 1740 + int ret; 1741 + 1742 + ret = __pwmchip_add(chip, owner); 1743 + if (ret) 1744 + return ret; 1745 + 1746 + return devm_add_action_or_reset(dev, devm_pwmchip_remove, chip); 1747 + } 1748 + EXPORT_SYMBOL_GPL(__devm_pwmchip_add); 1749 + 1750 + /** 1751 + * pwm_add_table() - register PWM device consumers 1752 + * @table: array of consumers to register 1753 + * @num: number of consumers in table 1754 + */ 1755 + void pwm_add_table(struct pwm_lookup *table, size_t num) 1756 + { 1757 + guard(mutex)(&pwm_lookup_lock); 1758 + 1759 + while (num--) { 1760 + list_add_tail(&table->list, &pwm_lookup_list); 1761 + table++; 1762 + } 1763 + } 1764 + 1765 + /** 1766 + * pwm_remove_table() - unregister PWM device consumers 1767 + * @table: array of consumers to unregister 1768 + * @num: number of consumers in table 1769 + */ 1770 + void pwm_remove_table(struct pwm_lookup *table, size_t num) 1771 + { 1772 + guard(mutex)(&pwm_lookup_lock); 1773 + 1774 + while (num--) { 1775 + list_del(&table->list); 1776 + table++; 1777 + } 1778 + } 2020 1779 2021 1780 static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) 2022 1781 {

+108 -46

drivers/pwm/pwm-axi-pwmgen.c

··· 23 23 #include <linux/err.h> 24 24 #include <linux/fpga/adi-axi-common.h> 25 25 #include <linux/io.h> 26 + #include <linux/minmax.h> 26 27 #include <linux/module.h> 27 28 #include <linux/platform_device.h> 28 29 #include <linux/pwm.h> ··· 54 53 .max_register = 0xFC, 55 54 }; 56 55 57 - static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm, 58 - const struct pwm_state *state) 56 + /* This represents a hardware configuration for one channel */ 57 + struct axi_pwmgen_waveform { 58 + u32 period_cnt; 59 + u32 duty_cycle_cnt; 60 + u32 duty_offset_cnt; 61 + }; 62 + 63 + static int axi_pwmgen_round_waveform_tohw(struct pwm_chip *chip, 64 + struct pwm_device *pwm, 65 + const struct pwm_waveform *wf, 66 + void *_wfhw) 59 67 { 68 + struct axi_pwmgen_waveform *wfhw = _wfhw; 60 69 struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); 61 - unsigned int ch = pwm->hwpwm; 70 + 71 + if (wf->period_length_ns == 0) { 72 + *wfhw = (struct axi_pwmgen_waveform){ 73 + .period_cnt = 0, 74 + .duty_cycle_cnt = 0, 75 + .duty_offset_cnt = 0, 76 + }; 77 + } else { 78 + /* With ddata->clk_rate_hz < NSEC_PER_SEC this won't overflow. */ 79 + wfhw->period_cnt = min_t(u64, 80 + mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC), 81 + U32_MAX); 82 + 83 + if (wfhw->period_cnt == 0) { 84 + /* 85 + * The specified period is too short for the hardware. 86 + * Let's round .duty_cycle down to 0 to get a (somewhat) 87 + * valid result. 88 + */ 89 + wfhw->period_cnt = 1; 90 + wfhw->duty_cycle_cnt = 0; 91 + wfhw->duty_offset_cnt = 0; 92 + } else { 93 + wfhw->duty_cycle_cnt = min_t(u64, 94 + mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC), 95 + U32_MAX); 96 + wfhw->duty_offset_cnt = min_t(u64, 97 + mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC), 98 + U32_MAX); 99 + } 100 + } 101 + 102 + dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> PERIOD: %08x, DUTY: %08x, OFFSET: %08x\n", 103 + pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, 104 + ddata->clk_rate_hz, wfhw->period_cnt, wfhw->duty_cycle_cnt, wfhw->duty_offset_cnt); 105 + 106 + return 0; 107 + } 108 + 109 + static int axi_pwmgen_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm, 110 + const void *_wfhw, struct pwm_waveform *wf) 111 + { 112 + const struct axi_pwmgen_waveform *wfhw = _wfhw; 113 + struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); 114 + 115 + wf->period_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->period_cnt * NSEC_PER_SEC, 116 + ddata->clk_rate_hz); 117 + 118 + wf->duty_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_cycle_cnt * NSEC_PER_SEC, 119 + ddata->clk_rate_hz); 120 + 121 + wf->duty_offset_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_offset_cnt * NSEC_PER_SEC, 122 + ddata->clk_rate_hz); 123 + 124 + return 0; 125 + } 126 + 127 + static int axi_pwmgen_write_waveform(struct pwm_chip *chip, 128 + struct pwm_device *pwm, 129 + const void *_wfhw) 130 + { 131 + const struct axi_pwmgen_waveform *wfhw = _wfhw; 132 + struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); 62 133 struct regmap *regmap = ddata->regmap; 63 - u64 period_cnt, duty_cnt; 134 + unsigned int ch = pwm->hwpwm; 64 135 int ret; 65 136 66 - if (state->polarity != PWM_POLARITY_NORMAL) 67 - return -EINVAL; 137 + ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), wfhw->period_cnt); 138 + if (ret) 139 + return ret; 68 140 69 - if (state->enabled) { 70 - period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC); 71 - if (period_cnt > UINT_MAX) 72 - period_cnt = UINT_MAX; 141 + ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), wfhw->duty_cycle_cnt); 142 + if (ret) 143 + return ret; 73 144 74 - if (period_cnt == 0) 75 - return -EINVAL; 76 - 77 - ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt); 78 - if (ret) 79 - return ret; 80 - 81 - duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC); 82 - if (duty_cnt > UINT_MAX) 83 - duty_cnt = UINT_MAX; 84 - 85 - ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt); 86 - if (ret) 87 - return ret; 88 - } else { 89 - ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0); 90 - if (ret) 91 - return ret; 92 - 93 - ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0); 94 - if (ret) 95 - return ret; 96 - } 145 + ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), wfhw->duty_offset_cnt); 146 + if (ret) 147 + return ret; 97 148 98 149 return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG); 99 150 } 100 151 101 - static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 102 - struct pwm_state *state) 152 + static int axi_pwmgen_read_waveform(struct pwm_chip *chip, 153 + struct pwm_device *pwm, 154 + void *_wfhw) 103 155 { 156 + struct axi_pwmgen_waveform *wfhw = _wfhw; 104 157 struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); 105 158 struct regmap *regmap = ddata->regmap; 106 159 unsigned int ch = pwm->hwpwm; 107 - u32 cnt; 108 160 int ret; 109 161 110 - ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt); 162 + ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &wfhw->period_cnt); 111 163 if (ret) 112 164 return ret; 113 165 114 - state->enabled = cnt != 0; 115 - 116 - state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); 117 - 118 - ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt); 166 + ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &wfhw->duty_cycle_cnt); 119 167 if (ret) 120 168 return ret; 121 169 122 - state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); 170 + ret = regmap_read(regmap, AXI_PWMGEN_CHX_OFFSET(ch), &wfhw->duty_offset_cnt); 171 + if (ret) 172 + return ret; 123 173 124 - state->polarity = PWM_POLARITY_NORMAL; 174 + if (wfhw->duty_cycle_cnt > wfhw->period_cnt) 175 + wfhw->duty_cycle_cnt = wfhw->period_cnt; 176 + 177 + /* XXX: is this the actual behaviour of the hardware? */ 178 + if (wfhw->duty_offset_cnt >= wfhw->period_cnt) { 179 + wfhw->duty_cycle_cnt = 0; 180 + wfhw->duty_offset_cnt = 0; 181 + } 125 182 126 183 return 0; 127 184 } 128 185 129 186 static const struct pwm_ops axi_pwmgen_pwm_ops = { 130 - .apply = axi_pwmgen_apply, 131 - .get_state = axi_pwmgen_get_state, 187 + .sizeof_wfhw = sizeof(struct axi_pwmgen_waveform), 188 + .round_waveform_tohw = axi_pwmgen_round_waveform_tohw, 189 + .round_waveform_fromhw = axi_pwmgen_round_waveform_fromhw, 190 + .read_waveform = axi_pwmgen_read_waveform, 191 + .write_waveform = axi_pwmgen_write_waveform, 132 192 }; 133 193 134 194 static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)

+391 -221

drivers/pwm/pwm-stm32.c

··· 51 51 return ccer & TIM_CCER_CCXE; 52 52 } 53 53 54 + struct stm32_pwm_waveform { 55 + u32 ccer; 56 + u32 psc; 57 + u32 arr; 58 + u32 ccr; 59 + }; 60 + 61 + static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip, 62 + struct pwm_device *pwm, 63 + const struct pwm_waveform *wf, 64 + void *_wfhw) 65 + { 66 + struct stm32_pwm_waveform *wfhw = _wfhw; 67 + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 68 + unsigned int ch = pwm->hwpwm; 69 + unsigned long rate; 70 + u64 ccr, duty; 71 + int ret; 72 + 73 + if (wf->period_length_ns == 0) { 74 + *wfhw = (struct stm32_pwm_waveform){ 75 + .ccer = 0, 76 + }; 77 + 78 + return 0; 79 + } 80 + 81 + ret = clk_enable(priv->clk); 82 + if (ret) 83 + return ret; 84 + 85 + wfhw->ccer = TIM_CCER_CCxE(ch + 1); 86 + if (priv->have_complementary_output) 87 + wfhw->ccer = TIM_CCER_CCxNE(ch + 1); 88 + 89 + rate = clk_get_rate(priv->clk); 90 + 91 + if (active_channels(priv) & ~(1 << ch * 4)) { 92 + u64 arr; 93 + 94 + /* 95 + * Other channels are already enabled, so the configured PSC and 96 + * ARR must be used for this channel, too. 97 + */ 98 + ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc); 99 + if (ret) 100 + goto out; 101 + 102 + ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr); 103 + if (ret) 104 + goto out; 105 + 106 + /* 107 + * calculate the best value for ARR for the given PSC, refuse if 108 + * the resulting period gets bigger than the requested one. 109 + */ 110 + arr = mul_u64_u64_div_u64(wf->period_length_ns, rate, 111 + (u64)NSEC_PER_SEC * (wfhw->psc + 1)); 112 + if (arr <= wfhw->arr) { 113 + /* 114 + * requested period is small than the currently 115 + * configured and unchangable period, report back the smallest 116 + * possible period, i.e. the current state; Initialize 117 + * ccr to anything valid. 118 + */ 119 + wfhw->ccr = 0; 120 + ret = 1; 121 + goto out; 122 + } 123 + 124 + } else { 125 + /* 126 + * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so 127 + * the calculations here won't overflow. 128 + * First we need to find the minimal value for prescaler such that 129 + * 130 + * period_ns * clkrate 131 + * ------------------------------ < max_arr + 1 132 + * NSEC_PER_SEC * (prescaler + 1) 133 + * 134 + * This equation is equivalent to 135 + * 136 + * period_ns * clkrate 137 + * ---------------------------- < prescaler + 1 138 + * NSEC_PER_SEC * (max_arr + 1) 139 + * 140 + * Using integer division and knowing that the right hand side is 141 + * integer, this is further equivalent to 142 + * 143 + * (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler 144 + */ 145 + u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate, 146 + (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1)); 147 + u64 arr; 148 + 149 + wfhw->psc = min_t(u64, psc, MAX_TIM_PSC); 150 + 151 + arr = mul_u64_u64_div_u64(wf->period_length_ns, rate, 152 + (u64)NSEC_PER_SEC * (wfhw->psc + 1)); 153 + if (!arr) { 154 + /* 155 + * requested period is too small, report back the smallest 156 + * possible period, i.e. ARR = 0. The only valid CCR 157 + * value is then zero, too. 158 + */ 159 + wfhw->arr = 0; 160 + wfhw->ccr = 0; 161 + ret = 1; 162 + goto out; 163 + } 164 + 165 + /* 166 + * ARR is limited intentionally to values less than 167 + * priv->max_arr to allow 100% duty cycle. 168 + */ 169 + wfhw->arr = min_t(u64, arr, priv->max_arr) - 1; 170 + } 171 + 172 + duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate, 173 + (u64)NSEC_PER_SEC * (wfhw->psc + 1)); 174 + duty = min_t(u64, duty, wfhw->arr + 1); 175 + 176 + if (wf->duty_length_ns && wf->duty_offset_ns && 177 + wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) { 178 + wfhw->ccer |= TIM_CCER_CCxP(ch + 1); 179 + if (priv->have_complementary_output) 180 + wfhw->ccer |= TIM_CCER_CCxNP(ch + 1); 181 + 182 + ccr = wfhw->arr + 1 - duty; 183 + } else { 184 + ccr = duty; 185 + } 186 + 187 + wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1); 188 + 189 + dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n", 190 + pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns, 191 + rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr); 192 + 193 + out: 194 + clk_disable(priv->clk); 195 + 196 + return ret; 197 + } 198 + 199 + /* 200 + * This should be moved to lib/math/div64.c. Currently there are some changes 201 + * pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles. 202 + */ 203 + static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c) 204 + { 205 + u64 res = mul_u64_u64_div_u64(a, b, c); 206 + /* Those multiplications might overflow but it doesn't matter */ 207 + u64 rem = a * b - c * res; 208 + 209 + if (rem) 210 + res += 1; 211 + 212 + return res; 213 + } 214 + 215 + static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip, 216 + struct pwm_device *pwm, 217 + const void *_wfhw, 218 + struct pwm_waveform *wf) 219 + { 220 + const struct stm32_pwm_waveform *wfhw = _wfhw; 221 + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 222 + unsigned int ch = pwm->hwpwm; 223 + 224 + if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { 225 + unsigned long rate = clk_get_rate(priv->clk); 226 + u64 ccr_ns; 227 + 228 + /* The result doesn't overflow for rate >= 15259 */ 229 + wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1), 230 + NSEC_PER_SEC, rate); 231 + 232 + ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr, 233 + NSEC_PER_SEC, rate); 234 + 235 + if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) { 236 + wf->duty_length_ns = 237 + stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr), 238 + NSEC_PER_SEC, rate); 239 + 240 + wf->duty_offset_ns = ccr_ns; 241 + } else { 242 + wf->duty_length_ns = ccr_ns; 243 + wf->duty_offset_ns = 0; 244 + } 245 + 246 + dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n", 247 + pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate, 248 + wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns); 249 + 250 + } else { 251 + *wf = (struct pwm_waveform){ 252 + .period_length_ns = 0, 253 + }; 254 + } 255 + 256 + return 0; 257 + } 258 + 259 + static int stm32_pwm_read_waveform(struct pwm_chip *chip, 260 + struct pwm_device *pwm, 261 + void *_wfhw) 262 + { 263 + struct stm32_pwm_waveform *wfhw = _wfhw; 264 + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 265 + unsigned int ch = pwm->hwpwm; 266 + int ret; 267 + 268 + ret = clk_enable(priv->clk); 269 + if (ret) 270 + return ret; 271 + 272 + ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer); 273 + if (ret) 274 + goto out; 275 + 276 + if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { 277 + ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc); 278 + if (ret) 279 + goto out; 280 + 281 + ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr); 282 + if (ret) 283 + goto out; 284 + 285 + if (wfhw->arr == U32_MAX) 286 + wfhw->arr -= 1; 287 + 288 + ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr); 289 + if (ret) 290 + goto out; 291 + 292 + if (wfhw->ccr > wfhw->arr + 1) 293 + wfhw->ccr = wfhw->arr + 1; 294 + } 295 + 296 + out: 297 + clk_disable(priv->clk); 298 + 299 + return ret; 300 + } 301 + 302 + static int stm32_pwm_write_waveform(struct pwm_chip *chip, 303 + struct pwm_device *pwm, 304 + const void *_wfhw) 305 + { 306 + const struct stm32_pwm_waveform *wfhw = _wfhw; 307 + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 308 + unsigned int ch = pwm->hwpwm; 309 + int ret; 310 + 311 + ret = clk_enable(priv->clk); 312 + if (ret) 313 + return ret; 314 + 315 + if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) { 316 + u32 ccer, mask; 317 + unsigned int shift; 318 + u32 ccmr; 319 + 320 + ret = regmap_read(priv->regmap, TIM_CCER, &ccer); 321 + if (ret) 322 + goto out; 323 + 324 + /* If there are other channels enabled, don't update PSC and ARR */ 325 + if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) { 326 + u32 psc, arr; 327 + 328 + ret = regmap_read(priv->regmap, TIM_PSC, &psc); 329 + if (ret) 330 + goto out; 331 + 332 + if (psc != wfhw->psc) { 333 + ret = -EBUSY; 334 + goto out; 335 + } 336 + 337 + ret = regmap_read(priv->regmap, TIM_ARR, &arr); 338 + if (ret) 339 + goto out; 340 + 341 + if (arr != wfhw->arr) { 342 + ret = -EBUSY; 343 + goto out; 344 + } 345 + } else { 346 + ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc); 347 + if (ret) 348 + goto out; 349 + 350 + ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr); 351 + if (ret) 352 + goto out; 353 + 354 + ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 355 + if (ret) 356 + goto out; 357 + 358 + } 359 + 360 + /* set polarity */ 361 + mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1); 362 + ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer); 363 + if (ret) 364 + goto out; 365 + 366 + ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr); 367 + if (ret) 368 + goto out; 369 + 370 + /* Configure output mode */ 371 + shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; 372 + ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; 373 + mask = CCMR_CHANNEL_MASK << shift; 374 + 375 + if (ch < 2) 376 + ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); 377 + else 378 + ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); 379 + if (ret) 380 + goto out; 381 + 382 + ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); 383 + if (ret) 384 + goto out; 385 + 386 + if (!(ccer & TIM_CCER_CCxE(ch + 1))) { 387 + mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1); 388 + 389 + ret = clk_enable(priv->clk); 390 + if (ret) 391 + goto out; 392 + 393 + ccer = (ccer & ~mask) | (wfhw->ccer & mask); 394 + regmap_write(priv->regmap, TIM_CCER, ccer); 395 + 396 + /* Make sure that registers are updated */ 397 + regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 398 + 399 + /* Enable controller */ 400 + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 401 + } 402 + 403 + } else { 404 + /* disable channel */ 405 + u32 mask, ccer; 406 + 407 + mask = TIM_CCER_CCxE(ch + 1); 408 + if (priv->have_complementary_output) 409 + mask |= TIM_CCER_CCxNE(ch + 1); 410 + 411 + ret = regmap_read(priv->regmap, TIM_CCER, &ccer); 412 + if (ret) 413 + goto out; 414 + 415 + if (ccer & mask) { 416 + ccer = ccer & ~mask; 417 + 418 + ret = regmap_write(priv->regmap, TIM_CCER, ccer); 419 + if (ret) 420 + goto out; 421 + 422 + if (!(ccer & TIM_CCER_CCXE)) { 423 + /* When all channels are disabled, we can disable the controller */ 424 + ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 425 + if (ret) 426 + goto out; 427 + } 428 + 429 + clk_disable(priv->clk); 430 + } 431 + } 432 + 433 + out: 434 + clk_disable(priv->clk); 435 + 436 + return ret; 437 + } 438 + 54 439 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) 55 440 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) 56 441 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) ··· 693 308 return ret; 694 309 } 695 310 696 - static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch, 697 - u64 duty_ns, u64 period_ns) 698 - { 699 - unsigned long long prd, dty; 700 - unsigned long long prescaler; 701 - u32 ccmr, mask, shift; 702 - 703 - /* 704 - * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so 705 - * the calculations here won't overflow. 706 - * First we need to find the minimal value for prescaler such that 707 - * 708 - * period_ns * clkrate 709 - * ------------------------------ < max_arr + 1 710 - * NSEC_PER_SEC * (prescaler + 1) 711 - * 712 - * This equation is equivalent to 713 - * 714 - * period_ns * clkrate 715 - * ---------------------------- < prescaler + 1 716 - * NSEC_PER_SEC * (max_arr + 1) 717 - * 718 - * Using integer division and knowing that the right hand side is 719 - * integer, this is further equivalent to 720 - * 721 - * (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler 722 - */ 723 - 724 - prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk), 725 - (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1)); 726 - if (prescaler > MAX_TIM_PSC) 727 - return -EINVAL; 728 - 729 - prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk), 730 - (u64)NSEC_PER_SEC * (prescaler + 1)); 731 - if (!prd) 732 - return -EINVAL; 733 - 734 - /* 735 - * All channels share the same prescaler and counter so when two 736 - * channels are active at the same time we can't change them 737 - */ 738 - if (active_channels(priv) & ~(1 << ch * 4)) { 739 - u32 psc, arr; 740 - 741 - regmap_read(priv->regmap, TIM_PSC, &psc); 742 - regmap_read(priv->regmap, TIM_ARR, &arr); 743 - 744 - if ((psc != prescaler) || (arr != prd - 1)) 745 - return -EBUSY; 746 - } 747 - 748 - regmap_write(priv->regmap, TIM_PSC, prescaler); 749 - regmap_write(priv->regmap, TIM_ARR, prd - 1); 750 - regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); 751 - 752 - /* Calculate the duty cycles */ 753 - dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk), 754 - (u64)NSEC_PER_SEC * (prescaler + 1)); 755 - 756 - regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty); 757 - 758 - /* Configure output mode */ 759 - shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; 760 - ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; 761 - mask = CCMR_CHANNEL_MASK << shift; 762 - 763 - if (ch < 2) 764 - regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); 765 - else 766 - regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); 767 - 768 - regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); 769 - 770 - return 0; 771 - } 772 - 773 - static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch, 774 - enum pwm_polarity polarity) 775 - { 776 - u32 mask; 777 - 778 - mask = TIM_CCER_CCxP(ch + 1); 779 - if (priv->have_complementary_output) 780 - mask |= TIM_CCER_CCxNP(ch + 1); 781 - 782 - regmap_update_bits(priv->regmap, TIM_CCER, mask, 783 - polarity == PWM_POLARITY_NORMAL ? 0 : mask); 784 - 785 - return 0; 786 - } 787 - 788 - static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) 789 - { 790 - u32 mask; 791 - int ret; 792 - 793 - ret = clk_enable(priv->clk); 794 - if (ret) 795 - return ret; 796 - 797 - /* Enable channel */ 798 - mask = TIM_CCER_CCxE(ch + 1); 799 - if (priv->have_complementary_output) 800 - mask |= TIM_CCER_CCxNE(ch + 1); 801 - 802 - regmap_set_bits(priv->regmap, TIM_CCER, mask); 803 - 804 - /* Make sure that registers are updated */ 805 - regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); 806 - 807 - /* Enable controller */ 808 - regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 809 - 810 - return 0; 811 - } 812 - 813 - static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch) 814 - { 815 - u32 mask; 816 - 817 - /* Disable channel */ 818 - mask = TIM_CCER_CCxE(ch + 1); 819 - if (priv->have_complementary_output) 820 - mask |= TIM_CCER_CCxNE(ch + 1); 821 - 822 - regmap_clear_bits(priv->regmap, TIM_CCER, mask); 823 - 824 - /* When all channels are disabled, we can disable the controller */ 825 - if (!active_channels(priv)) 826 - regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); 827 - 828 - clk_disable(priv->clk); 829 - } 830 - 831 - static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 832 - const struct pwm_state *state) 833 - { 834 - bool enabled; 835 - struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 836 - int ret; 837 - 838 - enabled = pwm->state.enabled; 839 - 840 - if (!state->enabled) { 841 - if (enabled) 842 - stm32_pwm_disable(priv, pwm->hwpwm); 843 - return 0; 844 - } 845 - 846 - if (state->polarity != pwm->state.polarity) 847 - stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); 848 - 849 - ret = stm32_pwm_config(priv, pwm->hwpwm, 850 - state->duty_cycle, state->period); 851 - if (ret) 852 - return ret; 853 - 854 - if (!enabled && state->enabled) 855 - ret = stm32_pwm_enable(priv, pwm->hwpwm); 856 - 857 - return ret; 858 - } 859 - 860 - static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, 861 - const struct pwm_state *state) 862 - { 863 - struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 864 - int ret; 865 - 866 - /* protect common prescaler for all active channels */ 867 - mutex_lock(&priv->lock); 868 - ret = stm32_pwm_apply(chip, pwm, state); 869 - mutex_unlock(&priv->lock); 870 - 871 - return ret; 872 - } 873 - 874 - static int stm32_pwm_get_state(struct pwm_chip *chip, 875 - struct pwm_device *pwm, struct pwm_state *state) 876 - { 877 - struct stm32_pwm *priv = to_stm32_pwm_dev(chip); 878 - int ch = pwm->hwpwm; 879 - unsigned long rate; 880 - u32 ccer, psc, arr, ccr; 881 - u64 dty, prd; 882 - int ret; 883 - 884 - mutex_lock(&priv->lock); 885 - 886 - ret = regmap_read(priv->regmap, TIM_CCER, &ccer); 887 - if (ret) 888 - goto out; 889 - 890 - state->enabled = ccer & TIM_CCER_CCxE(ch + 1); 891 - state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ? 892 - PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; 893 - ret = regmap_read(priv->regmap, TIM_PSC, &psc); 894 - if (ret) 895 - goto out; 896 - ret = regmap_read(priv->regmap, TIM_ARR, &arr); 897 - if (ret) 898 - goto out; 899 - ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr); 900 - if (ret) 901 - goto out; 902 - 903 - rate = clk_get_rate(priv->clk); 904 - 905 - prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1); 906 - state->period = DIV_ROUND_UP_ULL(prd, rate); 907 - dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr; 908 - state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); 909 - 910 - out: 911 - mutex_unlock(&priv->lock); 912 - return ret; 913 - } 914 - 915 311 static const struct pwm_ops stm32pwm_ops = { 916 - .apply = stm32_pwm_apply_locked, 917 - .get_state = stm32_pwm_get_state, 312 + .sizeof_wfhw = sizeof(struct stm32_pwm_waveform), 313 + .round_waveform_tohw = stm32_pwm_round_waveform_tohw, 314 + .round_waveform_fromhw = stm32_pwm_round_waveform_fromhw, 315 + .read_waveform = stm32_pwm_read_waveform, 316 + .write_waveform = stm32_pwm_write_waveform, 317 + 918 318 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, 919 319 }; 920 320

+59 -1

include/linux/pwm.h

··· 49 49 PWMF_EXPORTED = 1, 50 50 }; 51 51 52 + /** 53 + * struct pwm_waveform - description of a PWM waveform 54 + * @period_length_ns: PWM period 55 + * @duty_length_ns: PWM duty cycle 56 + * @duty_offset_ns: offset of the rising edge from the period's start 57 + * 58 + * This is a representation of a PWM waveform alternative to struct pwm_state 59 + * below. It's more expressive than struct pwm_state as it contains a 60 + * duty_offset_ns and so can represent offsets other than zero (with .polarity = 61 + * PWM_POLARITY_NORMAL) and period - duty_cycle (.polarity = 62 + * PWM_POLARITY_INVERSED). 63 + * 64 + * Note there is no explicit bool for enabled. A "disabled" PWM is represented 65 + * by .period_length_ns = 0. Note further that the behaviour of a "disabled" PWM 66 + * is undefined. Depending on the hardware's capabilities it might drive the 67 + * active or inactive level, go high-z or even continue to toggle. 68 + * 69 + * The unit for all three members is nanoseconds. 70 + */ 71 + struct pwm_waveform { 72 + u64 period_length_ns; 73 + u64 duty_length_ns; 74 + u64 duty_offset_ns; 75 + }; 76 + 52 77 /* 53 78 * struct pwm_state - state of a PWM channel 54 79 * @period: PWM period (in nanoseconds) ··· 276 251 * @request: optional hook for requesting a PWM 277 252 * @free: optional hook for freeing a PWM 278 253 * @capture: capture and report PWM signal 254 + * @sizeof_wfhw: size (in bytes) of driver specific waveform presentation 255 + * @round_waveform_tohw: convert a struct pwm_waveform to driver specific presentation 256 + * @round_waveform_fromhw: convert a driver specific waveform presentation to struct pwm_waveform 257 + * @read_waveform: read driver specific waveform presentation from hardware 258 + * @write_waveform: write driver specific waveform presentation to hardware 279 259 * @apply: atomically apply a new PWM config 280 260 * @get_state: get the current PWM state. 281 261 */ ··· 289 259 void (*free)(struct pwm_chip *chip, struct pwm_device *pwm); 290 260 int (*capture)(struct pwm_chip *chip, struct pwm_device *pwm, 291 261 struct pwm_capture *result, unsigned long timeout); 262 + 263 + size_t sizeof_wfhw; 264 + int (*round_waveform_tohw)(struct pwm_chip *chip, struct pwm_device *pwm, 265 + const struct pwm_waveform *wf, void *wfhw); 266 + int (*round_waveform_fromhw)(struct pwm_chip *chip, struct pwm_device *pwm, 267 + const void *wfhw, struct pwm_waveform *wf); 268 + int (*read_waveform)(struct pwm_chip *chip, struct pwm_device *pwm, 269 + void *wfhw); 270 + int (*write_waveform)(struct pwm_chip *chip, struct pwm_device *pwm, 271 + const void *wfhw); 272 + 292 273 int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm, 293 274 const struct pwm_state *state); 294 275 int (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, ··· 316 275 * @of_xlate: request a PWM device given a device tree PWM specifier 317 276 * @atomic: can the driver's ->apply() be called in atomic context 318 277 * @uses_pwmchip_alloc: signals if pwmchip_allow was used to allocate this chip 278 + * @operational: signals if the chip can be used (or is already deregistered) 279 + * @nonatomic_lock: mutex for nonatomic chips 280 + * @atomic_lock: mutex for atomic chips 319 281 * @pwms: array of PWM devices allocated by the framework 320 282 */ 321 283 struct pwm_chip { ··· 334 290 335 291 /* only used internally by the PWM framework */ 336 292 bool uses_pwmchip_alloc; 293 + bool operational; 294 + union { 295 + /* 296 + * depending on the chip being atomic or not either the mutex or 297 + * the spinlock is used. It protects .operational and 298 + * synchronizes the callbacks in .ops 299 + */ 300 + struct mutex nonatomic_lock; 301 + spinlock_t atomic_lock; 302 + }; 337 303 struct pwm_device pwms[] __counted_by(npwm); 338 304 }; 339 305 ··· 363 309 } 364 310 365 311 #if IS_ENABLED(CONFIG_PWM) 366 - /* PWM user APIs */ 312 + 313 + /* PWM consumer APIs */ 314 + int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf); 315 + int pwm_get_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf); 316 + int pwm_set_waveform_might_sleep(struct pwm_device *pwm, const struct pwm_waveform *wf, bool exact); 367 317 int pwm_apply_might_sleep(struct pwm_device *pwm, const struct pwm_state *state); 368 318 int pwm_apply_atomic(struct pwm_device *pwm, const struct pwm_state *state); 369 319 int pwm_adjust_config(struct pwm_device *pwm);

+126 -8

include/trace/events/pwm.h

··· 8 8 #include <linux/pwm.h> 9 9 #include <linux/tracepoint.h> 10 10 11 + #define TP_PROTO_pwm(args...) \ 12 + TP_PROTO(struct pwm_device *pwm, args) 13 + 14 + #define TP_ARGS_pwm(args...) \ 15 + TP_ARGS(pwm, args) 16 + 17 + #define TP_STRUCT__entry_pwm(args...) \ 18 + TP_STRUCT__entry( \ 19 + __field(unsigned int, chipid) \ 20 + __field(unsigned int, hwpwm) \ 21 + args) 22 + 23 + #define TP_fast_assign_pwm(args...) \ 24 + TP_fast_assign( \ 25 + __entry->chipid = pwm->chip->id; \ 26 + __entry->hwpwm = pwm->hwpwm; \ 27 + args) 28 + 29 + #define TP_printk_pwm(fmt, args...) \ 30 + TP_printk("pwmchip%u.%u: " fmt, __entry->chipid, __entry->hwpwm, args) 31 + 32 + #define __field_pwmwf(wf) \ 33 + __field(u64, wf ## _period_length_ns) \ 34 + __field(u64, wf ## _duty_length_ns) \ 35 + __field(u64, wf ## _duty_offset_ns) \ 36 + 37 + #define fast_assign_pwmwf(wf) \ 38 + __entry->wf ## _period_length_ns = wf->period_length_ns; \ 39 + __entry->wf ## _duty_length_ns = wf->duty_length_ns; \ 40 + __entry->wf ## _duty_offset_ns = wf->duty_offset_ns 41 + 42 + #define printk_pwmwf_format(wf) \ 43 + "%lld/%lld [+%lld]" 44 + 45 + #define printk_pwmwf_formatargs(wf) \ 46 + __entry->wf ## _duty_length_ns, __entry->wf ## _period_length_ns, __entry->wf ## _duty_offset_ns 47 + 48 + TRACE_EVENT(pwm_round_waveform_tohw, 49 + 50 + TP_PROTO_pwm(const struct pwm_waveform *wf, void *wfhw, int err), 51 + 52 + TP_ARGS_pwm(wf, wfhw, err), 53 + 54 + TP_STRUCT__entry_pwm( 55 + __field_pwmwf(wf) 56 + __field(void *, wfhw) 57 + __field(int, err) 58 + ), 59 + 60 + TP_fast_assign_pwm( 61 + fast_assign_pwmwf(wf); 62 + __entry->wfhw = wfhw; 63 + __entry->err = err; 64 + ), 65 + 66 + TP_printk_pwm(printk_pwmwf_format(wf) " > %p err=%d", 67 + printk_pwmwf_formatargs(wf), __entry->wfhw, __entry->err) 68 + ); 69 + 70 + TRACE_EVENT(pwm_round_waveform_fromhw, 71 + 72 + TP_PROTO_pwm(const void *wfhw, struct pwm_waveform *wf, int err), 73 + 74 + TP_ARGS_pwm(wfhw, wf, err), 75 + 76 + TP_STRUCT__entry_pwm( 77 + __field(const void *, wfhw) 78 + __field_pwmwf(wf) 79 + __field(int, err) 80 + ), 81 + 82 + TP_fast_assign_pwm( 83 + __entry->wfhw = wfhw; 84 + fast_assign_pwmwf(wf); 85 + __entry->err = err; 86 + ), 87 + 88 + TP_printk_pwm("%p > " printk_pwmwf_format(wf) " err=%d", 89 + __entry->wfhw, printk_pwmwf_formatargs(wf), __entry->err) 90 + ); 91 + 92 + TRACE_EVENT(pwm_read_waveform, 93 + 94 + TP_PROTO_pwm(void *wfhw, int err), 95 + 96 + TP_ARGS_pwm(wfhw, err), 97 + 98 + TP_STRUCT__entry_pwm( 99 + __field(void *, wfhw) 100 + __field(int, err) 101 + ), 102 + 103 + TP_fast_assign_pwm( 104 + __entry->wfhw = wfhw; 105 + __entry->err = err; 106 + ), 107 + 108 + TP_printk_pwm("%p err=%d", 109 + __entry->wfhw, __entry->err) 110 + ); 111 + 112 + TRACE_EVENT(pwm_write_waveform, 113 + 114 + TP_PROTO_pwm(const void *wfhw, int err), 115 + 116 + TP_ARGS_pwm(wfhw, err), 117 + 118 + TP_STRUCT__entry_pwm( 119 + __field(const void *, wfhw) 120 + __field(int, err) 121 + ), 122 + 123 + TP_fast_assign_pwm( 124 + __entry->wfhw = wfhw; 125 + __entry->err = err; 126 + ), 127 + 128 + TP_printk_pwm("%p err=%d", 129 + __entry->wfhw, __entry->err) 130 + ); 131 + 132 + 11 133 DECLARE_EVENT_CLASS(pwm, 12 134 13 135 TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), 14 136 15 137 TP_ARGS(pwm, state, err), 16 138 17 - TP_STRUCT__entry( 18 - __field(unsigned int, chipid) 19 - __field(unsigned int, hwpwm) 139 + TP_STRUCT__entry_pwm( 20 140 __field(u64, period) 21 141 __field(u64, duty_cycle) 22 142 __field(enum pwm_polarity, polarity) ··· 144 24 __field(int, err) 145 25 ), 146 26 147 - TP_fast_assign( 148 - __entry->chipid = pwm->chip->id; 149 - __entry->hwpwm = pwm->hwpwm; 27 + TP_fast_assign_pwm( 150 28 __entry->period = state->period; 151 29 __entry->duty_cycle = state->duty_cycle; 152 30 __entry->polarity = state->polarity; ··· 152 34 __entry->err = err; 153 35 ), 154 36 155 - TP_printk("pwmchip%u.%u: period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d", 156 - __entry->chipid, __entry->hwpwm, __entry->period, __entry->duty_cycle, 37 + TP_printk_pwm("period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d", 38 + __entry->period, __entry->duty_cycle, 157 39 __entry->polarity, __entry->enabled, __entry->err) 158 40 159 41 );

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