Merge branch 'r8152-add-support-for-the-rtl8157-5gbit-usb-ethernet-chip'

+811 -202

1 changed file

expand all

drivers

net

usb

r8152.c

+811 -202

drivers/net/usb/r8152.c

··· 123 123 #define USB_CSR_DUMMY1 0xb464 124 124 #define USB_CSR_DUMMY2 0xb466 125 125 #define USB_DEV_STAT 0xb808 126 + #define USB_U2P3_V2_CTRL 0xc2c0 126 127 #define USB_CONNECT_TIMER 0xcbf8 127 128 #define USB_MSC_TIMER 0xcbfc 128 129 #define USB_BURST_SIZE 0xcfc0 ··· 157 156 #define USB_U1U2_TIMER 0xd4da 158 157 #define USB_FW_TASK 0xd4e8 /* RTL8153B */ 159 158 #define USB_RX_AGGR_NUM 0xd4ee 159 + #define USB_ADV_ADDR 0xd5d6 160 + #define USB_ADV_DATA 0xd5d8 161 + #define USB_ADV_CMD 0xd5dc 160 162 #define USB_UPS_CTRL 0xd800 161 163 #define USB_POWER_CUT 0xd80a 162 164 #define USB_MISC_0 0xd81a ··· 496 492 /* USB_RX_AGGR_NUM */ 497 493 #define RX_AGGR_NUM_MASK 0x1ff 498 494 495 + /* USB_ADV_CMD */ 496 + #define ADV_CMD_BMU 0 497 + #define ADV_CMD_BUSY BIT(0) 498 + #define ADV_CMD_WR BIT(1) 499 + #define ADV_CMD_IP BIT(2) 500 + 499 501 /* USB_UPS_CTRL */ 500 502 #define POWER_CUT 0x0100 501 503 ··· 541 531 #define CDC_ECM_EN BIT(3) 542 532 #define RX_AGG_DISABLE 0x0010 543 533 #define RX_ZERO_EN 0x0080 534 + #define RX_DESC_16B 0x0400 544 535 545 536 /* USB_U2P3_CTRL */ 546 537 #define U2P3_ENABLE 0x0001 547 538 #define RX_DETECT8 BIT(3) 539 + 540 + /* USB_U2P3_V2_CTRL */ 541 + #define U2P3_V2_ENABLE BIT(29) 548 542 549 543 /* USB_POWER_CUT */ 550 544 #define PWR_EN 0x0001 ··· 620 606 FORCE_100M_FULL, 621 607 FORCE_1000M_FULL, 622 608 NWAY_2500M_FULL, 609 + NWAY_5000M_FULL, 623 610 }; 624 611 625 612 /* OCP_ALDPS_CONFIG */ ··· 742 727 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ 743 728 744 729 enum rtl_register_content { 730 + _5000bps = BIT(12), 745 731 _2500bps = BIT(10), 746 732 _1250bps = BIT(9), 747 733 _500bps = BIT(8), ··· 756 740 }; 757 741 758 742 #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) 743 + #define is_speed_5000(_speed) (((_speed) & (_5000bps | LINK_STATUS)) == (_5000bps | LINK_STATUS)) 759 744 #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) 760 745 761 746 #define RTL8152_MAX_TX 4 762 747 #define RTL8152_MAX_RX 10 763 748 #define INTBUFSIZE 2 764 - #define TX_ALIGN 4 765 - #define RX_ALIGN 8 766 749 767 750 #define RTL8152_RX_MAX_PENDING 4096 768 751 #define RTL8152_RXFG_HEADSZ 256 ··· 773 758 #define RTL8152_TX_TIMEOUT (5 * HZ) 774 759 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) 775 760 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) 776 - #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) 777 761 778 762 /* rtl8152 flags */ 779 763 enum rtl8152_flags { ··· 857 843 #define TX_VLAN_TAG BIT(16) 858 844 }; 859 845 846 + struct rx_desc_v2 { 847 + __le32 opts1; 848 + #define RX_LEN_MASK_2 0xfffe0000 849 + #define rx_v2_get_len(x) (((x) & RX_LEN_MASK_2) >> 17) 850 + #define RX_VLAN_TAG_2 BIT(3) 851 + #define RX_VER_MASK 0x3 852 + 853 + __le32 opts2; 854 + 855 + __le32 opts3; 856 + #define IPF_2 BIT(26) /* IP checksum fail */ 857 + #define UDPF_2 BIT(25) /* UDP checksum fail */ 858 + #define TCPF_2 BIT(24) /* TCP checksum fail */ 859 + #define RD_IPV6_CS_2 BIT(15) 860 + #define RD_IPV4_CS_2 BIT(14) 861 + #define RD_UDP_CS_2 BIT(11) 862 + #define RD_TCP_CS_2 BIT(10) 863 + 864 + __le32 opts4; 865 + }; 866 + 867 + struct tx_desc_v2 { 868 + __le32 opts1; 869 + 870 + __le32 opts2; 871 + #define TCPHO_MAX_2 0x3ffU 872 + 873 + __le32 opts3; 874 + #define tx_v2_set_len(x) ((x) << 4) 875 + 876 + __le32 opts4; 877 + #define TX_SIG (0x15 << 27) 878 + }; 879 + 860 880 struct r8152; 861 881 862 882 struct rx_agg { ··· 964 916 u32 ctap_short_off:1; 965 917 } ups_info; 966 918 919 + struct desc_info { 920 + void (*vlan_tag)(void *desc, struct sk_buff *skb); 921 + u8 align; 922 + u8 size; 923 + } rx_desc, tx_desc; 924 + 925 + struct desc_ops { 926 + void (*tx_len)(struct r8152 *tp, void *desc, u32 len); 927 + u32 (*rx_len)(struct r8152 *tp, void *desc); 928 + u8 (*rx_csum)(struct r8152 *tp, void *desc); 929 + int (*tx_csum)(struct r8152 *tp, void *desc, struct sk_buff *skb, u32 len); 930 + } desc_ops; 931 + 967 932 #define RTL_VER_SIZE 32 968 933 969 934 struct rtl_fw { ··· 1007 946 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out; 1008 947 1009 948 u32 support_2500full:1; 949 + u32 support_5000full:1; 1010 950 u32 lenovo_macpassthru:1; 1011 951 u32 dell_tb_rx_agg_bug:1; 1012 952 u16 ocp_base; ··· 1241 1179 RTL_VER_13, 1242 1180 RTL_VER_14, 1243 1181 RTL_VER_15, 1182 + RTL_VER_16, 1244 1183 1245 1184 RTL_VER_MAX 1246 1185 }; ··· 1259 1196 #define RTL_ADVERTISED_1000_HALF BIT(4) 1260 1197 #define RTL_ADVERTISED_1000_FULL BIT(5) 1261 1198 #define RTL_ADVERTISED_2500_FULL BIT(6) 1199 + #define RTL_ADVERTISED_5000_FULL BIT(7) 1262 1200 1263 1201 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 1264 1202 * The RTL chips use a 64 element hash table based on the Ethernet CRC. ··· 1267 1203 static const int multicast_filter_limit = 32; 1268 1204 static unsigned int agg_buf_sz = 16384; 1269 1205 1270 - #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) 1206 + #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - tp->tx_desc.size) 1271 1207 1272 1208 /* If register access fails then we block access and issue a reset. If this 1273 1209 * happens too many times in a row without a successful access then we stop ··· 1676 1612 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1677 1613 { 1678 1614 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1615 + } 1616 + 1617 + static int wait_cmd_ready(struct r8152 *tp, u16 cmd) 1618 + { 1619 + return poll_timeout_us(u16 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, cmd), 1620 + !(ocp_data & ADV_CMD_BUSY), 2000, 20000, false); 1621 + } 1622 + 1623 + static int ocp_adv_read(struct r8152 *tp, u16 cmd, u16 addr, u32 *data) 1624 + { 1625 + int ret; 1626 + 1627 + ret = wait_cmd_ready(tp, USB_ADV_CMD); 1628 + if (ret < 0) 1629 + goto out; 1630 + 1631 + ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_ADDR, addr); 1632 + 1633 + cmd |= ADV_CMD_BUSY; 1634 + ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_CMD, cmd); 1635 + 1636 + ret = wait_cmd_ready(tp, USB_ADV_CMD); 1637 + if (ret < 0) 1638 + goto out; 1639 + 1640 + *data = ocp_read_dword(tp, MCU_TYPE_USB, USB_ADV_DATA); 1641 + 1642 + out: 1643 + return ret; 1644 + } 1645 + 1646 + static int ocp_adv_write(struct r8152 *tp, u16 cmd, u16 addr, u32 data) 1647 + { 1648 + int ret; 1649 + 1650 + ret = wait_cmd_ready(tp, USB_ADV_CMD); 1651 + if (ret < 0) 1652 + goto out; 1653 + 1654 + cmd |= ADV_CMD_WR; 1655 + ocp_write_dword(tp, MCU_TYPE_USB, USB_ADV_DATA, data); 1656 + 1657 + ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_ADDR, addr); 1658 + 1659 + cmd |= ADV_CMD_BUSY; 1660 + ocp_write_word(tp, MCU_TYPE_USB, USB_ADV_CMD, cmd); 1661 + 1662 + out: 1663 + return ret; 1664 + } 1665 + 1666 + static int rtl_bmu_read(struct r8152 *tp, u16 addr, u32 *data) 1667 + { 1668 + return ocp_adv_read(tp, ADV_CMD_BMU, addr, data); 1669 + } 1670 + 1671 + static int rtl_bmu_write(struct r8152 *tp, u16 addr, u32 data) 1672 + { 1673 + return ocp_adv_write(tp, ADV_CMD_BMU, addr, data); 1674 + } 1675 + 1676 + static int rtl_bmu_w0w1(struct r8152 *tp, u16 addr, u32 clear, u32 set) 1677 + { 1678 + u32 bmu; 1679 + int ret; 1680 + 1681 + ret = rtl_bmu_read(tp, addr, &bmu); 1682 + if (ret < 0) 1683 + goto out; 1684 + 1685 + bmu = (bmu & ~clear) | set; 1686 + ret = rtl_bmu_write(tp, addr, bmu); 1687 + 1688 + out: 1689 + return ret; 1690 + } 1691 + 1692 + static int rtl_bmu_clr_bits(struct r8152 *tp, u16 addr, u32 clear) 1693 + { 1694 + return rtl_bmu_w0w1(tp, addr, clear, 0); 1695 + } 1696 + 1697 + static int rtl_ip_read(struct r8152 *tp, u16 addr, u32 *data) 1698 + { 1699 + return ocp_adv_read(tp, ADV_CMD_IP, addr, data); 1700 + } 1701 + 1702 + static int rtl_ip_write(struct r8152 *tp, u16 addr, u32 data) 1703 + { 1704 + return ocp_adv_write(tp, ADV_CMD_IP, addr, data); 1705 + } 1706 + 1707 + static int rtl_ip_w0w1(struct r8152 *tp, u16 addr, u32 clear, u32 set) 1708 + { 1709 + int ret; 1710 + u32 ip; 1711 + 1712 + ret = rtl_ip_read(tp, addr, &ip); 1713 + if (ret < 0) 1714 + goto out; 1715 + 1716 + ip = (ip & ~clear) | set; 1717 + ret = rtl_ip_write(tp, addr, ip); 1718 + 1719 + out: 1720 + return ret; 1721 + } 1722 + 1723 + static int rtl_ip_clr_bits(struct r8152 *tp, u16 addr, u32 clear) 1724 + { 1725 + return rtl_ip_w0w1(tp, addr, clear, 0); 1726 + } 1727 + 1728 + static int rtl_ip_set_bits(struct r8152 *tp, u16 addr, u32 set) 1729 + { 1730 + return rtl_ip_w0w1(tp, addr, 0, set); 1679 1731 } 1680 1732 1681 1733 static void sram_write(struct r8152 *tp, u16 addr, u16 data) ··· 2357 2177 } 2358 2178 } 2359 2179 2360 - static inline void *rx_agg_align(void *data) 2180 + static void *rx_agg_align(struct r8152 *tp, void *data) 2361 2181 { 2362 - return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 2182 + return (void *)ALIGN((uintptr_t)data, tp->rx_desc.align); 2363 2183 } 2364 2184 2365 - static inline void *tx_agg_align(void *data) 2185 + static void *tx_agg_align(struct r8152 *tp, void *data) 2366 2186 { 2367 - return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 2187 + return (void *)ALIGN((uintptr_t)data, tp->tx_desc.align); 2368 2188 } 2369 2189 2370 2190 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) ··· 2482 2302 if (!buf) 2483 2303 goto err1; 2484 2304 2485 - if (buf != tx_agg_align(buf)) { 2305 + if (buf != tx_agg_align(tp, buf)) { 2486 2306 kfree(buf); 2487 - buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 2307 + buf = kmalloc_node(agg_buf_sz + tp->tx_desc.align, GFP_KERNEL, 2488 2308 node); 2489 2309 if (!buf) 2490 2310 goto err1; ··· 2500 2320 tp->tx_info[i].context = tp; 2501 2321 tp->tx_info[i].urb = urb; 2502 2322 tp->tx_info[i].buffer = buf; 2503 - tp->tx_info[i].head = tx_agg_align(buf); 2323 + tp->tx_info[i].head = tx_agg_align(tp, buf); 2504 2324 2505 2325 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 2506 2326 } ··· 2587 2407 } 2588 2408 } 2589 2409 2590 - static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 2410 + static void r8152_tx_len(struct r8152 *tp, void *tx_desc, u32 len) 2591 2411 { 2412 + struct tx_desc *desc = tx_desc; 2413 + 2414 + desc->opts1 |= cpu_to_le32(len); 2415 + } 2416 + 2417 + static void r8152_tx_vlan_tag(void *d, struct sk_buff *skb) 2418 + { 2419 + struct tx_desc *desc = d; 2420 + 2592 2421 if (skb_vlan_tag_present(skb)) { 2593 2422 u32 opts2; 2594 2423 ··· 2606 2417 } 2607 2418 } 2608 2419 2609 - static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 2420 + static void r8152_rx_vlan_tag(void *d, struct sk_buff *skb) 2610 2421 { 2422 + struct rx_desc *desc = d; 2423 + 2611 2424 u32 opts2 = le32_to_cpu(desc->opts2); 2612 2425 2613 2426 if (opts2 & RX_VLAN_TAG) ··· 2617 2426 swab16(opts2 & 0xffff)); 2618 2427 } 2619 2428 2620 - static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 2429 + static int r8152_tx_csum(struct r8152 *tp, void *d, 2621 2430 struct sk_buff *skb, u32 len) 2622 2431 { 2623 2432 u32 mss = skb_shinfo(skb)->gso_size; 2433 + struct tx_desc *desc = d; 2624 2434 u32 opts1, opts2 = 0; 2625 2435 int ret = TX_CSUM_SUCCESS; 2626 2436 ··· 2706 2514 return ret; 2707 2515 } 2708 2516 2517 + static u32 r8152_rx_len(struct r8152 *tp, void *d) 2518 + { 2519 + struct rx_desc *desc = d; 2520 + 2521 + return le32_to_cpu(desc->opts1) & RX_LEN_MASK; 2522 + } 2523 + 2524 + static u32 r8157_rx_len(struct r8152 *tp, void *d) 2525 + { 2526 + struct rx_desc_v2 *desc = d; 2527 + 2528 + return rx_v2_get_len(le32_to_cpu(desc->opts1)); 2529 + } 2530 + 2531 + static void r8157_rx_vlan_tag(void *desc, struct sk_buff *skb) 2532 + { 2533 + struct rx_desc_v2 *d = desc; 2534 + u32 opts1; 2535 + 2536 + opts1 = le32_to_cpu(d->opts1); 2537 + if (opts1 & RX_VLAN_TAG_2) { 2538 + u32 opts2 = le32_to_cpu(d->opts2); 2539 + 2540 + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2541 + swab16((opts2 >> 16) & 0xffff)); 2542 + } 2543 + } 2544 + 2545 + static int r8157_tx_csum(struct r8152 *tp, void *tx_desc, struct sk_buff *skb, u32 len) 2546 + { 2547 + u32 mss = skb_shinfo(skb)->gso_size; 2548 + 2549 + if (!mss && skb->ip_summed == CHECKSUM_PARTIAL) { 2550 + u32 transport_offset = (u32)skb_transport_offset(skb); 2551 + 2552 + if (transport_offset > TCPHO_MAX_2) { 2553 + netif_warn(tp, tx_err, tp->netdev, 2554 + "Invalid transport offset 0x%x\n", 2555 + transport_offset); 2556 + return TX_CSUM_NONE; 2557 + } 2558 + } 2559 + 2560 + return r8152_tx_csum(tp, tx_desc, skb, len); 2561 + } 2562 + 2563 + static void r8157_tx_len(struct r8152 *tp, void *tx_desc, u32 len) 2564 + { 2565 + struct tx_desc_v2 *desc = tx_desc; 2566 + 2567 + desc->opts3 = cpu_to_le32(tx_v2_set_len(len)); 2568 + desc->opts4 = cpu_to_le32(TX_SIG); 2569 + } 2570 + 2571 + static int rtl_tx_csum(struct r8152 *tp, void *desc, struct sk_buff *skb, 2572 + u32 len) 2573 + { 2574 + int ret = TX_CSUM_SUCCESS; 2575 + 2576 + WARN_ON_ONCE(len > TX_LEN_MAX); 2577 + 2578 + ret = tp->desc_ops.tx_csum(tp, desc, skb, len); 2579 + if (!ret) 2580 + tp->desc_ops.tx_len(tp, desc, len); 2581 + 2582 + return ret; 2583 + } 2584 + 2709 2585 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 2710 2586 { 2711 2587 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; ··· 2790 2530 agg->skb_len = 0; 2791 2531 remain = agg_buf_sz; 2792 2532 2793 - while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 2794 - struct tx_desc *tx_desc; 2533 + while (remain >= ETH_ZLEN + tp->tx_desc.size) { 2795 2534 struct sk_buff *skb; 2796 2535 unsigned int len; 2536 + void *tx_desc; 2797 2537 2798 2538 skb = __skb_dequeue(&skb_head); 2799 2539 if (!skb) 2800 2540 break; 2801 2541 2802 - len = skb->len + sizeof(*tx_desc); 2542 + len = skb->len + tp->tx_desc.size; 2803 2543 2804 2544 if (len > remain) { 2805 2545 __skb_queue_head(&skb_head, skb); 2806 2546 break; 2807 2547 } 2808 2548 2809 - tx_data = tx_agg_align(tx_data); 2810 - tx_desc = (struct tx_desc *)tx_data; 2549 + tx_data = tx_agg_align(tp, tx_data); 2550 + tx_desc = (void *)tx_data; 2811 2551 2812 - if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) { 2552 + if (rtl_tx_csum(tp, tx_desc, skb, skb->len)) { 2813 2553 r8152_csum_workaround(tp, skb, &skb_head); 2814 2554 continue; 2815 2555 } 2816 2556 2817 - rtl_tx_vlan_tag(tx_desc, skb); 2557 + tp->tx_desc.vlan_tag(tx_desc, skb); 2818 2558 2819 - tx_data += sizeof(*tx_desc); 2559 + tx_data += tp->tx_desc.size; 2820 2560 2821 2561 len = skb->len; 2822 2562 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { ··· 2824 2564 2825 2565 stats->tx_dropped++; 2826 2566 dev_kfree_skb_any(skb); 2827 - tx_data -= sizeof(*tx_desc); 2567 + tx_data -= tp->tx_desc.size; 2828 2568 continue; 2829 2569 } 2830 2570 ··· 2834 2574 2835 2575 dev_kfree_skb_any(skb); 2836 2576 2837 - remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 2577 + remain = agg_buf_sz - (int)(tx_agg_align(tp, tx_data) - agg->head); 2838 2578 2839 2579 if (tp->dell_tb_rx_agg_bug) 2840 2580 break; ··· 2872 2612 return ret; 2873 2613 } 2874 2614 2875 - static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 2615 + static u8 r8152_rx_csum(struct r8152 *tp, void *d) 2876 2616 { 2617 + struct rx_desc *rx_desc = d; 2877 2618 u8 checksum = CHECKSUM_NONE; 2878 2619 u32 opts2, opts3; 2879 2620 ··· 2900 2639 2901 2640 return_result: 2902 2641 return checksum; 2642 + } 2643 + 2644 + static u8 r8157_rx_csum(struct r8152 *tp, void *desc) 2645 + { 2646 + struct rx_desc_v2 *d = desc; 2647 + u8 checksum = CHECKSUM_NONE; 2648 + u32 opts3; 2649 + 2650 + if (!(tp->netdev->features & NETIF_F_RXCSUM)) 2651 + goto return_result; 2652 + 2653 + opts3 = le32_to_cpu(d->opts3); 2654 + 2655 + if ((opts3 & (RD_IPV4_CS_2 | IPF_2)) == (RD_IPV4_CS_2 | IPF_2)) { 2656 + checksum = CHECKSUM_NONE; 2657 + } else if (opts3 & (RD_IPV4_CS_2 | RD_IPV6_CS_2)) { 2658 + if ((opts3 & (RD_UDP_CS_2 | UDPF_2)) == RD_UDP_CS_2) 2659 + checksum = CHECKSUM_UNNECESSARY; 2660 + else if ((opts3 & (RD_TCP_CS_2 | TCPF_2)) == RD_TCP_CS_2) 2661 + checksum = CHECKSUM_UNNECESSARY; 2662 + } 2663 + 2664 + return_result: 2665 + return checksum; 2903 2666 } 2904 2667 2905 2668 static inline bool rx_count_exceed(struct r8152 *tp) ··· 3001 2716 spin_unlock_irqrestore(&tp->rx_lock, flags); 3002 2717 3003 2718 list_for_each_safe(cursor, next, &rx_queue) { 3004 - struct rx_desc *rx_desc; 3005 2719 struct rx_agg *agg, *agg_free; 3006 2720 int len_used = 0; 3007 2721 struct urb *urb; 2722 + void *rx_desc; 3008 2723 u8 *rx_data; 3009 2724 3010 2725 /* A bulk transfer of USB may contain may packets, so the ··· 3027 2742 3028 2743 rx_desc = agg->buffer; 3029 2744 rx_data = agg->buffer; 3030 - len_used += sizeof(struct rx_desc); 2745 + len_used += tp->rx_desc.size; 3031 2746 3032 2747 while (urb->actual_length > len_used) { 3033 2748 struct net_device *netdev = tp->netdev; ··· 3038 2753 3039 2754 WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000); 3040 2755 3041 - pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 2756 + pkt_len = tp->desc_ops.rx_len(tp, rx_desc); 3042 2757 if (pkt_len < ETH_ZLEN) 3043 2758 break; 3044 2759 ··· 3048 2763 3049 2764 pkt_len -= ETH_FCS_LEN; 3050 2765 len = pkt_len; 3051 - rx_data += sizeof(struct rx_desc); 2766 + rx_data += tp->rx_desc.size; 3052 2767 3053 2768 if (!agg_free || tp->rx_copybreak > len) 3054 2769 use_frags = false; ··· 3079 2794 goto find_next_rx; 3080 2795 } 3081 2796 3082 - skb->ip_summed = r8152_rx_csum(tp, rx_desc); 3083 - rtl_rx_vlan_tag(rx_desc, skb); 2797 + skb->ip_summed = tp->desc_ops.rx_csum(tp, rx_desc); 2798 + tp->rx_desc.vlan_tag(rx_desc, skb); 3084 2799 3085 2800 if (use_frags) { 3086 2801 if (rx_frag_head_sz) { ··· 3117 2832 } 3118 2833 3119 2834 find_next_rx: 3120 - rx_data = rx_agg_align(rx_data + len + ETH_FCS_LEN); 3121 - rx_desc = (struct rx_desc *)rx_data; 2835 + rx_data = rx_agg_align(tp, rx_data + len + ETH_FCS_LEN); 2836 + rx_desc = rx_data; 3122 2837 len_used = agg_offset(agg, rx_data); 3123 - len_used += sizeof(struct rx_desc); 2838 + len_used += tp->rx_desc.size; 3124 2839 } 3125 2840 3126 2841 WARN_ON(!agg_free && page_count(agg->page) > 1); ··· 3363 3078 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 3364 3079 netdev_features_t features) 3365 3080 { 3081 + struct r8152 *tp = netdev_priv(dev); 3366 3082 u32 mss = skb_shinfo(skb)->gso_size; 3367 - int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 3083 + int max_offset; 3084 + 3085 + if (tp->version < RTL_VER_16) 3086 + max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 3087 + else 3088 + max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX_2; 3368 3089 3369 3090 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && 3370 3091 skb_transport_offset(skb) > max_offset) 3371 3092 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3372 - else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 3093 + else if ((skb->len + tp->tx_desc.size) > agg_buf_sz) 3373 3094 features &= ~NETIF_F_GSO_MASK; 3374 3095 3375 3096 return features; ··· 3413 3122 3414 3123 static void rtl8152_nic_reset(struct r8152 *tp) 3415 3124 { 3416 - int i; 3417 - 3418 3125 switch (tp->version) { 3419 3126 case RTL_TEST_01: 3420 3127 case RTL_VER_10: 3421 3128 case RTL_VER_11: 3422 3129 ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_TE); 3423 - 3424 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, 3425 - BMU_RESET_EP_IN); 3426 - 3130 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, BMU_RESET_EP_IN); 3427 3131 ocp_word_set_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); 3428 - 3429 3132 ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE); 3430 - 3431 - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, 3432 - BMU_RESET_EP_IN); 3433 - 3133 + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, BMU_RESET_EP_IN); 3434 3134 ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); 3135 + break; 3136 + 3137 + case RTL_VER_16: 3138 + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE | CR_TE); 3435 3139 break; 3436 3140 3437 3141 default: 3438 3142 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 3439 3143 3440 - for (i = 0; i < 1000; i++) { 3144 + for (int i = 0; i < 1000; i++) { 3441 3145 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3442 3146 break; 3443 3147 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) ··· 3445 3159 3446 3160 static void set_tx_qlen(struct r8152 *tp) 3447 3161 { 3448 - tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); 3162 + tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + tp->tx_desc.size); 3449 3163 } 3450 3164 3451 3165 static inline u16 rtl8152_get_speed(struct r8152 *tp) ··· 3649 3363 case RTL_VER_12: 3650 3364 case RTL_VER_13: 3651 3365 case RTL_VER_15: 3366 + case RTL_VER_16: 3652 3367 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3653 3368 640 / 8); 3654 3369 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, ··· 3661 3374 } 3662 3375 } 3663 3376 3377 + static u32 rx_reserved_size(struct r8152 *tp, u32 mtu) 3378 + { 3379 + return mtu_to_size(mtu) + tp->rx_desc.size + tp->rx_desc.align; 3380 + } 3381 + 3664 3382 static void r8153_set_rx_early_size(struct r8152 *tp) 3665 3383 { 3666 - u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); 3384 + u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp, tp->netdev->mtu); 3667 3385 3668 3386 switch (tp->version) { 3669 3387 case RTL_VER_03: ··· 3692 3400 case RTL_VER_15: 3693 3401 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3694 3402 ocp_data / 8); 3403 + break; 3404 + case RTL_VER_16: 3405 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3406 + ocp_data / 16); 3695 3407 break; 3696 3408 default: 3697 3409 WARN_ON_ONCE(1); ··· 3808 3512 case RTL_VER_12: 3809 3513 case RTL_VER_13: 3810 3514 case RTL_VER_15: 3515 + case RTL_VER_16: 3811 3516 default: 3812 3517 if (enable) 3813 3518 ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RCR1, ··· 3964 3667 ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); 3965 3668 else 3966 3669 ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); 3670 + } 3671 + 3672 + static int r8157_u2p3en(struct r8152 *tp, bool enable) 3673 + { 3674 + if (enable) 3675 + return rtl_ip_set_bits(tp, USB_U2P3_V2_CTRL, U2P3_V2_ENABLE); 3676 + else 3677 + return rtl_ip_clr_bits(tp, USB_U2P3_V2_CTRL, U2P3_V2_ENABLE); 3967 3678 } 3968 3679 3969 3680 static void r8153b_ups_flags(struct r8152 *tp) ··· 4319 4014 ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); 4320 4015 } 4321 4016 4017 + static void r8157_power_cut_en(struct r8152 *tp, bool enable) 4018 + { 4019 + if (enable) { 4020 + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN | PHASE2_EN); 4021 + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(1)); 4022 + } else { 4023 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN); 4024 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); 4025 + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(1)); 4026 + } 4027 + } 4028 + 4322 4029 static void r8153_queue_wake(struct r8152 *tp, bool enable) 4323 4030 { 4324 4031 if (enable) ··· 4447 4130 } 4448 4131 } 4449 4132 4133 + static void rtl8157_runtime_enable(struct r8152 *tp, bool enable) 4134 + { 4135 + if (enable) { 4136 + r8153_queue_wake(tp, true); 4137 + r8153b_u1u2en(tp, false); 4138 + r8157_u2p3en(tp, false); 4139 + rtl_runtime_suspend_enable(tp, true); 4140 + } else { 4141 + r8153_queue_wake(tp, false); 4142 + rtl_runtime_suspend_enable(tp, false); 4143 + r8157_u2p3en(tp, true); 4144 + if (tp->udev->speed >= USB_SPEED_SUPER) 4145 + r8153b_u1u2en(tp, true); 4146 + } 4147 + } 4148 + 4450 4149 static void r8153_teredo_off(struct r8152 *tp) 4451 4150 { 4452 4151 switch (tp->version) { ··· 4487 4154 case RTL_VER_13: 4488 4155 case RTL_VER_14: 4489 4156 case RTL_VER_15: 4157 + case RTL_VER_16: 4490 4158 default: 4491 4159 /* The bit 0 ~ 7 are relative with teredo settings. They are 4492 4160 * W1C (write 1 to clear), so set all 1 to disable it. ··· 4541 4207 bp_num = 8; 4542 4208 break; 4543 4209 case RTL_VER_14: 4210 + case RTL_VER_16: 4544 4211 default: 4545 4212 ocp_write_word(tp, type, USB_BP2_EN, 0); 4546 4213 bp_num = 16; ··· 4649 4314 case RTL_VER_11: 4650 4315 case RTL_VER_12: 4651 4316 case RTL_VER_14: 4317 + case RTL_VER_16: 4652 4318 goto out; 4653 4319 case RTL_VER_13: 4654 4320 case RTL_VER_15: ··· 5757 5421 5758 5422 static void r8156_eee_en(struct r8152 *tp, bool enable) 5759 5423 { 5424 + u16 config; 5425 + 5760 5426 r8153_eee_en(tp, enable); 5761 5427 5428 + config = ocp_reg_read(tp, OCP_EEE_ADV2); 5429 + 5762 5430 if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT)) 5763 - ocp_reg_set_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); 5431 + config |= MDIO_EEE_2_5GT; 5764 5432 else 5765 - ocp_reg_clr_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); 5433 + config &= ~MDIO_EEE_2_5GT; 5434 + 5435 + if (enable && (tp->eee_adv2 & MDIO_EEE_5GT)) 5436 + config |= MDIO_EEE_5GT; 5437 + else 5438 + config &= ~MDIO_EEE_5GT; 5439 + 5440 + ocp_reg_write(tp, OCP_EEE_ADV2, config); 5766 5441 } 5767 5442 5768 5443 static void rtl_eee_enable(struct r8152 *tp, bool enable) ··· 5811 5464 case RTL_VER_12: 5812 5465 case RTL_VER_13: 5813 5466 case RTL_VER_15: 5467 + case RTL_VER_16: 5814 5468 if (enable) { 5815 5469 r8156_eee_en(tp, true); 5816 5470 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); ··· 6396 6048 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6397 6049 return -ENODEV; 6398 6050 6399 - r8156_fc_parameter(tp); 6051 + if (tp->version < RTL_VER_12) 6052 + r8156_fc_parameter(tp); 6053 + 6400 6054 set_tx_qlen(tp); 6401 6055 rtl_set_eee_plus(tp); 6056 + 6057 + if (tp->version >= RTL_VER_12 && tp->version <= RTL_VER_16) 6058 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); 6059 + 6402 6060 r8153_set_rx_early_timeout(tp); 6403 6061 r8153_set_rx_early_size(tp); 6404 6062 6405 6063 speed = rtl8152_get_speed(tp); 6406 6064 rtl_set_ifg(tp, speed); 6065 + 6066 + if (tp->version >= RTL_VER_16) 6067 + return rtl_enable(tp); 6407 6068 6408 6069 if (speed & _2500bps) 6409 6070 ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ··· 6421 6064 ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 6422 6065 IDLE_SPDWN_EN); 6423 6066 6424 - if (speed & _1000bps) 6425 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); 6426 - else if (speed & _500bps) 6427 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); 6067 + if (tp->version < RTL_VER_12) { 6068 + if (speed & _1000bps) 6069 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); 6070 + else if (speed & _500bps) 6071 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); 6072 + } 6428 6073 6429 6074 if (tp->udev->speed == USB_SPEED_HIGH) { 6430 6075 /* USB 0xb45e[3:0] l1_nyet_hird */ ··· 6449 6090 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0); 6450 6091 6451 6092 rtl8153_disable(tp); 6452 - } 6453 - 6454 - static int rtl8156b_enable(struct r8152 *tp) 6455 - { 6456 - u16 speed; 6457 - 6458 - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6459 - return -ENODEV; 6460 - 6461 - set_tx_qlen(tp); 6462 - rtl_set_eee_plus(tp); 6463 - 6464 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); 6465 - 6466 - r8153_set_rx_early_timeout(tp); 6467 - r8153_set_rx_early_size(tp); 6468 - 6469 - speed = rtl8152_get_speed(tp); 6470 - rtl_set_ifg(tp, speed); 6471 - 6472 - if (speed & _2500bps) 6473 - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 6474 - IDLE_SPDWN_EN); 6475 - else 6476 - ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 6477 - IDLE_SPDWN_EN); 6478 - 6479 - if (tp->udev->speed == USB_SPEED_HIGH) { 6480 - if (is_flow_control(speed)) 6481 - ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); 6482 - else 6483 - ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); 6484 - } 6485 - 6486 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); 6487 - usleep_range(1000, 2000); 6488 - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); 6489 - 6490 - return rtl_enable(tp); 6491 6093 } 6492 6094 6493 6095 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, ··· 6510 6190 6511 6191 if (tp->support_2500full) 6512 6192 support |= RTL_ADVERTISED_2500_FULL; 6193 + 6194 + if (tp->support_5000full) 6195 + support |= RTL_ADVERTISED_5000_FULL; 6513 6196 } 6514 6197 6515 - if (!(advertising & support)) 6198 + advertising &= support; 6199 + if (!advertising) 6516 6200 return -EINVAL; 6517 6201 6518 6202 orig = r8152_mdio_read(tp, MII_ADVERTISE); ··· 6559 6235 r8152_mdio_write(tp, MII_CTRL1000, new1); 6560 6236 } 6561 6237 6562 - if (tp->support_2500full) { 6238 + if (tp->support_2500full || tp->support_5000full) { 6563 6239 orig = ocp_reg_read(tp, OCP_10GBT_CTRL); 6564 - new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; 6240 + new1 = orig & ~(MDIO_AN_10GBT_CTRL_ADV2_5G | MDIO_AN_10GBT_CTRL_ADV5G); 6565 6241 6566 6242 if (advertising & RTL_ADVERTISED_2500_FULL) { 6567 6243 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; 6568 6244 tp->ups_info.speed_duplex = NWAY_2500M_FULL; 6245 + } 6246 + 6247 + if (advertising & RTL_ADVERTISED_5000_FULL) { 6248 + new1 |= MDIO_AN_10GBT_CTRL_ADV5G; 6249 + tp->ups_info.speed_duplex = NWAY_5000M_FULL; 6569 6250 } 6570 6251 6571 6252 if (orig != new1) ··· 6793 6464 /* TX share fifo free credit full threshold */ 6794 6465 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); 6795 6466 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 6796 - ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); 6467 + ALIGN(rx_max_size + tp->tx_desc.size, 1024) / 16); 6797 6468 } 6798 6469 6799 6470 static void rtl8156_up(struct r8152 *tp) ··· 6802 6473 return; 6803 6474 6804 6475 r8153b_u1u2en(tp, false); 6805 - r8153_u2p3en(tp, false); 6476 + if (tp->version != RTL_VER_16) 6477 + r8153_u2p3en(tp, false); 6806 6478 r8153_aldps_en(tp, false); 6807 6479 6808 6480 rxdy_gated_en(tp, true); ··· 6815 6485 rtl_reset_bmu(tp); 6816 6486 6817 6487 ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); 6488 + 6489 + if (tp->version == RTL_VER_16) 6490 + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, BIT(3)); 6818 6491 6819 6492 ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); 6820 6493 ··· 6842 6509 ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 6843 6510 PLA_MCU_SPDWN_EN); 6844 6511 6845 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 6846 - RG_PWRDN_EN | ALL_SPEED_OFF); 6512 + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); 6513 + 6514 + if (tp->version != RTL_VER_16) 6515 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 6516 + RG_PWRDN_EN | ALL_SPEED_OFF); 6847 6517 6848 6518 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); 6849 6519 ··· 6856 6520 } 6857 6521 6858 6522 r8153_aldps_en(tp, true); 6859 - r8153_u2p3en(tp, true); 6523 + if (tp->version != RTL_VER_16) 6524 + r8153_u2p3en(tp, true); 6860 6525 6861 - if (tp->udev->speed >= USB_SPEED_SUPER) 6526 + if (tp->version != RTL_VER_16 && tp->udev->speed >= USB_SPEED_SUPER) 6862 6527 r8153b_u1u2en(tp, true); 6863 6528 } 6864 6529 ··· 6874 6537 PLA_MCU_SPDWN_EN); 6875 6538 6876 6539 r8153b_u1u2en(tp, false); 6877 - r8153_u2p3en(tp, false); 6878 - r8153b_power_cut_en(tp, false); 6540 + if (tp->version != RTL_VER_16) { 6541 + r8153_u2p3en(tp, false); 6542 + r8153b_power_cut_en(tp, false); 6543 + } 6879 6544 r8153_aldps_en(tp, false); 6880 6545 6881 6546 ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); ··· 7950 7611 set_bit(PHY_RESET, &tp->flags); 7951 7612 } 7952 7613 7953 - static void r8156_init(struct r8152 *tp) 7614 + static void r8157_hw_phy_cfg(struct r8152 *tp) 7954 7615 { 7616 + u32 ocp_data; 7955 7617 u16 data; 7956 - int i; 7618 + int ret; 7957 7619 7958 - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7959 - return; 7620 + r8156b_wait_loading_flash(tp); 7960 7621 7961 - ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); 7962 - 7963 - ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 7964 - 7965 - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); 7966 - 7967 - r8153b_u1u2en(tp, false); 7968 - 7969 - for (i = 0; i < 500; i++) { 7970 - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 7971 - AUTOLOAD_DONE) 7972 - break; 7973 - 7974 - msleep(20); 7975 - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7976 - return; 7622 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 7623 + if (ocp_data & PCUT_STATUS) { 7624 + ocp_data &= ~PCUT_STATUS; 7625 + ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 7977 7626 } 7978 7627 7979 7628 data = r8153_phy_status(tp, 0); 7980 - if (data == PHY_STAT_EXT_INIT) 7629 + switch (data) { 7630 + case PHY_STAT_EXT_INIT: 7631 + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); 7981 7632 ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); 7633 + break; 7634 + case PHY_STAT_LAN_ON: 7635 + case PHY_STAT_PWRDN: 7636 + default: 7637 + break; 7638 + } 7982 7639 7983 - r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); 7640 + data = r8152_mdio_read(tp, MII_BMCR); 7641 + if (data & BMCR_PDOWN) { 7642 + data &= ~BMCR_PDOWN; 7643 + r8152_mdio_write(tp, MII_BMCR, data); 7644 + } 7984 7645 7985 - data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7986 - WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 7646 + r8153_aldps_en(tp, false); 7647 + rtl_eee_enable(tp, false); 7987 7648 7988 - r8153_u2p3en(tp, false); 7649 + ret = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7650 + if (ret < 0) 7651 + return; 7652 + WARN_ON_ONCE(ret != PHY_STAT_LAN_ON); 7989 7653 7990 - /* MSC timer = 0xfff * 8ms = 32760 ms */ 7991 - ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 7654 + /* PFM mode */ 7655 + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); 7992 7656 7993 - /* U1/U2/L1 idle timer. 500 us */ 7994 - ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 7657 + /* Advanced Power Saving parameter */ 7658 + ocp_reg_set_bits(tp, 0xa430, BIT(0) | BIT(1)); 7995 7659 7996 - r8153b_power_cut_en(tp, false); 7997 - r8156_ups_en(tp, false); 7998 - r8153_queue_wake(tp, false); 7999 - rtl_runtime_suspend_enable(tp, false); 7660 + /* aldpsce force mode */ 7661 + ocp_reg_clr_bits(tp, 0xa44a, BIT(2)); 8000 7662 8001 - if (tp->udev->speed >= USB_SPEED_SUPER) 8002 - r8153b_u1u2en(tp, true); 7663 + switch (tp->version) { 7664 + case RTL_VER_16: 7665 + /* XG_INRX parameter */ 7666 + sram_write_w0w1(tp, 0x8183, 0xff00, 0x5900); 7667 + ocp_reg_set_bits(tp, 0xa654, BIT(11)); 7668 + ocp_reg_set_bits(tp, 0xb648, BIT(14)); 7669 + ocp_reg_clr_bits(tp, 0xad2c, BIT(15)); 7670 + ocp_reg_set_bits(tp, 0xad94, BIT(5)); 7671 + ocp_reg_set_bits(tp, 0xada0, BIT(1)); 7672 + ocp_reg_w0w1(tp, 0xae06, 0xfc00, 0x7c00); 7673 + sram2_write_w0w1(tp, 0x8647, 0xff00, 0xe600); 7674 + sram2_write_w0w1(tp, 0x8036, 0xff00, 0x3000); 7675 + sram2_write_w0w1(tp, 0x8078, 0xff00, 0x3000); 8003 7676 8004 - usb_enable_lpm(tp->udev); 7677 + /* green mode */ 7678 + sram2_write_w0w1(tp, 0x89e9, 0xff00, 0); 7679 + sram2_write_w0w1(tp, 0x8ffd, 0xff00, 0x0100); 7680 + sram2_write_w0w1(tp, 0x8ffe, 0xff00, 0x0200); 7681 + sram2_write_w0w1(tp, 0x8fff, 0xff00, 0x0400); 8005 7682 8006 - r8156_mac_clk_spd(tp, true); 7683 + /* recognize AQC/Bcom function */ 7684 + sram_write_w0w1(tp, 0x8018, 0xff00, 0x7700); 7685 + ocp_reg_write(tp, OCP_SRAM_ADDR, 0x8f9c); 7686 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0005); 7687 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); 7688 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x00ed); 7689 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0502); 7690 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0b00); 7691 + ocp_reg_write(tp, OCP_SRAM_DATA, 0xd401); 7692 + sram_write_w0w1(tp, 0x8fa8, 0xff00, 0x2900); 8007 7693 8008 - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 8009 - PLA_MCU_SPDWN_EN); 7694 + /* RFI_corr_thd 5g */ 7695 + sram2_write_w0w1(tp, 0x814b, 0xff00, 0x1100); 7696 + sram2_write_w0w1(tp, 0x814d, 0xff00, 0x1100); 7697 + sram2_write_w0w1(tp, 0x814f, 0xff00, 0x0b00); 7698 + sram2_write_w0w1(tp, 0x8142, 0xff00, 0x0100); 7699 + sram2_write_w0w1(tp, 0x8144, 0xff00, 0x0100); 7700 + sram2_write_w0w1(tp, 0x8150, 0xff00, 0x0100); 8010 7701 8011 - if (rtl8152_get_speed(tp) & LINK_STATUS) 8012 - ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, 8013 - CUR_LINK_OK | POLL_LINK_CHG); 8014 - else 8015 - ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, 8016 - POLL_LINK_CHG); 7702 + /* RFI_corr_thd 2p5g */ 7703 + sram2_write_w0w1(tp, 0x8118, 0xff00, 0x0700); 7704 + sram2_write_w0w1(tp, 0x811a, 0xff00, 0x0700); 7705 + sram2_write_w0w1(tp, 0x811c, 0xff00, 0x0500); 7706 + sram2_write_w0w1(tp, 0x810f, 0xff00, 0x0100); 7707 + sram2_write_w0w1(tp, 0x8111, 0xff00, 0x0100); 7708 + sram2_write_w0w1(tp, 0x811d, 0xff00, 0x0100); 8017 7709 8018 - set_bit(GREEN_ETHERNET, &tp->flags); 7710 + /* RFI parameter */ 7711 + ocp_reg_clr_bits(tp, 0xad1c, BIT(8)); 7712 + ocp_reg_w0w1(tp, 0xade8, 0xffc0, 0x1400); 7713 + sram2_write_w0w1(tp, 0x864b, 0xff00, 0x9d00); 7714 + sram2_write_w0w1(tp, 0x862c, 0xff00, 0x1200); 7715 + ocp_reg_write(tp, OCP_SRAM_ADDR, 0x8566); 7716 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x003f); 7717 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x3f02); 7718 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x023c); 7719 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x3b0a); 7720 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x1c00); 7721 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); 7722 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); 7723 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); 7724 + ocp_reg_write(tp, OCP_SRAM_DATA, 0x0000); 8019 7725 8020 - /* rx aggregation */ 8021 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, 8022 - RX_AGG_DISABLE | RX_ZERO_EN); 7726 + /* RFI-color noise gen parameter 5g */ 7727 + ocp_reg_set_bits(tp, 0xad9c, BIT(5)); 7728 + sram2_write_w0w1(tp, 0x8122, 0xff00, 0x0c00); 7729 + ocp_reg_write(tp, OCP_SRAM2_ADDR, 0x82c8); 7730 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ed); 7731 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ff); 7732 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0009); 7733 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03fe); 7734 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000b); 7735 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0021); 7736 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f7); 7737 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03b8); 7738 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03e0); 7739 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0049); 7740 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0049); 7741 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03e0); 7742 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03b8); 7743 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f7); 7744 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0021); 7745 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000b); 7746 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03fe); 7747 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0009); 7748 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ff); 7749 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ed); 8023 7750 8024 - ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); 7751 + /* RFI-color noise gen parameter 2p5g */ 7752 + sram2_write_w0w1(tp, 0x80ef, 0xff00, 0x0c00); 7753 + ocp_reg_write(tp, OCP_SRAM2_ADDR, 0x82a0); 7754 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000e); 7755 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03fe); 7756 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ed); 7757 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0006); 7758 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x001a); 7759 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f1); 7760 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03d8); 7761 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0023); 7762 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0054); 7763 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0322); 7764 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x00dd); 7765 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03ab); 7766 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03dc); 7767 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0027); 7768 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x000e); 7769 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03e5); 7770 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f9); 7771 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0012); 7772 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x0001); 7773 + ocp_reg_write(tp, OCP_SRAM2_DATA, 0x03f1); 8025 7774 8026 - r8156_mdio_force_mode(tp); 8027 - rtl_tally_reset(tp); 7775 + /* modify thermal speed down threshold */ 7776 + ocp_reg_w0w1(tp, 0xb54c, 0xffc0, 0x3700); 8028 7777 8029 - tp->coalesce = 15000; /* 15 us */ 7778 + /* XG compatibility modification */ 7779 + ocp_reg_set_bits(tp, 0xb648, BIT(6)); 7780 + sram2_write_w0w1(tp, 0x8082, 0xff00, 0x5d00); 7781 + sram2_write_w0w1(tp, 0x807c, 0xff00, 0x5000); 7782 + sram2_write_w0w1(tp, 0x809d, 0xff00, 0x5000); 7783 + break; 7784 + default: 7785 + break; 7786 + } 7787 + 7788 + if (rtl_phy_patch_request(tp, true, true)) 7789 + return; 7790 + 7791 + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); 7792 + 7793 + ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, EN_10M_CLKDIV); 7794 + 7795 + tp->ups_info._10m_ckdiv = true; 7796 + tp->ups_info.eee_plloff_100 = false; 7797 + tp->ups_info.eee_plloff_giga = false; 7798 + 7799 + ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); 7800 + tp->ups_info.eee_ckdiv = true; 7801 + 7802 + rtl_phy_patch_request(tp, false, true); 7803 + 7804 + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 7805 + 7806 + ocp_reg_clr_bits(tp, 0xa428, BIT(9)); 7807 + ocp_reg_clr_bits(tp, 0xa5ea, BIT(0) | BIT(1)); 7808 + tp->ups_info.lite_mode = 0; 7809 + 7810 + if (tp->eee_en) 7811 + rtl_eee_enable(tp, true); 7812 + 7813 + r8153_aldps_en(tp, true); 7814 + r8152b_enable_fc(tp); 7815 + 7816 + set_bit(PHY_RESET, &tp->flags); 8030 7817 } 8031 7818 8032 - static void r8156b_init(struct r8152 *tp) 7819 + static void r8156_init(struct r8152 *tp) 8033 7820 { 7821 + u32 ocp_data; 8034 7822 u16 data; 8035 7823 int i; 8036 7824 8037 7825 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8038 7826 return; 8039 7827 7828 + if (tp->version == RTL_VER_16) { 7829 + ocp_byte_set_bits(tp, MCU_TYPE_USB, 0xcffe, BIT(3)); 7830 + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd3ca, BIT(0)); 7831 + } 7832 + 8040 7833 ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); 8041 7834 8042 - ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 7835 + if (tp->version != RTL_VER_16) 7836 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 8043 7837 8044 7838 ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); 8045 7839 8046 - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); 7840 + if (tp->version >= RTL_VER_12 && tp->version <= RTL_VER_15) 7841 + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); 8047 7842 8048 7843 r8153b_u1u2en(tp, false); 8049 7844 8050 7845 switch (tp->version) { 8051 7846 case RTL_VER_13: 8052 7847 case RTL_VER_15: 7848 + case RTL_VER_16: 8053 7849 r8156b_wait_loading_flash(tp); 8054 7850 break; 8055 7851 default: ··· 8204 7730 data = r8153_phy_status(tp, 0); 8205 7731 if (data == PHY_STAT_EXT_INIT) { 8206 7732 ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); 8207 - ocp_reg_clr_bits(tp, 0xa466, BIT(0)); 7733 + if (tp->version >= RTL_VER_12) 7734 + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); 8208 7735 } 8209 7736 8210 - r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); 7737 + data = r8152_mdio_read(tp, MII_BMCR); 7738 + if (data & BMCR_PDOWN) { 7739 + data &= ~BMCR_PDOWN; 7740 + r8152_mdio_write(tp, MII_BMCR, data); 7741 + } 8211 7742 8212 7743 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 8213 7744 8214 - r8153_u2p3en(tp, false); 7745 + if (tp->version == RTL_VER_16) 7746 + r8157_u2p3en(tp, false); 7747 + else 7748 + r8153_u2p3en(tp, false); 8215 7749 8216 7750 /* MSC timer = 0xfff * 8ms = 32760 ms */ 8217 7751 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); ··· 8227 7745 /* U1/U2/L1 idle timer. 500 us */ 8228 7746 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 8229 7747 8230 - r8153b_power_cut_en(tp, false); 7748 + if (tp->version == RTL_VER_16) 7749 + r8157_power_cut_en(tp, false); 7750 + else 7751 + r8153b_power_cut_en(tp, false); 7752 + 8231 7753 r8156_ups_en(tp, false); 8232 7754 r8153_queue_wake(tp, false); 8233 7755 rtl_runtime_suspend_enable(tp, false); ··· 8241 7755 8242 7756 usb_enable_lpm(tp->udev); 8243 7757 8244 - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); 7758 + if (tp->version >= RTL_VER_12 && tp->version <= RTL_VER_15) { 7759 + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); 8245 7760 8246 - ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); 7761 + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); 8247 7762 8248 - /* enable fc timer and set timer to 600 ms. */ 8249 - ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, 8250 - CTRL_TIMER_EN | (600 / 8)); 7763 + /* enable fc timer and set timer to 600 ms. */ 7764 + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, CTRL_TIMER_EN | (600 / 8)); 8251 7765 8252 - if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) 8253 - ocp_word_w0w1(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP, 8254 - FLOW_CTRL_PATCH_2); 8255 - else 8256 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); 7766 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 7767 + if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) 7768 + ocp_data |= FLOW_CTRL_PATCH_2; 7769 + ocp_data &= ~AUTO_SPEEDUP; 7770 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 8257 7771 8258 - ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); 7772 + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); 7773 + } 8259 7774 8260 7775 r8156_mac_clk_spd(tp, true); 8261 7776 8262 - ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 8263 - PLA_MCU_SPDWN_EN); 7777 + if (tp->version != RTL_VER_16) 7778 + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, PLA_MCU_SPDWN_EN); 8264 7779 7780 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 8265 7781 if (rtl8152_get_speed(tp) & LINK_STATUS) 8266 - ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, 8267 - CUR_LINK_OK | POLL_LINK_CHG); 7782 + ocp_data |= CUR_LINK_OK; 8268 7783 else 8269 - ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, 8270 - POLL_LINK_CHG); 7784 + ocp_data &= ~CUR_LINK_OK; 7785 + ocp_data |= POLL_LINK_CHG; 7786 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 8271 7787 8272 7788 set_bit(GREEN_ETHERNET, &tp->flags); 8273 7789 8274 - /* rx aggregation */ 8275 - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, 8276 - RX_AGG_DISABLE | RX_ZERO_EN); 7790 + /* rx aggregation / 16 bytes Rx descriptor */ 7791 + if (tp->version == RTL_VER_16) 7792 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_AGG_DISABLE | RX_DESC_16B); 7793 + else 7794 + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_AGG_DISABLE | RX_ZERO_EN); 7795 + 7796 + if (tp->version < RTL_VER_12) 7797 + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); 7798 + 7799 + if (tp->version == RTL_VER_16) { 7800 + /* Disable Rx Zero Len */ 7801 + rtl_bmu_clr_bits(tp, 0x2300, BIT(3)); 7802 + /* TX descriptor Signature */ 7803 + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); 7804 + } 8277 7805 8278 7806 r8156_mdio_force_mode(tp); 8279 7807 rtl_tally_reset(tp); ··· 8720 8220 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8721 8221 cmd->link_modes.supported, tp->support_2500full); 8722 8222 8723 - if (tp->support_2500full) { 8724 - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8725 - cmd->link_modes.advertising, 8726 - ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); 8223 + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 8224 + cmd->link_modes.supported, tp->support_5000full); 8727 8225 8728 - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8729 - cmd->link_modes.lp_advertising, 8730 - ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); 8226 + if (tp->support_2500full || tp->support_5000full) { 8227 + u16 ocp_10gbt_ctrl = ocp_reg_read(tp, OCP_10GBT_CTRL); 8228 + u16 ocp_10gbt_stat = ocp_reg_read(tp, OCP_10GBT_STAT); 8731 8229 8732 - if (is_speed_2500(rtl8152_get_speed(tp))) 8733 - cmd->base.speed = SPEED_2500; 8230 + if (tp->support_2500full) { 8231 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8232 + cmd->link_modes.advertising, 8233 + ocp_10gbt_ctrl & MDIO_AN_10GBT_CTRL_ADV2_5G); 8234 + 8235 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8236 + cmd->link_modes.lp_advertising, 8237 + ocp_10gbt_stat & MDIO_AN_10GBT_STAT_LP2_5G); 8238 + 8239 + if (is_speed_2500(rtl8152_get_speed(tp))) 8240 + cmd->base.speed = SPEED_2500; 8241 + } 8242 + 8243 + if (tp->support_5000full) { 8244 + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 8245 + cmd->link_modes.advertising, 8246 + ocp_10gbt_ctrl & MDIO_AN_10GBT_CTRL_ADV5G); 8247 + 8248 + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 8249 + cmd->link_modes.lp_advertising, 8250 + ocp_10gbt_stat & MDIO_AN_10GBT_STAT_LP5G); 8251 + 8252 + if (is_speed_5000(rtl8152_get_speed(tp))) 8253 + cmd->base.speed = SPEED_5000; 8254 + } 8734 8255 } 8735 8256 8736 8257 mutex_unlock(&tp->control); ··· 8800 8279 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8801 8280 cmd->link_modes.advertising)) 8802 8281 advertising |= RTL_ADVERTISED_2500_FULL; 8282 + 8283 + if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 8284 + cmd->link_modes.advertising)) 8285 + advertising |= RTL_ADVERTISED_5000_FULL; 8803 8286 8804 8287 mutex_lock(&tp->control); 8805 8288 ··· 8922 8397 8923 8398 tp->eee_en = eee->eee_enabled; 8924 8399 tp->eee_adv = val; 8925 - if (tp->support_2500full) { 8400 + if (tp->support_2500full || tp->support_5000full) { 8926 8401 val = linkmode_to_mii_eee_cap2_t(eee->advertised); 8927 8402 tp->eee_adv2 = val; 8928 8403 } ··· 8946 8421 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 8947 8422 mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); 8948 8423 8949 - if (tp->support_2500full) { 8950 - linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported); 8951 - 8424 + if (tp->support_2500full || tp->support_5000full) { 8952 8425 val = ocp_reg_read(tp, OCP_EEE_ADV2); 8953 8426 mii_eee_cap2_mod_linkmode_adv_t(eee->advertised, val); 8954 8427 8955 8428 val = ocp_reg_read(tp, OCP_EEE_LPABLE2); 8956 8429 mii_eee_cap2_mod_linkmode_adv_t(eee->lp_advertised, val); 8430 + } 8431 + 8432 + if (tp->support_2500full) { 8433 + linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, eee->supported); 8957 8434 8958 8435 if (speed & _2500bps) 8959 8436 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, common); 8437 + } 8438 + 8439 + if (tp->support_5000full) { 8440 + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, eee->supported); 8441 + 8442 + if (speed & _5000bps) 8443 + linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, common); 8960 8444 } 8961 8445 8962 8446 eee->eee_enabled = tp->eee_en; ··· 9437 8903 return; 9438 8904 9439 8905 r8153_power_cut_en(tp, false); 8906 + 8907 + if (tp->version >= RTL_VER_16) { 8908 + /* Disable Interrupt Mitigation */ 8909 + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, BIT(0) | BIT(1) | BIT(2) | BIT(7)); 8910 + } 9440 8911 } 9441 8912 9442 8913 static void rtl8153b_unload(struct r8152 *tp) ··· 9450 8911 return; 9451 8912 9452 8913 r8153b_power_cut_en(tp, false); 8914 + } 8915 + 8916 + static int r8152_desc_init(struct r8152 *tp) 8917 + { 8918 + tp->rx_desc.size = sizeof(struct rx_desc); 8919 + tp->rx_desc.align = 8; 8920 + tp->rx_desc.vlan_tag = r8152_rx_vlan_tag; 8921 + tp->desc_ops.rx_csum = r8152_rx_csum; 8922 + tp->desc_ops.rx_len = r8152_rx_len; 8923 + tp->tx_desc.size = sizeof(struct tx_desc); 8924 + tp->tx_desc.align = 4; 8925 + tp->tx_desc.vlan_tag = r8152_tx_vlan_tag; 8926 + tp->desc_ops.tx_csum = r8152_tx_csum; 8927 + tp->desc_ops.tx_len = r8152_tx_len; 8928 + 8929 + return 0; 8930 + } 8931 + 8932 + static int r8157_desc_init(struct r8152 *tp) 8933 + { 8934 + tp->rx_desc.size = sizeof(struct rx_desc_v2); 8935 + tp->rx_desc.align = 16; 8936 + tp->rx_desc.vlan_tag = r8157_rx_vlan_tag; 8937 + tp->desc_ops.rx_csum = r8157_rx_csum; 8938 + tp->desc_ops.rx_len = r8157_rx_len; 8939 + tp->tx_desc.size = sizeof(struct tx_desc_v2); 8940 + tp->tx_desc.align = 16; 8941 + tp->tx_desc.vlan_tag = r8152_tx_vlan_tag; 8942 + tp->desc_ops.tx_csum = r8157_tx_csum; 8943 + tp->desc_ops.tx_len = r8157_tx_len; 8944 + 8945 + return 0; 9453 8946 } 9454 8947 9455 8948 static int rtl_ops_init(struct r8152 *tp) ··· 9507 8936 tp->rx_buf_sz = 16 * 1024; 9508 8937 tp->eee_en = true; 9509 8938 tp->eee_adv = MDIO_EEE_100TX; 8939 + r8152_desc_init(tp); 9510 8940 break; 9511 8941 9512 8942 case RTL_VER_03: ··· 9532 8960 tp->rx_buf_sz = 32 * 1024; 9533 8961 tp->eee_en = true; 9534 8962 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 8963 + r8152_desc_init(tp); 9535 8964 break; 9536 8965 9537 8966 case RTL_VER_08: ··· 9552 8979 tp->rx_buf_sz = 32 * 1024; 9553 8980 tp->eee_en = true; 9554 8981 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 8982 + r8152_desc_init(tp); 9555 8983 break; 9556 8984 9557 8985 case RTL_VER_11: ··· 9575 9001 ops->change_mtu = rtl8156_change_mtu; 9576 9002 tp->rx_buf_sz = 48 * 1024; 9577 9003 tp->support_2500full = 1; 9004 + r8152_desc_init(tp); 9578 9005 break; 9579 9006 9580 9007 case RTL_VER_12: ··· 9586 9011 tp->eee_en = true; 9587 9012 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9588 9013 tp->eee_adv2 = MDIO_EEE_2_5GT; 9589 - ops->init = r8156b_init; 9590 - ops->enable = rtl8156b_enable; 9014 + ops->init = r8156_init; 9015 + ops->enable = rtl8156_enable; 9591 9016 ops->disable = rtl8153_disable; 9592 9017 ops->up = rtl8156_up; 9593 9018 ops->down = rtl8156_down; ··· 9599 9024 ops->autosuspend_en = rtl8156_runtime_enable; 9600 9025 ops->change_mtu = rtl8156_change_mtu; 9601 9026 tp->rx_buf_sz = 48 * 1024; 9027 + r8152_desc_init(tp); 9602 9028 break; 9603 9029 9604 9030 case RTL_VER_14: ··· 9618 9042 tp->rx_buf_sz = 32 * 1024; 9619 9043 tp->eee_en = true; 9620 9044 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9045 + r8152_desc_init(tp); 9046 + break; 9047 + 9048 + case RTL_VER_16: 9049 + tp->eee_en = true; 9050 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9051 + tp->eee_adv2 = MDIO_EEE_2_5GT | MDIO_EEE_5GT; 9052 + ops->init = r8156_init; 9053 + ops->enable = rtl8156_enable; 9054 + ops->disable = rtl8153_disable; 9055 + ops->up = rtl8156_up; 9056 + ops->down = rtl8156_down; 9057 + ops->unload = rtl8153_unload; 9058 + ops->eee_get = r8153_get_eee; 9059 + ops->eee_set = r8152_set_eee; 9060 + ops->in_nway = rtl8153_in_nway; 9061 + ops->hw_phy_cfg = r8157_hw_phy_cfg; 9062 + ops->autosuspend_en = rtl8157_runtime_enable; 9063 + ops->change_mtu = rtl8156_change_mtu; 9064 + tp->rx_buf_sz = 32 * 1024; 9065 + tp->support_2500full = 1; 9066 + tp->support_5000full = 1; 9067 + r8157_desc_init(tp); 9621 9068 break; 9622 9069 9623 9070 default: ··· 9793 9194 case 0x7420: 9794 9195 version = RTL_VER_15; 9795 9196 break; 9197 + case 0x1030: 9198 + version = RTL_VER_16; 9199 + break; 9796 9200 default: 9797 9201 version = RTL_VER_UNKNOWN; 9798 9202 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); ··· 9947 9345 case RTL_VER_12: 9948 9346 case RTL_VER_13: 9949 9347 case RTL_VER_15: 9348 + case RTL_VER_16: 9950 9349 netdev->max_mtu = size_to_mtu(16 * 1024); 9951 9350 break; 9952 9351 case RTL_VER_01: ··· 9976 9373 tp->advertising |= RTL_ADVERTISED_2500_FULL; 9977 9374 } else { 9978 9375 tp->speed = SPEED_1000; 9376 + } 9377 + if (tp->support_5000full && 9378 + tp->udev->speed >= USB_SPEED_SUPER) { 9379 + tp->speed = SPEED_5000; 9380 + tp->advertising |= RTL_ADVERTISED_5000_FULL; 9979 9381 } 9980 9382 tp->advertising |= RTL_ADVERTISED_1000_FULL; 9981 9383 } ··· 10107 9499 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, 10108 9500 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, 10109 9501 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, 9502 + { USB_DEVICE(VENDOR_ID_REALTEK, 0x8157) }, 10110 9503 10111 9504 /* Microsoft */ 10112 9505 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },

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