Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/wm: Add WM0 prefill helpers
Add skl_wm0_prefill_lines() (based on the actual state) and
skl_wm0_prefill_lines_worst() (worst case estimate) which
tell us how many extra lines are needed in prefill for WM0.
The returned numbers are in .16 binary fixed point.
TODO: skl_wm0_prefill_lines_worst() is a bit rough still
v2: Drop all pre-icl FIXMEs since this only gets used for VRR guardband
Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-8-ville.syrjala@linux.intel.com
+95
-1
+31
-1
drivers/gpu/drm/i915/display/skl_scaler.c
+31
-1
drivers/gpu/drm/i915/display/skl_scaler.c
···
1026
1026
crtc_state->hw.pipe_mode.crtc_clock));
1027
1027
}
1028
1028
1029
-
static unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
1029
+
unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state)
1030
+
{
1031
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1032
+
unsigned int max_scale;
1033
+
1034
+
if (crtc->num_scalers < 1)
1035
+
return 0x10000;
1036
+
1037
+
/* FIXME find out the max downscale factors properly */
1038
+
max_scale = 9 << 16;
1039
+
if (crtc->num_scalers > 1)
1040
+
max_scale *= 9;
1041
+
1042
+
return _skl_scaler_max_scale(crtc_state, max_scale);
1043
+
}
1044
+
1045
+
unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state)
1046
+
{
1047
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1048
+
unsigned int max_scale;
1049
+
1050
+
if (crtc->num_scalers < 1)
1051
+
return 0x10000;
1052
+
1053
+
/* FIXME find out the max downscale factors properly */
1054
+
max_scale = 3 << 16;
1055
+
1056
+
return _skl_scaler_max_scale(crtc_state, max_scale);
1057
+
}
1058
+
1059
+
unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state)
1030
1060
{
1031
1061
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1032
1062
unsigned int max_scale;
+4
drivers/gpu/drm/i915/display/skl_scaler.h
+4
drivers/gpu/drm/i915/display/skl_scaler.h
···
46
46
47
47
void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
48
48
49
+
unsigned int skl_scaler_max_total_scale(const struct intel_crtc_state *crtc_state);
50
+
unsigned int skl_scaler_max_scale(const struct intel_crtc_state *crtc_state);
51
+
unsigned int skl_scaler_max_hscale(const struct intel_crtc_state *crtc_state);
52
+
49
53
unsigned int skl_scaler_1st_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
50
54
unsigned int skl_scaler_2nd_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state);
51
55
unsigned int skl_scaler_1st_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
+57
drivers/gpu/drm/i915/display/skl_watermark.c
+57
drivers/gpu/drm/i915/display/skl_watermark.c
···
30
30
#include "intel_plane.h"
31
31
#include "intel_vblank.h"
32
32
#include "intel_wm.h"
33
+
#include "skl_scaler.h"
33
34
#include "skl_universal_plane_regs.h"
34
35
#include "skl_watermark.h"
35
36
#include "skl_watermark_regs.h"
···
2246
2245
intel_crtc_vblank_length(crtc_state);
2247
2246
}
2248
2247
2248
+
unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state)
2249
+
{
2250
+
struct intel_display *display = to_intel_display(crtc_state);
2251
+
struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->primary);
2252
+
const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2253
+
int ret, pixel_rate, width, level = 0;
2254
+
const struct drm_format_info *info;
2255
+
struct skl_wm_level wm = {};
2256
+
struct skl_wm_params wp;
2257
+
unsigned int latency;
2258
+
u64 modifier;
2259
+
u32 format;
2260
+
2261
+
/* only expected to be used for VRR guardband calculation */
2262
+
drm_WARN_ON(display->drm, !HAS_VRR(display));
2263
+
2264
+
/* FIXME rather ugly to pick this by hand but maybe no better way? */
2265
+
format = DRM_FORMAT_XBGR16161616F;
2266
+
if (HAS_4TILE(display))
2267
+
modifier = I915_FORMAT_MOD_4_TILED;
2268
+
else
2269
+
modifier = I915_FORMAT_MOD_Y_TILED;
2270
+
2271
+
info = drm_get_format_info(display->drm, format, modifier);
2272
+
2273
+
pixel_rate = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_total_scale(crtc_state),
2274
+
pipe_mode->crtc_clock),
2275
+
0x10000);
2276
+
2277
+
/* FIXME limit to max plane width? */
2278
+
width = DIV_ROUND_UP_ULL(mul_u32_u32(skl_scaler_max_hscale(crtc_state),
2279
+
pipe_mode->crtc_hdisplay),
2280
+
0x10000);
2281
+
2282
+
/* FIXME is 90/270 rotation worse than 0/180? */
2283
+
ret = skl_compute_wm_params(crtc_state, width, info,
2284
+
modifier, DRM_MODE_ROTATE_0,
2285
+
pixel_rate, &wp, 0, 1);
2286
+
drm_WARN_ON(display->drm, ret);
2287
+
2288
+
latency = skl_wm_latency(display, level, &wp);
2289
+
2290
+
skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
2291
+
2292
+
/* FIXME is this sane? */
2293
+
if (wm.min_ddb_alloc == U16_MAX)
2294
+
wm.lines = skl_wm_max_lines(display);
2295
+
2296
+
return wm.lines << 16;
2297
+
}
2298
+
2249
2299
static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
2250
2300
{
2251
2301
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
···
2311
2259
}
2312
2260
2313
2261
return wm0_lines;
2262
+
}
2263
+
2264
+
unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state)
2265
+
{
2266
+
return skl_max_wm0_lines(crtc_state) << 16;
2314
2267
}
2315
2268
2316
2269
/*
+3
drivers/gpu/drm/i915/display/skl_watermark.h
+3
drivers/gpu/drm/i915/display/skl_watermark.h
···
79
79
80
80
bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
81
81
82
+
unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
83
+
unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state);
84
+
82
85
#endif /* __SKL_WATERMARK_H__ */
83
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