drm/amdgpu: clean unused functions of uvd/vcn/vce

-274

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

··· 1462 1462 amdgpu_ring_write(ring, val); 1463 1463 } 1464 1464 1465 - #if 0 1466 - static bool uvd_v7_0_is_idle(void *handle) 1467 - { 1468 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 - 1470 - return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1471 - } 1472 - 1473 - static int uvd_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1474 - { 1475 - unsigned i; 1476 - struct amdgpu_device *adev = ip_block->adev; 1477 - 1478 - for (i = 0; i < adev->usec_timeout; i++) { 1479 - if (uvd_v7_0_is_idle(handle)) 1480 - return 0; 1481 - } 1482 - return -ETIMEDOUT; 1483 - } 1484 - 1485 - #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1486 - static bool uvd_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 1487 - { 1488 - struct amdgpu_device *adev = ip_block->adev; 1489 - u32 srbm_soft_reset = 0; 1490 - u32 tmp = RREG32(mmSRBM_STATUS); 1491 - 1492 - if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1493 - REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1494 - (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & 1495 - AMDGPU_UVD_STATUS_BUSY_MASK)) 1496 - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1497 - SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1498 - 1499 - if (srbm_soft_reset) { 1500 - adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; 1501 - return true; 1502 - } else { 1503 - adev->uvd.inst[ring->me].srbm_soft_reset = 0; 1504 - return false; 1505 - } 1506 - } 1507 - 1508 - static int uvd_v7_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 1509 - { 1510 - struct amdgpu_device *adev = ip_block->adev; 1511 - 1512 - if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1513 - return 0; 1514 - 1515 - uvd_v7_0_stop(adev); 1516 - return 0; 1517 - } 1518 - 1519 - static int uvd_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 1520 - { 1521 - struct amdgpu_device *adev = ip_block->adev; 1522 - u32 srbm_soft_reset; 1523 - 1524 - if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1525 - return 0; 1526 - srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; 1527 - 1528 - if (srbm_soft_reset) { 1529 - u32 tmp; 1530 - 1531 - tmp = RREG32(mmSRBM_SOFT_RESET); 1532 - tmp |= srbm_soft_reset; 1533 - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1534 - WREG32(mmSRBM_SOFT_RESET, tmp); 1535 - tmp = RREG32(mmSRBM_SOFT_RESET); 1536 - 1537 - udelay(50); 1538 - 1539 - tmp &= ~srbm_soft_reset; 1540 - WREG32(mmSRBM_SOFT_RESET, tmp); 1541 - tmp = RREG32(mmSRBM_SOFT_RESET); 1542 - 1543 - /* Wait a little for things to settle down */ 1544 - udelay(50); 1545 - } 1546 - 1547 - return 0; 1548 - } 1549 - 1550 - static int uvd_v7_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 1551 - { 1552 - struct amdgpu_device *adev = ip_block->adev; 1553 - 1554 - if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1555 - return 0; 1556 - 1557 - mdelay(5); 1558 - 1559 - return uvd_v7_0_start(adev); 1560 - } 1561 - #endif 1562 - 1563 1465 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1564 1466 struct amdgpu_irq_src *source, 1565 1467 unsigned type, ··· 1511 1609 return 0; 1512 1610 } 1513 1611 1514 - #if 0 1515 - static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) 1516 - { 1517 - uint32_t data, data1, data2, suvd_flags; 1518 - 1519 - data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1520 - data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1521 - data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1522 - 1523 - data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1524 - UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1525 - 1526 - suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1527 - UVD_SUVD_CGC_GATE__SIT_MASK | 1528 - UVD_SUVD_CGC_GATE__SMP_MASK | 1529 - UVD_SUVD_CGC_GATE__SCM_MASK | 1530 - UVD_SUVD_CGC_GATE__SDB_MASK; 1531 - 1532 - data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1533 - (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1534 - (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1535 - 1536 - data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1537 - UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1538 - UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1539 - UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1540 - UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1541 - UVD_CGC_CTRL__SYS_MODE_MASK | 1542 - UVD_CGC_CTRL__UDEC_MODE_MASK | 1543 - UVD_CGC_CTRL__MPEG2_MODE_MASK | 1544 - UVD_CGC_CTRL__REGS_MODE_MASK | 1545 - UVD_CGC_CTRL__RBC_MODE_MASK | 1546 - UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1547 - UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1548 - UVD_CGC_CTRL__IDCT_MODE_MASK | 1549 - UVD_CGC_CTRL__MPRD_MODE_MASK | 1550 - UVD_CGC_CTRL__MPC_MODE_MASK | 1551 - UVD_CGC_CTRL__LBSI_MODE_MASK | 1552 - UVD_CGC_CTRL__LRBBM_MODE_MASK | 1553 - UVD_CGC_CTRL__WCB_MODE_MASK | 1554 - UVD_CGC_CTRL__VCPU_MODE_MASK | 1555 - UVD_CGC_CTRL__JPEG_MODE_MASK | 1556 - UVD_CGC_CTRL__JPEG2_MODE_MASK | 1557 - UVD_CGC_CTRL__SCPU_MODE_MASK); 1558 - data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1559 - UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1560 - UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1561 - UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1562 - UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1563 - data1 |= suvd_flags; 1564 - 1565 - WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); 1566 - WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); 1567 - WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1568 - WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); 1569 - } 1570 - 1571 - static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) 1572 - { 1573 - uint32_t data, data1, cgc_flags, suvd_flags; 1574 - 1575 - data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); 1576 - data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1577 - 1578 - cgc_flags = UVD_CGC_GATE__SYS_MASK | 1579 - UVD_CGC_GATE__UDEC_MASK | 1580 - UVD_CGC_GATE__MPEG2_MASK | 1581 - UVD_CGC_GATE__RBC_MASK | 1582 - UVD_CGC_GATE__LMI_MC_MASK | 1583 - UVD_CGC_GATE__IDCT_MASK | 1584 - UVD_CGC_GATE__MPRD_MASK | 1585 - UVD_CGC_GATE__MPC_MASK | 1586 - UVD_CGC_GATE__LBSI_MASK | 1587 - UVD_CGC_GATE__LRBBM_MASK | 1588 - UVD_CGC_GATE__UDEC_RE_MASK | 1589 - UVD_CGC_GATE__UDEC_CM_MASK | 1590 - UVD_CGC_GATE__UDEC_IT_MASK | 1591 - UVD_CGC_GATE__UDEC_DB_MASK | 1592 - UVD_CGC_GATE__UDEC_MP_MASK | 1593 - UVD_CGC_GATE__WCB_MASK | 1594 - UVD_CGC_GATE__VCPU_MASK | 1595 - UVD_CGC_GATE__SCPU_MASK | 1596 - UVD_CGC_GATE__JPEG_MASK | 1597 - UVD_CGC_GATE__JPEG2_MASK; 1598 - 1599 - suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1600 - UVD_SUVD_CGC_GATE__SIT_MASK | 1601 - UVD_SUVD_CGC_GATE__SMP_MASK | 1602 - UVD_SUVD_CGC_GATE__SCM_MASK | 1603 - UVD_SUVD_CGC_GATE__SDB_MASK; 1604 - 1605 - data |= cgc_flags; 1606 - data1 |= suvd_flags; 1607 - 1608 - WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); 1609 - WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1610 - } 1611 - 1612 - static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 1613 - { 1614 - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1615 - 1616 - if (enable) 1617 - tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1618 - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1619 - else 1620 - tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1621 - GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1622 - 1623 - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 1624 - } 1625 - 1626 - 1627 - static int uvd_v7_0_set_clockgating_state(void *handle, 1628 - enum amd_clockgating_state state) 1629 - { 1630 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1631 - bool enable = (state == AMD_CG_STATE_GATE); 1632 - struct amdgpu_ip_block *ip_block; 1633 - 1634 - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD); 1635 - if (!ip_block) 1636 - return -EINVAL; 1637 - 1638 - uvd_v7_0_set_bypass_mode(adev, enable); 1639 - 1640 - if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 1641 - return 0; 1642 - 1643 - if (enable) { 1644 - /* disable HW gating and enable Sw gating */ 1645 - uvd_v7_0_set_sw_clock_gating(adev); 1646 - } else { 1647 - /* wait for STATUS to clear */ 1648 - if (uvd_v7_0_wait_for_idle(ip_block)) 1649 - return -EBUSY; 1650 - 1651 - /* enable HW gates because UVD is idle */ 1652 - /* uvd_v7_0_set_hw_clock_gating(adev); */ 1653 - } 1654 - 1655 - return 0; 1656 - } 1657 - 1658 - static int uvd_v7_0_set_powergating_state(void *handle, 1659 - enum amd_powergating_state state) 1660 - { 1661 - /* This doesn't actually powergate the UVD block. 1662 - * That's done in the dpm code via the SMC. This 1663 - * just re-inits the block as necessary. The actual 1664 - * gating still happens in the dpm code. We should 1665 - * revisit this when there is a cleaner line between 1666 - * the smc and the hw blocks 1667 - */ 1668 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1669 - 1670 - if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1671 - return 0; 1672 - 1673 - WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1674 - 1675 - if (state == AMD_PG_STATE_GATE) { 1676 - uvd_v7_0_stop(adev); 1677 - return 0; 1678 - } else { 1679 - return uvd_v7_0_start(adev); 1680 - } 1681 - } 1682 - #endif 1683 - 1684 1612 static int uvd_v7_0_set_clockgating_state(void *handle, 1685 1613 enum amd_clockgating_state state) 1686 1614 { ··· 1528 1796 .prepare_suspend = uvd_v7_0_prepare_suspend, 1529 1797 .suspend = uvd_v7_0_suspend, 1530 1798 .resume = uvd_v7_0_resume, 1531 - .is_idle = NULL /* uvd_v7_0_is_idle */, 1532 - .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, 1533 - .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, 1534 - .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, 1535 - .soft_reset = NULL /* uvd_v7_0_soft_reset */, 1536 - .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, 1537 1799 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1538 1800 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1539 1801 };

-273

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

··· 691 691 return 0; 692 692 } 693 693 694 - #if 0 695 - static bool vce_v4_0_is_idle(void *handle) 696 - { 697 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 698 - u32 mask = 0; 699 - 700 - mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK; 701 - mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK; 702 - 703 - return !(RREG32(mmSRBM_STATUS2) & mask); 704 - } 705 - 706 - static int vce_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 707 - { 708 - unsigned i; 709 - struct amdgpu_device *adev = ip_block->adev; 710 - 711 - for (i = 0; i < adev->usec_timeout; i++) 712 - if (vce_v4_0_is_idle(handle)) 713 - return 0; 714 - 715 - return -ETIMEDOUT; 716 - } 717 - 718 - #define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK 0x00000008L /* AUTO_BUSY */ 719 - #define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK 0x00000010L /* RB0_BUSY */ 720 - #define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK 0x00000020L /* RB1_BUSY */ 721 - #define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \ 722 - VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK) 723 - 724 - static bool vce_v4_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 725 - { 726 - struct amdgpu_device *adev = ip_block->adev; 727 - u32 srbm_soft_reset = 0; 728 - 729 - /* According to VCE team , we should use VCE_STATUS instead 730 - * SRBM_STATUS.VCE_BUSY bit for busy status checking. 731 - * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE 732 - * instance's registers are accessed 733 - * (0 for 1st instance, 10 for 2nd instance). 734 - * 735 - *VCE_STATUS 736 - *|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB | 737 - *|----+----+-----------+----+----+----+----------+---------+----| 738 - *|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0| 739 - * 740 - * VCE team suggest use bit 3--bit 6 for busy status check 741 - */ 742 - mutex_lock(&adev->grbm_idx_mutex); 743 - WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 744 - if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { 745 - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); 746 - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); 747 - } 748 - WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10); 749 - if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) { 750 - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1); 751 - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); 752 - } 753 - WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0); 754 - mutex_unlock(&adev->grbm_idx_mutex); 755 - 756 - if (srbm_soft_reset) { 757 - adev->vce.srbm_soft_reset = srbm_soft_reset; 758 - return true; 759 - } else { 760 - adev->vce.srbm_soft_reset = 0; 761 - return false; 762 - } 763 - } 764 - 765 - static int vce_v4_0_soft_reset(struct amdgpu_ip_block *ip_block) 766 - { 767 - struct amdgpu_device *adev = ip_block->adev; 768 - u32 srbm_soft_reset; 769 - 770 - if (!adev->vce.srbm_soft_reset) 771 - return 0; 772 - srbm_soft_reset = adev->vce.srbm_soft_reset; 773 - 774 - if (srbm_soft_reset) { 775 - u32 tmp; 776 - 777 - tmp = RREG32(mmSRBM_SOFT_RESET); 778 - tmp |= srbm_soft_reset; 779 - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 780 - WREG32(mmSRBM_SOFT_RESET, tmp); 781 - tmp = RREG32(mmSRBM_SOFT_RESET); 782 - 783 - udelay(50); 784 - 785 - tmp &= ~srbm_soft_reset; 786 - WREG32(mmSRBM_SOFT_RESET, tmp); 787 - tmp = RREG32(mmSRBM_SOFT_RESET); 788 - 789 - /* Wait a little for things to settle down */ 790 - udelay(50); 791 - } 792 - 793 - return 0; 794 - } 795 - 796 - static int vce_v4_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 797 - { 798 - struct amdgpu_device *adev = ip_block->adev; 799 - 800 - if (!adev->vce.srbm_soft_reset) 801 - return 0; 802 - 803 - mdelay(5); 804 - 805 - return vce_v4_0_suspend(adev); 806 - } 807 - 808 - 809 - static int vce_v4_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 810 - { 811 - struct amdgpu_device *adev = ip_block->adev; 812 - 813 - if (!adev->vce.srbm_soft_reset) 814 - return 0; 815 - 816 - mdelay(5); 817 - 818 - return vce_v4_0_resume(adev); 819 - } 820 - 821 - static void vce_v4_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override) 822 - { 823 - u32 tmp, data; 824 - 825 - tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL)); 826 - if (override) 827 - data |= VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK; 828 - else 829 - data &= ~VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK; 830 - 831 - if (tmp != data) 832 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data); 833 - } 834 - 835 - static void vce_v4_0_set_vce_sw_clock_gating(struct amdgpu_device *adev, 836 - bool gated) 837 - { 838 - u32 data; 839 - 840 - /* Set Override to disable Clock Gating */ 841 - vce_v4_0_override_vce_clock_gating(adev, true); 842 - 843 - /* This function enables MGCG which is controlled by firmware. 844 - With the clocks in the gated state the core is still 845 - accessible but the firmware will throttle the clocks on the 846 - fly as necessary. 847 - */ 848 - if (gated) { 849 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B)); 850 - data |= 0x1ff; 851 - data &= ~0xef0000; 852 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data); 853 - 854 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); 855 - data |= 0x3ff000; 856 - data &= ~0xffc00000; 857 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); 858 - 859 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2)); 860 - data |= 0x2; 861 - data &= ~0x00010000; 862 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data); 863 - 864 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING)); 865 - data |= 0x37f; 866 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data); 867 - 868 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); 869 - data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK | 870 - VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK | 871 - VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK | 872 - 0x8; 873 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); 874 - } else { 875 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B)); 876 - data &= ~0x80010; 877 - data |= 0xe70008; 878 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data); 879 - 880 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING)); 881 - data |= 0xffc00000; 882 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data); 883 - 884 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2)); 885 - data |= 0x10000; 886 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data); 887 - 888 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING)); 889 - data &= ~0xffc00000; 890 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data); 891 - 892 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); 893 - data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK | 894 - VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK | 895 - VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK | 896 - 0x8); 897 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); 898 - } 899 - vce_v4_0_override_vce_clock_gating(adev, false); 900 - } 901 - 902 - static void vce_v4_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 903 - { 904 - u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 905 - 906 - if (enable) 907 - tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; 908 - else 909 - tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; 910 - 911 - WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 912 - } 913 - 914 - static int vce_v4_0_set_clockgating_state(void *handle, 915 - enum amd_clockgating_state state) 916 - { 917 - struct amdgpu_device *adev = (struct amdgpu_device *)handle; 918 - bool enable = (state == AMD_CG_STATE_GATE); 919 - int i; 920 - 921 - if ((adev->asic_type == CHIP_POLARIS10) || 922 - (adev->asic_type == CHIP_TONGA) || 923 - (adev->asic_type == CHIP_FIJI)) 924 - vce_v4_0_set_bypass_mode(adev, enable); 925 - 926 - if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) 927 - return 0; 928 - 929 - mutex_lock(&adev->grbm_idx_mutex); 930 - for (i = 0; i < 2; i++) { 931 - /* Program VCE Instance 0 or 1 if not harvested */ 932 - if (adev->vce.harvest_config & (1 << i)) 933 - continue; 934 - 935 - WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i); 936 - 937 - if (enable) { 938 - /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */ 939 - uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A); 940 - data &= ~(0xf | 0xff0); 941 - data |= ((0x0 << 0) | (0x04 << 4)); 942 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data); 943 - 944 - /* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */ 945 - data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING); 946 - data &= ~(0xf | 0xff0); 947 - data |= ((0x0 << 0) | (0x04 << 4)); 948 - WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data); 949 - } 950 - 951 - vce_v4_0_set_vce_sw_clock_gating(adev, enable); 952 - } 953 - 954 - WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); 955 - mutex_unlock(&adev->grbm_idx_mutex); 956 - 957 - return 0; 958 - } 959 - #endif 960 - 961 694 static int vce_v4_0_set_powergating_state(void *handle, 962 695 enum amd_powergating_state state) 963 696 { ··· 815 1082 .hw_fini = vce_v4_0_hw_fini, 816 1083 .suspend = vce_v4_0_suspend, 817 1084 .resume = vce_v4_0_resume, 818 - .is_idle = NULL /* vce_v4_0_is_idle */, 819 - .wait_for_idle = NULL /* vce_v4_0_wait_for_idle */, 820 - .check_soft_reset = NULL /* vce_v4_0_check_soft_reset */, 821 - .pre_soft_reset = NULL /* vce_v4_0_pre_soft_reset */, 822 - .soft_reset = NULL /* vce_v4_0_soft_reset */, 823 - .post_soft_reset = NULL /* vce_v4_0_post_soft_reset */, 824 1085 .set_clockgating_state = vce_v4_0_set_clockgating_state, 825 1086 .set_powergating_state = vce_v4_0_set_powergating_state, 826 1087 };

-4

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

··· 1995 1995 .resume = vcn_v1_0_resume, 1996 1996 .is_idle = vcn_v1_0_is_idle, 1997 1997 .wait_for_idle = vcn_v1_0_wait_for_idle, 1998 - .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1999 - .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 2000 - .soft_reset = NULL /* vcn_v1_0_soft_reset */, 2001 - .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 2002 1998 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 2003 1999 .set_powergating_state = vcn_v1_0_set_powergating_state, 2004 2000 .dump_ip_state = vcn_v1_0_dump_ip_state,

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