tjh.dev / kernel
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Merge tag 'cris-changes-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris

Pull arch/chris updates from Jesper Nilsson:
"Mostly cleanup and build fixes for CRISv32 allmodconfig

God Jul och Gott Nytt år!"

* tag 'cris-changes-for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris:
CRISv32: Remove last remnants of ETRAX_SPI_MMC_BOARD
CRISv32: ETRAXFS: Fix recursive spinlock
CRISv32: Select MTDRAM for axisflashmap
CRISv32: Implement early console
CRIS: Use KALLSYMs if available in call stack dump
CRISv32: Fix declaration mismatch
CRISv32: Rewrite of synchronous serial port driver
CRIS: Update init memory handling
CRISv32: Better handling of watchdog bite
CRIS: Export missing function symbols
CRIS: Export ioremap_nocache
CRIS: Fix headers_install
CRISv32: Add missing include for mm.h
CRISv32: Drop obsolete file for SPI driver

Linus Torvalds 971d9e07 acab1f88

+1049 -826
+7 -7
arch/cris/arch-v10/lib/usercopy.c
··· 30 30 /* Copy to userspace. This is based on the memcpy used for 31 31 kernel-to-kernel copying; see "string.c". */ 32 32 33 - unsigned long 34 - __copy_user (void __user *pdst, const void *psrc, unsigned long pn) 33 + unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn) 35 34 { 36 35 /* We want the parameters put in special registers. 37 36 Make sure the compiler is able to make something useful of this. ··· 186 187 187 188 return retn; 188 189 } 190 + EXPORT_SYMBOL(__copy_user); 189 191 190 192 /* Copy from user to kernel, zeroing the bytes that were inaccessible in 191 193 userland. The return-value is the number of bytes that were 192 194 inaccessible. */ 193 195 194 - unsigned long 195 - __copy_user_zeroing(void *pdst, const void __user *psrc, unsigned long pn) 196 + unsigned long __copy_user_zeroing(void *pdst, const void __user *psrc, 197 + unsigned long pn) 196 198 { 197 199 /* We want the parameters put in special registers. 198 200 Make sure the compiler is able to make something useful of this. ··· 369 369 370 370 return retn + n; 371 371 } 372 + EXPORT_SYMBOL(__copy_user_zeroing); 372 373 373 374 /* Zero userspace. */ 374 - 375 - unsigned long 376 - __do_clear_user (void __user *pto, unsigned long pn) 375 + unsigned long __do_clear_user(void __user *pto, unsigned long pn) 377 376 { 378 377 /* We want the parameters put in special registers. 379 378 Make sure the compiler is able to make something useful of this. ··· 520 521 521 522 return retn; 522 523 } 524 + EXPORT_SYMBOL(__do_clear_user);
+1 -7
arch/cris/arch-v32/drivers/Kconfig
··· 108 108 select MTD_JEDECPROBE 109 109 select MTD_BLOCK 110 110 select MTD_COMPLEX_MAPPINGS 111 + select MTD_MTDRAM 111 112 help 112 113 This option enables MTD mapping of flash devices. Needed to use 113 114 flash memories. If unsure, say Y. ··· 359 358 default MMC 360 359 select SPI 361 360 select MMC_SPI 362 - select ETRAX_SPI_MMC_BOARD 363 - 364 - # For the parts that can't be a module (due to restrictions in 365 - # framework elsewhere). 366 - config ETRAX_SPI_MMC_BOARD 367 - boolean 368 - default n 369 361 370 362 # While the board info is MMC_SPI only, the drivers are written to be 371 363 # independent of MMC_SPI, so we'll keep SPI non-dependent on the
-1
arch/cris/arch-v32/drivers/Makefile
··· 10 10 obj-$(CONFIG_ETRAX_I2C) += i2c.o 11 11 obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o 12 12 obj-$(CONFIG_PCI) += pci/ 13 - obj-$(CONFIG_ETRAX_SPI_MMC_BOARD) += board_mmcspi.o
-1
arch/cris/arch-v32/drivers/i2c.h
··· 2 2 #include <linux/init.h> 3 3 4 4 /* High level I2C actions */ 5 - int __init i2c_init(void); 6 5 int i2c_write(unsigned char theSlave, void *data, size_t nbytes); 7 6 int i2c_read(unsigned char theSlave, void *data, size_t nbytes); 8 7 int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
+794 -642
arch/cris/arch-v32/drivers/sync_serial.c
··· 1 1 /* 2 - * Simple synchronous serial port driver for ETRAX FS and Artpec-3. 2 + * Simple synchronous serial port driver for ETRAX FS and ARTPEC-3. 3 3 * 4 - * Copyright (c) 2005 Axis Communications AB 5 - * 4 + * Copyright (c) 2005, 2008 Axis Communications AB 6 5 * Author: Mikael Starvik 7 6 * 8 7 */ ··· 15 16 #include <linux/mutex.h> 16 17 #include <linux/interrupt.h> 17 18 #include <linux/poll.h> 18 - #include <linux/init.h> 19 - #include <linux/timer.h> 20 - #include <linux/spinlock.h> 19 + #include <linux/fs.h> 20 + #include <linux/cdev.h> 21 + #include <linux/device.h> 21 22 #include <linux/wait.h> 22 23 23 24 #include <asm/io.h> 24 - #include <dma.h> 25 + #include <mach/dma.h> 25 26 #include <pinmux.h> 26 27 #include <hwregs/reg_rdwr.h> 27 28 #include <hwregs/sser_defs.h> 29 + #include <hwregs/timer_defs.h> 28 30 #include <hwregs/dma_defs.h> 29 31 #include <hwregs/dma.h> 30 32 #include <hwregs/intr_vect_defs.h> ··· 59 59 /* the rest of the data pointed out by Descr1 and set readp to the start */ 60 60 /* of Descr2 */ 61 61 62 - #define SYNC_SERIAL_MAJOR 125 63 - 64 62 /* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ 65 63 /* words can be handled */ 66 - #define IN_BUFFER_SIZE 12288 67 - #define IN_DESCR_SIZE 256 68 - #define NBR_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) 64 + #define IN_DESCR_SIZE SSP_INPUT_CHUNK_SIZE 65 + #define NBR_IN_DESCR (8*6) 66 + #define IN_BUFFER_SIZE (IN_DESCR_SIZE * NBR_IN_DESCR) 69 67 70 - #define OUT_BUFFER_SIZE 1024*8 71 68 #define NBR_OUT_DESCR 8 69 + #define OUT_BUFFER_SIZE (1024 * NBR_OUT_DESCR) 72 70 73 71 #define DEFAULT_FRAME_RATE 0 74 72 #define DEFAULT_WORD_RATE 7 75 73 74 + /* To be removed when we move to pure udev. */ 75 + #define SYNC_SERIAL_MAJOR 125 76 + 76 77 /* NOTE: Enabling some debug will likely cause overrun or underrun, 77 - * especially if manual mode is use. 78 + * especially if manual mode is used. 78 79 */ 79 80 #define DEBUG(x) 80 81 #define DEBUGREAD(x) ··· 86 85 #define DEBUGTRDMA(x) 87 86 #define DEBUGOUTBUF(x) 88 87 89 - typedef struct sync_port 90 - { 91 - reg_scope_instances regi_sser; 92 - reg_scope_instances regi_dmain; 93 - reg_scope_instances regi_dmaout; 88 + enum syncser_irq_setup { 89 + no_irq_setup = 0, 90 + dma_irq_setup = 1, 91 + manual_irq_setup = 2, 92 + }; 93 + 94 + struct sync_port { 95 + unsigned long regi_sser; 96 + unsigned long regi_dmain; 97 + unsigned long regi_dmaout; 98 + 99 + /* Interrupt vectors. */ 100 + unsigned long dma_in_intr_vect; /* Used for DMA in. */ 101 + unsigned long dma_out_intr_vect; /* Used for DMA out. */ 102 + unsigned long syncser_intr_vect; /* Used when no DMA. */ 103 + 104 + /* DMA number for in and out. */ 105 + unsigned int dma_in_nbr; 106 + unsigned int dma_out_nbr; 107 + 108 + /* DMA owner. */ 109 + enum dma_owner req_dma; 94 110 95 111 char started; /* 1 if port has been started */ 96 112 char port_nbr; /* Port 0 or 1 */ ··· 117 99 char use_dma; /* 1 if port uses dma */ 118 100 char tr_running; 119 101 120 - char init_irqs; 102 + enum syncser_irq_setup init_irqs; 121 103 int output; 122 104 int input; 123 105 124 106 /* Next byte to be read by application */ 125 - volatile unsigned char *volatile readp; 107 + unsigned char *readp; 126 108 /* Next byte to be written by etrax */ 127 - volatile unsigned char *volatile writep; 109 + unsigned char *writep; 128 110 129 111 unsigned int in_buffer_size; 112 + unsigned int in_buffer_len; 130 113 unsigned int inbufchunk; 131 - unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); 132 - unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); 133 - unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); 134 - struct dma_descr_data* next_rx_desc; 135 - struct dma_descr_data* prev_rx_desc; 114 + /* Data buffers for in and output. */ 115 + unsigned char out_buffer[OUT_BUFFER_SIZE] __aligned(32); 116 + unsigned char in_buffer[IN_BUFFER_SIZE] __aligned(32); 117 + unsigned char flip[IN_BUFFER_SIZE] __aligned(32); 118 + struct timespec timestamp[NBR_IN_DESCR]; 119 + struct dma_descr_data *next_rx_desc; 120 + struct dma_descr_data *prev_rx_desc; 121 + 122 + struct timeval last_timestamp; 123 + int read_ts_idx; 124 + int write_ts_idx; 136 125 137 126 /* Pointer to the first available descriptor in the ring, 138 127 * unless active_tr_descr == catch_tr_descr and a dma ··· 160 135 /* Number of bytes currently locked for being read by DMA */ 161 136 int out_buf_count; 162 137 163 - dma_descr_data in_descr[NBR_IN_DESCR] __attribute__ ((__aligned__(16))); 164 - dma_descr_context in_context __attribute__ ((__aligned__(32))); 165 - dma_descr_data out_descr[NBR_OUT_DESCR] 166 - __attribute__ ((__aligned__(16))); 167 - dma_descr_context out_context __attribute__ ((__aligned__(32))); 138 + dma_descr_context in_context __aligned(32); 139 + dma_descr_context out_context __aligned(32); 140 + dma_descr_data in_descr[NBR_IN_DESCR] __aligned(16); 141 + dma_descr_data out_descr[NBR_OUT_DESCR] __aligned(16); 142 + 168 143 wait_queue_head_t out_wait_q; 169 144 wait_queue_head_t in_wait_q; 170 145 171 146 spinlock_t lock; 172 - } sync_port; 147 + }; 173 148 174 149 static DEFINE_MUTEX(sync_serial_mutex); 175 150 static int etrax_sync_serial_init(void); 176 151 static void initialize_port(int portnbr); 177 152 static inline int sync_data_avail(struct sync_port *port); 178 153 179 - static int sync_serial_open(struct inode *, struct file*); 180 - static int sync_serial_release(struct inode*, struct file*); 154 + static int sync_serial_open(struct inode *, struct file *); 155 + static int sync_serial_release(struct inode *, struct file *); 181 156 static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); 182 157 183 - static int sync_serial_ioctl(struct file *, 184 - unsigned int cmd, unsigned long arg); 185 - static ssize_t sync_serial_write(struct file * file, const char * buf, 158 + static long sync_serial_ioctl(struct file *file, 159 + unsigned int cmd, unsigned long arg); 160 + static int sync_serial_ioctl_unlocked(struct file *file, 161 + unsigned int cmd, unsigned long arg); 162 + static ssize_t sync_serial_write(struct file *file, const char __user *buf, 186 163 size_t count, loff_t *ppos); 187 - static ssize_t sync_serial_read(struct file *file, char *buf, 164 + static ssize_t sync_serial_read(struct file *file, char __user *buf, 188 165 size_t count, loff_t *ppos); 189 166 190 - #if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 191 - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 192 - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 193 - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)) 167 + #if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 168 + defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 169 + (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 170 + defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 194 171 #define SYNC_SER_DMA 172 + #else 173 + #define SYNC_SER_MANUAL 195 174 #endif 196 175 197 - static void send_word(sync_port* port); 198 - static void start_dma_out(struct sync_port *port, const char *data, int count); 199 - static void start_dma_in(sync_port* port); 200 176 #ifdef SYNC_SER_DMA 177 + static void start_dma_out(struct sync_port *port, const char *data, int count); 178 + static void start_dma_in(struct sync_port *port); 201 179 static irqreturn_t tr_interrupt(int irq, void *dev_id); 202 180 static irqreturn_t rx_interrupt(int irq, void *dev_id); 203 181 #endif 204 - 205 - #if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 206 - !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 207 - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 208 - !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)) 209 - #define SYNC_SER_MANUAL 210 - #endif 211 182 #ifdef SYNC_SER_MANUAL 183 + static void send_word(struct sync_port *port); 212 184 static irqreturn_t manual_interrupt(int irq, void *dev_id); 213 185 #endif 214 186 215 - #ifdef CONFIG_ETRAXFS /* ETRAX FS */ 216 - #define OUT_DMA_NBR 4 217 - #define IN_DMA_NBR 5 218 - #define PINMUX_SSER pinmux_sser0 219 - #define SYNCSER_INST regi_sser0 220 - #define SYNCSER_INTR_VECT SSER0_INTR_VECT 221 - #define OUT_DMA_INST regi_dma4 222 - #define IN_DMA_INST regi_dma5 223 - #define DMA_OUT_INTR_VECT DMA4_INTR_VECT 224 - #define DMA_IN_INTR_VECT DMA5_INTR_VECT 225 - #define REQ_DMA_SYNCSER dma_sser0 226 - #else /* Artpec-3 */ 227 - #define OUT_DMA_NBR 6 228 - #define IN_DMA_NBR 7 229 - #define PINMUX_SSER pinmux_sser 230 - #define SYNCSER_INST regi_sser 231 - #define SYNCSER_INTR_VECT SSER_INTR_VECT 232 - #define OUT_DMA_INST regi_dma6 233 - #define IN_DMA_INST regi_dma7 234 - #define DMA_OUT_INTR_VECT DMA6_INTR_VECT 235 - #define DMA_IN_INTR_VECT DMA7_INTR_VECT 236 - #define REQ_DMA_SYNCSER dma_sser 187 + #define artpec_pinmux_alloc_fixed crisv32_pinmux_alloc_fixed 188 + #define artpec_request_dma crisv32_request_dma 189 + #define artpec_free_dma crisv32_free_dma 190 + 191 + #ifdef CONFIG_ETRAXFS 192 + /* ETRAX FS */ 193 + #define DMA_OUT_NBR0 SYNC_SER0_TX_DMA_NBR 194 + #define DMA_IN_NBR0 SYNC_SER0_RX_DMA_NBR 195 + #define DMA_OUT_NBR1 SYNC_SER1_TX_DMA_NBR 196 + #define DMA_IN_NBR1 SYNC_SER1_RX_DMA_NBR 197 + #define PINMUX_SSER0 pinmux_sser0 198 + #define PINMUX_SSER1 pinmux_sser1 199 + #define SYNCSER_INST0 regi_sser0 200 + #define SYNCSER_INST1 regi_sser1 201 + #define SYNCSER_INTR_VECT0 SSER0_INTR_VECT 202 + #define SYNCSER_INTR_VECT1 SSER1_INTR_VECT 203 + #define OUT_DMA_INST0 regi_dma4 204 + #define IN_DMA_INST0 regi_dma5 205 + #define DMA_OUT_INTR_VECT0 DMA4_INTR_VECT 206 + #define DMA_OUT_INTR_VECT1 DMA7_INTR_VECT 207 + #define DMA_IN_INTR_VECT0 DMA5_INTR_VECT 208 + #define DMA_IN_INTR_VECT1 DMA6_INTR_VECT 209 + #define REQ_DMA_SYNCSER0 dma_sser0 210 + #define REQ_DMA_SYNCSER1 dma_sser1 211 + #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 212 + #define PORT1_DMA 1 213 + #else 214 + #define PORT1_DMA 0 215 + #endif 216 + #elif defined(CONFIG_CRIS_MACH_ARTPEC3) 217 + /* ARTPEC-3 */ 218 + #define DMA_OUT_NBR0 SYNC_SER_TX_DMA_NBR 219 + #define DMA_IN_NBR0 SYNC_SER_RX_DMA_NBR 220 + #define PINMUX_SSER0 pinmux_sser 221 + #define SYNCSER_INST0 regi_sser 222 + #define SYNCSER_INTR_VECT0 SSER_INTR_VECT 223 + #define OUT_DMA_INST0 regi_dma6 224 + #define IN_DMA_INST0 regi_dma7 225 + #define DMA_OUT_INTR_VECT0 DMA6_INTR_VECT 226 + #define DMA_IN_INTR_VECT0 DMA7_INTR_VECT 227 + #define REQ_DMA_SYNCSER0 dma_sser 228 + #define REQ_DMA_SYNCSER1 dma_sser 229 + #endif 230 + 231 + #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 232 + #define PORT0_DMA 1 233 + #else 234 + #define PORT0_DMA 0 237 235 #endif 238 236 239 237 /* The ports */ 240 - static struct sync_port ports[]= 241 - { 238 + static struct sync_port ports[] = { 242 239 { 243 - .regi_sser = SYNCSER_INST, 244 - .regi_dmaout = OUT_DMA_INST, 245 - .regi_dmain = IN_DMA_INST, 246 - #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 247 - .use_dma = 1, 248 - #else 249 - .use_dma = 0, 250 - #endif 251 - } 240 + .regi_sser = SYNCSER_INST0, 241 + .regi_dmaout = OUT_DMA_INST0, 242 + .regi_dmain = IN_DMA_INST0, 243 + .use_dma = PORT0_DMA, 244 + .dma_in_intr_vect = DMA_IN_INTR_VECT0, 245 + .dma_out_intr_vect = DMA_OUT_INTR_VECT0, 246 + .dma_in_nbr = DMA_IN_NBR0, 247 + .dma_out_nbr = DMA_OUT_NBR0, 248 + .req_dma = REQ_DMA_SYNCSER0, 249 + .syncser_intr_vect = SYNCSER_INTR_VECT0, 250 + }, 252 251 #ifdef CONFIG_ETRAXFS 253 - , 254 - 255 252 { 256 - .regi_sser = regi_sser1, 257 - .regi_dmaout = regi_dma6, 258 - .regi_dmain = regi_dma7, 259 - #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 260 - .use_dma = 1, 261 - #else 262 - .use_dma = 0, 263 - #endif 264 - } 253 + .regi_sser = SYNCSER_INST1, 254 + .regi_dmaout = regi_dma6, 255 + .regi_dmain = regi_dma7, 256 + .use_dma = PORT1_DMA, 257 + .dma_in_intr_vect = DMA_IN_INTR_VECT1, 258 + .dma_out_intr_vect = DMA_OUT_INTR_VECT1, 259 + .dma_in_nbr = DMA_IN_NBR1, 260 + .dma_out_nbr = DMA_OUT_NBR1, 261 + .req_dma = REQ_DMA_SYNCSER1, 262 + .syncser_intr_vect = SYNCSER_INTR_VECT1, 263 + }, 265 264 #endif 266 265 }; 267 266 268 267 #define NBR_PORTS ARRAY_SIZE(ports) 269 268 270 - static const struct file_operations sync_serial_fops = { 269 + static const struct file_operations syncser_fops = { 271 270 .owner = THIS_MODULE, 272 271 .write = sync_serial_write, 273 272 .read = sync_serial_read, ··· 302 253 .llseek = noop_llseek, 303 254 }; 304 255 305 - static int __init etrax_sync_serial_init(void) 256 + static dev_t syncser_first; 257 + static int minor_count = NBR_PORTS; 258 + #define SYNCSER_NAME "syncser" 259 + static struct cdev *syncser_cdev; 260 + static struct class *syncser_class; 261 + 262 + static void sync_serial_start_port(struct sync_port *port) 306 263 { 307 - ports[0].enabled = 0; 308 - #ifdef CONFIG_ETRAXFS 309 - ports[1].enabled = 0; 310 - #endif 311 - if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial", 312 - &sync_serial_fops) < 0) { 313 - printk(KERN_WARNING 314 - "Unable to get major for synchronous serial port\n"); 315 - return -EBUSY; 316 - } 317 - 318 - /* Initialize Ports */ 319 - #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 320 - if (crisv32_pinmux_alloc_fixed(PINMUX_SSER)) { 321 - printk(KERN_WARNING 322 - "Unable to alloc pins for synchronous serial port 0\n"); 323 - return -EIO; 324 - } 325 - ports[0].enabled = 1; 326 - initialize_port(0); 327 - #endif 328 - 329 - #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 330 - if (crisv32_pinmux_alloc_fixed(pinmux_sser1)) { 331 - printk(KERN_WARNING 332 - "Unable to alloc pins for synchronous serial port 0\n"); 333 - return -EIO; 334 - } 335 - ports[1].enabled = 1; 336 - initialize_port(1); 337 - #endif 338 - 339 - #ifdef CONFIG_ETRAXFS 340 - printk(KERN_INFO "ETRAX FS synchronous serial port driver\n"); 341 - #else 342 - printk(KERN_INFO "Artpec-3 synchronous serial port driver\n"); 343 - #endif 344 - return 0; 264 + reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); 265 + reg_sser_rw_tr_cfg tr_cfg = 266 + REG_RD(sser, port->regi_sser, rw_tr_cfg); 267 + reg_sser_rw_rec_cfg rec_cfg = 268 + REG_RD(sser, port->regi_sser, rw_rec_cfg); 269 + cfg.en = regk_sser_yes; 270 + tr_cfg.tr_en = regk_sser_yes; 271 + rec_cfg.rec_en = regk_sser_yes; 272 + REG_WR(sser, port->regi_sser, rw_cfg, cfg); 273 + REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); 274 + REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); 275 + port->started = 1; 345 276 } 346 277 347 278 static void __init initialize_port(int portnbr) 348 279 { 349 - int __attribute__((unused)) i; 350 280 struct sync_port *port = &ports[portnbr]; 351 - reg_sser_rw_cfg cfg = {0}; 352 - reg_sser_rw_frm_cfg frm_cfg = {0}; 353 - reg_sser_rw_tr_cfg tr_cfg = {0}; 354 - reg_sser_rw_rec_cfg rec_cfg = {0}; 281 + reg_sser_rw_cfg cfg = { 0 }; 282 + reg_sser_rw_frm_cfg frm_cfg = { 0 }; 283 + reg_sser_rw_tr_cfg tr_cfg = { 0 }; 284 + reg_sser_rw_rec_cfg rec_cfg = { 0 }; 355 285 356 - DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr)); 286 + DEBUG(pr_info("Init sync serial port %d\n", portnbr)); 357 287 358 288 port->port_nbr = portnbr; 359 - port->init_irqs = 1; 289 + port->init_irqs = no_irq_setup; 360 290 361 291 port->out_rd_ptr = port->out_buffer; 362 292 port->out_buf_count = 0; ··· 346 318 port->readp = port->flip; 347 319 port->writep = port->flip; 348 320 port->in_buffer_size = IN_BUFFER_SIZE; 321 + port->in_buffer_len = 0; 349 322 port->inbufchunk = IN_DESCR_SIZE; 350 - port->next_rx_desc = &port->in_descr[0]; 351 - port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR-1]; 352 - port->prev_rx_desc->eol = 1; 323 + 324 + port->read_ts_idx = 0; 325 + port->write_ts_idx = 0; 353 326 354 327 init_waitqueue_head(&port->out_wait_q); 355 328 init_waitqueue_head(&port->in_wait_q); ··· 397 368 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); 398 369 399 370 #ifdef SYNC_SER_DMA 400 - /* Setup the descriptor ring for dma out/transmit. */ 401 - for (i = 0; i < NBR_OUT_DESCR; i++) { 402 - port->out_descr[i].wait = 0; 403 - port->out_descr[i].intr = 1; 404 - port->out_descr[i].eol = 0; 405 - port->out_descr[i].out_eop = 0; 406 - port->out_descr[i].next = 407 - (dma_descr_data *)virt_to_phys(&port->out_descr[i+1]); 371 + { 372 + int i; 373 + /* Setup the descriptor ring for dma out/transmit. */ 374 + for (i = 0; i < NBR_OUT_DESCR; i++) { 375 + dma_descr_data *descr = &port->out_descr[i]; 376 + descr->wait = 0; 377 + descr->intr = 1; 378 + descr->eol = 0; 379 + descr->out_eop = 0; 380 + descr->next = 381 + (dma_descr_data *)virt_to_phys(&descr[i+1]); 382 + } 408 383 } 409 384 410 385 /* Create a ring from the list. */ ··· 424 391 425 392 static inline int sync_data_avail(struct sync_port *port) 426 393 { 427 - int avail; 428 - unsigned char *start; 429 - unsigned char *end; 430 - 431 - start = (unsigned char*)port->readp; /* cast away volatile */ 432 - end = (unsigned char*)port->writep; /* cast away volatile */ 433 - /* 0123456789 0123456789 434 - * ----- - ----- 435 - * ^rp ^wp ^wp ^rp 436 - */ 437 - 438 - if (end >= start) 439 - avail = end - start; 440 - else 441 - avail = port->in_buffer_size - (start - end); 442 - return avail; 443 - } 444 - 445 - static inline int sync_data_avail_to_end(struct sync_port *port) 446 - { 447 - int avail; 448 - unsigned char *start; 449 - unsigned char *end; 450 - 451 - start = (unsigned char*)port->readp; /* cast away volatile */ 452 - end = (unsigned char*)port->writep; /* cast away volatile */ 453 - /* 0123456789 0123456789 454 - * ----- ----- 455 - * ^rp ^wp ^wp ^rp 456 - */ 457 - 458 - if (end >= start) 459 - avail = end - start; 460 - else 461 - avail = port->flip + port->in_buffer_size - start; 462 - return avail; 394 + return port->in_buffer_len; 463 395 } 464 396 465 397 static int sync_serial_open(struct inode *inode, struct file *file) 466 398 { 399 + int ret = 0; 467 400 int dev = iminor(inode); 468 - int ret = -EBUSY; 469 - sync_port *port; 470 - reg_dma_rw_cfg cfg = {.en = regk_dma_yes}; 471 - reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes}; 401 + struct sync_port *port; 402 + #ifdef SYNC_SER_DMA 403 + reg_dma_rw_cfg cfg = { .en = regk_dma_yes }; 404 + reg_dma_rw_intr_mask intr_mask = { .data = regk_dma_yes }; 405 + #endif 472 406 473 - mutex_lock(&sync_serial_mutex); 474 - DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); 407 + DEBUG(pr_debug("Open sync serial port %d\n", dev)); 475 408 476 - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) 477 - { 478 - DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 479 - ret = -ENODEV; 480 - goto out; 409 + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { 410 + DEBUG(pr_info("Invalid minor %d\n", dev)); 411 + return -ENODEV; 481 412 } 482 413 port = &ports[dev]; 483 414 /* Allow open this device twice (assuming one reader and one writer) */ 484 - if (port->busy == 2) 485 - { 486 - DEBUG(printk(KERN_DEBUG "Device is busy.. \n")); 487 - goto out; 415 + if (port->busy == 2) { 416 + DEBUG(pr_info("syncser%d is busy\n", dev)); 417 + return -EBUSY; 488 418 } 489 419 420 + mutex_lock(&sync_serial_mutex); 490 421 491 - if (port->init_irqs) { 492 - if (port->use_dma) { 493 - if (port == &ports[0]) { 494 - #ifdef SYNC_SER_DMA 495 - if (request_irq(DMA_OUT_INTR_VECT, 496 - tr_interrupt, 497 - 0, 498 - "synchronous serial 0 dma tr", 499 - &ports[0])) { 500 - printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ"); 501 - goto out; 502 - } else if (request_irq(DMA_IN_INTR_VECT, 503 - rx_interrupt, 504 - 0, 505 - "synchronous serial 1 dma rx", 506 - &ports[0])) { 507 - free_irq(DMA_OUT_INTR_VECT, &port[0]); 508 - printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ"); 509 - goto out; 510 - } else if (crisv32_request_dma(OUT_DMA_NBR, 511 - "synchronous serial 0 dma tr", 512 - DMA_VERBOSE_ON_ERROR, 513 - 0, 514 - REQ_DMA_SYNCSER)) { 515 - free_irq(DMA_OUT_INTR_VECT, &port[0]); 516 - free_irq(DMA_IN_INTR_VECT, &port[0]); 517 - printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel"); 518 - goto out; 519 - } else if (crisv32_request_dma(IN_DMA_NBR, 520 - "synchronous serial 0 dma rec", 521 - DMA_VERBOSE_ON_ERROR, 522 - 0, 523 - REQ_DMA_SYNCSER)) { 524 - crisv32_free_dma(OUT_DMA_NBR); 525 - free_irq(DMA_OUT_INTR_VECT, &port[0]); 526 - free_irq(DMA_IN_INTR_VECT, &port[0]); 527 - printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel"); 528 - goto out; 529 - } 530 - #endif 531 - } 532 - #ifdef CONFIG_ETRAXFS 533 - else if (port == &ports[1]) { 534 - #ifdef SYNC_SER_DMA 535 - if (request_irq(DMA6_INTR_VECT, 536 - tr_interrupt, 537 - 0, 538 - "synchronous serial 1 dma tr", 539 - &ports[1])) { 540 - printk(KERN_CRIT "Can't allocate sync serial port 1 IRQ"); 541 - goto out; 542 - } else if (request_irq(DMA7_INTR_VECT, 543 - rx_interrupt, 544 - 0, 545 - "synchronous serial 1 dma rx", 546 - &ports[1])) { 547 - free_irq(DMA6_INTR_VECT, &ports[1]); 548 - printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ"); 549 - goto out; 550 - } else if (crisv32_request_dma( 551 - SYNC_SER1_TX_DMA_NBR, 552 - "synchronous serial 1 dma tr", 553 - DMA_VERBOSE_ON_ERROR, 554 - 0, 555 - dma_sser1)) { 556 - free_irq(DMA6_INTR_VECT, &ports[1]); 557 - free_irq(DMA7_INTR_VECT, &ports[1]); 558 - printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel"); 559 - goto out; 560 - } else if (crisv32_request_dma( 561 - SYNC_SER1_RX_DMA_NBR, 562 - "synchronous serial 3 dma rec", 563 - DMA_VERBOSE_ON_ERROR, 564 - 0, 565 - dma_sser1)) { 566 - crisv32_free_dma(SYNC_SER1_TX_DMA_NBR); 567 - free_irq(DMA6_INTR_VECT, &ports[1]); 568 - free_irq(DMA7_INTR_VECT, &ports[1]); 569 - printk(KERN_CRIT "Can't allocate sync serial port 3 RX DMA channel"); 570 - goto out; 571 - } 572 - #endif 573 - } 574 - #endif 575 - /* Enable DMAs */ 576 - REG_WR(dma, port->regi_dmain, rw_cfg, cfg); 577 - REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); 578 - /* Enable DMA IRQs */ 579 - REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); 580 - REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); 581 - /* Set up wordsize = 1 for DMAs. */ 582 - DMA_WR_CMD (port->regi_dmain, regk_dma_set_w_size1); 583 - DMA_WR_CMD (port->regi_dmaout, regk_dma_set_w_size1); 422 + /* Clear any stale date left in the flip buffer */ 423 + port->readp = port->writep = port->flip; 424 + port->in_buffer_len = 0; 425 + port->read_ts_idx = 0; 426 + port->write_ts_idx = 0; 584 427 585 - start_dma_in(port); 586 - port->init_irqs = 0; 587 - } else { /* !port->use_dma */ 588 - #ifdef SYNC_SER_MANUAL 589 - if (port == &ports[0]) { 590 - if (request_irq(SYNCSER_INTR_VECT, 591 - manual_interrupt, 592 - 0, 593 - "synchronous serial manual irq", 594 - &ports[0])) { 595 - printk("Can't allocate sync serial manual irq"); 596 - goto out; 597 - } 598 - } 599 - #ifdef CONFIG_ETRAXFS 600 - else if (port == &ports[1]) { 601 - if (request_irq(SSER1_INTR_VECT, 602 - manual_interrupt, 603 - 0, 604 - "synchronous serial manual irq", 605 - &ports[1])) { 606 - printk(KERN_CRIT "Can't allocate sync serial manual irq"); 607 - goto out; 608 - } 609 - } 610 - #endif 611 - port->init_irqs = 0; 612 - #else 613 - panic("sync_serial: Manual mode not supported.\n"); 614 - #endif /* SYNC_SER_MANUAL */ 428 + if (port->init_irqs != no_irq_setup) { 429 + /* Init only on first call. */ 430 + port->busy++; 431 + mutex_unlock(&sync_serial_mutex); 432 + return 0; 433 + } 434 + if (port->use_dma) { 435 + #ifdef SYNC_SER_DMA 436 + const char *tmp; 437 + DEBUG(pr_info("Using DMA for syncser%d\n", dev)); 438 + 439 + tmp = dev == 0 ? "syncser0 tx" : "syncser1 tx"; 440 + if (request_irq(port->dma_out_intr_vect, tr_interrupt, 0, 441 + tmp, port)) { 442 + pr_err("Can't alloc syncser%d TX IRQ", dev); 443 + ret = -EBUSY; 444 + goto unlock_and_exit; 615 445 } 446 + if (artpec_request_dma(port->dma_out_nbr, tmp, 447 + DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) { 448 + free_irq(port->dma_out_intr_vect, port); 449 + pr_err("Can't alloc syncser%d TX DMA", dev); 450 + ret = -EBUSY; 451 + goto unlock_and_exit; 452 + } 453 + tmp = dev == 0 ? "syncser0 rx" : "syncser1 rx"; 454 + if (request_irq(port->dma_in_intr_vect, rx_interrupt, 0, 455 + tmp, port)) { 456 + artpec_free_dma(port->dma_out_nbr); 457 + free_irq(port->dma_out_intr_vect, port); 458 + pr_err("Can't alloc syncser%d RX IRQ", dev); 459 + ret = -EBUSY; 460 + goto unlock_and_exit; 461 + } 462 + if (artpec_request_dma(port->dma_in_nbr, tmp, 463 + DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) { 464 + artpec_free_dma(port->dma_out_nbr); 465 + free_irq(port->dma_out_intr_vect, port); 466 + free_irq(port->dma_in_intr_vect, port); 467 + pr_err("Can't alloc syncser%d RX DMA", dev); 468 + ret = -EBUSY; 469 + goto unlock_and_exit; 470 + } 471 + /* Enable DMAs */ 472 + REG_WR(dma, port->regi_dmain, rw_cfg, cfg); 473 + REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); 474 + /* Enable DMA IRQs */ 475 + REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); 476 + REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); 477 + /* Set up wordsize = 1 for DMAs. */ 478 + DMA_WR_CMD(port->regi_dmain, regk_dma_set_w_size1); 479 + DMA_WR_CMD(port->regi_dmaout, regk_dma_set_w_size1); 616 480 617 - } /* port->init_irqs */ 618 - 481 + start_dma_in(port); 482 + port->init_irqs = dma_irq_setup; 483 + #endif 484 + } else { /* !port->use_dma */ 485 + #ifdef SYNC_SER_MANUAL 486 + const char *tmp = dev == 0 ? "syncser0 manual irq" : 487 + "syncser1 manual irq"; 488 + if (request_irq(port->syncser_intr_vect, manual_interrupt, 489 + 0, tmp, port)) { 490 + pr_err("Can't alloc syncser%d manual irq", 491 + dev); 492 + ret = -EBUSY; 493 + goto unlock_and_exit; 494 + } 495 + port->init_irqs = manual_irq_setup; 496 + #else 497 + panic("sync_serial: Manual mode not supported\n"); 498 + #endif /* SYNC_SER_MANUAL */ 499 + } 619 500 port->busy++; 620 501 ret = 0; 621 - out: 502 + 503 + unlock_and_exit: 622 504 mutex_unlock(&sync_serial_mutex); 623 505 return ret; 624 506 } ··· 541 593 static int sync_serial_release(struct inode *inode, struct file *file) 542 594 { 543 595 int dev = iminor(inode); 544 - sync_port *port; 596 + struct sync_port *port; 545 597 546 - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) 547 - { 548 - DEBUG(printk("Invalid minor %d\n", dev)); 598 + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { 599 + DEBUG(pr_info("Invalid minor %d\n", dev)); 549 600 return -ENODEV; 550 601 } 551 602 port = &ports[dev]; 552 603 if (port->busy) 553 604 port->busy--; 554 605 if (!port->busy) 555 - /* XXX */ ; 606 + /* XXX */; 556 607 return 0; 557 608 } 558 609 ··· 559 612 { 560 613 int dev = iminor(file_inode(file)); 561 614 unsigned int mask = 0; 562 - sync_port *port; 563 - DEBUGPOLL( static unsigned int prev_mask = 0; ); 615 + struct sync_port *port; 616 + DEBUGPOLL( 617 + static unsigned int prev_mask; 618 + ); 564 619 565 620 port = &ports[dev]; 566 621 567 - if (!port->started) { 568 - reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); 569 - reg_sser_rw_rec_cfg rec_cfg = 570 - REG_RD(sser, port->regi_sser, rw_rec_cfg); 571 - cfg.en = regk_sser_yes; 572 - rec_cfg.rec_en = port->input; 573 - REG_WR(sser, port->regi_sser, rw_cfg, cfg); 574 - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); 575 - port->started = 1; 576 - } 622 + if (!port->started) 623 + sync_serial_start_port(port); 577 624 578 625 poll_wait(file, &port->out_wait_q, wait); 579 626 poll_wait(file, &port->in_wait_q, wait); ··· 586 645 if (port->input && sync_data_avail(port) >= port->inbufchunk) 587 646 mask |= POLLIN | POLLRDNORM; 588 647 589 - DEBUGPOLL(if (mask != prev_mask) 590 - printk("sync_serial_poll: mask 0x%08X %s %s\n", mask, 591 - mask&POLLOUT?"POLLOUT":"", mask&POLLIN?"POLLIN":""); 592 - prev_mask = mask; 593 - ); 648 + DEBUGPOLL( 649 + if (mask != prev_mask) 650 + pr_info("sync_serial_poll: mask 0x%08X %s %s\n", 651 + mask, 652 + mask & POLLOUT ? "POLLOUT" : "", 653 + mask & POLLIN ? "POLLIN" : ""); 654 + prev_mask = mask; 655 + ); 594 656 return mask; 595 657 } 596 658 597 - static int sync_serial_ioctl(struct file *file, 598 - unsigned int cmd, unsigned long arg) 659 + static ssize_t __sync_serial_read(struct file *file, 660 + char __user *buf, 661 + size_t count, 662 + loff_t *ppos, 663 + struct timespec *ts) 664 + { 665 + unsigned long flags; 666 + int dev = MINOR(file->f_dentry->d_inode->i_rdev); 667 + int avail; 668 + struct sync_port *port; 669 + unsigned char *start; 670 + unsigned char *end; 671 + 672 + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { 673 + DEBUG(pr_info("Invalid minor %d\n", dev)); 674 + return -ENODEV; 675 + } 676 + port = &ports[dev]; 677 + 678 + if (!port->started) 679 + sync_serial_start_port(port); 680 + 681 + /* Calculate number of available bytes */ 682 + /* Save pointers to avoid that they are modified by interrupt */ 683 + spin_lock_irqsave(&port->lock, flags); 684 + start = port->readp; 685 + end = port->writep; 686 + spin_unlock_irqrestore(&port->lock, flags); 687 + 688 + while ((start == end) && !port->in_buffer_len) { 689 + if (file->f_flags & O_NONBLOCK) 690 + return -EAGAIN; 691 + 692 + wait_event_interruptible(port->in_wait_q, 693 + !(start == end && !port->full)); 694 + 695 + if (signal_pending(current)) 696 + return -EINTR; 697 + 698 + spin_lock_irqsave(&port->lock, flags); 699 + start = port->readp; 700 + end = port->writep; 701 + spin_unlock_irqrestore(&port->lock, flags); 702 + } 703 + 704 + DEBUGREAD(pr_info("R%d c %d ri %u wi %u /%u\n", 705 + dev, count, 706 + start - port->flip, end - port->flip, 707 + port->in_buffer_size)); 708 + 709 + /* Lazy read, never return wrapped data. */ 710 + if (end > start) 711 + avail = end - start; 712 + else 713 + avail = port->flip + port->in_buffer_size - start; 714 + 715 + count = count > avail ? avail : count; 716 + if (copy_to_user(buf, start, count)) 717 + return -EFAULT; 718 + 719 + /* If timestamp requested, find timestamp of first returned byte 720 + * and copy it. 721 + * N.B: Applications that request timstamps MUST read data in 722 + * chunks that are multiples of IN_DESCR_SIZE. 723 + * Otherwise the timestamps will not be aligned to the data read. 724 + */ 725 + if (ts != NULL) { 726 + int idx = port->read_ts_idx; 727 + memcpy(ts, &port->timestamp[idx], sizeof(struct timespec)); 728 + port->read_ts_idx += count / IN_DESCR_SIZE; 729 + if (port->read_ts_idx >= NBR_IN_DESCR) 730 + port->read_ts_idx = 0; 731 + } 732 + 733 + spin_lock_irqsave(&port->lock, flags); 734 + port->readp += count; 735 + /* Check for wrap */ 736 + if (port->readp >= port->flip + port->in_buffer_size) 737 + port->readp = port->flip; 738 + port->in_buffer_len -= count; 739 + port->full = 0; 740 + spin_unlock_irqrestore(&port->lock, flags); 741 + 742 + DEBUGREAD(pr_info("r %d\n", count)); 743 + 744 + return count; 745 + } 746 + 747 + static ssize_t sync_serial_input(struct file *file, unsigned long arg) 748 + { 749 + struct ssp_request req; 750 + int count; 751 + int ret; 752 + 753 + /* Copy the request structure from user-mode. */ 754 + ret = copy_from_user(&req, (struct ssp_request __user *)arg, 755 + sizeof(struct ssp_request)); 756 + 757 + if (ret) { 758 + DEBUG(pr_info("sync_serial_input copy from user failed\n")); 759 + return -EFAULT; 760 + } 761 + 762 + /* To get the timestamps aligned, make sure that 'len' 763 + * is a multiple of IN_DESCR_SIZE. 764 + */ 765 + if ((req.len % IN_DESCR_SIZE) != 0) { 766 + DEBUG(pr_info("sync_serial: req.len %x, IN_DESCR_SIZE %x\n", 767 + req.len, IN_DESCR_SIZE)); 768 + return -EFAULT; 769 + } 770 + 771 + /* Do the actual read. */ 772 + /* Note that req.buf is actually a pointer to user space. */ 773 + count = __sync_serial_read(file, req.buf, req.len, 774 + NULL, &req.ts); 775 + 776 + if (count < 0) { 777 + DEBUG(pr_info("sync_serial_input read failed\n")); 778 + return count; 779 + } 780 + 781 + /* Copy the request back to user-mode. */ 782 + ret = copy_to_user((struct ssp_request __user *)arg, &req, 783 + sizeof(struct ssp_request)); 784 + 785 + if (ret) { 786 + DEBUG(pr_info("syncser input copy2user failed\n")); 787 + return -EFAULT; 788 + } 789 + 790 + /* Return the number of bytes read. */ 791 + return count; 792 + } 793 + 794 + 795 + static int sync_serial_ioctl_unlocked(struct file *file, 796 + unsigned int cmd, unsigned long arg) 599 797 { 600 798 int return_val = 0; 601 799 int dma_w_size = regk_dma_set_w_size1; 602 800 int dev = iminor(file_inode(file)); 603 - sync_port *port; 801 + struct sync_port *port; 604 802 reg_sser_rw_tr_cfg tr_cfg; 605 803 reg_sser_rw_rec_cfg rec_cfg; 606 804 reg_sser_rw_frm_cfg frm_cfg; 607 805 reg_sser_rw_cfg gen_cfg; 608 806 reg_sser_rw_intr_mask intr_mask; 609 807 610 - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) 611 - { 612 - DEBUG(printk("Invalid minor %d\n", dev)); 808 + if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { 809 + DEBUG(pr_info("Invalid minor %d\n", dev)); 613 810 return -1; 614 811 } 615 - port = &ports[dev]; 812 + 813 + if (cmd == SSP_INPUT) 814 + return sync_serial_input(file, arg); 815 + 816 + port = &ports[dev]; 616 817 spin_lock_irq(&port->lock); 617 818 618 819 tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); ··· 763 680 gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg); 764 681 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); 765 682 766 - switch(cmd) 767 - { 683 + switch (cmd) { 768 684 case SSP_SPEED: 769 - if (GET_SPEED(arg) == CODEC) 770 - { 685 + if (GET_SPEED(arg) == CODEC) { 771 686 unsigned int freq; 772 687 773 688 gen_cfg.base_freq = regk_sser_f32; ··· 782 701 case FREQ_256kHz: 783 702 gen_cfg.clk_div = 125 * 784 703 (1 << (freq - FREQ_256kHz)) - 1; 785 - break; 704 + break; 786 705 case FREQ_512kHz: 787 706 gen_cfg.clk_div = 62; 788 - break; 707 + break; 789 708 case FREQ_1MHz: 790 709 case FREQ_2MHz: 791 710 case FREQ_4MHz: 792 711 gen_cfg.clk_div = 8 * (1 << freq) - 1; 793 - break; 712 + break; 713 + } 714 + } else if (GET_SPEED(arg) == CODEC_f32768) { 715 + gen_cfg.base_freq = regk_sser_f32_768; 716 + switch (GET_FREQ(arg)) { 717 + case FREQ_4096kHz: 718 + gen_cfg.clk_div = 7; 719 + break; 720 + default: 721 + spin_unlock_irq(&port->lock); 722 + return -EINVAL; 794 723 } 795 724 } else { 796 725 gen_cfg.base_freq = regk_sser_f29_493; ··· 858 767 859 768 break; 860 769 case SSP_MODE: 861 - switch(arg) 862 - { 863 - case MASTER_OUTPUT: 864 - port->output = 1; 865 - port->input = 0; 866 - frm_cfg.out_on = regk_sser_tr; 867 - frm_cfg.frame_pin_dir = regk_sser_out; 868 - gen_cfg.clk_dir = regk_sser_out; 869 - break; 870 - case SLAVE_OUTPUT: 871 - port->output = 1; 872 - port->input = 0; 873 - frm_cfg.frame_pin_dir = regk_sser_in; 874 - gen_cfg.clk_dir = regk_sser_in; 875 - break; 876 - case MASTER_INPUT: 877 - port->output = 0; 878 - port->input = 1; 879 - frm_cfg.frame_pin_dir = regk_sser_out; 880 - frm_cfg.out_on = regk_sser_intern_tb; 881 - gen_cfg.clk_dir = regk_sser_out; 882 - break; 883 - case SLAVE_INPUT: 884 - port->output = 0; 885 - port->input = 1; 886 - frm_cfg.frame_pin_dir = regk_sser_in; 887 - gen_cfg.clk_dir = regk_sser_in; 888 - break; 889 - case MASTER_BIDIR: 890 - port->output = 1; 891 - port->input = 1; 892 - frm_cfg.frame_pin_dir = regk_sser_out; 893 - frm_cfg.out_on = regk_sser_intern_tb; 894 - gen_cfg.clk_dir = regk_sser_out; 895 - break; 896 - case SLAVE_BIDIR: 897 - port->output = 1; 898 - port->input = 1; 899 - frm_cfg.frame_pin_dir = regk_sser_in; 900 - gen_cfg.clk_dir = regk_sser_in; 901 - break; 902 - default: 903 - spin_unlock_irq(&port->lock); 904 - return -EINVAL; 770 + switch (arg) { 771 + case MASTER_OUTPUT: 772 + port->output = 1; 773 + port->input = 0; 774 + frm_cfg.out_on = regk_sser_tr; 775 + frm_cfg.frame_pin_dir = regk_sser_out; 776 + gen_cfg.clk_dir = regk_sser_out; 777 + break; 778 + case SLAVE_OUTPUT: 779 + port->output = 1; 780 + port->input = 0; 781 + frm_cfg.frame_pin_dir = regk_sser_in; 782 + gen_cfg.clk_dir = regk_sser_in; 783 + break; 784 + case MASTER_INPUT: 785 + port->output = 0; 786 + port->input = 1; 787 + frm_cfg.frame_pin_dir = regk_sser_out; 788 + frm_cfg.out_on = regk_sser_intern_tb; 789 + gen_cfg.clk_dir = regk_sser_out; 790 + break; 791 + case SLAVE_INPUT: 792 + port->output = 0; 793 + port->input = 1; 794 + frm_cfg.frame_pin_dir = regk_sser_in; 795 + gen_cfg.clk_dir = regk_sser_in; 796 + break; 797 + case MASTER_BIDIR: 798 + port->output = 1; 799 + port->input = 1; 800 + frm_cfg.frame_pin_dir = regk_sser_out; 801 + frm_cfg.out_on = regk_sser_intern_tb; 802 + gen_cfg.clk_dir = regk_sser_out; 803 + break; 804 + case SLAVE_BIDIR: 805 + port->output = 1; 806 + port->input = 1; 807 + frm_cfg.frame_pin_dir = regk_sser_in; 808 + gen_cfg.clk_dir = regk_sser_in; 809 + break; 810 + default: 811 + spin_unlock_irq(&port->lock); 812 + return -EINVAL; 905 813 } 906 - if (!port->use_dma || (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)) 814 + if (!port->use_dma || arg == MASTER_OUTPUT || 815 + arg == SLAVE_OUTPUT) 907 816 intr_mask.rdav = regk_sser_yes; 908 817 break; 909 818 case SSP_FRAME_SYNC: 910 819 if (arg & NORMAL_SYNC) { 911 820 frm_cfg.rec_delay = 1; 912 821 frm_cfg.tr_delay = 1; 913 - } 914 - else if (arg & EARLY_SYNC) 822 + } else if (arg & EARLY_SYNC) 915 823 frm_cfg.rec_delay = frm_cfg.tr_delay = 0; 916 - else if (arg & SECOND_WORD_SYNC) { 824 + else if (arg & LATE_SYNC) { 825 + frm_cfg.tr_delay = 2; 826 + frm_cfg.rec_delay = 2; 827 + } else if (arg & SECOND_WORD_SYNC) { 917 828 frm_cfg.rec_delay = 7; 918 829 frm_cfg.tr_delay = 1; 919 830 } ··· 1007 914 frm_cfg.type = regk_sser_level; 1008 915 frm_cfg.tr_delay = 1; 1009 916 frm_cfg.level = regk_sser_neg_lo; 1010 - if (arg & SPI_SLAVE) 1011 - { 917 + if (arg & SPI_SLAVE) { 1012 918 rec_cfg.clk_pol = regk_sser_neg; 1013 919 gen_cfg.clk_dir = regk_sser_in; 1014 920 port->input = 1; 1015 921 port->output = 0; 1016 - } 1017 - else 1018 - { 922 + } else { 1019 923 gen_cfg.out_clk_pol = regk_sser_pos; 1020 924 port->input = 0; 1021 925 port->output = 1; ··· 1055 965 } 1056 966 1057 967 static long sync_serial_ioctl(struct file *file, 1058 - unsigned int cmd, unsigned long arg) 968 + unsigned int cmd, unsigned long arg) 1059 969 { 1060 - long ret; 970 + long ret; 1061 971 1062 - mutex_lock(&sync_serial_mutex); 1063 - ret = sync_serial_ioctl_unlocked(file, cmd, arg); 1064 - mutex_unlock(&sync_serial_mutex); 972 + mutex_lock(&sync_serial_mutex); 973 + ret = sync_serial_ioctl_unlocked(file, cmd, arg); 974 + mutex_unlock(&sync_serial_mutex); 1065 975 1066 - return ret; 976 + return ret; 1067 977 } 1068 978 1069 979 /* NOTE: sync_serial_write does not support concurrency */ 1070 - static ssize_t sync_serial_write(struct file *file, const char *buf, 980 + static ssize_t sync_serial_write(struct file *file, const char __user *buf, 1071 981 size_t count, loff_t *ppos) 1072 982 { 1073 983 int dev = iminor(file_inode(file)); ··· 1083 993 unsigned char *buf_stop_ptr; /* Last byte + 1 */ 1084 994 1085 995 if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { 1086 - DEBUG(printk("Invalid minor %d\n", dev)); 996 + DEBUG(pr_info("Invalid minor %d\n", dev)); 1087 997 return -ENODEV; 1088 998 } 1089 999 port = &ports[dev]; ··· 1096 1006 * |_________|___________________|________________________| 1097 1007 * ^ rd_ptr ^ wr_ptr 1098 1008 */ 1099 - DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu a: %p c: %p\n", 1100 - port->port_nbr, count, port->active_tr_descr, 1101 - port->catch_tr_descr)); 1009 + DEBUGWRITE(pr_info("W d%d c %u a: %p c: %p\n", 1010 + port->port_nbr, count, port->active_tr_descr, 1011 + port->catch_tr_descr)); 1102 1012 1103 1013 /* Read variables that may be updated by interrupts */ 1104 1014 spin_lock_irqsave(&port->lock, flags); ··· 1110 1020 if (port->tr_running && 1111 1021 ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) || 1112 1022 out_buf_count >= OUT_BUFFER_SIZE)) { 1113 - DEBUGWRITE(printk(KERN_DEBUG "sser%d full\n", dev)); 1023 + DEBUGWRITE(pr_info("sser%d full\n", dev)); 1114 1024 return -EAGAIN; 1115 1025 } 1116 1026 ··· 1133 1043 if (copy_from_user(wr_ptr, buf, trunc_count)) 1134 1044 return -EFAULT; 1135 1045 1136 - DEBUGOUTBUF(printk(KERN_DEBUG "%-4d + %-4d = %-4d %p %p %p\n", 1137 - out_buf_count, trunc_count, 1138 - port->out_buf_count, port->out_buffer, 1139 - wr_ptr, buf_stop_ptr)); 1046 + DEBUGOUTBUF(pr_info("%-4d + %-4d = %-4d %p %p %p\n", 1047 + out_buf_count, trunc_count, 1048 + port->out_buf_count, port->out_buffer, 1049 + wr_ptr, buf_stop_ptr)); 1140 1050 1141 1051 /* Make sure transmitter/receiver is running */ 1142 1052 if (!port->started) { 1143 1053 reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); 1144 - reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); 1054 + reg_sser_rw_rec_cfg rec_cfg = 1055 + REG_RD(sser, port->regi_sser, rw_rec_cfg); 1145 1056 cfg.en = regk_sser_yes; 1146 1057 rec_cfg.rec_en = port->input; 1147 1058 REG_WR(sser, port->regi_sser, rw_cfg, cfg); ··· 1159 1068 spin_lock_irqsave(&port->lock, flags); 1160 1069 port->out_buf_count += trunc_count; 1161 1070 if (port->use_dma) { 1071 + #ifdef SYNC_SER_DMA 1162 1072 start_dma_out(port, wr_ptr, trunc_count); 1073 + #endif 1163 1074 } else if (!port->tr_running) { 1075 + #ifdef SYNC_SER_MANUAL 1164 1076 reg_sser_rw_intr_mask intr_mask; 1165 1077 intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); 1166 1078 /* Start sender by writing data */ ··· 1171 1077 /* and enable transmitter ready IRQ */ 1172 1078 intr_mask.trdy = 1; 1173 1079 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); 1080 + #endif 1174 1081 } 1175 1082 spin_unlock_irqrestore(&port->lock, flags); 1176 1083 1177 1084 /* Exit if non blocking */ 1178 1085 if (file->f_flags & O_NONBLOCK) { 1179 - DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu %08x\n", 1180 - port->port_nbr, trunc_count, 1181 - REG_RD_INT(dma, port->regi_dmaout, r_intr))); 1086 + DEBUGWRITE(pr_info("w d%d c %u %08x\n", 1087 + port->port_nbr, trunc_count, 1088 + REG_RD_INT(dma, port->regi_dmaout, r_intr))); 1182 1089 return trunc_count; 1183 1090 } 1184 1091 ··· 1189 1094 if (signal_pending(current)) 1190 1095 return -EINTR; 1191 1096 1192 - DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", 1193 - port->port_nbr, trunc_count)); 1097 + DEBUGWRITE(pr_info("w d%d c %u\n", port->port_nbr, trunc_count)); 1194 1098 return trunc_count; 1195 1099 } 1196 1100 1197 - static ssize_t sync_serial_read(struct file * file, char * buf, 1101 + static ssize_t sync_serial_read(struct file *file, char __user *buf, 1198 1102 size_t count, loff_t *ppos) 1199 1103 { 1200 - int dev = iminor(file_inode(file)); 1201 - int avail; 1202 - sync_port *port; 1203 - unsigned char* start; 1204 - unsigned char* end; 1205 - unsigned long flags; 1206 - 1207 - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) 1208 - { 1209 - DEBUG(printk("Invalid minor %d\n", dev)); 1210 - return -ENODEV; 1211 - } 1212 - port = &ports[dev]; 1213 - 1214 - DEBUGREAD(printk("R%d c %d ri %lu wi %lu /%lu\n", dev, count, port->readp - port->flip, port->writep - port->flip, port->in_buffer_size)); 1215 - 1216 - if (!port->started) 1217 - { 1218 - reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); 1219 - reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); 1220 - reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); 1221 - cfg.en = regk_sser_yes; 1222 - tr_cfg.tr_en = regk_sser_yes; 1223 - rec_cfg.rec_en = regk_sser_yes; 1224 - REG_WR(sser, port->regi_sser, rw_cfg, cfg); 1225 - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); 1226 - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); 1227 - port->started = 1; 1228 - } 1229 - 1230 - /* Calculate number of available bytes */ 1231 - /* Save pointers to avoid that they are modified by interrupt */ 1232 - spin_lock_irqsave(&port->lock, flags); 1233 - start = (unsigned char*)port->readp; /* cast away volatile */ 1234 - end = (unsigned char*)port->writep; /* cast away volatile */ 1235 - spin_unlock_irqrestore(&port->lock, flags); 1236 - while ((start == end) && !port->full) /* No data */ 1237 - { 1238 - DEBUGREAD(printk(KERN_DEBUG "&")); 1239 - if (file->f_flags & O_NONBLOCK) 1240 - return -EAGAIN; 1241 - 1242 - wait_event_interruptible(port->in_wait_q, 1243 - !(start == end && !port->full)); 1244 - if (signal_pending(current)) 1245 - return -EINTR; 1246 - 1247 - spin_lock_irqsave(&port->lock, flags); 1248 - start = (unsigned char*)port->readp; /* cast away volatile */ 1249 - end = (unsigned char*)port->writep; /* cast away volatile */ 1250 - spin_unlock_irqrestore(&port->lock, flags); 1251 - } 1252 - 1253 - /* Lazy read, never return wrapped data. */ 1254 - if (port->full) 1255 - avail = port->in_buffer_size; 1256 - else if (end > start) 1257 - avail = end - start; 1258 - else 1259 - avail = port->flip + port->in_buffer_size - start; 1260 - 1261 - count = count > avail ? avail : count; 1262 - if (copy_to_user(buf, start, count)) 1263 - return -EFAULT; 1264 - /* Disable interrupts while updating readp */ 1265 - spin_lock_irqsave(&port->lock, flags); 1266 - port->readp += count; 1267 - if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ 1268 - port->readp = port->flip; 1269 - port->full = 0; 1270 - spin_unlock_irqrestore(&port->lock, flags); 1271 - DEBUGREAD(printk("r %d\n", count)); 1272 - return count; 1104 + return __sync_serial_read(file, buf, count, ppos, NULL); 1273 1105 } 1274 1106 1275 - static void send_word(sync_port* port) 1107 + #ifdef SYNC_SER_MANUAL 1108 + static void send_word(struct sync_port *port) 1276 1109 { 1277 1110 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); 1278 1111 reg_sser_rw_tr_data tr_data = {0}; 1279 1112 1280 - switch(tr_cfg.sample_size) 1113 + switch (tr_cfg.sample_size) { 1114 + case 8: 1115 + port->out_buf_count--; 1116 + tr_data.data = *port->out_rd_ptr++; 1117 + REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); 1118 + if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) 1119 + port->out_rd_ptr = port->out_buffer; 1120 + break; 1121 + case 12: 1281 1122 { 1282 - case 8: 1283 - port->out_buf_count--; 1284 - tr_data.data = *port->out_rd_ptr++; 1285 - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); 1286 - if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) 1287 - port->out_rd_ptr = port->out_buffer; 1288 - break; 1289 - case 12: 1290 - { 1291 1123 int data = (*port->out_rd_ptr++) << 8; 1292 1124 data |= *port->out_rd_ptr++; 1293 1125 port->out_buf_count -= 2; ··· 1222 1200 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); 1223 1201 if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) 1224 1202 port->out_rd_ptr = port->out_buffer; 1203 + break; 1225 1204 } 1226 - break; 1227 1205 case 16: 1228 1206 port->out_buf_count -= 2; 1229 1207 tr_data.data = *(unsigned short *)port->out_rd_ptr; ··· 1255 1233 break; 1256 1234 } 1257 1235 } 1236 + #endif 1258 1237 1259 - static void start_dma_out(struct sync_port *port, 1260 - const char *data, int count) 1238 + #ifdef SYNC_SER_DMA 1239 + static void start_dma_out(struct sync_port *port, const char *data, int count) 1261 1240 { 1262 - port->active_tr_descr->buf = (char *) virt_to_phys((char *) data); 1241 + port->active_tr_descr->buf = (char *)virt_to_phys((char *)data); 1263 1242 port->active_tr_descr->after = port->active_tr_descr->buf + count; 1264 1243 port->active_tr_descr->intr = 1; 1265 1244 1266 1245 port->active_tr_descr->eol = 1; 1267 1246 port->prev_tr_descr->eol = 0; 1268 1247 1269 - DEBUGTRDMA(printk(KERN_DEBUG "Inserting eolr:%p eol@:%p\n", 1248 + DEBUGTRDMA(pr_info("Inserting eolr:%p eol@:%p\n", 1270 1249 port->prev_tr_descr, port->active_tr_descr)); 1271 1250 port->prev_tr_descr = port->active_tr_descr; 1272 - port->active_tr_descr = phys_to_virt((int) port->active_tr_descr->next); 1251 + port->active_tr_descr = phys_to_virt((int)port->active_tr_descr->next); 1273 1252 1274 1253 if (!port->tr_running) { 1275 1254 reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, 1276 1255 rw_tr_cfg); 1277 1256 1278 - port->out_context.next = 0; 1257 + port->out_context.next = NULL; 1279 1258 port->out_context.saved_data = 1280 1259 (dma_descr_data *)virt_to_phys(port->prev_tr_descr); 1281 1260 port->out_context.saved_data_buf = port->prev_tr_descr->buf; ··· 1286 1263 1287 1264 tr_cfg.tr_en = regk_sser_yes; 1288 1265 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); 1289 - DEBUGTRDMA(printk(KERN_DEBUG "dma s\n");); 1266 + DEBUGTRDMA(pr_info(KERN_INFO "dma s\n");); 1290 1267 } else { 1291 1268 DMA_CONTINUE_DATA(port->regi_dmaout); 1292 - DEBUGTRDMA(printk(KERN_DEBUG "dma c\n");); 1269 + DEBUGTRDMA(pr_info("dma c\n");); 1293 1270 } 1294 1271 1295 1272 port->tr_running = 1; 1296 1273 } 1297 1274 1298 - static void start_dma_in(sync_port *port) 1275 + static void start_dma_in(struct sync_port *port) 1299 1276 { 1300 1277 int i; 1301 1278 char *buf; 1279 + unsigned long flags; 1280 + spin_lock_irqsave(&port->lock, flags); 1302 1281 port->writep = port->flip; 1282 + spin_unlock_irqrestore(&port->lock, flags); 1303 1283 1304 - if (port->writep > port->flip + port->in_buffer_size) { 1305 - panic("Offset too large in sync serial driver\n"); 1306 - return; 1307 - } 1308 - buf = (char*)virt_to_phys(port->in_buffer); 1284 + buf = (char *)virt_to_phys(port->in_buffer); 1309 1285 for (i = 0; i < NBR_IN_DESCR; i++) { 1310 1286 port->in_descr[i].buf = buf; 1311 1287 port->in_descr[i].after = buf + port->inbufchunk; 1312 1288 port->in_descr[i].intr = 1; 1313 - port->in_descr[i].next = (dma_descr_data*)virt_to_phys(&port->in_descr[i+1]); 1289 + port->in_descr[i].next = 1290 + (dma_descr_data *)virt_to_phys(&port->in_descr[i+1]); 1314 1291 port->in_descr[i].buf = buf; 1315 1292 buf += port->inbufchunk; 1316 1293 } 1317 1294 /* Link the last descriptor to the first */ 1318 - port->in_descr[i-1].next = (dma_descr_data*)virt_to_phys(&port->in_descr[0]); 1295 + port->in_descr[i-1].next = 1296 + (dma_descr_data *)virt_to_phys(&port->in_descr[0]); 1319 1297 port->in_descr[i-1].eol = regk_sser_yes; 1320 1298 port->next_rx_desc = &port->in_descr[0]; 1321 1299 port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1]; 1322 - port->in_context.saved_data = (dma_descr_data*)virt_to_phys(&port->in_descr[0]); 1300 + port->in_context.saved_data = 1301 + (dma_descr_data *)virt_to_phys(&port->in_descr[0]); 1323 1302 port->in_context.saved_data_buf = port->in_descr[0].buf; 1324 1303 DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context)); 1325 1304 } 1326 1305 1327 - #ifdef SYNC_SER_DMA 1328 1306 static irqreturn_t tr_interrupt(int irq, void *dev_id) 1329 1307 { 1330 1308 reg_dma_r_masked_intr masked; 1331 - reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes}; 1309 + reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes }; 1332 1310 reg_dma_rw_stat stat; 1333 1311 int i; 1334 1312 int found = 0; 1335 1313 int stop_sser = 0; 1336 1314 1337 1315 for (i = 0; i < NBR_PORTS; i++) { 1338 - sync_port *port = &ports[i]; 1339 - if (!port->enabled || !port->use_dma) 1316 + struct sync_port *port = &ports[i]; 1317 + if (!port->enabled || !port->use_dma) 1340 1318 continue; 1341 1319 1342 1320 /* IRQ active for the port? */ ··· 1362 1338 int sent; 1363 1339 sent = port->catch_tr_descr->after - 1364 1340 port->catch_tr_descr->buf; 1365 - DEBUGTXINT(printk(KERN_DEBUG "%-4d - %-4d = %-4d\t" 1366 - "in descr %p (ac: %p)\n", 1367 - port->out_buf_count, sent, 1368 - port->out_buf_count - sent, 1369 - port->catch_tr_descr, 1370 - port->active_tr_descr);); 1341 + DEBUGTXINT(pr_info("%-4d - %-4d = %-4d\t" 1342 + "in descr %p (ac: %p)\n", 1343 + port->out_buf_count, sent, 1344 + port->out_buf_count - sent, 1345 + port->catch_tr_descr, 1346 + port->active_tr_descr);); 1371 1347 port->out_buf_count -= sent; 1372 1348 port->catch_tr_descr = 1373 1349 phys_to_virt((int) port->catch_tr_descr->next); 1374 1350 port->out_rd_ptr = 1375 1351 phys_to_virt((int) port->catch_tr_descr->buf); 1376 1352 } else { 1377 - int i, sent; 1353 + reg_sser_rw_tr_cfg tr_cfg; 1354 + int j, sent; 1378 1355 /* EOL handler. 1379 1356 * Note that if an EOL was encountered during the irq 1380 1357 * locked section of sync_ser_write the DMA will be ··· 1383 1358 * The remaining descriptors will be traversed by 1384 1359 * the descriptor interrupts as usual. 1385 1360 */ 1386 - i = 0; 1361 + j = 0; 1387 1362 while (!port->catch_tr_descr->eol) { 1388 1363 sent = port->catch_tr_descr->after - 1389 1364 port->catch_tr_descr->buf; 1390 - DEBUGOUTBUF(printk(KERN_DEBUG 1365 + DEBUGOUTBUF(pr_info( 1391 1366 "traversing descr %p -%d (%d)\n", 1392 1367 port->catch_tr_descr, 1393 1368 sent, ··· 1395 1370 port->out_buf_count -= sent; 1396 1371 port->catch_tr_descr = phys_to_virt( 1397 1372 (int)port->catch_tr_descr->next); 1398 - i++; 1399 - if (i >= NBR_OUT_DESCR) { 1373 + j++; 1374 + if (j >= NBR_OUT_DESCR) { 1400 1375 /* TODO: Reset and recover */ 1401 1376 panic("sync_serial: missing eol"); 1402 1377 } 1403 1378 } 1404 1379 sent = port->catch_tr_descr->after - 1405 1380 port->catch_tr_descr->buf; 1406 - DEBUGOUTBUF(printk(KERN_DEBUG 1407 - "eol at descr %p -%d (%d)\n", 1381 + DEBUGOUTBUF(pr_info("eol at descr %p -%d (%d)\n", 1408 1382 port->catch_tr_descr, 1409 1383 sent, 1410 1384 port->out_buf_count)); ··· 1418 1394 OUT_BUFFER_SIZE) 1419 1395 port->out_rd_ptr = port->out_buffer; 1420 1396 1421 - reg_sser_rw_tr_cfg tr_cfg = 1422 - REG_RD(sser, port->regi_sser, rw_tr_cfg); 1423 - DEBUGTXINT(printk(KERN_DEBUG 1397 + tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); 1398 + DEBUGTXINT(pr_info( 1424 1399 "tr_int DMA stop %d, set catch @ %p\n", 1425 1400 port->out_buf_count, 1426 1401 port->active_tr_descr)); 1427 1402 if (port->out_buf_count != 0) 1428 - printk(KERN_CRIT "sync_ser: buffer not " 1429 - "empty after eol.\n"); 1403 + pr_err("sync_ser: buf not empty after eol\n"); 1430 1404 port->catch_tr_descr = port->active_tr_descr; 1431 1405 port->tr_running = 0; 1432 1406 tr_cfg.tr_en = regk_sser_no; ··· 1436 1414 return IRQ_RETVAL(found); 1437 1415 } /* tr_interrupt */ 1438 1416 1417 + 1418 + static inline void handle_rx_packet(struct sync_port *port) 1419 + { 1420 + int idx; 1421 + reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes }; 1422 + unsigned long flags; 1423 + 1424 + DEBUGRXINT(pr_info(KERN_INFO "!")); 1425 + spin_lock_irqsave(&port->lock, flags); 1426 + 1427 + /* If we overrun the user experience is crap regardless if we 1428 + * drop new or old data. Its much easier to get it right when 1429 + * dropping new data so lets do that. 1430 + */ 1431 + if ((port->writep + port->inbufchunk <= 1432 + port->flip + port->in_buffer_size) && 1433 + (port->in_buffer_len + port->inbufchunk < IN_BUFFER_SIZE)) { 1434 + memcpy(port->writep, 1435 + phys_to_virt((unsigned)port->next_rx_desc->buf), 1436 + port->inbufchunk); 1437 + port->writep += port->inbufchunk; 1438 + if (port->writep >= port->flip + port->in_buffer_size) 1439 + port->writep = port->flip; 1440 + 1441 + /* Timestamp the new data chunk. */ 1442 + if (port->write_ts_idx == NBR_IN_DESCR) 1443 + port->write_ts_idx = 0; 1444 + idx = port->write_ts_idx++; 1445 + do_posix_clock_monotonic_gettime(&port->timestamp[idx]); 1446 + port->in_buffer_len += port->inbufchunk; 1447 + } 1448 + spin_unlock_irqrestore(&port->lock, flags); 1449 + 1450 + port->next_rx_desc->eol = 1; 1451 + port->prev_rx_desc->eol = 0; 1452 + /* Cache bug workaround */ 1453 + flush_dma_descr(port->prev_rx_desc, 0); 1454 + port->prev_rx_desc = port->next_rx_desc; 1455 + port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next); 1456 + /* Cache bug workaround */ 1457 + flush_dma_descr(port->prev_rx_desc, 1); 1458 + /* wake up the waiting process */ 1459 + wake_up_interruptible(&port->in_wait_q); 1460 + DMA_CONTINUE(port->regi_dmain); 1461 + REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr); 1462 + 1463 + } 1464 + 1439 1465 static irqreturn_t rx_interrupt(int irq, void *dev_id) 1440 1466 { 1441 1467 reg_dma_r_masked_intr masked; 1442 - reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes}; 1443 1468 1444 1469 int i; 1445 1470 int found = 0; 1446 1471 1447 - for (i = 0; i < NBR_PORTS; i++) 1448 - { 1449 - sync_port *port = &ports[i]; 1472 + DEBUG(pr_info("rx_interrupt\n")); 1450 1473 1451 - if (!port->enabled || !port->use_dma ) 1474 + for (i = 0; i < NBR_PORTS; i++) { 1475 + struct sync_port *port = &ports[i]; 1476 + 1477 + if (!port->enabled || !port->use_dma) 1452 1478 continue; 1453 1479 1454 1480 masked = REG_RD(dma, port->regi_dmain, r_masked_intr); 1455 1481 1456 - if (masked.data) /* Descriptor interrupt */ 1457 - { 1458 - found = 1; 1459 - while (REG_RD(dma, port->regi_dmain, rw_data) != 1460 - virt_to_phys(port->next_rx_desc)) { 1461 - DEBUGRXINT(printk(KERN_DEBUG "!")); 1462 - if (port->writep + port->inbufchunk > port->flip + port->in_buffer_size) { 1463 - int first_size = port->flip + port->in_buffer_size - port->writep; 1464 - memcpy((char*)port->writep, phys_to_virt((unsigned)port->next_rx_desc->buf), first_size); 1465 - memcpy(port->flip, phys_to_virt((unsigned)port->next_rx_desc->buf+first_size), port->inbufchunk - first_size); 1466 - port->writep = port->flip + port->inbufchunk - first_size; 1467 - } else { 1468 - memcpy((char*)port->writep, 1469 - phys_to_virt((unsigned)port->next_rx_desc->buf), 1470 - port->inbufchunk); 1471 - port->writep += port->inbufchunk; 1472 - if (port->writep >= port->flip + port->in_buffer_size) 1473 - port->writep = port->flip; 1474 - } 1475 - if (port->writep == port->readp) 1476 - { 1477 - port->full = 1; 1478 - } 1482 + if (!masked.data) 1483 + continue; 1479 1484 1480 - port->next_rx_desc->eol = 1; 1481 - port->prev_rx_desc->eol = 0; 1482 - /* Cache bug workaround */ 1483 - flush_dma_descr(port->prev_rx_desc, 0); 1484 - port->prev_rx_desc = port->next_rx_desc; 1485 - port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next); 1486 - /* Cache bug workaround */ 1487 - flush_dma_descr(port->prev_rx_desc, 1); 1488 - /* wake up the waiting process */ 1489 - wake_up_interruptible(&port->in_wait_q); 1490 - DMA_CONTINUE(port->regi_dmain); 1491 - REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr); 1492 - 1493 - } 1494 - } 1485 + /* Descriptor interrupt */ 1486 + found = 1; 1487 + while (REG_RD(dma, port->regi_dmain, rw_data) != 1488 + virt_to_phys(port->next_rx_desc)) 1489 + handle_rx_packet(port); 1495 1490 } 1496 1491 return IRQ_RETVAL(found); 1497 1492 } /* rx_interrupt */ ··· 1517 1478 #ifdef SYNC_SER_MANUAL 1518 1479 static irqreturn_t manual_interrupt(int irq, void *dev_id) 1519 1480 { 1481 + unsigned long flags; 1520 1482 int i; 1521 1483 int found = 0; 1522 1484 reg_sser_r_masked_intr masked; 1523 1485 1524 - for (i = 0; i < NBR_PORTS; i++) 1525 - { 1526 - sync_port *port = &ports[i]; 1486 + for (i = 0; i < NBR_PORTS; i++) { 1487 + struct sync_port *port = &ports[i]; 1527 1488 1528 1489 if (!port->enabled || port->use_dma) 1529 - { 1530 1490 continue; 1531 - } 1532 1491 1533 1492 masked = REG_RD(sser, port->regi_sser, r_masked_intr); 1534 - if (masked.rdav) /* Data received? */ 1535 - { 1536 - reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); 1537 - reg_sser_r_rec_data data = REG_RD(sser, port->regi_sser, r_rec_data); 1493 + /* Data received? */ 1494 + if (masked.rdav) { 1495 + reg_sser_rw_rec_cfg rec_cfg = 1496 + REG_RD(sser, port->regi_sser, rw_rec_cfg); 1497 + reg_sser_r_rec_data data = REG_RD(sser, 1498 + port->regi_sser, r_rec_data); 1538 1499 found = 1; 1539 1500 /* Read data */ 1540 - switch(rec_cfg.sample_size) 1541 - { 1501 + spin_lock_irqsave(&port->lock, flags); 1502 + switch (rec_cfg.sample_size) { 1542 1503 case 8: 1543 1504 *port->writep++ = data.data & 0xff; 1544 1505 break; 1545 1506 case 12: 1546 1507 *port->writep = (data.data & 0x0ff0) >> 4; 1547 1508 *(port->writep + 1) = data.data & 0x0f; 1548 - port->writep+=2; 1509 + port->writep += 2; 1549 1510 break; 1550 1511 case 16: 1551 - *(unsigned short*)port->writep = data.data; 1552 - port->writep+=2; 1512 + *(unsigned short *)port->writep = data.data; 1513 + port->writep += 2; 1553 1514 break; 1554 1515 case 24: 1555 - *(unsigned int*)port->writep = data.data; 1556 - port->writep+=3; 1516 + *(unsigned int *)port->writep = data.data; 1517 + port->writep += 3; 1557 1518 break; 1558 1519 case 32: 1559 - *(unsigned int*)port->writep = data.data; 1560 - port->writep+=4; 1520 + *(unsigned int *)port->writep = data.data; 1521 + port->writep += 4; 1561 1522 break; 1562 1523 } 1563 1524 1564 - if (port->writep >= port->flip + port->in_buffer_size) /* Wrap? */ 1525 + /* Wrap? */ 1526 + if (port->writep >= port->flip + port->in_buffer_size) 1565 1527 port->writep = port->flip; 1566 1528 if (port->writep == port->readp) { 1567 - /* receive buffer overrun, discard oldest data 1568 - */ 1529 + /* Receive buf overrun, discard oldest data */ 1569 1530 port->readp++; 1570 - if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ 1531 + /* Wrap? */ 1532 + if (port->readp >= port->flip + 1533 + port->in_buffer_size) 1571 1534 port->readp = port->flip; 1572 1535 } 1536 + spin_unlock_irqrestore(&port->lock, flags); 1573 1537 if (sync_data_avail(port) >= port->inbufchunk) 1574 - wake_up_interruptible(&port->in_wait_q); /* Wake up application */ 1538 + /* Wake up application */ 1539 + wake_up_interruptible(&port->in_wait_q); 1575 1540 } 1576 1541 1577 - if (masked.trdy) /* Transmitter ready? */ 1578 - { 1542 + /* Transmitter ready? */ 1543 + if (masked.trdy) { 1579 1544 found = 1; 1580 - if (port->out_buf_count > 0) /* More data to send */ 1545 + /* More data to send */ 1546 + if (port->out_buf_count > 0) 1581 1547 send_word(port); 1582 - else /* transmission finished */ 1583 - { 1548 + else { 1549 + /* Transmission finished */ 1584 1550 reg_sser_rw_intr_mask intr_mask; 1585 - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); 1551 + intr_mask = REG_RD(sser, port->regi_sser, 1552 + rw_intr_mask); 1586 1553 intr_mask.trdy = 0; 1587 - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); 1588 - wake_up_interruptible(&port->out_wait_q); /* Wake up application */ 1554 + REG_WR(sser, port->regi_sser, 1555 + rw_intr_mask, intr_mask); 1556 + /* Wake up application */ 1557 + wake_up_interruptible(&port->out_wait_q); 1589 1558 } 1590 1559 } 1591 1560 } ··· 1601 1554 } 1602 1555 #endif 1603 1556 1557 + static int __init etrax_sync_serial_init(void) 1558 + { 1559 + #if 1 1560 + /* This code will be removed when we move to udev for all devices. */ 1561 + syncser_first = MKDEV(SYNC_SERIAL_MAJOR, 0); 1562 + if (register_chrdev_region(syncser_first, minor_count, SYNCSER_NAME)) { 1563 + pr_err("Failed to register major %d\n", SYNC_SERIAL_MAJOR); 1564 + return -1; 1565 + } 1566 + #else 1567 + /* Allocate dynamic major number. */ 1568 + if (alloc_chrdev_region(&syncser_first, 0, minor_count, SYNCSER_NAME)) { 1569 + pr_err("Failed to allocate character device region\n"); 1570 + return -1; 1571 + } 1572 + #endif 1573 + syncser_cdev = cdev_alloc(); 1574 + if (!syncser_cdev) { 1575 + pr_err("Failed to allocate cdev for syncser\n"); 1576 + unregister_chrdev_region(syncser_first, minor_count); 1577 + return -1; 1578 + } 1579 + cdev_init(syncser_cdev, &syncser_fops); 1580 + 1581 + /* Create a sysfs class for syncser */ 1582 + syncser_class = class_create(THIS_MODULE, "syncser_class"); 1583 + 1584 + /* Initialize Ports */ 1585 + #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 1586 + if (artpec_pinmux_alloc_fixed(PINMUX_SSER0)) { 1587 + pr_warn("Unable to alloc pins for synchronous serial port 0\n"); 1588 + unregister_chrdev_region(syncser_first, minor_count); 1589 + return -EIO; 1590 + } 1591 + initialize_port(0); 1592 + ports[0].enabled = 1; 1593 + /* Register with sysfs so udev can pick it up. */ 1594 + device_create(syncser_class, NULL, syncser_first, NULL, 1595 + "%s%d", SYNCSER_NAME, 0); 1596 + #endif 1597 + 1598 + #if defined(CONFIG_ETRAXFS) && defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 1599 + if (artpec_pinmux_alloc_fixed(PINMUX_SSER1)) { 1600 + pr_warn("Unable to alloc pins for synchronous serial port 1\n"); 1601 + unregister_chrdev_region(syncser_first, minor_count); 1602 + class_destroy(syncser_class); 1603 + return -EIO; 1604 + } 1605 + initialize_port(1); 1606 + ports[1].enabled = 1; 1607 + /* Register with sysfs so udev can pick it up. */ 1608 + device_create(syncser_class, NULL, syncser_first, NULL, 1609 + "%s%d", SYNCSER_NAME, 0); 1610 + #endif 1611 + 1612 + /* Add it to system */ 1613 + if (cdev_add(syncser_cdev, syncser_first, minor_count) < 0) { 1614 + pr_err("Failed to add syncser as char device\n"); 1615 + device_destroy(syncser_class, syncser_first); 1616 + class_destroy(syncser_class); 1617 + cdev_del(syncser_cdev); 1618 + unregister_chrdev_region(syncser_first, minor_count); 1619 + return -1; 1620 + } 1621 + 1622 + 1623 + pr_info("ARTPEC synchronous serial port (%s: %d, %d)\n", 1624 + SYNCSER_NAME, MAJOR(syncser_first), MINOR(syncser_first)); 1625 + 1626 + return 0; 1627 + } 1628 + 1629 + static void __exit etrax_sync_serial_exit(void) 1630 + { 1631 + int i; 1632 + device_destroy(syncser_class, syncser_first); 1633 + class_destroy(syncser_class); 1634 + 1635 + if (syncser_cdev) { 1636 + cdev_del(syncser_cdev); 1637 + unregister_chrdev_region(syncser_first, minor_count); 1638 + } 1639 + for (i = 0; i < NBR_PORTS; i++) { 1640 + struct sync_port *port = &ports[i]; 1641 + if (port->init_irqs == dma_irq_setup) { 1642 + /* Free dma irqs and dma channels. */ 1643 + #ifdef SYNC_SER_DMA 1644 + artpec_free_dma(port->dma_in_nbr); 1645 + artpec_free_dma(port->dma_out_nbr); 1646 + free_irq(port->dma_out_intr_vect, port); 1647 + free_irq(port->dma_in_intr_vect, port); 1648 + #endif 1649 + } else if (port->init_irqs == manual_irq_setup) { 1650 + /* Free manual irq. */ 1651 + free_irq(port->syncser_intr_vect, port); 1652 + } 1653 + } 1654 + 1655 + pr_info("ARTPEC synchronous serial port unregistered\n"); 1656 + } 1657 + 1604 1658 module_init(etrax_sync_serial_init); 1659 + module_exit(etrax_sync_serial_exit); 1660 + 1661 + MODULE_LICENSE("GPL"); 1662 +
+56 -26
arch/cris/arch-v32/kernel/debugport.c
··· 3 3 */ 4 4 5 5 #include <linux/console.h> 6 + #include <linux/kernel.h> 6 7 #include <linux/init.h> 8 + #include <linux/string.h> 7 9 #include <hwregs/reg_rdwr.h> 8 10 #include <hwregs/reg_map.h> 9 11 #include <hwregs/ser_defs.h> ··· 67 65 }, 68 66 #endif 69 67 }; 68 + 70 69 static struct dbg_port *port = 71 70 #if defined(CONFIG_ETRAX_DEBUG_PORT0) 72 71 &ports[0]; ··· 100 97 #endif 101 98 #endif 102 99 103 - static void 104 - start_port(struct dbg_port* p) 100 + static void start_port(struct dbg_port *p) 105 101 { 106 - if (!p) 102 + /* Set up serial port registers */ 103 + reg_ser_rw_tr_ctrl tr_ctrl = {0}; 104 + reg_ser_rw_tr_dma_en tr_dma_en = {0}; 105 + 106 + reg_ser_rw_rec_ctrl rec_ctrl = {0}; 107 + reg_ser_rw_tr_baud_div tr_baud_div = {0}; 108 + reg_ser_rw_rec_baud_div rec_baud_div = {0}; 109 + 110 + if (!p || p->started) 107 111 return; 108 112 109 - if (p->started) 110 - return; 111 113 p->started = 1; 112 114 113 115 if (p->nbr == 1) ··· 126 118 crisv32_pinmux_alloc_fixed(pinmux_ser4); 127 119 #endif 128 120 129 - /* Set up serial port registers */ 130 - reg_ser_rw_tr_ctrl tr_ctrl = {0}; 131 - reg_ser_rw_tr_dma_en tr_dma_en = {0}; 132 - 133 - reg_ser_rw_rec_ctrl rec_ctrl = {0}; 134 - reg_ser_rw_tr_baud_div tr_baud_div = {0}; 135 - reg_ser_rw_rec_baud_div rec_baud_div = {0}; 136 - 137 121 tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493; 138 122 tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no; 139 123 tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8; 140 124 tr_ctrl.en = rec_ctrl.en = 1; 141 125 142 - if (p->parity == 'O') 143 - { 126 + if (p->parity == 'O') { 144 127 tr_ctrl.par_en = regk_ser_yes; 145 128 tr_ctrl.par = regk_ser_odd; 146 129 rec_ctrl.par_en = regk_ser_yes; 147 130 rec_ctrl.par = regk_ser_odd; 148 - } 149 - else if (p->parity == 'E') 150 - { 131 + } else if (p->parity == 'E') { 151 132 tr_ctrl.par_en = regk_ser_yes; 152 133 tr_ctrl.par = regk_ser_even; 153 134 rec_ctrl.par_en = regk_ser_yes; 154 135 rec_ctrl.par = regk_ser_odd; 155 136 } 156 137 157 - if (p->bits == 7) 158 - { 138 + if (p->bits == 7) { 159 139 tr_ctrl.data_bits = regk_ser_bits7; 160 140 rec_ctrl.data_bits = regk_ser_bits7; 161 141 } ··· 157 161 158 162 #ifdef CONFIG_ETRAX_KGDB 159 163 /* Use polling to get a single character from the kernel debug port */ 160 - int 161 - getDebugChar(void) 164 + int getDebugChar(void) 162 165 { 163 166 reg_ser_rs_stat_din stat; 164 167 reg_ser_rw_ack_intr ack_intr = { 0 }; ··· 174 179 } 175 180 176 181 /* Use polling to put a single character to the kernel debug port */ 177 - void 178 - putDebugChar(int val) 182 + void putDebugChar(int val) 179 183 { 180 184 reg_ser_r_stat_din stat; 181 185 do { ··· 184 190 } 185 191 #endif /* CONFIG_ETRAX_KGDB */ 186 192 193 + static void __init early_putch(int c) 194 + { 195 + reg_ser_r_stat_din stat; 196 + /* Wait until transmitter is ready and send. */ 197 + do 198 + stat = REG_RD(ser, port->instance, r_stat_din); 199 + while (!stat.tr_rdy); 200 + REG_WR_INT(ser, port->instance, rw_dout, c); 201 + } 202 + 203 + static void __init 204 + early_console_write(struct console *con, const char *s, unsigned n) 205 + { 206 + extern void reset_watchdog(void); 207 + int i; 208 + 209 + /* Send data. */ 210 + for (i = 0; i < n; i++) { 211 + /* TODO: the '\n' -> '\n\r' translation should be done at the 212 + receiver. Remove it when the serial driver removes it. */ 213 + if (s[i] == '\n') 214 + early_putch('\r'); 215 + early_putch(s[i]); 216 + reset_watchdog(); 217 + } 218 + } 219 + 220 + static struct console early_console_dev __initdata = { 221 + .name = "early", 222 + .write = early_console_write, 223 + .flags = CON_PRINTBUFFER | CON_BOOT, 224 + .index = -1 225 + }; 226 + 187 227 /* Register console for printk's, etc. */ 188 - int __init 189 - init_etrax_debug(void) 228 + int __init init_etrax_debug(void) 190 229 { 191 230 start_port(port); 231 + 232 + /* Register an early console if a debug port was chosen. */ 233 + register_console(&early_console_dev); 192 234 193 235 #ifdef CONFIG_ETRAX_KGDB 194 236 start_port(kgdb_port);
+18 -11
arch/cris/arch-v32/kernel/time.c
··· 14 14 #include <linux/init.h> 15 15 #include <linux/threads.h> 16 16 #include <linux/cpufreq.h> 17 + #include <linux/mm.h> 17 18 #include <asm/types.h> 18 19 #include <asm/signal.h> 19 20 #include <asm/io.h> ··· 57 56 } 58 57 arch_initcall(etrax_init_cont_rotime); 59 58 60 - 61 59 unsigned long timer_regs[NR_CPUS] = 62 60 { 63 61 regi_timer0, ··· 68 68 extern int set_rtc_mmss(unsigned long nowtime); 69 69 70 70 #ifdef CONFIG_CPU_FREQ 71 - static int 72 - cris_time_freq_notifier(struct notifier_block *nb, unsigned long val, 73 - void *data); 71 + static int cris_time_freq_notifier(struct notifier_block *nb, 72 + unsigned long val, void *data); 74 73 75 74 static struct notifier_block cris_time_freq_notifier_block = { 76 75 .notifier_call = cris_time_freq_notifier, ··· 85 86 ns = (TIMER0_DIV - data) * 10; 86 87 return ns; 87 88 } 88 - 89 89 90 90 /* From timer MDS describing the hardware watchdog: 91 91 * 4.3.1 Watchdog Operation ··· 107 109 * is used though, so set this really low. */ 108 110 #define WATCHDOG_MIN_FREE_PAGES 8 109 111 112 + /* for reliable NICE_DOGGY behaviour */ 113 + static int bite_in_progress; 114 + 110 115 void reset_watchdog(void) 111 116 { 112 117 #if defined(CONFIG_ETRAX_WATCHDOG) 113 118 reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; 114 119 120 + #if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) 121 + if (unlikely(bite_in_progress)) 122 + return; 123 + #endif 115 124 /* Only keep watchdog happy as long as we have memory left! */ 116 125 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { 117 126 /* Reset the watchdog with the inverse of the old key */ ··· 153 148 #if defined(CONFIG_ETRAX_WATCHDOG) 154 149 extern int cause_of_death; 155 150 151 + nmi_enter(); 156 152 oops_in_progress = 1; 153 + bite_in_progress = 1; 157 154 printk(KERN_WARNING "Watchdog bite\n"); 158 155 159 156 /* Check if forced restart or unexpected watchdog */ ··· 177 170 printk(KERN_WARNING "Oops: bitten by watchdog\n"); 178 171 show_registers(regs); 179 172 oops_in_progress = 0; 173 + printk("\n"); /* Flush mtdoops. */ 180 174 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY 181 175 reset_watchdog(); 182 176 #endif ··· 210 202 /* Reset watchdog otherwise it resets us! */ 211 203 reset_watchdog(); 212 204 213 - /* Update statistics. */ 205 + /* Update statistics. */ 214 206 update_process_times(user_mode(regs)); 215 207 216 208 cris_do_profile(regs); /* Save profiling information */ ··· 221 213 222 214 /* Call the real timer interrupt handler */ 223 215 xtime_update(1); 224 - return IRQ_HANDLED; 216 + return IRQ_HANDLED; 225 217 } 226 218 227 219 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */ ··· 301 293 302 294 #ifdef CONFIG_CPU_FREQ 303 295 cpufreq_register_notifier(&cris_time_freq_notifier_block, 304 - CPUFREQ_TRANSITION_NOTIFIER); 296 + CPUFREQ_TRANSITION_NOTIFIER); 305 297 #endif 306 298 } 307 299 308 300 #ifdef CONFIG_CPU_FREQ 309 - static int 310 - cris_time_freq_notifier(struct notifier_block *nb, unsigned long val, 311 - void *data) 301 + static int cris_time_freq_notifier(struct notifier_block *nb, 302 + unsigned long val, void *data) 312 303 { 313 304 struct cpufreq_freqs *freqs = data; 314 305 if (val == CPUFREQ_POSTCHANGE) {
+7 -8
arch/cris/arch-v32/lib/usercopy.c
··· 26 26 /* Copy to userspace. This is based on the memcpy used for 27 27 kernel-to-kernel copying; see "string.c". */ 28 28 29 - unsigned long 30 - __copy_user (void __user *pdst, const void *psrc, unsigned long pn) 29 + unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn) 31 30 { 32 31 /* We want the parameters put in special registers. 33 32 Make sure the compiler is able to make something useful of this. ··· 154 155 155 156 return retn; 156 157 } 158 + EXPORT_SYMBOL(__copy_user); 157 159 158 160 /* Copy from user to kernel, zeroing the bytes that were inaccessible in 159 161 userland. The return-value is the number of bytes that were 160 162 inaccessible. */ 161 - 162 - unsigned long 163 - __copy_user_zeroing(void *pdst, const void __user *psrc, unsigned long pn) 163 + unsigned long __copy_user_zeroing(void *pdst, const void __user *psrc, 164 + unsigned long pn) 164 165 { 165 166 /* We want the parameters put in special registers. 166 167 Make sure the compiler is able to make something useful of this. ··· 320 321 321 322 return retn + n; 322 323 } 324 + EXPORT_SYMBOL(__copy_user_zeroing); 323 325 324 326 /* Zero userspace. */ 325 - 326 - unsigned long 327 - __do_clear_user (void __user *pto, unsigned long pn) 327 + unsigned long __do_clear_user(void __user *pto, unsigned long pn) 328 328 { 329 329 /* We want the parameters put in special registers. 330 330 Make sure the compiler is able to make something useful of this. ··· 466 468 467 469 return retn; 468 470 } 471 + EXPORT_SYMBOL(__do_clear_user);
+90 -76
arch/cris/arch-v32/mach-fs/pinmux.c
··· 26 26 27 27 static void crisv32_pinmux_set(int port); 28 28 29 - int crisv32_pinmux_init(void) 30 - { 31 - static int initialized; 32 - 33 - if (!initialized) { 34 - reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); 35 - initialized = 1; 36 - REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); 37 - pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 = 38 - pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes; 39 - REG_WR(pinmux, regi_pinmux, rw_pa, pa); 40 - crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio); 41 - crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio); 42 - crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio); 43 - crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio); 44 - } 45 - 46 - return 0; 47 - } 48 - 49 - int 50 - crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode) 29 + static int __crisv32_pinmux_alloc(int port, int first_pin, int last_pin, 30 + enum pin_mode mode) 51 31 { 52 32 int i; 53 - unsigned long flags; 54 - 55 - crisv32_pinmux_init(); 56 - 57 - if (port > PORTS || port < 0) 58 - return -EINVAL; 59 - 60 - spin_lock_irqsave(&pinmux_lock, flags); 61 33 62 34 for (i = first_pin; i <= last_pin; i++) { 63 35 if ((pins[port][i] != pinmux_none) 64 36 && (pins[port][i] != pinmux_gpio) 65 37 && (pins[port][i] != mode)) { 66 - spin_unlock_irqrestore(&pinmux_lock, flags); 67 38 #ifdef DEBUG 68 39 panic("Pinmux alloc failed!\n"); 69 40 #endif ··· 46 75 pins[port][i] = mode; 47 76 48 77 crisv32_pinmux_set(port); 78 + } 79 + 80 + static int crisv32_pinmux_init(void) 81 + { 82 + static int initialized; 83 + 84 + if (!initialized) { 85 + reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); 86 + initialized = 1; 87 + REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); 88 + pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 = 89 + pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes; 90 + REG_WR(pinmux, regi_pinmux, rw_pa, pa); 91 + __crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio); 92 + __crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio); 93 + __crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio); 94 + __crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio); 95 + } 96 + 97 + return 0; 98 + } 99 + 100 + int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, 101 + enum pin_mode mode) 102 + { 103 + unsigned long flags; 104 + int ret; 105 + 106 + crisv32_pinmux_init(); 107 + 108 + if (port > PORTS || port < 0) 109 + return -EINVAL; 110 + 111 + spin_lock_irqsave(&pinmux_lock, flags); 112 + 113 + ret = __crisv32_pinmux_alloc(port, first_pin, last_pin, mode); 49 114 50 115 spin_unlock_irqrestore(&pinmux_lock, flags); 51 116 52 - return 0; 117 + return ret; 53 118 } 54 119 55 120 int crisv32_pinmux_alloc_fixed(enum fixed_function function) ··· 105 98 106 99 switch (function) { 107 100 case pinmux_ser1: 108 - ret = crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed); 101 + ret = __crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed); 109 102 hwprot.ser1 = regk_pinmux_yes; 110 103 break; 111 104 case pinmux_ser2: 112 - ret = crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed); 105 + ret = __crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed); 113 106 hwprot.ser2 = regk_pinmux_yes; 114 107 break; 115 108 case pinmux_ser3: 116 - ret = crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed); 109 + ret = __crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed); 117 110 hwprot.ser3 = regk_pinmux_yes; 118 111 break; 119 112 case pinmux_sser0: 120 - ret = crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed); 121 - ret |= crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); 113 + ret = __crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed); 114 + ret |= __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); 122 115 hwprot.sser0 = regk_pinmux_yes; 123 116 break; 124 117 case pinmux_sser1: 125 - ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); 118 + ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); 126 119 hwprot.sser1 = regk_pinmux_yes; 127 120 break; 128 121 case pinmux_ata0: 129 - ret = crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed); 130 - ret |= crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed); 122 + ret = __crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed); 123 + ret |= __crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed); 131 124 hwprot.ata0 = regk_pinmux_yes; 132 125 break; 133 126 case pinmux_ata1: 134 - ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); 135 - ret |= crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed); 127 + ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); 128 + ret |= __crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed); 136 129 hwprot.ata1 = regk_pinmux_yes; 137 130 break; 138 131 case pinmux_ata2: 139 - ret = crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed); 140 - ret |= crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed); 132 + ret = __crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed); 133 + ret |= __crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed); 141 134 hwprot.ata2 = regk_pinmux_yes; 142 135 break; 143 136 case pinmux_ata3: 144 - ret = crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed); 145 - ret |= crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed); 137 + ret = __crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed); 138 + ret |= __crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed); 146 139 hwprot.ata2 = regk_pinmux_yes; 147 140 break; 148 141 case pinmux_ata: 149 - ret = crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed); 150 - ret |= crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed); 142 + ret = __crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed); 143 + ret |= __crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed); 151 144 hwprot.ata = regk_pinmux_yes; 152 145 break; 153 146 case pinmux_eth1: 154 - ret = crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed); 147 + ret = __crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed); 155 148 hwprot.eth1 = regk_pinmux_yes; 156 149 hwprot.eth1_mgm = regk_pinmux_yes; 157 150 break; 158 151 case pinmux_timer: 159 - ret = crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); 152 + ret = __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); 160 153 hwprot.timer = regk_pinmux_yes; 161 154 spin_unlock_irqrestore(&pinmux_lock, flags); 162 155 return ret; ··· 195 188 #endif 196 189 } 197 190 198 - int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) 191 + static int __crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) 199 192 { 200 193 int i; 194 + 195 + for (i = first_pin; i <= last_pin; i++) 196 + pins[port][i] = pinmux_none; 197 + 198 + crisv32_pinmux_set(port); 199 + return 0; 200 + } 201 + 202 + int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) 203 + { 201 204 unsigned long flags; 202 205 203 206 crisv32_pinmux_init(); ··· 216 199 return -EINVAL; 217 200 218 201 spin_lock_irqsave(&pinmux_lock, flags); 219 - 220 - for (i = first_pin; i <= last_pin; i++) 221 - pins[port][i] = pinmux_none; 222 - 223 - crisv32_pinmux_set(port); 202 + __crisv32_pinmux_dealloc(port, first_pin, last_pin); 224 203 spin_unlock_irqrestore(&pinmux_lock, flags); 225 204 226 205 return 0; ··· 239 226 240 227 switch (function) { 241 228 case pinmux_ser1: 242 - ret = crisv32_pinmux_dealloc(PORT_C, 4, 7); 229 + ret = __crisv32_pinmux_dealloc(PORT_C, 4, 7); 243 230 hwprot.ser1 = regk_pinmux_no; 244 231 break; 245 232 case pinmux_ser2: 246 - ret = crisv32_pinmux_dealloc(PORT_C, 8, 11); 233 + ret = __crisv32_pinmux_dealloc(PORT_C, 8, 11); 247 234 hwprot.ser2 = regk_pinmux_no; 248 235 break; 249 236 case pinmux_ser3: 250 - ret = crisv32_pinmux_dealloc(PORT_C, 12, 15); 237 + ret = __crisv32_pinmux_dealloc(PORT_C, 12, 15); 251 238 hwprot.ser3 = regk_pinmux_no; 252 239 break; 253 240 case pinmux_sser0: 254 - ret = crisv32_pinmux_dealloc(PORT_C, 0, 3); 255 - ret |= crisv32_pinmux_dealloc(PORT_C, 16, 16); 241 + ret = __crisv32_pinmux_dealloc(PORT_C, 0, 3); 242 + ret |= __crisv32_pinmux_dealloc(PORT_C, 16, 16); 256 243 hwprot.sser0 = regk_pinmux_no; 257 244 break; 258 245 case pinmux_sser1: 259 - ret = crisv32_pinmux_dealloc(PORT_D, 0, 4); 246 + ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4); 260 247 hwprot.sser1 = regk_pinmux_no; 261 248 break; 262 249 case pinmux_ata0: 263 - ret = crisv32_pinmux_dealloc(PORT_D, 5, 7); 264 - ret |= crisv32_pinmux_dealloc(PORT_D, 15, 17); 250 + ret = __crisv32_pinmux_dealloc(PORT_D, 5, 7); 251 + ret |= __crisv32_pinmux_dealloc(PORT_D, 15, 17); 265 252 hwprot.ata0 = regk_pinmux_no; 266 253 break; 267 254 case pinmux_ata1: 268 - ret = crisv32_pinmux_dealloc(PORT_D, 0, 4); 269 - ret |= crisv32_pinmux_dealloc(PORT_E, 17, 17); 255 + ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4); 256 + ret |= __crisv32_pinmux_dealloc(PORT_E, 17, 17); 270 257 hwprot.ata1 = regk_pinmux_no; 271 258 break; 272 259 case pinmux_ata2: 273 - ret = crisv32_pinmux_dealloc(PORT_C, 11, 15); 274 - ret |= crisv32_pinmux_dealloc(PORT_E, 3, 3); 260 + ret = __crisv32_pinmux_dealloc(PORT_C, 11, 15); 261 + ret |= __crisv32_pinmux_dealloc(PORT_E, 3, 3); 275 262 hwprot.ata2 = regk_pinmux_no; 276 263 break; 277 264 case pinmux_ata3: 278 - ret = crisv32_pinmux_dealloc(PORT_C, 8, 10); 279 - ret |= crisv32_pinmux_dealloc(PORT_C, 0, 2); 265 + ret = __crisv32_pinmux_dealloc(PORT_C, 8, 10); 266 + ret |= __crisv32_pinmux_dealloc(PORT_C, 0, 2); 280 267 hwprot.ata2 = regk_pinmux_no; 281 268 break; 282 269 case pinmux_ata: 283 - ret = crisv32_pinmux_dealloc(PORT_B, 0, 15); 284 - ret |= crisv32_pinmux_dealloc(PORT_D, 8, 15); 270 + ret = __crisv32_pinmux_dealloc(PORT_B, 0, 15); 271 + ret |= __crisv32_pinmux_dealloc(PORT_D, 8, 15); 285 272 hwprot.ata = regk_pinmux_no; 286 273 break; 287 274 case pinmux_eth1: 288 - ret = crisv32_pinmux_dealloc(PORT_E, 0, 17); 275 + ret = __crisv32_pinmux_dealloc(PORT_E, 0, 17); 289 276 hwprot.eth1 = regk_pinmux_no; 290 277 hwprot.eth1_mgm = regk_pinmux_no; 291 278 break; 292 279 case pinmux_timer: 293 - ret = crisv32_pinmux_dealloc(PORT_C, 16, 16); 280 + ret = __crisv32_pinmux_dealloc(PORT_C, 16, 16); 294 281 hwprot.timer = regk_pinmux_no; 295 282 spin_unlock_irqrestore(&pinmux_lock, flags); 296 283 return ret; ··· 306 293 return ret; 307 294 } 308 295 309 - void crisv32_pinmux_dump(void) 296 + #ifdef DEBUG 297 + static void crisv32_pinmux_dump(void) 310 298 { 311 299 int i, j; 312 300 ··· 319 305 printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]); 320 306 } 321 307 } 322 - 308 + #endif 323 309 __initcall(crisv32_pinmux_init);
-2
arch/cris/include/arch-v32/mach-fs/mach/pinmux.h
··· 28 28 pinmux_timer 29 29 }; 30 30 31 - int crisv32_pinmux_init(void); 32 31 int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); 33 32 int crisv32_pinmux_alloc_fixed(enum fixed_function function); 34 33 int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); 35 34 int crisv32_pinmux_dealloc_fixed(enum fixed_function function); 36 - void crisv32_pinmux_dump(void); 37 35 38 36 #endif
-4
arch/cris/include/asm/Kbuild
··· 1 1 2 - header-y += arch-v10/ 3 - header-y += arch-v32/ 4 - 5 - 6 2 generic-y += barrier.h 7 3 generic-y += clkdev.h 8 4 generic-y += cputime.h
+2 -2
arch/cris/include/uapi/asm/Kbuild
··· 1 1 # UAPI Header export list 2 2 include include/uapi/asm-generic/Kbuild.asm 3 3 4 - header-y += arch-v10/ 5 - header-y += arch-v32/ 4 + header-y += ../arch-v10/arch/ 5 + header-y += ../arch-v32/arch/ 6 6 header-y += auxvec.h 7 7 header-y += bitsperlong.h 8 8 header-y += byteorder.h
+5 -4
arch/cris/kernel/crisksyms.c
··· 47 47 EXPORT_SYMBOL(__ioremap); 48 48 EXPORT_SYMBOL(iounmap); 49 49 50 - /* Userspace access functions */ 51 - EXPORT_SYMBOL(__copy_user_zeroing); 52 - EXPORT_SYMBOL(__copy_user); 53 - 54 50 #undef memcpy 55 51 #undef memset 56 52 extern void * memset(void *, int, __kernel_size_t); 57 53 extern void * memcpy(void *, const void *, __kernel_size_t); 58 54 EXPORT_SYMBOL(memcpy); 59 55 EXPORT_SYMBOL(memset); 56 + #ifdef CONFIG_ETRAX_ARCH_V32 57 + #undef strcmp 58 + EXPORT_SYMBOL(strcmp); 59 + #endif 60 60 61 61 #ifdef CONFIG_ETRAX_FAST_TIMER 62 62 /* Fast timer functions */ ··· 66 66 EXPORT_SYMBOL(schedule_usleep); 67 67 #endif 68 68 EXPORT_SYMBOL(csum_partial); 69 + EXPORT_SYMBOL(csum_partial_copy_from_user);
+34 -27
arch/cris/kernel/traps.c
··· 14 14 15 15 #include <linux/init.h> 16 16 #include <linux/module.h> 17 + #include <linux/utsname.h> 18 + #ifdef CONFIG_KALLSYMS 19 + #include <linux/kallsyms.h> 20 + #endif 17 21 18 22 #include <asm/pgtable.h> 19 23 #include <asm/uaccess.h> ··· 38 34 39 35 void (*nmi_handler)(struct pt_regs *); 40 36 41 - void 42 - show_trace(unsigned long *stack) 37 + void show_trace(unsigned long *stack) 43 38 { 44 39 unsigned long addr, module_start, module_end; 45 40 extern char _stext, _etext; 46 41 int i; 47 42 48 - printk("\nCall Trace: "); 43 + pr_err("\nCall Trace: "); 49 44 50 45 i = 1; 51 46 module_start = VMALLOC_START; 52 47 module_end = VMALLOC_END; 53 48 54 - while (((long)stack & (THREAD_SIZE-1)) != 0) { 49 + while (((long)stack & (THREAD_SIZE - 1)) != 0) { 55 50 if (__get_user(addr, stack)) { 56 51 /* This message matches "failing address" marked 57 52 s390 in ksymoops, so lines containing it will 58 53 not be filtered out by ksymoops. */ 59 - printk("Failing address 0x%lx\n", (unsigned long)stack); 54 + pr_err("Failing address 0x%lx\n", (unsigned long)stack); 60 55 break; 61 56 } 62 57 stack++; ··· 71 68 if (((addr >= (unsigned long)&_stext) && 72 69 (addr <= (unsigned long)&_etext)) || 73 70 ((addr >= module_start) && (addr <= module_end))) { 71 + #ifdef CONFIG_KALLSYMS 72 + print_ip_sym(addr); 73 + #else 74 74 if (i && ((i % 8) == 0)) 75 - printk("\n "); 76 - printk("[<%08lx>] ", addr); 75 + pr_err("\n "); 76 + pr_err("[<%08lx>] ", addr); 77 77 i++; 78 + #endif 78 79 } 79 80 } 80 81 } ··· 118 111 119 112 stack = sp; 120 113 121 - printk("\nStack from %08lx:\n ", (unsigned long)stack); 114 + pr_err("\nStack from %08lx:\n ", (unsigned long)stack); 122 115 for (i = 0; i < kstack_depth_to_print; i++) { 123 116 if (((long)stack & (THREAD_SIZE-1)) == 0) 124 117 break; 125 118 if (i && ((i % 8) == 0)) 126 - printk("\n "); 119 + pr_err("\n "); 127 120 if (__get_user(addr, stack)) { 128 121 /* This message matches "failing address" marked 129 122 s390 in ksymoops, so lines containing it will 130 123 not be filtered out by ksymoops. */ 131 - printk("Failing address 0x%lx\n", (unsigned long)stack); 124 + pr_err("Failing address 0x%lx\n", (unsigned long)stack); 132 125 break; 133 126 } 134 127 stack++; 135 - printk("%08lx ", addr); 128 + pr_err("%08lx ", addr); 136 129 } 137 130 show_trace(sp); 138 131 } ··· 146 139 unsigned long *sp = (unsigned long *)rdusp(); 147 140 int i; 148 141 149 - printk("Stack dump [0x%08lx]:\n", (unsigned long)sp); 142 + pr_err("Stack dump [0x%08lx]:\n", (unsigned long)sp); 150 143 for (i = 0; i < 16; i++) 151 - printk("sp + %d: 0x%08lx\n", i*4, sp[i]); 144 + pr_err("sp + %d: 0x%08lx\n", i*4, sp[i]); 152 145 return 0; 153 146 } 154 147 #endif 155 148 156 - void 157 - set_nmi_handler(void (*handler)(struct pt_regs *)) 149 + void set_nmi_handler(void (*handler)(struct pt_regs *)) 158 150 { 159 151 nmi_handler = handler; 160 152 arch_enable_nmi(); 161 153 } 162 154 163 155 #ifdef CONFIG_DEBUG_NMI_OOPS 164 - void 165 - oops_nmi_handler(struct pt_regs *regs) 156 + void oops_nmi_handler(struct pt_regs *regs) 166 157 { 167 158 stop_watchdog(); 168 159 oops_in_progress = 1; 169 - printk("NMI!\n"); 160 + pr_err("NMI!\n"); 170 161 show_registers(regs); 171 162 oops_in_progress = 0; 163 + oops_exit(); 164 + pr_err("\n"); /* Flush mtdoops. */ 172 165 } 173 166 174 - static int __init 175 - oops_nmi_register(void) 167 + static int __init oops_nmi_register(void) 176 168 { 177 169 set_nmi_handler(oops_nmi_handler); 178 170 return 0; ··· 186 180 * similar to an Oops dump, and if the kernel is configured to be a nice 187 181 * doggy, then halt instead of reboot. 188 182 */ 189 - void 190 - watchdog_bite_hook(struct pt_regs *regs) 183 + void watchdog_bite_hook(struct pt_regs *regs) 191 184 { 192 185 #ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY 193 186 local_irq_disable(); ··· 201 196 } 202 197 203 198 /* This is normally the Oops function. */ 204 - void 205 - die_if_kernel(const char *str, struct pt_regs *regs, long err) 199 + void die_if_kernel(const char *str, struct pt_regs *regs, long err) 206 200 { 207 201 if (user_mode(regs)) 208 202 return; ··· 215 211 stop_watchdog(); 216 212 #endif 217 213 214 + oops_enter(); 218 215 handle_BUG(regs); 219 216 220 - printk("%s: %04lx\n", str, err & 0xffff); 217 + pr_err("Linux %s %s\n", utsname()->release, utsname()->version); 218 + pr_err("%s: %04lx\n", str, err & 0xffff); 221 219 222 220 show_registers(regs); 223 221 222 + oops_exit(); 224 223 oops_in_progress = 0; 224 + pr_err("\n"); /* Flush mtdoops. */ 225 225 226 226 #ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY 227 227 reset_watchdog(); ··· 233 225 do_exit(SIGSEGV); 234 226 } 235 227 236 - void __init 237 - trap_init(void) 228 + void __init trap_init(void) 238 229 { 239 230 /* Nothing needs to be done */ 240 231 }
+33 -5
arch/cris/mm/init.c
··· 11 11 #include <linux/gfp.h> 12 12 #include <linux/init.h> 13 13 #include <linux/bootmem.h> 14 + #include <linux/proc_fs.h> 15 + #include <linux/kcore.h> 14 16 #include <asm/tlb.h> 15 17 #include <asm/sections.h> 16 18 17 19 unsigned long empty_zero_page; 20 + EXPORT_SYMBOL(empty_zero_page); 18 21 19 - void __init 20 - mem_init(void) 22 + void __init mem_init(void) 21 23 { 22 24 BUG_ON(!mem_map); 23 25 ··· 33 31 mem_init_print_info(NULL); 34 32 } 35 33 36 - /* free the pages occupied by initialization code */ 34 + /* Free a range of init pages. Virtual addresses. */ 37 35 38 - void 39 - free_initmem(void) 36 + void free_init_pages(const char *what, unsigned long begin, unsigned long end) 37 + { 38 + unsigned long addr; 39 + 40 + for (addr = begin; addr < end; addr += PAGE_SIZE) { 41 + ClearPageReserved(virt_to_page(addr)); 42 + init_page_count(virt_to_page(addr)); 43 + free_page(addr); 44 + totalram_pages++; 45 + } 46 + 47 + printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); 48 + } 49 + 50 + /* Free the pages occupied by initialization code. */ 51 + 52 + void free_initmem(void) 40 53 { 41 54 free_initmem_default(-1); 42 55 } 56 + 57 + /* Free the pages occupied by initrd code. */ 58 + 59 + #ifdef CONFIG_BLK_DEV_INITRD 60 + void free_initrd_mem(unsigned long start, unsigned long end) 61 + { 62 + free_init_pages("initrd memory", 63 + start, 64 + end); 65 + } 66 + #endif
+2 -1
arch/cris/mm/ioremap.c
··· 76 76 * Must be freed with iounmap. 77 77 */ 78 78 79 - void __iomem *ioremap_nocache (unsigned long phys_addr, unsigned long size) 79 + void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size) 80 80 { 81 81 return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0); 82 82 } 83 + EXPORT_SYMBOL(ioremap_nocache); 83 84 84 85 void iounmap(volatile void __iomem *addr) 85 86 {
-2
scripts/headers.sh
··· 19 19 case ${arch} in 20 20 um) # no userspace export 21 21 ;; 22 - cris) # headers export are known broken 23 - ;; 24 22 *) 25 23 if [ -d ${srctree}/arch/${arch} ]; then 26 24 do_command $1 ${arch}