tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie:
"A bunch of fixes across drivers:

radeon:
disable two ended allocation for now, it breaks some stuff

amdkfd:
misc fixes

nouveau:
fix irq loop problem, add basic support for GM206 (new hw)

i915:
fix some WARNs people were seeing

exynos:
fix some iommu interactions causing boot failures"

* git://people.freedesktop.org/~airlied/linux:
drm/radeon: drop ttm two ended allocation
drm/exynos: fix the initialization order in FIMD
drm/exynos: fix typo config name correctly.
drm/exynos: Check for NULL dereference of crtc
drm/exynos: IS_ERR() vs NULL bug
drm/exynos: remove unused files
drm/i915: Make sure the primary plane is enabled before reading out the fb state
drm/nouveau/bios: fix i2c table parsing for dcb 4.1
drm/nouveau/device/gm100: Basic GM206 bring up (as copy of GM204)
drm/nouveau/device: post write to NV_PMC_BOOT_1 when flipping endian switch
drm/nouveau/gr/gf100: fix some accidental or'ing of buffer addresses
drm/nouveau/fifo/nv04: remove the loop from the interrupt handler
drm/radeon: Changing number of compute pipe lines
drm/amdkfd: Fix SDMA queue init. in non-HWS mode
drm/amdkfd: destroy mqd when destroying kernel queue
drm/i915: Ensure plane->state->fb stays in sync with plane->fb

Linus Torvalds 97448d5b bb8ef2fb

+167 -380
+9 -1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
··· 645 645 pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id); 646 646 pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id); 647 647 648 + init_sdma_vm(dqm, q, qpd); 648 649 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, 649 650 &q->gart_mqd_addr, &q->properties); 650 651 if (retval != 0) { ··· 653 652 return retval; 654 653 } 655 654 656 - init_sdma_vm(dqm, q, qpd); 655 + retval = mqd->load_mqd(mqd, q->mqd, 0, 656 + 0, NULL); 657 + if (retval != 0) { 658 + deallocate_sdma_queue(dqm, q->sdma_id); 659 + mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); 660 + return retval; 661 + } 662 + 657 663 return 0; 658 664 } 659 665
+13 -9
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
··· 44 44 BUG_ON(!kq || !dev); 45 45 BUG_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ); 46 46 47 - pr_debug("kfd: In func %s initializing queue type %d size %d\n", 47 + pr_debug("amdkfd: In func %s initializing queue type %d size %d\n", 48 48 __func__, KFD_QUEUE_TYPE_HIQ, queue_size); 49 49 50 50 nop.opcode = IT_NOP; ··· 69 69 70 70 prop.doorbell_ptr = kfd_get_kernel_doorbell(dev, &prop.doorbell_off); 71 71 72 - if (prop.doorbell_ptr == NULL) 72 + if (prop.doorbell_ptr == NULL) { 73 + pr_err("amdkfd: error init doorbell"); 73 74 goto err_get_kernel_doorbell; 75 + } 74 76 75 77 retval = kfd_gtt_sa_allocate(dev, queue_size, &kq->pq); 76 - if (retval != 0) 78 + if (retval != 0) { 79 + pr_err("amdkfd: error init pq queues size (%d)\n", queue_size); 77 80 goto err_pq_allocate_vidmem; 81 + } 78 82 79 83 kq->pq_kernel_addr = kq->pq->cpu_ptr; 80 84 kq->pq_gpu_addr = kq->pq->gpu_addr; ··· 169 165 err_eop_allocate_vidmem: 170 166 kfd_gtt_sa_free(dev, kq->pq); 171 167 err_pq_allocate_vidmem: 172 - pr_err("kfd: error init pq\n"); 173 168 kfd_release_kernel_doorbell(dev, prop.doorbell_ptr); 174 169 err_get_kernel_doorbell: 175 - pr_err("kfd: error init doorbell"); 176 170 return false; 177 171 178 172 } ··· 188 186 kq->queue->queue); 189 187 else if (kq->queue->properties.type == KFD_QUEUE_TYPE_DIQ) 190 188 kfd_gtt_sa_free(kq->dev, kq->fence_mem_obj); 189 + 190 + kq->mqd->uninit_mqd(kq->mqd, kq->queue->mqd, kq->queue->mqd_mem_obj); 191 191 192 192 kfd_gtt_sa_free(kq->dev, kq->rptr_mem); 193 193 kfd_gtt_sa_free(kq->dev, kq->wptr_mem); ··· 215 211 queue_address = (unsigned int *)kq->pq_kernel_addr; 216 212 queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t); 217 213 218 - pr_debug("kfd: In func %s\nrptr: %d\nwptr: %d\nqueue_address 0x%p\n", 214 + pr_debug("amdkfd: In func %s\nrptr: %d\nwptr: %d\nqueue_address 0x%p\n", 219 215 __func__, rptr, wptr, queue_address); 220 216 221 217 available_size = (rptr - 1 - wptr + queue_size_dwords) % ··· 300 296 } 301 297 302 298 if (kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE) == false) { 303 - pr_err("kfd: failed to init kernel queue\n"); 299 + pr_err("amdkfd: failed to init kernel queue\n"); 304 300 kfree(kq); 305 301 return NULL; 306 302 } ··· 323 319 324 320 BUG_ON(!dev); 325 321 326 - pr_err("kfd: starting kernel queue test\n"); 322 + pr_err("amdkfd: starting kernel queue test\n"); 327 323 328 324 kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); 329 325 BUG_ON(!kq); ··· 334 330 buffer[i] = kq->nop_packet; 335 331 kq->ops.submit_packet(kq); 336 332 337 - pr_err("kfd: ending kernel queue test\n"); 333 + pr_err("amdkfd: ending kernel queue test\n"); 338 334 } 339 335 340 336
+1 -1
drivers/gpu/drm/exynos/Kconfig
··· 50 50 51 51 config DRM_EXYNOS_DP 52 52 bool "EXYNOS DRM DP driver support" 53 - depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) 53 + depends on (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) && ARCH_EXYNOS && (DRM_PTN3460=n || DRM_PTN3460=y || DRM_PTN3460=DRM_EXYNOS) 54 54 default DRM_EXYNOS 55 55 select DRM_PANEL 56 56 help
+2 -2
drivers/gpu/drm/exynos/exynos7_drm_decon.c
··· 888 888 of_node_put(i80_if_timings); 889 889 890 890 ctx->regs = of_iomap(dev->of_node, 0); 891 - if (IS_ERR(ctx->regs)) { 892 - ret = PTR_ERR(ctx->regs); 891 + if (!ctx->regs) { 892 + ret = -ENOMEM; 893 893 goto err_del_component; 894 894 } 895 895
-245
drivers/gpu/drm/exynos/exynos_drm_connector.c
··· 1 - /* 2 - * Copyright (c) 2011 Samsung Electronics Co., Ltd. 3 - * Authors: 4 - * Inki Dae <inki.dae@samsung.com> 5 - * Joonyoung Shim <jy0922.shim@samsung.com> 6 - * Seung-Woo Kim <sw0312.kim@samsung.com> 7 - * 8 - * This program is free software; you can redistribute it and/or modify it 9 - * under the terms of the GNU General Public License as published by the 10 - * Free Software Foundation; either version 2 of the License, or (at your 11 - * option) any later version. 12 - */ 13 - 14 - #include <drm/drmP.h> 15 - #include <drm/drm_crtc_helper.h> 16 - 17 - #include <drm/exynos_drm.h> 18 - #include "exynos_drm_drv.h" 19 - #include "exynos_drm_encoder.h" 20 - #include "exynos_drm_connector.h" 21 - 22 - #define to_exynos_connector(x) container_of(x, struct exynos_drm_connector,\ 23 - drm_connector) 24 - 25 - struct exynos_drm_connector { 26 - struct drm_connector drm_connector; 27 - uint32_t encoder_id; 28 - struct exynos_drm_display *display; 29 - }; 30 - 31 - static int exynos_drm_connector_get_modes(struct drm_connector *connector) 32 - { 33 - struct exynos_drm_connector *exynos_connector = 34 - to_exynos_connector(connector); 35 - struct exynos_drm_display *display = exynos_connector->display; 36 - struct edid *edid = NULL; 37 - unsigned int count = 0; 38 - int ret; 39 - 40 - /* 41 - * if get_edid() exists then get_edid() callback of hdmi side 42 - * is called to get edid data through i2c interface else 43 - * get timing from the FIMD driver(display controller). 44 - * 45 - * P.S. in case of lcd panel, count is always 1 if success 46 - * because lcd panel has only one mode. 47 - */ 48 - if (display->ops->get_edid) { 49 - edid = display->ops->get_edid(display, connector); 50 - if (IS_ERR_OR_NULL(edid)) { 51 - ret = PTR_ERR(edid); 52 - edid = NULL; 53 - DRM_ERROR("Panel operation get_edid failed %d\n", ret); 54 - goto out; 55 - } 56 - 57 - count = drm_add_edid_modes(connector, edid); 58 - if (!count) { 59 - DRM_ERROR("Add edid modes failed %d\n", count); 60 - goto out; 61 - } 62 - 63 - drm_mode_connector_update_edid_property(connector, edid); 64 - } else { 65 - struct exynos_drm_panel_info *panel; 66 - struct drm_display_mode *mode = drm_mode_create(connector->dev); 67 - if (!mode) { 68 - DRM_ERROR("failed to create a new display mode.\n"); 69 - return 0; 70 - } 71 - 72 - if (display->ops->get_panel) 73 - panel = display->ops->get_panel(display); 74 - else { 75 - drm_mode_destroy(connector->dev, mode); 76 - return 0; 77 - } 78 - 79 - drm_display_mode_from_videomode(&panel->vm, mode); 80 - mode->width_mm = panel->width_mm; 81 - mode->height_mm = panel->height_mm; 82 - connector->display_info.width_mm = mode->width_mm; 83 - connector->display_info.height_mm = mode->height_mm; 84 - 85 - mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 86 - drm_mode_set_name(mode); 87 - drm_mode_probed_add(connector, mode); 88 - 89 - count = 1; 90 - } 91 - 92 - out: 93 - kfree(edid); 94 - return count; 95 - } 96 - 97 - static int exynos_drm_connector_mode_valid(struct drm_connector *connector, 98 - struct drm_display_mode *mode) 99 - { 100 - struct exynos_drm_connector *exynos_connector = 101 - to_exynos_connector(connector); 102 - struct exynos_drm_display *display = exynos_connector->display; 103 - int ret = MODE_BAD; 104 - 105 - DRM_DEBUG_KMS("%s\n", __FILE__); 106 - 107 - if (display->ops->check_mode) 108 - if (!display->ops->check_mode(display, mode)) 109 - ret = MODE_OK; 110 - 111 - return ret; 112 - } 113 - 114 - static struct drm_encoder *exynos_drm_best_encoder( 115 - struct drm_connector *connector) 116 - { 117 - struct drm_device *dev = connector->dev; 118 - struct exynos_drm_connector *exynos_connector = 119 - to_exynos_connector(connector); 120 - return drm_encoder_find(dev, exynos_connector->encoder_id); 121 - } 122 - 123 - static struct drm_connector_helper_funcs exynos_connector_helper_funcs = { 124 - .get_modes = exynos_drm_connector_get_modes, 125 - .mode_valid = exynos_drm_connector_mode_valid, 126 - .best_encoder = exynos_drm_best_encoder, 127 - }; 128 - 129 - static int exynos_drm_connector_fill_modes(struct drm_connector *connector, 130 - unsigned int max_width, unsigned int max_height) 131 - { 132 - struct exynos_drm_connector *exynos_connector = 133 - to_exynos_connector(connector); 134 - struct exynos_drm_display *display = exynos_connector->display; 135 - unsigned int width, height; 136 - 137 - width = max_width; 138 - height = max_height; 139 - 140 - /* 141 - * if specific driver want to find desired_mode using maxmum 142 - * resolution then get max width and height from that driver. 143 - */ 144 - if (display->ops->get_max_resol) 145 - display->ops->get_max_resol(display, &width, &height); 146 - 147 - return drm_helper_probe_single_connector_modes(connector, width, 148 - height); 149 - } 150 - 151 - /* get detection status of display device. */ 152 - static enum drm_connector_status 153 - exynos_drm_connector_detect(struct drm_connector *connector, bool force) 154 - { 155 - struct exynos_drm_connector *exynos_connector = 156 - to_exynos_connector(connector); 157 - struct exynos_drm_display *display = exynos_connector->display; 158 - enum drm_connector_status status = connector_status_disconnected; 159 - 160 - if (display->ops->is_connected) { 161 - if (display->ops->is_connected(display)) 162 - status = connector_status_connected; 163 - else 164 - status = connector_status_disconnected; 165 - } 166 - 167 - return status; 168 - } 169 - 170 - static void exynos_drm_connector_destroy(struct drm_connector *connector) 171 - { 172 - struct exynos_drm_connector *exynos_connector = 173 - to_exynos_connector(connector); 174 - 175 - drm_connector_unregister(connector); 176 - drm_connector_cleanup(connector); 177 - kfree(exynos_connector); 178 - } 179 - 180 - static struct drm_connector_funcs exynos_connector_funcs = { 181 - .dpms = drm_helper_connector_dpms, 182 - .fill_modes = exynos_drm_connector_fill_modes, 183 - .detect = exynos_drm_connector_detect, 184 - .destroy = exynos_drm_connector_destroy, 185 - }; 186 - 187 - struct drm_connector *exynos_drm_connector_create(struct drm_device *dev, 188 - struct drm_encoder *encoder) 189 - { 190 - struct exynos_drm_connector *exynos_connector; 191 - struct exynos_drm_display *display = exynos_drm_get_display(encoder); 192 - struct drm_connector *connector; 193 - int type; 194 - int err; 195 - 196 - exynos_connector = kzalloc(sizeof(*exynos_connector), GFP_KERNEL); 197 - if (!exynos_connector) 198 - return NULL; 199 - 200 - connector = &exynos_connector->drm_connector; 201 - 202 - switch (display->type) { 203 - case EXYNOS_DISPLAY_TYPE_HDMI: 204 - type = DRM_MODE_CONNECTOR_HDMIA; 205 - connector->interlace_allowed = true; 206 - connector->polled = DRM_CONNECTOR_POLL_HPD; 207 - break; 208 - case EXYNOS_DISPLAY_TYPE_VIDI: 209 - type = DRM_MODE_CONNECTOR_VIRTUAL; 210 - connector->polled = DRM_CONNECTOR_POLL_HPD; 211 - break; 212 - default: 213 - type = DRM_MODE_CONNECTOR_Unknown; 214 - break; 215 - } 216 - 217 - drm_connector_init(dev, connector, &exynos_connector_funcs, type); 218 - drm_connector_helper_add(connector, &exynos_connector_helper_funcs); 219 - 220 - err = drm_connector_register(connector); 221 - if (err) 222 - goto err_connector; 223 - 224 - exynos_connector->encoder_id = encoder->base.id; 225 - exynos_connector->display = display; 226 - connector->dpms = DRM_MODE_DPMS_OFF; 227 - connector->encoder = encoder; 228 - 229 - err = drm_mode_connector_attach_encoder(connector, encoder); 230 - if (err) { 231 - DRM_ERROR("failed to attach a connector to a encoder\n"); 232 - goto err_sysfs; 233 - } 234 - 235 - DRM_DEBUG_KMS("connector has been created\n"); 236 - 237 - return connector; 238 - 239 - err_sysfs: 240 - drm_connector_unregister(connector); 241 - err_connector: 242 - drm_connector_cleanup(connector); 243 - kfree(exynos_connector); 244 - return NULL; 245 - }
-20
drivers/gpu/drm/exynos/exynos_drm_connector.h
··· 1 - /* 2 - * Copyright (c) 2011 Samsung Electronics Co., Ltd. 3 - * Authors: 4 - * Inki Dae <inki.dae@samsung.com> 5 - * Joonyoung Shim <jy0922.shim@samsung.com> 6 - * Seung-Woo Kim <sw0312.kim@samsung.com> 7 - * 8 - * This program is free software; you can redistribute it and/or modify it 9 - * under the terms of the GNU General Public License as published by the 10 - * Free Software Foundation; either version 2 of the License, or (at your 11 - * option) any later version. 12 - */ 13 - 14 - #ifndef _EXYNOS_DRM_CONNECTOR_H_ 15 - #define _EXYNOS_DRM_CONNECTOR_H_ 16 - 17 - struct drm_connector *exynos_drm_connector_create(struct drm_device *dev, 18 - struct drm_encoder *encoder); 19 - 20 - #endif
+11 -18
drivers/gpu/drm/exynos/exynos_drm_fimd.c
··· 284 284 } 285 285 } 286 286 287 - static int fimd_ctx_initialize(struct fimd_context *ctx, 287 + static int fimd_iommu_attach_devices(struct fimd_context *ctx, 288 288 struct drm_device *drm_dev) 289 289 { 290 - struct exynos_drm_private *priv; 291 - priv = drm_dev->dev_private; 292 - 293 - ctx->drm_dev = drm_dev; 294 - ctx->pipe = priv->pipe++; 295 290 296 291 /* attach this sub driver to iommu mapping if supported. */ 297 292 if (is_drm_iommu_supported(ctx->drm_dev)) { ··· 308 313 return 0; 309 314 } 310 315 311 - static void fimd_ctx_remove(struct fimd_context *ctx) 316 + static void fimd_iommu_detach_devices(struct fimd_context *ctx) 312 317 { 313 318 /* detach this sub driver from iommu mapping if supported. */ 314 319 if (is_drm_iommu_supported(ctx->drm_dev)) ··· 1051 1056 { 1052 1057 struct fimd_context *ctx = dev_get_drvdata(dev); 1053 1058 struct drm_device *drm_dev = data; 1059 + struct exynos_drm_private *priv = drm_dev->dev_private; 1054 1060 int ret; 1055 1061 1056 - ret = fimd_ctx_initialize(ctx, drm_dev); 1057 - if (ret) { 1058 - DRM_ERROR("fimd_ctx_initialize failed.\n"); 1059 - return ret; 1060 - } 1062 + ctx->drm_dev = drm_dev; 1063 + ctx->pipe = priv->pipe++; 1061 1064 1062 1065 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe, 1063 1066 EXYNOS_DISPLAY_TYPE_LCD, 1064 1067 &fimd_crtc_ops, ctx); 1065 - if (IS_ERR(ctx->crtc)) { 1066 - fimd_ctx_remove(ctx); 1067 - return PTR_ERR(ctx->crtc); 1068 - } 1069 1068 1070 1069 if (ctx->display) 1071 1070 exynos_drm_create_enc_conn(drm_dev, ctx->display); 1071 + 1072 + ret = fimd_iommu_attach_devices(ctx, drm_dev); 1073 + if (ret) 1074 + return ret; 1072 1075 1073 1076 return 0; 1074 1077 ··· 1079 1086 1080 1087 fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); 1081 1088 1089 + fimd_iommu_detach_devices(ctx); 1090 + 1082 1091 if (ctx->display) 1083 1092 exynos_dpi_remove(ctx->display); 1084 - 1085 - fimd_ctx_remove(ctx); 1086 1093 } 1087 1094 1088 1095 static const struct component_ops fimd_component_ops = {
+1 -1
drivers/gpu/drm/exynos/exynos_drm_plane.c
··· 175 175 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); 176 176 struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(plane->crtc); 177 177 178 - if (exynos_crtc->ops->win_disable) 178 + if (exynos_crtc && exynos_crtc->ops->win_disable) 179 179 exynos_crtc->ops->win_disable(exynos_crtc, 180 180 exynos_plane->zpos); 181 181
+28 -4
drivers/gpu/drm/i915/intel_display.c
··· 37 37 #include <drm/i915_drm.h> 38 38 #include "i915_drv.h" 39 39 #include "i915_trace.h" 40 + #include <drm/drm_atomic.h> 40 41 #include <drm/drm_atomic_helper.h> 41 42 #include <drm/drm_dp_helper.h> 42 43 #include <drm/drm_crtc_helper.h> ··· 2417 2416 return false; 2418 2417 } 2419 2418 2419 + /* Update plane->state->fb to match plane->fb after driver-internal updates */ 2420 + static void 2421 + update_state_fb(struct drm_plane *plane) 2422 + { 2423 + if (plane->fb != plane->state->fb) 2424 + drm_atomic_set_fb_for_plane(plane->state, plane->fb); 2425 + } 2426 + 2420 2427 static void 2421 2428 intel_find_plane_obj(struct intel_crtc *intel_crtc, 2422 2429 struct intel_initial_plane_config *plane_config) ··· 2471 2462 break; 2472 2463 } 2473 2464 } 2465 + 2466 + update_state_fb(intel_crtc->base.primary); 2474 2467 } 2475 2468 2476 2469 static void i9xx_update_primary_plane(struct drm_crtc *crtc, ··· 6613 6602 struct drm_framebuffer *fb; 6614 6603 struct intel_framebuffer *intel_fb; 6615 6604 6605 + val = I915_READ(DSPCNTR(plane)); 6606 + if (!(val & DISPLAY_PLANE_ENABLE)) 6607 + return; 6608 + 6616 6609 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 6617 6610 if (!intel_fb) { 6618 6611 DRM_DEBUG_KMS("failed to alloc fb\n"); ··· 6624 6609 } 6625 6610 6626 6611 fb = &intel_fb->base; 6627 - 6628 - val = I915_READ(DSPCNTR(plane)); 6629 6612 6630 6613 if (INTEL_INFO(dev)->gen >= 4) 6631 6614 if (val & DISPPLANE_TILED) ··· 6663 6650 plane_config->size); 6664 6651 6665 6652 crtc->base.primary->fb = fb; 6653 + update_state_fb(crtc->base.primary); 6666 6654 } 6667 6655 6668 6656 static void chv_crtc_clock_get(struct intel_crtc *crtc, ··· 7657 7643 fb = &intel_fb->base; 7658 7644 7659 7645 val = I915_READ(PLANE_CTL(pipe, 0)); 7646 + if (!(val & PLANE_CTL_ENABLE)) 7647 + goto error; 7648 + 7660 7649 if (val & PLANE_CTL_TILED_MASK) 7661 7650 plane_config->tiling = I915_TILING_X; 7662 7651 ··· 7704 7687 plane_config->size); 7705 7688 7706 7689 crtc->base.primary->fb = fb; 7690 + update_state_fb(crtc->base.primary); 7707 7691 return; 7708 7692 7709 7693 error: ··· 7748 7730 struct drm_framebuffer *fb; 7749 7731 struct intel_framebuffer *intel_fb; 7750 7732 7733 + val = I915_READ(DSPCNTR(pipe)); 7734 + if (!(val & DISPLAY_PLANE_ENABLE)) 7735 + return; 7736 + 7751 7737 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 7752 7738 if (!intel_fb) { 7753 7739 DRM_DEBUG_KMS("failed to alloc fb\n"); ··· 7759 7737 } 7760 7738 7761 7739 fb = &intel_fb->base; 7762 - 7763 - val = I915_READ(DSPCNTR(pipe)); 7764 7740 7765 7741 if (INTEL_INFO(dev)->gen >= 4) 7766 7742 if (val & DISPPLANE_TILED) ··· 7798 7778 plane_config->size); 7799 7779 7800 7780 crtc->base.primary->fb = fb; 7781 + update_state_fb(crtc->base.primary); 7801 7782 } 7802 7783 7803 7784 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, ··· 9837 9816 drm_gem_object_reference(&obj->base); 9838 9817 9839 9818 crtc->primary->fb = fb; 9819 + update_state_fb(crtc->primary); 9840 9820 9841 9821 work->pending_flip_obj = obj; 9842 9822 ··· 9906 9884 cleanup_pending: 9907 9885 atomic_dec(&intel_crtc->unpin_work_count); 9908 9886 crtc->primary->fb = old_fb; 9887 + update_state_fb(crtc->primary); 9909 9888 drm_gem_object_unreference(&work->old_fb_obj->base); 9910 9889 drm_gem_object_unreference(&obj->base); 9911 9890 mutex_unlock(&dev->struct_mutex); ··· 13741 13718 to_intel_crtc(c)->pipe); 13742 13719 drm_framebuffer_unreference(c->primary->fb); 13743 13720 c->primary->fb = NULL; 13721 + update_state_fb(c->primary); 13744 13722 } 13745 13723 } 13746 13724 mutex_unlock(&dev->struct_mutex);
+4 -2
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
··· 340 340 341 341 /* switch mmio to cpu's native endianness */ 342 342 #ifndef __BIG_ENDIAN 343 - if (ioread32_native(map + 0x000004) != 0x00000000) 343 + if (ioread32_native(map + 0x000004) != 0x00000000) { 344 344 #else 345 - if (ioread32_native(map + 0x000004) == 0x00000000) 345 + if (ioread32_native(map + 0x000004) == 0x00000000) { 346 346 #endif 347 347 iowrite32_native(0x01000001, map + 0x000004); 348 + ioread32_native(map); 349 + } 348 350 349 351 /* read boot0 and strapping information */ 350 352 boot0 = ioread32_native(map + 0x000000);
+43
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
··· 142 142 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; 143 143 #endif 144 144 break; 145 + case 0x126: 146 + device->cname = "GM206"; 147 + device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; 148 + device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; 149 + device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; 150 + device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; 151 + #if 0 152 + /* looks to be some non-trivial changes */ 153 + device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass; 154 + /* priv ring says no to 0x10eb14 writes */ 155 + device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; 156 + #endif 157 + device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; 158 + device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass; 159 + device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; 160 + device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; 161 + device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; 162 + device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; 163 + device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; 164 + device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 165 + device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 166 + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; 167 + device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 168 + device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; 169 + #if 0 170 + device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 171 + #endif 172 + device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; 173 + #if 0 174 + device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; 175 + device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; 176 + device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; 177 + #endif 178 + device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; 179 + #if 0 180 + device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; 181 + device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; 182 + device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; 183 + device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; 184 + device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; 185 + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; 186 + #endif 187 + break; 145 188 default: 146 189 nv_fatal(device, "unknown Maxwell chipset\n"); 147 190 return -EINVAL;
+43 -58
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
··· 502 502 { 503 503 struct nvkm_device *device = nv_device(subdev); 504 504 struct nv04_fifo_priv *priv = (void *)subdev; 505 - uint32_t status, reassign; 506 - int cnt = 0; 505 + u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0); 506 + u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask; 507 + u32 reassign, chid, get, sem; 507 508 508 509 reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; 509 - while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) { 510 - uint32_t chid, get; 510 + nv_wr32(priv, NV03_PFIFO_CACHES, 0); 511 511 512 - nv_wr32(priv, NV03_PFIFO_CACHES, 0); 512 + chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; 513 + get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); 513 514 514 - chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; 515 - get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); 516 - 517 - if (status & NV_PFIFO_INTR_CACHE_ERROR) { 518 - nv04_fifo_cache_error(device, priv, chid, get); 519 - status &= ~NV_PFIFO_INTR_CACHE_ERROR; 520 - } 521 - 522 - if (status & NV_PFIFO_INTR_DMA_PUSHER) { 523 - nv04_fifo_dma_pusher(device, priv, chid); 524 - status &= ~NV_PFIFO_INTR_DMA_PUSHER; 525 - } 526 - 527 - if (status & NV_PFIFO_INTR_SEMAPHORE) { 528 - uint32_t sem; 529 - 530 - status &= ~NV_PFIFO_INTR_SEMAPHORE; 531 - nv_wr32(priv, NV03_PFIFO_INTR_0, 532 - NV_PFIFO_INTR_SEMAPHORE); 533 - 534 - sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); 535 - nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); 536 - 537 - nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); 538 - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); 539 - } 540 - 541 - if (device->card_type == NV_50) { 542 - if (status & 0x00000010) { 543 - status &= ~0x00000010; 544 - nv_wr32(priv, 0x002100, 0x00000010); 545 - } 546 - 547 - if (status & 0x40000000) { 548 - nv_wr32(priv, 0x002100, 0x40000000); 549 - nvkm_fifo_uevent(&priv->base); 550 - status &= ~0x40000000; 551 - } 552 - } 553 - 554 - if (status) { 555 - nv_warn(priv, "unknown intr 0x%08x, ch %d\n", 556 - status, chid); 557 - nv_wr32(priv, NV03_PFIFO_INTR_0, status); 558 - status = 0; 559 - } 560 - 561 - nv_wr32(priv, NV03_PFIFO_CACHES, reassign); 515 + if (stat & NV_PFIFO_INTR_CACHE_ERROR) { 516 + nv04_fifo_cache_error(device, priv, chid, get); 517 + stat &= ~NV_PFIFO_INTR_CACHE_ERROR; 562 518 } 563 519 564 - if (status) { 565 - nv_error(priv, "still angry after %d spins, halt\n", cnt); 566 - nv_wr32(priv, 0x002140, 0); 567 - nv_wr32(priv, 0x000140, 0); 520 + if (stat & NV_PFIFO_INTR_DMA_PUSHER) { 521 + nv04_fifo_dma_pusher(device, priv, chid); 522 + stat &= ~NV_PFIFO_INTR_DMA_PUSHER; 568 523 } 569 524 570 - nv_wr32(priv, 0x000100, 0x00000100); 525 + if (stat & NV_PFIFO_INTR_SEMAPHORE) { 526 + stat &= ~NV_PFIFO_INTR_SEMAPHORE; 527 + nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); 528 + 529 + sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); 530 + nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); 531 + 532 + nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); 533 + nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); 534 + } 535 + 536 + if (device->card_type == NV_50) { 537 + if (stat & 0x00000010) { 538 + stat &= ~0x00000010; 539 + nv_wr32(priv, 0x002100, 0x00000010); 540 + } 541 + 542 + if (stat & 0x40000000) { 543 + nv_wr32(priv, 0x002100, 0x40000000); 544 + nvkm_fifo_uevent(&priv->base); 545 + stat &= ~0x40000000; 546 + } 547 + } 548 + 549 + if (stat) { 550 + nv_warn(priv, "unknown intr 0x%08x\n", stat); 551 + nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); 552 + nv_wr32(priv, NV03_PFIFO_INTR_0, stat); 553 + } 554 + 555 + nv_wr32(priv, NV03_PFIFO_CACHES, reassign); 571 556 } 572 557 573 558 static int
+2 -2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
··· 1032 1032 const int s = 8; 1033 1033 const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); 1034 1034 mmio_refn(info, 0x408004, 0x00000000, s, b); 1035 - mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); 1035 + mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); 1036 1036 mmio_refn(info, 0x418808, 0x00000000, s, b); 1037 - mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); 1037 + mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s)); 1038 1038 } 1039 1039 1040 1040 void
+2 -2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
··· 851 851 const int s = 8; 852 852 const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); 853 853 mmio_refn(info, 0x408004, 0x00000000, s, b); 854 - mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); 854 + mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); 855 855 mmio_refn(info, 0x418808, 0x00000000, s, b); 856 - mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); 856 + mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s)); 857 857 mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); 858 858 } 859 859
+2 -2
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
··· 871 871 const int s = 8; 872 872 const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); 873 873 mmio_refn(info, 0x408004, 0x00000000, s, b); 874 - mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); 874 + mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); 875 875 mmio_refn(info, 0x418e24, 0x00000000, s, b); 876 - mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b); 876 + mmio_wr32(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s)); 877 877 mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); 878 878 } 879 879
+5 -1
drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.c
··· 74 74 u16 ent = dcb_i2c_entry(bios, idx, &ver, &len); 75 75 if (ent) { 76 76 if (ver >= 0x41) { 77 - if (!(nv_ro32(bios, ent) & 0x80000000)) 77 + u32 ent_value = nv_ro32(bios, ent); 78 + u8 i2c_port = (ent_value >> 27) & 0x1f; 79 + u8 dpaux_port = (ent_value >> 22) & 0x1f; 80 + /* value 0x1f means unused according to DCB 4.x spec */ 81 + if (i2c_port == 0x1f && dpaux_port == 0x1f) 78 82 info->type = DCB_I2C_UNUSED; 79 83 else 80 84 info->type = DCB_I2C_PMGR;
+1 -1
drivers/gpu/drm/radeon/radeon_kfd.c
··· 153 153 .compute_vmid_bitmap = 0xFF00, 154 154 155 155 .first_compute_pipe = 1, 156 - .compute_pipe_count = 8 - 1, 156 + .compute_pipe_count = 4 - 1, 157 157 }; 158 158 159 159 radeon_doorbell_get_kfd_info(rdev,
-11
drivers/gpu/drm/radeon/radeon_object.c
··· 173 173 else 174 174 rbo->placements[i].lpfn = 0; 175 175 } 176 - 177 - /* 178 - * Use two-ended allocation depending on the buffer size to 179 - * improve fragmentation quality. 180 - * 512kb was measured as the most optimal number. 181 - */ 182 - if (rbo->tbo.mem.size > 512 * 1024) { 183 - for (i = 0; i < c; i++) { 184 - rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN; 185 - } 186 - } 187 176 } 188 177 189 178 int radeon_bo_create(struct radeon_device *rdev,