tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
"People are back from the holiday breaks, and it shows. Here are a
bunch of fixes for a number of platforms:
- A couple of small fixes for Nomadik
- A larger set of changes for kirkwood/mvebu
- uart driver selection, dt clocks, gpio-poweroff fixups, a few
__init annotation fixes and some error handling improvement in
their xor dma driver.
- i.MX had a couple of minor fixes (and a critical one for flexcan2
clock setup)
- MXS has a small board fix and a framebuffer bugfix
- A set of fixes for Samsung Exynos, fixing default bootargs and some
Exynos5440 clock issues
- A set of OMAP changes including PM fixes and a few sparse warning
fixups

All in all a bit more positive code delta than we'd ideally want to
see here, mostly from the OMAP PM changes, but nothing overly crazy."

* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
ARM: clps711x: Fix bad merge of clockevents setup
ARM: highbank: save and restore L2 cache and GIC on suspend
ARM: highbank: add a power request clear
ARM: highbank: fix secondary boot and hotplug
ARM: highbank: fix typos with hignbank in power request functions
ARM: dts: fix highbank cpu mpidr values
ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
ARM: mx5: Fix MX53 flexcan2 clock
ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
pinctrl: mvebu: make pdma clock on dove mandatory
ARM: Dove: Add pinctrl clock to DT
dma: mv_xor: fix error handling for clocks
dma: mv_xor: fix error handling of mv_xor_channel_add()
arm: mvebu: Add missing ; for cpu node.
arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces
arm: mvebu: Armada XP MV78230 has two cores, not one
clk: mvebu: Remove inappropriate __init tagging
ARM: Kirkwood: Use fixed-regulator instead of board gpio call
ARM: Kirkwood: Fix missing sdio clock
ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers
...

Linus Torvalds 974b3358 ca5c8a4c

+351 -183
-5
Documentation/devicetree/bindings/clock/imx23-clock.txt
··· 60 60 compatible = "fsl,imx23-clkctrl"; 61 61 reg = <0x80040000 0x2000>; 62 62 #clock-cells = <1>; 63 - clock-output-names = 64 - ... 65 - "uart", /* 32 */ 66 - ... 67 - "end_of_list"; 68 63 }; 69 64 70 65 auart0: serial@8006c000 {
-4
Documentation/devicetree/bindings/clock/imx25-clock.txt
··· 146 146 compatible = "fsl,imx25-ccm"; 147 147 reg = <0x53f80000 0x4000>; 148 148 interrupts = <31>; 149 - clock-output-names = ... 150 - "uart_ipg", 151 - "uart_serial", 152 - ...; 153 149 }; 154 150 155 151 uart1: serial@43f90000 {
-5
Documentation/devicetree/bindings/clock/imx28-clock.txt
··· 83 83 compatible = "fsl,imx28-clkctrl"; 84 84 reg = <0x80040000 0x2000>; 85 85 #clock-cells = <1>; 86 - clock-output-names = 87 - ... 88 - "uart", /* 45 */ 89 - ... 90 - "end_of_list"; 91 86 }; 92 87 93 88 auart0: serial@8006a000 {
-4
Documentation/devicetree/bindings/clock/imx6q-clock.txt
··· 211 211 reg = <0x020c4000 0x4000>; 212 212 interrupts = <0 87 0x04 0 88 0x04>; 213 213 #clock-cells = <1>; 214 - clock-output-names = ... 215 - "uart_ipg", 216 - "uart_serial", 217 - ...; 218 214 }; 219 215 220 216 uart1: serial@02020000 {
+17 -3
Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
··· 1 - GPIO line that should be set high/low to power off a device 1 + Driver a GPIO line that can be used to turn the power off. 2 + 3 + The driver supports both level triggered and edge triggered power off. 4 + At driver load time, the driver will request the given gpio line and 5 + install a pm_power_off handler. If the optional properties 'input' is 6 + not found, the GPIO line will be driven in the inactive 7 + state. Otherwise its configured as an input. 8 + 9 + When the pm_power_off is called, the gpio is configured as an output, 10 + and drive active, so triggering a level triggered power off 11 + condition. This will also cause an inactive->active edge condition, so 12 + triggering positive edge triggered power off. After a delay of 100ms, 13 + the GPIO is set to inactive, thus causing an active->inactive edge, 14 + triggering negative edge triggered power off. After another 100ms 15 + delay the GPIO is driver active again. If the power is still on and 16 + the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted. 2 17 3 18 Required properties: 4 19 - compatible : should be "gpio-poweroff". ··· 28 13 property is not specified, the GPIO is initialized as an output in its 29 14 inactive state. 30 15 31 - 32 16 Examples: 33 17 34 18 gpio-poweroff { 35 19 compatible = "gpio-poweroff"; 36 - gpios = <&gpio 4 0>; /* GPIO 4 Active Low */ 20 + gpios = <&gpio 4 0>; 37 21 };
-1
arch/arm/Kconfig
··· 371 371 config ARCH_CLPS711X 372 372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 373 373 select ARCH_REQUIRE_GPIOLIB 374 - select ARCH_USES_GETTIMEOFFSET 375 374 select AUTO_ZRELADDR 376 375 select CLKDEV_LOOKUP 377 376 select COMMON_CLK
+4 -2
arch/arm/boot/dts/armada-370-xp.dtsi
··· 50 50 ranges; 51 51 52 52 serial@d0012000 { 53 - compatible = "ns16550"; 53 + compatible = "snps,dw-apb-uart"; 54 54 reg = <0xd0012000 0x100>; 55 55 reg-shift = <2>; 56 56 interrupts = <41>; 57 + reg-io-width = <4>; 57 58 status = "disabled"; 58 59 }; 59 60 serial@d0012100 { 60 - compatible = "ns16550"; 61 + compatible = "snps,dw-apb-uart"; 61 62 reg = <0xd0012100 0x100>; 62 63 reg-shift = <2>; 63 64 interrupts = <42>; 65 + reg-io-width = <4>; 64 66 status = "disabled"; 65 67 }; 66 68
+8 -1
arch/arm/boot/dts/armada-xp-mv78230.dtsi
··· 34 34 reg = <0>; 35 35 clocks = <&cpuclk 0>; 36 36 }; 37 - } 37 + 38 + cpu@1 { 39 + device_type = "cpu"; 40 + compatible = "marvell,sheeva-v7"; 41 + reg = <1>; 42 + clocks = <&cpuclk 1>; 43 + }; 44 + }; 38 45 39 46 soc { 40 47 pinctrl {
+8
arch/arm/boot/dts/armada-xp-mv78260.dtsi
··· 85 85 #interrupts-cells = <2>; 86 86 interrupts = <24>; 87 87 }; 88 + 89 + ethernet@d0034000 { 90 + compatible = "marvell,armada-370-neta"; 91 + reg = <0xd0034000 0x2500>; 92 + interrupts = <14>; 93 + clocks = <&gateclk 1>; 94 + status = "disabled"; 95 + }; 88 96 }; 89 97 };
+8
arch/arm/boot/dts/armada-xp-mv78460.dtsi
··· 100 100 #interrupts-cells = <2>; 101 101 interrupts = <24>; 102 102 }; 103 + 104 + ethernet@d0034000 { 105 + compatible = "marvell,armada-370-neta"; 106 + reg = <0xd0034000 0x2500>; 107 + interrupts = <14>; 108 + clocks = <&gateclk 1>; 109 + status = "disabled"; 110 + }; 103 111 }; 104 112 };
+4 -10
arch/arm/boot/dts/armada-xp.dtsi
··· 42 42 43 43 soc { 44 44 serial@d0012200 { 45 - compatible = "ns16550"; 45 + compatible = "snps,dw-apb-uart"; 46 46 reg = <0xd0012200 0x100>; 47 47 reg-shift = <2>; 48 48 interrupts = <43>; 49 + reg-io-width = <4>; 49 50 status = "disabled"; 50 51 }; 51 52 serial@d0012300 { 52 - compatible = "ns16550"; 53 + compatible = "snps,dw-apb-uart"; 53 54 reg = <0xd0012300 0x100>; 54 55 reg-shift = <2>; 55 56 interrupts = <44>; 57 + reg-io-width = <4>; 56 58 status = "disabled"; 57 59 }; 58 60 ··· 92 90 reg = <0xd0030000 0x2500>; 93 91 interrupts = <12>; 94 92 clocks = <&gateclk 2>; 95 - status = "disabled"; 96 - }; 97 - 98 - ethernet@d0034000 { 99 - compatible = "marvell,armada-370-neta"; 100 - reg = <0xd0034000 0x2500>; 101 - interrupts = <14>; 102 - clocks = <&gateclk 1>; 103 93 status = "disabled"; 104 94 }; 105 95
+1
arch/arm/boot/dts/dove.dtsi
··· 117 117 pinctrl: pinctrl@d0200 { 118 118 compatible = "marvell,dove-pinctrl"; 119 119 reg = <0xd0200 0x10>; 120 + clocks = <&gate_clk 22>; 120 121 }; 121 122 122 123 spi0: spi@10600 {
+4
arch/arm/boot/dts/ecx-2000.dts
··· 32 32 33 33 cpu@0 { 34 34 compatible = "arm,cortex-a15"; 35 + device_type = "cpu"; 35 36 reg = <0>; 36 37 clocks = <&a9pll>; 37 38 clock-names = "cpu"; ··· 40 39 41 40 cpu@1 { 42 41 compatible = "arm,cortex-a15"; 42 + device_type = "cpu"; 43 43 reg = <1>; 44 44 clocks = <&a9pll>; 45 45 clock-names = "cpu"; ··· 48 46 49 47 cpu@2 { 50 48 compatible = "arm,cortex-a15"; 49 + device_type = "cpu"; 51 50 reg = <2>; 52 51 clocks = <&a9pll>; 53 52 clock-names = "cpu"; ··· 56 53 57 54 cpu@3 { 58 55 compatible = "arm,cortex-a15"; 56 + device_type = "cpu"; 59 57 reg = <3>; 60 58 clocks = <&a9pll>; 61 59 clock-names = "cpu";
+1 -1
arch/arm/boot/dts/exynos4210-smdkv310.dts
··· 26 26 }; 27 27 28 28 chosen { 29 - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 29 + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; 30 30 }; 31 31 32 32 sdhci@12530000 {
+1 -1
arch/arm/boot/dts/exynos5250.dtsi
··· 574 574 575 575 hdmi { 576 576 compatible = "samsung,exynos5-hdmi"; 577 - reg = <0x14530000 0x100000>; 577 + reg = <0x14530000 0x70000>; 578 578 interrupts = <0 95 0>; 579 579 }; 580 580
+1 -1
arch/arm/boot/dts/exynos5440-ssdk5440.dts
··· 21 21 }; 22 22 23 23 chosen { 24 - bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC2,115200 init=/linuxrc"; 24 + bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc"; 25 25 }; 26 26 27 27 spi {
+12 -8
arch/arm/boot/dts/highbank.dts
··· 30 30 #address-cells = <1>; 31 31 #size-cells = <0>; 32 32 33 - cpu@0 { 33 + cpu@900 { 34 34 compatible = "arm,cortex-a9"; 35 - reg = <0>; 35 + device_type = "cpu"; 36 + reg = <0x900>; 36 37 next-level-cache = <&L2>; 37 38 clocks = <&a9pll>; 38 39 clock-names = "cpu"; 39 40 }; 40 41 41 - cpu@1 { 42 + cpu@901 { 42 43 compatible = "arm,cortex-a9"; 43 - reg = <1>; 44 + device_type = "cpu"; 45 + reg = <0x901>; 44 46 next-level-cache = <&L2>; 45 47 clocks = <&a9pll>; 46 48 clock-names = "cpu"; 47 49 }; 48 50 49 - cpu@2 { 51 + cpu@902 { 50 52 compatible = "arm,cortex-a9"; 51 - reg = <2>; 53 + device_type = "cpu"; 54 + reg = <0x902>; 52 55 next-level-cache = <&L2>; 53 56 clocks = <&a9pll>; 54 57 clock-names = "cpu"; 55 58 }; 56 59 57 - cpu@3 { 60 + cpu@903 { 58 61 compatible = "arm,cortex-a9"; 59 - reg = <3>; 62 + device_type = "cpu"; 63 + reg = <0x903>; 60 64 next-level-cache = <&L2>; 61 65 clocks = <&a9pll>; 62 66 clock-names = "cpu";
+4 -4
arch/arm/boot/dts/imx23-olinuxino.dts
··· 39 39 hog_pins_a: hog@0 { 40 40 reg = <0>; 41 41 fsl,pinmux-ids = < 42 - 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ 42 + 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ 43 43 >; 44 44 fsl,drive-strength = <0>; 45 45 fsl,voltage = <1>; 46 46 fsl,pull-up = <0>; 47 47 }; 48 48 49 - led_pin_gpio0_17: led_gpio0_17@0 { 49 + led_pin_gpio2_1: led_gpio2_1@0 { 50 50 reg = <0>; 51 51 fsl,pinmux-ids = < 52 - 0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */ 52 + 0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */ 53 53 >; 54 54 fsl,drive-strength = <0>; 55 55 fsl,voltage = <1>; ··· 110 110 leds { 111 111 compatible = "gpio-leds"; 112 112 pinctrl-names = "default"; 113 - pinctrl-0 = <&led_pin_gpio0_17>; 113 + pinctrl-0 = <&led_pin_gpio2_1>; 114 114 115 115 user { 116 116 label = "green";
+1 -1
arch/arm/boot/dts/imx31-bug.dts
··· 14 14 15 15 / { 16 16 model = "Buglabs i.MX31 Bug 1.x"; 17 - compatible = "fsl,imx31-bug", "fsl,imx31"; 17 + compatible = "buglabs,imx31-bug", "fsl,imx31"; 18 18 19 19 memory { 20 20 reg = <0x80000000 0x8000000>; /* 128M */
+1 -1
arch/arm/boot/dts/imx53.dtsi
··· 492 492 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 493 493 reg = <0x53fcc000 0x4000>; 494 494 interrupts = <83>; 495 - clocks = <&clks 158>, <&clks 157>; 495 + clocks = <&clks 87>, <&clks 86>; 496 496 clock-names = "ipg", "per"; 497 497 status = "disabled"; 498 498 };
+1
arch/arm/boot/dts/kirkwood-6282.dtsi
··· 39 39 #size-cells = <0>; 40 40 interrupts = <32>; 41 41 clock-frequency = <100000>; 42 + clocks = <&gate_clk 7>; 42 43 status = "disabled"; 43 44 }; 44 45 };
+17
arch/arm/boot/dts/kirkwood-topkick.dts
··· 82 82 gpios = <&gpio1 16 1>; 83 83 }; 84 84 }; 85 + regulators { 86 + compatible = "simple-bus"; 87 + #address-cells = <1>; 88 + #size-cells = <0>; 89 + 90 + sata0_power: regulator@1 { 91 + compatible = "regulator-fixed"; 92 + reg = <1>; 93 + regulator-name = "SATA0 Power"; 94 + regulator-min-microvolt = <5000000>; 95 + regulator-max-microvolt = <5000000>; 96 + enable-active-high; 97 + regulator-always-on; 98 + regulator-boot-on; 99 + gpio = <&gpio1 4 0>; 100 + }; 101 + }; 85 102 };
+1
arch/arm/boot/dts/kirkwood.dtsi
··· 144 144 compatible = "marvell,orion-ehci"; 145 145 reg = <0x50000 0x1000>; 146 146 interrupts = <19>; 147 + clocks = <&gate_clk 3>; 147 148 status = "okay"; 148 149 }; 149 150
+1 -3
arch/arm/configs/mvebu_defconfig
··· 33 33 CONFIG_MARVELL_PHY=y 34 34 CONFIG_SERIAL_8250=y 35 35 CONFIG_SERIAL_8250_CONSOLE=y 36 - CONFIG_SERIAL_OF_PLATFORM=y 37 - CONFIG_I2C=y 38 - CONFIG_I2C_MV64XXX=y 36 + CONFIG_SERIAL_8250_DW=y 39 37 CONFIG_GPIOLIB=y 40 38 CONFIG_GPIO_SYSFS=y 41 39 # CONFIG_USB_SUPPORT is not set
+2
arch/arm/mach-exynos/Kconfig
··· 74 74 depends on ARCH_EXYNOS5 75 75 select ARM_ARCH_TIMER 76 76 select AUTO_ZRELADDR 77 + select PINCTRL 78 + select PINCTRL_EXYNOS5440 77 79 help 78 80 Enable EXYNOS5440 SoC support 79 81
+7
arch/arm/mach-exynos/common.c
··· 424 424 { 425 425 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 426 426 427 + /* EXYNOS5440 can support only common clock framework */ 428 + 429 + if (soc_is_exynos5440()) 430 + return; 431 + 432 + #ifdef CONFIG_SOC_EXYNOS5250 427 433 s3c24xx_register_baseclocks(xtal); 428 434 s5p_register_clocks(xtal); 429 435 430 436 exynos5_register_clocks(); 431 437 exynos5_setup_clocks(); 438 + #endif 432 439 } 433 440 434 441 #define COMBINER_ENABLE_SET 0x0
+1 -1
arch/arm/mach-highbank/highbank.c
··· 135 135 136 136 static void highbank_power_off(void) 137 137 { 138 - hignbank_set_pwr_shutdown(); 138 + highbank_set_pwr_shutdown(); 139 139 140 140 while (1) 141 141 cpu_do_idle();
+1 -1
arch/arm/mach-highbank/hotplug.c
··· 30 30 { 31 31 flush_cache_all(); 32 32 33 - highbank_set_cpu_jump(cpu, secondary_startup); 33 + highbank_set_cpu_jump(cpu, phys_to_virt(0)); 34 34 highbank_set_core_pwr(); 35 35 36 36 cpu_do_idle();
+1 -11
arch/arm/mach-highbank/platsmp.c
··· 32 32 33 33 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) 34 34 { 35 + highbank_set_cpu_jump(cpu, secondary_startup); 35 36 gic_raise_softirq(cpumask_of(cpu), 0); 36 37 return 0; 37 38 } ··· 62 61 63 62 static void __init highbank_smp_prepare_cpus(unsigned int max_cpus) 64 63 { 65 - int i; 66 - 67 64 if (scu_base_addr) 68 65 scu_enable(scu_base_addr); 69 - 70 - /* 71 - * Write the address of secondary startup into the jump table 72 - * The cores are in wfi and wait until they receive a soft interrupt 73 - * and a non-zero value to jump to. Then the secondary CPU branches 74 - * to this address. 75 - */ 76 - for (i = 1; i < max_cpus; i++) 77 - highbank_set_cpu_jump(i, secondary_startup); 78 66 } 79 67 80 68 struct smp_operations highbank_smp_ops __initdata = {
+18 -1
arch/arm/mach-highbank/pm.c
··· 14 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 15 */ 16 16 17 + #include <linux/cpu_pm.h> 17 18 #include <linux/init.h> 18 19 #include <linux/io.h> 19 20 #include <linux/suspend.h> 20 21 22 + #include <asm/cacheflush.h> 21 23 #include <asm/proc-fns.h> 22 24 #include <asm/suspend.h> 23 25 ··· 28 26 29 27 static int highbank_suspend_finish(unsigned long val) 30 28 { 29 + outer_flush_all(); 30 + outer_disable(); 31 + 32 + highbank_set_pwr_suspend(); 33 + 31 34 cpu_do_idle(); 35 + 36 + highbank_clear_pwr_request(); 32 37 return 0; 33 38 } 34 39 35 40 static int highbank_pm_enter(suspend_state_t state) 36 41 { 37 - hignbank_set_pwr_suspend(); 42 + cpu_pm_enter(); 43 + cpu_cluster_pm_enter(); 44 + 38 45 highbank_set_cpu_jump(0, cpu_resume); 39 46 cpu_suspend(0, highbank_suspend_finish); 40 47 48 + cpu_cluster_pm_exit(); 49 + cpu_pm_exit(); 50 + 51 + highbank_smc1(0x102, 0x1); 52 + if (scu_base_addr) 53 + scu_enable(scu_base_addr); 41 54 return 0; 42 55 } 43 56
+19 -4
arch/arm/mach-highbank/sysregs.h
··· 44 44 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); 45 45 } 46 46 47 - static inline void hignbank_set_pwr_suspend(void) 47 + static inline void highbank_clear_core_pwr(void) 48 + { 49 + int cpu = cpu_logical_map(smp_processor_id()); 50 + if (scu_base_addr) 51 + scu_power_mode(scu_base_addr, SCU_PM_NORMAL); 52 + else 53 + writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); 54 + } 55 + 56 + static inline void highbank_set_pwr_suspend(void) 48 57 { 49 58 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); 50 59 highbank_set_core_pwr(); 51 60 } 52 61 53 - static inline void hignbank_set_pwr_shutdown(void) 62 + static inline void highbank_set_pwr_shutdown(void) 54 63 { 55 64 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); 56 65 highbank_set_core_pwr(); 57 66 } 58 67 59 - static inline void hignbank_set_pwr_soft_reset(void) 68 + static inline void highbank_set_pwr_soft_reset(void) 60 69 { 61 70 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); 62 71 highbank_set_core_pwr(); 63 72 } 64 73 65 - static inline void hignbank_set_pwr_hard_reset(void) 74 + static inline void highbank_set_pwr_hard_reset(void) 66 75 { 67 76 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); 68 77 highbank_set_core_pwr(); 78 + } 79 + 80 + static inline void highbank_clear_pwr_request(void) 81 + { 82 + writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); 83 + highbank_clear_core_pwr(); 69 84 } 70 85 71 86 #endif
+2 -2
arch/arm/mach-highbank/system.c
··· 22 22 void highbank_restart(char mode, const char *cmd) 23 23 { 24 24 if (mode == 'h') 25 - hignbank_set_pwr_hard_reset(); 25 + highbank_set_pwr_hard_reset(); 26 26 else 27 - hignbank_set_pwr_soft_reset(); 27 + highbank_set_pwr_soft_reset(); 28 28 29 29 while (1) 30 30 cpu_do_idle();
+4
arch/arm/mach-kirkwood/board-dt.c
··· 67 67 orion_clkdev_add(NULL, "mv643xx_eth_port.1", 68 68 of_clk_get_from_provider(&clkspec)); 69 69 70 + clkspec.args[0] = CGC_BIT_SDIO; 71 + orion_clkdev_add(NULL, "mvsdio", 72 + of_clk_get_from_provider(&clkspec)); 73 + 70 74 } 71 75 72 76 static void __init kirkwood_of_clk_init(void)
-4
arch/arm/mach-kirkwood/board-usi_topkick.c
··· 64 64 0 65 65 }; 66 66 67 - #define TOPKICK_SATA0_PWR_ENABLE 36 68 - 69 67 void __init usi_topkick_init(void) 70 68 { 71 69 /* ··· 71 73 */ 72 74 kirkwood_mpp_conf(topkick_mpp_config); 73 75 74 - /* SATA0 power enable */ 75 - gpio_set_value(TOPKICK_SATA0_PWR_ENABLE, 1); 76 76 77 77 kirkwood_ge00_init(&topkick_ge00_data); 78 78 kirkwood_sdio_init(&topkick_mvsdio_data);
-1
arch/arm/mach-nomadik/board-nhk8815.c
··· 27 27 #include <linux/pinctrl/machine.h> 28 28 #include <linux/platform_data/pinctrl-nomadik.h> 29 29 #include <linux/platform_data/clocksource-nomadik-mtu.h> 30 - #include <linux/platform_data/mtd-nomadik-nand.h> 31 30 #include <asm/hardware/vic.h> 32 31 #include <asm/sizes.h> 33 32 #include <asm/mach-types.h>
+39 -39
arch/arm/mach-nomadik/include/mach/irqs.h
··· 22 22 23 23 #include <mach/hardware.h> 24 24 25 - #define IRQ_VIC_START 1 /* first VIC interrupt is 1 */ 25 + #define IRQ_VIC_START 32 /* first VIC interrupt is 1 */ 26 26 27 27 /* 28 28 * Interrupt numbers generic for all Nomadik Chip cuts 29 29 */ 30 - #define IRQ_WATCHDOG 1 31 - #define IRQ_SOFTINT 2 32 - #define IRQ_CRYPTO 3 33 - #define IRQ_OWM 4 34 - #define IRQ_MTU0 5 35 - #define IRQ_MTU1 6 36 - #define IRQ_GPIO0 7 37 - #define IRQ_GPIO1 8 38 - #define IRQ_GPIO2 9 39 - #define IRQ_GPIO3 10 40 - #define IRQ_RTC_RTT 11 41 - #define IRQ_SSP 12 42 - #define IRQ_UART0 13 43 - #define IRQ_DMA1 14 44 - #define IRQ_CLCD_MDIF 15 45 - #define IRQ_DMA0 16 46 - #define IRQ_PWRFAIL 17 47 - #define IRQ_UART1 18 48 - #define IRQ_FIRDA 19 49 - #define IRQ_MSP0 20 50 - #define IRQ_I2C0 21 51 - #define IRQ_I2C1 22 52 - #define IRQ_SDMMC 23 53 - #define IRQ_USBOTG 24 54 - #define IRQ_SVA_IT0 25 55 - #define IRQ_SVA_IT1 26 56 - #define IRQ_SAA_IT0 27 57 - #define IRQ_SAA_IT1 28 58 - #define IRQ_UART2 29 59 - #define IRQ_MSP2 30 60 - #define IRQ_L2CC 49 61 - #define IRQ_HPI 50 62 - #define IRQ_SKE 51 63 - #define IRQ_KP 52 64 - #define IRQ_MEMST 55 65 - #define IRQ_SGA_IT 59 66 - #define IRQ_USBM 61 67 - #define IRQ_MSP1 63 30 + #define IRQ_WATCHDOG (IRQ_VIC_START+0) 31 + #define IRQ_SOFTINT (IRQ_VIC_START+1) 32 + #define IRQ_CRYPTO (IRQ_VIC_START+2) 33 + #define IRQ_OWM (IRQ_VIC_START+3) 34 + #define IRQ_MTU0 (IRQ_VIC_START+4) 35 + #define IRQ_MTU1 (IRQ_VIC_START+5) 36 + #define IRQ_GPIO0 (IRQ_VIC_START+6) 37 + #define IRQ_GPIO1 (IRQ_VIC_START+7) 38 + #define IRQ_GPIO2 (IRQ_VIC_START+8) 39 + #define IRQ_GPIO3 (IRQ_VIC_START+9) 40 + #define IRQ_RTC_RTT (IRQ_VIC_START+10) 41 + #define IRQ_SSP (IRQ_VIC_START+11) 42 + #define IRQ_UART0 (IRQ_VIC_START+12) 43 + #define IRQ_DMA1 (IRQ_VIC_START+13) 44 + #define IRQ_CLCD_MDIF (IRQ_VIC_START+14) 45 + #define IRQ_DMA0 (IRQ_VIC_START+15) 46 + #define IRQ_PWRFAIL (IRQ_VIC_START+16) 47 + #define IRQ_UART1 (IRQ_VIC_START+17) 48 + #define IRQ_FIRDA (IRQ_VIC_START+18) 49 + #define IRQ_MSP0 (IRQ_VIC_START+19) 50 + #define IRQ_I2C0 (IRQ_VIC_START+20) 51 + #define IRQ_I2C1 (IRQ_VIC_START+21) 52 + #define IRQ_SDMMC (IRQ_VIC_START+22) 53 + #define IRQ_USBOTG (IRQ_VIC_START+23) 54 + #define IRQ_SVA_IT0 (IRQ_VIC_START+24) 55 + #define IRQ_SVA_IT1 (IRQ_VIC_START+25) 56 + #define IRQ_SAA_IT0 (IRQ_VIC_START+26) 57 + #define IRQ_SAA_IT1 (IRQ_VIC_START+27) 58 + #define IRQ_UART2 (IRQ_VIC_START+28) 59 + #define IRQ_MSP2 (IRQ_VIC_START+29) 60 + #define IRQ_L2CC (IRQ_VIC_START+30) 61 + #define IRQ_HPI (IRQ_VIC_START+31) 62 + #define IRQ_SKE (IRQ_VIC_START+32) 63 + #define IRQ_KP (IRQ_VIC_START+33) 64 + #define IRQ_MEMST (IRQ_VIC_START+34) 65 + #define IRQ_SGA_IT (IRQ_VIC_START+35) 66 + #define IRQ_USBM (IRQ_VIC_START+36) 67 + #define IRQ_MSP1 (IRQ_VIC_START+37) 68 68 69 69 #define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64) 70 70
+1 -1
arch/arm/mach-omap1/board-ams-delta.c
··· 160 160 .ctrl_name = "internal", 161 161 }; 162 162 163 - static struct omap_usb_config ams_delta_usb_config = { 163 + static struct omap_usb_config ams_delta_usb_config __initdata = { 164 164 .register_host = 1, 165 165 .hmc_mode = 16, 166 166 .pins[0] = 2,
+7 -1
arch/arm/mach-omap1/usb.c
··· 629 629 static inline void omap_1510_usb_init(struct omap_usb_config *config) {} 630 630 #endif 631 631 632 - void __init omap1_usb_init(struct omap_usb_config *pdata) 632 + void __init omap1_usb_init(struct omap_usb_config *_pdata) 633 633 { 634 + struct omap_usb_config *pdata; 635 + 636 + pdata = kmemdup(_pdata, sizeof(*pdata), GFP_KERNEL); 637 + if (!pdata) 638 + return; 639 + 634 640 pdata->usb0_init = omap1_usb0_init; 635 641 pdata->usb1_init = omap1_usb1_init; 636 642 pdata->usb2_init = omap1_usb2_init;
+2
arch/arm/mach-omap2/cclock3xxx_data.c
··· 1167 1167 .recalc_rate = &omap2_clksel_recalc, 1168 1168 .get_parent = &omap2_clksel_find_parent_index, 1169 1169 .set_parent = &omap2_clksel_set_parent, 1170 + .enable = &omap2_clkops_enable_clkdm, 1171 + .disable = &omap2_clkops_disable_clkdm, 1170 1172 }; 1171 1173 1172 1174 static struct clk emu_src_ck;
+3 -3
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
··· 2070 2070 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, }, 2071 2071 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, }, 2072 2072 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, }, 2073 - { .irq = -1 + OMAP_INTC_START, }, 2073 + { .irq = -1, }, 2074 2074 }; 2075 2075 2076 2076 static struct omap_hwmod am33xx_usbss_hwmod = { ··· 2515 2515 .user = OCP_USER_MPU, 2516 2516 }; 2517 2517 2518 - struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = { 2518 + static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = { 2519 2519 { 2520 2520 .pa_start = 0x4A101000, 2521 2521 .pa_end = 0x4A101000 + SZ_256 - 1, ··· 2523 2523 { } 2524 2524 }; 2525 2525 2526 - struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { 2526 + static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { 2527 2527 .master = &am33xx_cpgmac0_hwmod, 2528 2528 .slave = &am33xx_mdio_hwmod, 2529 2529 .addr = am33xx_mdio_addr_space,
+85 -3
arch/arm/mach-omap2/prm2xxx.c
··· 28 28 #include "prm-regbits-24xx.h" 29 29 30 30 /* 31 + * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits - 32 + * these are reversed from the bits used on OMAP3+ 33 + */ 34 + #define OMAP24XX_PWRDM_POWER_ON 0x0 35 + #define OMAP24XX_PWRDM_POWER_RET 0x1 36 + #define OMAP24XX_PWRDM_POWER_OFF 0x3 37 + 38 + /* 31 39 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP 32 40 * hardware register (which are specific to the OMAP2xxx SoCs) to 33 41 * reset source ID bit shifts (which is an OMAP SoC-independent ··· 76 68 } 77 69 78 70 /** 71 + * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst 72 + * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert 73 + * 74 + * Return the common power state bits corresponding to the OMAP2xxx 75 + * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error. 76 + */ 77 + static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst) 78 + { 79 + u8 pwrst; 80 + 81 + switch (omap2xxx_pwrst) { 82 + case OMAP24XX_PWRDM_POWER_OFF: 83 + pwrst = PWRDM_POWER_OFF; 84 + break; 85 + case OMAP24XX_PWRDM_POWER_RET: 86 + pwrst = PWRDM_POWER_RET; 87 + break; 88 + case OMAP24XX_PWRDM_POWER_ON: 89 + pwrst = PWRDM_POWER_ON; 90 + break; 91 + default: 92 + return -EINVAL; 93 + } 94 + 95 + return pwrst; 96 + } 97 + 98 + /** 79 99 * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC 80 100 * 81 101 * Set the DPLL reset bit, which should reboot the SoC. This is the ··· 133 97 return 0; 134 98 } 135 99 100 + static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 101 + { 102 + u8 omap24xx_pwrst; 103 + 104 + switch (pwrst) { 105 + case PWRDM_POWER_OFF: 106 + omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF; 107 + break; 108 + case PWRDM_POWER_RET: 109 + omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET; 110 + break; 111 + case PWRDM_POWER_ON: 112 + omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON; 113 + break; 114 + default: 115 + return -EINVAL; 116 + } 117 + 118 + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, 119 + (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT), 120 + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 121 + return 0; 122 + } 123 + 124 + static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 125 + { 126 + u8 omap2xxx_pwrst; 127 + 128 + omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, 129 + OMAP2_PM_PWSTCTRL, 130 + OMAP_POWERSTATE_MASK); 131 + 132 + return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst); 133 + } 134 + 135 + static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm) 136 + { 137 + u8 omap2xxx_pwrst; 138 + 139 + omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, 140 + OMAP2_PM_PWSTST, 141 + OMAP_POWERSTATEST_MASK); 142 + 143 + return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst); 144 + } 145 + 136 146 struct pwrdm_ops omap2_pwrdm_operations = { 137 - .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, 138 - .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, 139 - .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, 147 + .pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst, 148 + .pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst, 149 + .pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst, 140 150 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, 141 151 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, 142 152 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
-22
arch/arm/mach-omap2/prm2xxx_3xxx.c
··· 103 103 /* Powerdomain low-level functions */ 104 104 105 105 /* Common functions across OMAP2 and OMAP3 */ 106 - int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 107 - { 108 - omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, 109 - (pwrst << OMAP_POWERSTATE_SHIFT), 110 - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 111 - return 0; 112 - } 113 - 114 - int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 115 - { 116 - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, 117 - OMAP2_PM_PWSTCTRL, 118 - OMAP_POWERSTATE_MASK); 119 - } 120 - 121 - int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) 122 - { 123 - return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, 124 - OMAP2_PM_PWSTST, 125 - OMAP_POWERSTATEST_MASK); 126 - } 127 - 128 106 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, 129 107 u8 pwrst) 130 108 {
+25 -3
arch/arm/mach-omap2/prm3xxx.c
··· 277 277 278 278 /* Powerdomain low-level functions */ 279 279 280 + static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 281 + { 282 + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, 283 + (pwrst << OMAP_POWERSTATE_SHIFT), 284 + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); 285 + return 0; 286 + } 287 + 288 + static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 289 + { 290 + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, 291 + OMAP2_PM_PWSTCTRL, 292 + OMAP_POWERSTATE_MASK); 293 + } 294 + 295 + static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm) 296 + { 297 + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, 298 + OMAP2_PM_PWSTST, 299 + OMAP_POWERSTATEST_MASK); 300 + } 301 + 280 302 /* Applicable only for OMAP3. Not supported on OMAP2 */ 281 303 static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) 282 304 { ··· 377 355 } 378 356 379 357 struct pwrdm_ops omap3_pwrdm_operations = { 380 - .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, 381 - .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, 382 - .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, 358 + .pwrdm_set_next_pwrst = omap3_pwrdm_set_next_pwrst, 359 + .pwrdm_read_next_pwrst = omap3_pwrdm_read_next_pwrst, 360 + .pwrdm_read_pwrst = omap3_pwrdm_read_pwrst, 383 361 .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, 384 362 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, 385 363 .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
+3 -3
arch/arm/mach-omap2/prm44xx.c
··· 56 56 * enumeration) 57 57 */ 58 58 static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { 59 - { OMAP4430_RST_GLOBAL_WARM_SW_SHIFT, 59 + { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT, 60 60 OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT }, 61 - { OMAP4430_RST_GLOBAL_COLD_SW_SHIFT, 61 + { OMAP4430_GLOBAL_COLD_RST_SHIFT, 62 62 OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT }, 63 63 { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT, 64 64 OMAP_SECU_VIOL_RST_SRC_ID_SHIFT }, ··· 333 333 u32 r = 0; 334 334 u32 v; 335 335 336 - v = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, 336 + v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, 337 337 OMAP4_RM_RSTST); 338 338 339 339 p = omap44xx_prm_reset_src_map;
+2 -2
arch/arm/mach-omap2/prm44xx.h
··· 62 62 63 63 /* OMAP4 specific register offsets */ 64 64 #define OMAP4_RM_RSTCTRL 0x0000 65 - #define OMAP4_RM_RSTTIME 0x0004 66 - #define OMAP4_RM_RSTST 0x0008 65 + #define OMAP4_RM_RSTST 0x0004 66 + #define OMAP4_RM_RSTTIME 0x0008 67 67 #define OMAP4_PM_PWSTCTRL 0x0000 68 68 #define OMAP4_PM_PWSTST 0x0004 69 69
+2
arch/arm/plat-omap/counter_32k.c
··· 22 22 #include <asm/mach/time.h> 23 23 #include <asm/sched_clock.h> 24 24 25 + #include <plat/counter-32k.h> 26 + 25 27 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ 26 28 #define OMAP2_32KSYNCNT_REV_OFF 0x0 27 29 #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
+2
arch/arm/plat-omap/sram.c
··· 26 26 27 27 #include <asm/mach/map.h> 28 28 29 + #include <plat/sram.h> 30 + 29 31 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 30 32 31 33 static void __iomem *omap_sram_base;
+1 -1
arch/arm/plat-samsung/include/plat/cpu.h
··· 43 43 #define EXYNOS4_CPU_MASK 0xFFFE0000 44 44 45 45 #define EXYNOS5250_SOC_ID 0x43520000 46 - #define EXYNOS5440_SOC_ID 0x54400000 46 + #define EXYNOS5440_SOC_ID 0xE5440000 47 47 #define EXYNOS5_SOC_MASK 0xFFFFF000 48 48 49 49 #define IS_SAMSUNG_CPU(name, id, mask) \
+1 -1
drivers/clk/mvebu/clk-gating-ctrl.c
··· 32 32 33 33 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 34 34 35 - static struct clk __init *mvebu_clk_gating_get_src( 35 + static struct clk *mvebu_clk_gating_get_src( 36 36 struct of_phandle_args *clkspec, void *data) 37 37 { 38 38 struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
+6 -3
drivers/dma/mv_xor.c
··· 1361 1361 err_channel_add: 1362 1362 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) 1363 1363 if (xordev->channels[i]) { 1364 + mv_xor_channel_remove(xordev->channels[i]); 1364 1365 if (pdev->dev.of_node) 1365 1366 irq_dispose_mapping(xordev->channels[i]->irq); 1366 - mv_xor_channel_remove(xordev->channels[i]); 1367 1367 } 1368 1368 1369 - clk_disable_unprepare(xordev->clk); 1370 - clk_put(xordev->clk); 1369 + if (!IS_ERR(xordev->clk)) { 1370 + clk_disable_unprepare(xordev->clk); 1371 + clk_put(xordev->clk); 1372 + } 1373 + 1371 1374 return ret; 1372 1375 } 1373 1376
+5 -2
drivers/pinctrl/mvebu/pinctrl-dove.c
··· 595 595 * grab clk to make sure it is ticking. 596 596 */ 597 597 clk = devm_clk_get(&pdev->dev, NULL); 598 - if (!IS_ERR(clk)) 599 - clk_prepare_enable(clk); 598 + if (IS_ERR(clk)) { 599 + dev_err(&pdev->dev, "Unable to get pdma clock"); 600 + return PTR_RET(clk); 601 + } 602 + clk_prepare_enable(clk); 600 603 601 604 return mvebu_pinctrl_probe(pdev); 602 605 }
+15 -18
drivers/power/reset/gpio-poweroff.c
··· 29 29 30 30 static void gpio_poweroff_do_poweroff(void) 31 31 { 32 - BUG_ON(gpio_num == -1); 32 + BUG_ON(!gpio_is_valid(gpio_num)); 33 33 34 - /* drive it active */ 34 + /* drive it active, also inactive->active edge */ 35 35 gpio_direction_output(gpio_num, !gpio_active_low); 36 36 mdelay(100); 37 - /* rising edge or drive inactive */ 37 + /* drive inactive, also active->inactive edge */ 38 38 gpio_set_value(gpio_num, gpio_active_low); 39 39 mdelay(100); 40 - /* falling edge */ 40 + 41 + /* drive it active, also inactive->active edge */ 41 42 gpio_set_value(gpio_num, !gpio_active_low); 42 43 43 44 /* give it some time */ ··· 61 60 } 62 61 63 62 gpio_num = of_get_gpio_flags(pdev->dev.of_node, 0, &flags); 64 - if (gpio_num < 0) { 65 - pr_err("%s: Could not get GPIO configuration: %d", 66 - __func__, gpio_num); 67 - return -ENODEV; 68 - } 63 + if (!gpio_is_valid(gpio_num)) 64 + return gpio_num; 65 + 69 66 gpio_active_low = flags & OF_GPIO_ACTIVE_LOW; 70 67 71 - if (of_get_property(pdev->dev.of_node, "input", NULL)) 72 - input = true; 68 + input = of_property_read_bool(pdev->dev.of_node, "input"); 73 69 74 70 ret = gpio_request(gpio_num, "poweroff-gpio"); 75 71 if (ret) { ··· 96 98 97 99 static int gpio_poweroff_remove(struct platform_device *pdev) 98 100 { 99 - if (gpio_num != -1) 100 - gpio_free(gpio_num); 101 + gpio_free(gpio_num); 101 102 if (pm_power_off == &gpio_poweroff_do_poweroff) 102 103 pm_power_off = NULL; 103 104 ··· 112 115 .probe = gpio_poweroff_probe, 113 116 .remove = gpio_poweroff_remove, 114 117 .driver = { 115 - .name = "poweroff-gpio", 116 - .owner = THIS_MODULE, 117 - .of_match_table = of_gpio_poweroff_match, 118 - }, 118 + .name = "poweroff-gpio", 119 + .owner = THIS_MODULE, 120 + .of_match_table = of_gpio_poweroff_match, 121 + }, 119 122 }; 120 123 121 124 module_platform_driver(gpio_poweroff_driver); 122 125 123 126 MODULE_AUTHOR("Jamie Lentin <jm@lentin.co.uk>"); 124 127 MODULE_DESCRIPTION("GPIO poweroff driver"); 125 - MODULE_LICENSE("GPL"); 128 + MODULE_LICENSE("GPL v2"); 126 129 MODULE_ALIAS("platform:poweroff-gpio");
+2 -1
drivers/video/mxsfb.c
··· 369 369 loop--; 370 370 } 371 371 372 - writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR); 372 + reg = readl(host->base + LCDC_VDCTRL4); 373 + writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4); 373 374 374 375 clk_disable_unprepare(host->clk); 375 376