Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
usb: dwc3: dwc3-octeon: Convert to glue driver
DWC3 as implemented in Cavium SoC is using UCTL bridge unit
between I/O interconnect and USB controller.
Currently there is no bond with dwc3 core code, so if anything goes
wrong in UCTL setup dwc3 is left in reset, which leads to bus error
while trying to read any device register. Thus any failure in UCTL
initialization ends with kernel panic.
To avoid this move Octeon DWC3 glue code from arch/mips and make it
proper glue driver which is used instead of dwc3-of-simple.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/ZMd/ReyiY7wS6DvN@lenoch
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Ladislav Michl
and committed by
Greg Kroah-Hartman
976f82e8
b35935d6
+66
-49
-1
arch/mips/cavium-octeon/Makefile
-1
arch/mips/cavium-octeon/Makefile
-1
arch/mips/cavium-octeon/octeon-platform.c
-1
arch/mips/cavium-octeon/octeon-platform.c
+55
-46
arch/mips/cavium-octeon/octeon-usb.c
drivers/usb/dwc3/dwc3-octeon.c
+55
-46
arch/mips/cavium-octeon/octeon-usb.c
drivers/usb/dwc3/dwc3-octeon.c
···
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#define USBDRD_UCTL_ECC 0xf0
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#define USBDRD_UCTL_SPARE1 0xf8
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-
static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
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+
struct dwc3_octeon {
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struct device *dev;
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+
void __iomem *base;
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};
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
···
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static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { }
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static inline void dwc3_octeon_config_gpio(int index, int gpio) { }
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static uint64_t octeon_get_io_clock_rate(void)
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{
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return 150000000;
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}
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#endif
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static int dwc3_octeon_get_divider(void)
···
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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}
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-
static int __init dwc3_octeon_device_init(void)
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+
static int dwc3_octeon_probe(struct platform_device *pdev)
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{
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const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
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struct platform_device *pdev;
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struct device_node *node;
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struct resource *res;
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void __iomem *base;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct dwc3_octeon *octeon;
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int err;
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/*
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* There should only be three universal controllers, "uctl"
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* in the device tree. Two USB and a SATA, which we ignore.
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*/
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node = NULL;
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do {
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node = of_find_node_by_name(node, "uctl");
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if (!node)
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return -ENODEV;
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octeon = devm_kzalloc(dev, sizeof(*octeon), GFP_KERNEL);
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if (!octeon)
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return -ENOMEM;
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-
if (of_device_is_compatible(node, compat_node_name)) {
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pdev = of_find_device_by_node(node);
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if (!pdev)
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return -ENODEV;
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+
octeon->dev = dev;
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octeon->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(octeon->base))
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return PTR_ERR(octeon->base);
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/*
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* The code below maps in the registers necessary for
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* setting up the clocks and reseting PHYs. We must
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* release the resources so the dwc3 subsystem doesn't
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* know the difference.
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*/
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base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(base)) {
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put_device(&pdev->dev);
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return PTR_ERR(base);
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}
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err = dwc3_octeon_clocks_start(dev, octeon->base);
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if (err)
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return err;
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mutex_lock(&dwc3_octeon_clocks_mutex);
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if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0)
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dev_info(&pdev->dev, "clocks initialized.\n");
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dwc3_octeon_set_endian_mode(base);
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dwc3_octeon_phy_reset(base);
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mutex_unlock(&dwc3_octeon_clocks_mutex);
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devm_iounmap(&pdev->dev, base);
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devm_release_mem_region(&pdev->dev, res->start,
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resource_size(res));
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put_device(&pdev->dev);
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}
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} while (node != NULL);
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dwc3_octeon_set_endian_mode(octeon->base);
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dwc3_octeon_phy_reset(octeon->base);
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return 0;
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platform_set_drvdata(pdev, octeon);
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return of_platform_populate(node, NULL, NULL, dev);
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}
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device_initcall(dwc3_octeon_device_init);
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static void dwc3_octeon_remove(struct platform_device *pdev)
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{
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struct dwc3_octeon *octeon = platform_get_drvdata(pdev);
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of_platform_depopulate(octeon->dev);
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platform_set_drvdata(pdev, NULL);
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}
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static const struct of_device_id dwc3_octeon_of_match[] = {
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{ .compatible = "cavium,octeon-7130-usb-uctl" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match);
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static struct platform_driver dwc3_octeon_driver = {
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.probe = dwc3_octeon_probe,
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.remove_new = dwc3_octeon_remove,
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.driver = {
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.name = "dwc3-octeon",
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.of_match_table = dwc3_octeon_of_match,
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},
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};
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module_platform_driver(dwc3_octeon_driver);
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MODULE_ALIAS("platform:dwc3-octeon");
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MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("USB driver for OCTEON III SoC");
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MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer");
+10
drivers/usb/dwc3/Kconfig
+10
drivers/usb/dwc3/Kconfig
···
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The Designware Core USB3 IP is programmed to operate in
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in USB 2.0 mode only.
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Say 'Y' or 'M' here if you have one such device
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config USB_DWC3_OCTEON
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tristate "Cavium Octeon Platforms"
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depends on CAVIUM_OCTEON_SOC || COMPILE_TEST
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default USB_DWC3
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help
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Support Cavium Octeon platforms with DesignWare Core USB3 IP.
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Only the host mode is currently supported.
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Say 'Y' or 'M' here if you have one such device.
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+
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endif
+1
drivers/usb/dwc3/Makefile
+1
drivers/usb/dwc3/Makefile
-1
drivers/usb/dwc3/dwc3-of-simple.c
-1
drivers/usb/dwc3/dwc3-of-simple.c
···
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static const struct of_device_id of_dwc3_simple_match[] = {
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{ .compatible = "rockchip,rk3399-dwc3" },
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{ .compatible = "cavium,octeon-7130-usb-uctl" },
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{ .compatible = "sprd,sc9860-dwc3" },
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{ .compatible = "allwinner,sun50i-h6-dwc3" },
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{ .compatible = "hisilicon,hi3670-dwc3" },