tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

usb: dwc3: add optional PHY interface clocks

On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
requires two extra clocks to be enabled. Without these extra clocks
hot-plugging USB devices is broken.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Sebastian Reichel and committed by
Greg Kroah-Hartman 97789b93 98bad5bc

+32
+28
drivers/usb/dwc3/core.c
··· 854 854 if (ret) 855 855 goto disable_ref_clk; 856 856 857 + ret = clk_prepare_enable(dwc->utmi_clk); 858 + if (ret) 859 + goto disable_susp_clk; 860 + 861 + ret = clk_prepare_enable(dwc->pipe_clk); 862 + if (ret) 863 + goto disable_utmi_clk; 864 + 857 865 return 0; 858 866 867 + disable_utmi_clk: 868 + clk_disable_unprepare(dwc->utmi_clk); 869 + disable_susp_clk: 870 + clk_disable_unprepare(dwc->susp_clk); 859 871 disable_ref_clk: 860 872 clk_disable_unprepare(dwc->ref_clk); 861 873 disable_bus_clk: ··· 877 865 878 866 static void dwc3_clk_disable(struct dwc3 *dwc) 879 867 { 868 + clk_disable_unprepare(dwc->pipe_clk); 869 + clk_disable_unprepare(dwc->utmi_clk); 880 870 clk_disable_unprepare(dwc->susp_clk); 881 871 clk_disable_unprepare(dwc->ref_clk); 882 872 clk_disable_unprepare(dwc->bus_clk); ··· 1885 1871 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1886 1872 "could not get suspend clock\n"); 1887 1873 } 1874 + } 1875 + 1876 + /* specific to Rockchip RK3588 */ 1877 + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); 1878 + if (IS_ERR(dwc->utmi_clk)) { 1879 + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), 1880 + "could not get utmi clock\n"); 1881 + } 1882 + 1883 + /* specific to Rockchip RK3588 */ 1884 + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); 1885 + if (IS_ERR(dwc->pipe_clk)) { 1886 + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), 1887 + "could not get pipe clock\n"); 1888 1888 } 1889 1889 1890 1890 return 0;
+4
drivers/usb/dwc3/core.h
··· 996 996 * @bus_clk: clock for accessing the registers 997 997 * @ref_clk: reference clock 998 998 * @susp_clk: clock used when the SS phy is in low power (S3) state 999 + * @utmi_clk: clock used for USB2 PHY communication 1000 + * @pipe_clk: clock used for USB3 PHY communication 999 1001 * @reset: reset control 1000 1002 * @regs: base address for our registers 1001 1003 * @regs_size: address space size ··· 1169 1167 struct clk *bus_clk; 1170 1168 struct clk *ref_clk; 1171 1169 struct clk *susp_clk; 1170 + struct clk *utmi_clk; 1171 + struct clk *pipe_clk; 1172 1172 1173 1173 struct reset_control *reset; 1174 1174