clk: mmp: Remove old non-OF clock drivers

-4

drivers/clk/mmp/Makefile

··· 11 11 obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o 12 12 obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o 13 13 14 - obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o 15 - obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o 16 - obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o 17 - 18 14 obj-y += clk-of-pxa1928.o

-454

drivers/clk/mmp/clk-mmp2.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * mmp2 clock framework source file 4 - * 5 - * Copyright (C) 2012 Marvell 6 - * Chao Xie <xiechao.mail@gmail.com> 7 - */ 8 - 9 - #include <linux/clk.h> 10 - #include <linux/module.h> 11 - #include <linux/kernel.h> 12 - #include <linux/spinlock.h> 13 - #include <linux/io.h> 14 - #include <linux/delay.h> 15 - #include <linux/err.h> 16 - #include <linux/clk/mmp.h> 17 - 18 - #include "clk.h" 19 - 20 - #define APBC_RTC 0x0 21 - #define APBC_TWSI0 0x4 22 - #define APBC_TWSI1 0x8 23 - #define APBC_TWSI2 0xc 24 - #define APBC_TWSI3 0x10 25 - #define APBC_TWSI4 0x7c 26 - #define APBC_TWSI5 0x80 27 - #define APBC_KPC 0x18 28 - #define APBC_UART0 0x2c 29 - #define APBC_UART1 0x30 30 - #define APBC_UART2 0x34 31 - #define APBC_UART3 0x88 32 - #define APBC_GPIO 0x38 33 - #define APBC_PWM0 0x3c 34 - #define APBC_PWM1 0x40 35 - #define APBC_PWM2 0x44 36 - #define APBC_PWM3 0x48 37 - #define APBC_SSP0 0x50 38 - #define APBC_SSP1 0x54 39 - #define APBC_SSP2 0x58 40 - #define APBC_SSP3 0x5c 41 - #define APMU_SDH0 0x54 42 - #define APMU_SDH1 0x58 43 - #define APMU_SDH2 0xe8 44 - #define APMU_SDH3 0xec 45 - #define APMU_USB 0x5c 46 - #define APMU_DISP0 0x4c 47 - #define APMU_DISP1 0x110 48 - #define APMU_CCIC0 0x50 49 - #define APMU_CCIC1 0xf4 50 - #define MPMU_UART_PLL 0x14 51 - 52 - static DEFINE_SPINLOCK(clk_lock); 53 - 54 - static struct mmp_clk_factor_masks uart_factor_masks = { 55 - .factor = 2, 56 - .num_mask = 0x1fff, 57 - .den_mask = 0x1fff, 58 - .num_shift = 16, 59 - .den_shift = 0, 60 - }; 61 - 62 - static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 63 - {.num = 8125, .den = 1536}, /*14.745MHZ */ 64 - {.num = 3521, .den = 689}, /*19.23MHZ */ 65 - }; 66 - 67 - static const char *uart_parent[] = {"uart_pll", "vctcxo"}; 68 - static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"}; 69 - static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"}; 70 - static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"}; 71 - static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"}; 72 - 73 - void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, 74 - phys_addr_t apbc_phys) 75 - { 76 - struct clk *clk; 77 - struct clk *vctcxo; 78 - void __iomem *mpmu_base; 79 - void __iomem *apmu_base; 80 - void __iomem *apbc_base; 81 - 82 - mpmu_base = ioremap(mpmu_phys, SZ_4K); 83 - if (!mpmu_base) { 84 - pr_err("error to ioremap MPMU base\n"); 85 - return; 86 - } 87 - 88 - apmu_base = ioremap(apmu_phys, SZ_4K); 89 - if (!apmu_base) { 90 - pr_err("error to ioremap APMU base\n"); 91 - return; 92 - } 93 - 94 - apbc_base = ioremap(apbc_phys, SZ_4K); 95 - if (!apbc_base) { 96 - pr_err("error to ioremap APBC base\n"); 97 - return; 98 - } 99 - 100 - clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); 101 - clk_register_clkdev(clk, "clk32", NULL); 102 - 103 - vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); 104 - clk_register_clkdev(vctcxo, "vctcxo", NULL); 105 - 106 - clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); 107 - clk_register_clkdev(clk, "pll1", NULL); 108 - 109 - clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000); 110 - clk_register_clkdev(clk, "usb_pll", NULL); 111 - 112 - clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); 113 - clk_register_clkdev(clk, "pll2", NULL); 114 - 115 - clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", 116 - CLK_SET_RATE_PARENT, 1, 2); 117 - clk_register_clkdev(clk, "pll1_2", NULL); 118 - 119 - clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", 120 - CLK_SET_RATE_PARENT, 1, 2); 121 - clk_register_clkdev(clk, "pll1_4", NULL); 122 - 123 - clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", 124 - CLK_SET_RATE_PARENT, 1, 2); 125 - clk_register_clkdev(clk, "pll1_8", NULL); 126 - 127 - clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", 128 - CLK_SET_RATE_PARENT, 1, 2); 129 - clk_register_clkdev(clk, "pll1_16", NULL); 130 - 131 - clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4", 132 - CLK_SET_RATE_PARENT, 1, 5); 133 - clk_register_clkdev(clk, "pll1_20", NULL); 134 - 135 - clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", 136 - CLK_SET_RATE_PARENT, 1, 3); 137 - clk_register_clkdev(clk, "pll1_3", NULL); 138 - 139 - clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3", 140 - CLK_SET_RATE_PARENT, 1, 2); 141 - clk_register_clkdev(clk, "pll1_6", NULL); 142 - 143 - clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", 144 - CLK_SET_RATE_PARENT, 1, 2); 145 - clk_register_clkdev(clk, "pll1_12", NULL); 146 - 147 - clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", 148 - CLK_SET_RATE_PARENT, 1, 2); 149 - clk_register_clkdev(clk, "pll2_2", NULL); 150 - 151 - clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2", 152 - CLK_SET_RATE_PARENT, 1, 2); 153 - clk_register_clkdev(clk, "pll2_4", NULL); 154 - 155 - clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4", 156 - CLK_SET_RATE_PARENT, 1, 2); 157 - clk_register_clkdev(clk, "pll2_8", NULL); 158 - 159 - clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8", 160 - CLK_SET_RATE_PARENT, 1, 2); 161 - clk_register_clkdev(clk, "pll2_16", NULL); 162 - 163 - clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", 164 - CLK_SET_RATE_PARENT, 1, 3); 165 - clk_register_clkdev(clk, "pll2_3", NULL); 166 - 167 - clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3", 168 - CLK_SET_RATE_PARENT, 1, 2); 169 - clk_register_clkdev(clk, "pll2_6", NULL); 170 - 171 - clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6", 172 - CLK_SET_RATE_PARENT, 1, 2); 173 - clk_register_clkdev(clk, "pll2_12", NULL); 174 - 175 - clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo", 176 - CLK_SET_RATE_PARENT, 1, 2); 177 - clk_register_clkdev(clk, "vctcxo_2", NULL); 178 - 179 - clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2", 180 - CLK_SET_RATE_PARENT, 1, 2); 181 - clk_register_clkdev(clk, "vctcxo_4", NULL); 182 - 183 - clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, 184 - mpmu_base + MPMU_UART_PLL, 185 - &uart_factor_masks, uart_factor_tbl, 186 - ARRAY_SIZE(uart_factor_tbl), &clk_lock); 187 - clk_set_rate(clk, 14745600); 188 - clk_register_clkdev(clk, "uart_pll", NULL); 189 - 190 - clk = mmp_clk_register_apbc("twsi0", "vctcxo", 191 - apbc_base + APBC_TWSI0, 10, 0, &clk_lock); 192 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); 193 - 194 - clk = mmp_clk_register_apbc("twsi1", "vctcxo", 195 - apbc_base + APBC_TWSI1, 10, 0, &clk_lock); 196 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); 197 - 198 - clk = mmp_clk_register_apbc("twsi2", "vctcxo", 199 - apbc_base + APBC_TWSI2, 10, 0, &clk_lock); 200 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); 201 - 202 - clk = mmp_clk_register_apbc("twsi3", "vctcxo", 203 - apbc_base + APBC_TWSI3, 10, 0, &clk_lock); 204 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); 205 - 206 - clk = mmp_clk_register_apbc("twsi4", "vctcxo", 207 - apbc_base + APBC_TWSI4, 10, 0, &clk_lock); 208 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); 209 - 210 - clk = mmp_clk_register_apbc("twsi5", "vctcxo", 211 - apbc_base + APBC_TWSI5, 10, 0, &clk_lock); 212 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); 213 - 214 - clk = mmp_clk_register_apbc("gpio", "vctcxo", 215 - apbc_base + APBC_GPIO, 10, 0, &clk_lock); 216 - clk_register_clkdev(clk, NULL, "mmp2-gpio"); 217 - 218 - clk = mmp_clk_register_apbc("kpc", "clk32", 219 - apbc_base + APBC_KPC, 10, 0, &clk_lock); 220 - clk_register_clkdev(clk, NULL, "pxa27x-keypad"); 221 - 222 - clk = mmp_clk_register_apbc("rtc", "clk32", 223 - apbc_base + APBC_RTC, 10, 0, &clk_lock); 224 - clk_register_clkdev(clk, NULL, "mmp-rtc"); 225 - 226 - clk = mmp_clk_register_apbc("pwm0", "vctcxo", 227 - apbc_base + APBC_PWM0, 10, 0, &clk_lock); 228 - clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); 229 - 230 - clk = mmp_clk_register_apbc("pwm1", "vctcxo", 231 - apbc_base + APBC_PWM1, 10, 0, &clk_lock); 232 - clk_register_clkdev(clk, NULL, "mmp2-pwm.1"); 233 - 234 - clk = mmp_clk_register_apbc("pwm2", "vctcxo", 235 - apbc_base + APBC_PWM2, 10, 0, &clk_lock); 236 - clk_register_clkdev(clk, NULL, "mmp2-pwm.2"); 237 - 238 - clk = mmp_clk_register_apbc("pwm3", "vctcxo", 239 - apbc_base + APBC_PWM3, 10, 0, &clk_lock); 240 - clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); 241 - 242 - clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 243 - ARRAY_SIZE(uart_parent), 244 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 245 - apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 246 - clk_set_parent(clk, vctcxo); 247 - clk_register_clkdev(clk, "uart_mux.0", NULL); 248 - 249 - clk = mmp_clk_register_apbc("uart0", "uart0_mux", 250 - apbc_base + APBC_UART0, 10, 0, &clk_lock); 251 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 252 - 253 - clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 254 - ARRAY_SIZE(uart_parent), 255 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 256 - apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 257 - clk_set_parent(clk, vctcxo); 258 - clk_register_clkdev(clk, "uart_mux.1", NULL); 259 - 260 - clk = mmp_clk_register_apbc("uart1", "uart1_mux", 261 - apbc_base + APBC_UART1, 10, 0, &clk_lock); 262 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 263 - 264 - clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 265 - ARRAY_SIZE(uart_parent), 266 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 267 - apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); 268 - clk_set_parent(clk, vctcxo); 269 - clk_register_clkdev(clk, "uart_mux.2", NULL); 270 - 271 - clk = mmp_clk_register_apbc("uart2", "uart2_mux", 272 - apbc_base + APBC_UART2, 10, 0, &clk_lock); 273 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 274 - 275 - clk = clk_register_mux(NULL, "uart3_mux", uart_parent, 276 - ARRAY_SIZE(uart_parent), 277 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 278 - apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); 279 - clk_set_parent(clk, vctcxo); 280 - clk_register_clkdev(clk, "uart_mux.3", NULL); 281 - 282 - clk = mmp_clk_register_apbc("uart3", "uart3_mux", 283 - apbc_base + APBC_UART3, 10, 0, &clk_lock); 284 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); 285 - 286 - clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 287 - ARRAY_SIZE(ssp_parent), 288 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 289 - apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 290 - clk_register_clkdev(clk, "uart_mux.0", NULL); 291 - 292 - clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", 293 - apbc_base + APBC_SSP0, 10, 0, &clk_lock); 294 - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 295 - 296 - clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 297 - ARRAY_SIZE(ssp_parent), 298 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 299 - apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 300 - clk_register_clkdev(clk, "ssp_mux.1", NULL); 301 - 302 - clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", 303 - apbc_base + APBC_SSP1, 10, 0, &clk_lock); 304 - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 305 - 306 - clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, 307 - ARRAY_SIZE(ssp_parent), 308 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 309 - apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); 310 - clk_register_clkdev(clk, "ssp_mux.2", NULL); 311 - 312 - clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", 313 - apbc_base + APBC_SSP2, 10, 0, &clk_lock); 314 - clk_register_clkdev(clk, NULL, "mmp-ssp.2"); 315 - 316 - clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, 317 - ARRAY_SIZE(ssp_parent), 318 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 319 - apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); 320 - clk_register_clkdev(clk, "ssp_mux.3", NULL); 321 - 322 - clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", 323 - apbc_base + APBC_SSP3, 10, 0, &clk_lock); 324 - clk_register_clkdev(clk, NULL, "mmp-ssp.3"); 325 - 326 - clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, 327 - ARRAY_SIZE(sdh_parent), 328 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 329 - apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); 330 - clk_register_clkdev(clk, "sdh_mux", NULL); 331 - 332 - clk = clk_register_divider(NULL, "sdh_div", "sdh_mux", 333 - CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, 334 - 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); 335 - clk_register_clkdev(clk, "sdh_div", NULL); 336 - 337 - clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, 338 - 0x1b, &clk_lock); 339 - clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); 340 - 341 - clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, 342 - 0x1b, &clk_lock); 343 - clk_register_clkdev(clk, NULL, "sdhci-pxav3.1"); 344 - 345 - clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2, 346 - 0x1b, &clk_lock); 347 - clk_register_clkdev(clk, NULL, "sdhci-pxav3.2"); 348 - 349 - clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3, 350 - 0x1b, &clk_lock); 351 - clk_register_clkdev(clk, NULL, "sdhci-pxav3.3"); 352 - 353 - clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 354 - 0x9, &clk_lock); 355 - clk_register_clkdev(clk, "usb_clk", NULL); 356 - 357 - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 358 - ARRAY_SIZE(disp_parent), 359 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 360 - apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); 361 - clk_register_clkdev(clk, "disp_mux.0", NULL); 362 - 363 - clk = clk_register_divider(NULL, "disp0_div", "disp0_mux", 364 - CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, 365 - 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); 366 - clk_register_clkdev(clk, "disp_div.0", NULL); 367 - 368 - clk = mmp_clk_register_apmu("disp0", "disp0_div", 369 - apmu_base + APMU_DISP0, 0x1b, &clk_lock); 370 - clk_register_clkdev(clk, NULL, "mmp-disp.0"); 371 - 372 - clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, 373 - apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); 374 - clk_register_clkdev(clk, "disp_sphy_div.0", NULL); 375 - 376 - clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div", 377 - apmu_base + APMU_DISP0, 0x1024, &clk_lock); 378 - clk_register_clkdev(clk, "disp_sphy.0", NULL); 379 - 380 - clk = clk_register_mux(NULL, "disp1_mux", disp_parent, 381 - ARRAY_SIZE(disp_parent), 382 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 383 - apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); 384 - clk_register_clkdev(clk, "disp_mux.1", NULL); 385 - 386 - clk = clk_register_divider(NULL, "disp1_div", "disp1_mux", 387 - CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, 388 - 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); 389 - clk_register_clkdev(clk, "disp_div.1", NULL); 390 - 391 - clk = mmp_clk_register_apmu("disp1", "disp1_div", 392 - apmu_base + APMU_DISP1, 0x1b, &clk_lock); 393 - clk_register_clkdev(clk, NULL, "mmp-disp.1"); 394 - 395 - clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo", 396 - apmu_base + APMU_CCIC0, 0x1800, &clk_lock); 397 - clk_register_clkdev(clk, "ccic_arbiter", NULL); 398 - 399 - clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 400 - ARRAY_SIZE(ccic_parent), 401 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 402 - apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); 403 - clk_register_clkdev(clk, "ccic_mux.0", NULL); 404 - 405 - clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux", 406 - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 407 - 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); 408 - clk_register_clkdev(clk, "ccic_div.0", NULL); 409 - 410 - clk = mmp_clk_register_apmu("ccic0", "ccic0_div", 411 - apmu_base + APMU_CCIC0, 0x1b, &clk_lock); 412 - clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); 413 - 414 - clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div", 415 - apmu_base + APMU_CCIC0, 0x24, &clk_lock); 416 - clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); 417 - 418 - clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div", 419 - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 420 - 10, 5, 0, &clk_lock); 421 - clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); 422 - 423 - clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", 424 - apmu_base + APMU_CCIC0, 0x300, &clk_lock); 425 - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); 426 - 427 - clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, 428 - ARRAY_SIZE(ccic_parent), 429 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 430 - apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); 431 - clk_register_clkdev(clk, "ccic_mux.1", NULL); 432 - 433 - clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux", 434 - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, 435 - 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); 436 - clk_register_clkdev(clk, "ccic_div.1", NULL); 437 - 438 - clk = mmp_clk_register_apmu("ccic1", "ccic1_div", 439 - apmu_base + APMU_CCIC1, 0x1b, &clk_lock); 440 - clk_register_clkdev(clk, "fnclk", "mmp-ccic.1"); 441 - 442 - clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div", 443 - apmu_base + APMU_CCIC1, 0x24, &clk_lock); 444 - clk_register_clkdev(clk, "phyclk", "mmp-ccic.1"); 445 - 446 - clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div", 447 - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, 448 - 10, 5, 0, &clk_lock); 449 - clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1"); 450 - 451 - clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div", 452 - apmu_base + APMU_CCIC1, 0x300, &clk_lock); 453 - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1"); 454 - }

-354

drivers/clk/mmp/clk-pxa168.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * pxa168 clock framework source file 4 - * 5 - * Copyright (C) 2012 Marvell 6 - * Chao Xie <xiechao.mail@gmail.com> 7 - */ 8 - 9 - #include <linux/clk.h> 10 - #include <linux/clk/mmp.h> 11 - #include <linux/module.h> 12 - #include <linux/kernel.h> 13 - #include <linux/spinlock.h> 14 - #include <linux/io.h> 15 - #include <linux/delay.h> 16 - #include <linux/err.h> 17 - 18 - #include "clk.h" 19 - 20 - #define APBC_RTC 0x28 21 - #define APBC_TWSI0 0x2c 22 - #define APBC_KPC 0x30 23 - #define APBC_UART0 0x0 24 - #define APBC_UART1 0x4 25 - #define APBC_GPIO 0x8 26 - #define APBC_PWM0 0xc 27 - #define APBC_PWM1 0x10 28 - #define APBC_PWM2 0x14 29 - #define APBC_PWM3 0x18 30 - #define APBC_SSP0 0x81c 31 - #define APBC_SSP1 0x820 32 - #define APBC_SSP2 0x84c 33 - #define APBC_SSP3 0x858 34 - #define APBC_SSP4 0x85c 35 - #define APBC_TWSI1 0x6c 36 - #define APBC_UART2 0x70 37 - #define APMU_SDH0 0x54 38 - #define APMU_SDH1 0x58 39 - #define APMU_USB 0x5c 40 - #define APMU_DISP0 0x4c 41 - #define APMU_CCIC0 0x50 42 - #define APMU_DFC 0x60 43 - #define MPMU_UART_PLL 0x14 44 - 45 - static DEFINE_SPINLOCK(clk_lock); 46 - 47 - static struct mmp_clk_factor_masks uart_factor_masks = { 48 - .factor = 2, 49 - .num_mask = 0x1fff, 50 - .den_mask = 0x1fff, 51 - .num_shift = 16, 52 - .den_shift = 0, 53 - }; 54 - 55 - static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 56 - {.num = 8125, .den = 1536}, /*14.745MHZ */ 57 - }; 58 - 59 - static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; 60 - static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; 61 - static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; 62 - static const char *disp_parent[] = {"pll1_2", "pll1_12"}; 63 - static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; 64 - static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; 65 - 66 - void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, 67 - phys_addr_t apbc_phys) 68 - { 69 - struct clk *clk; 70 - struct clk *uart_pll; 71 - void __iomem *mpmu_base; 72 - void __iomem *apmu_base; 73 - void __iomem *apbc_base; 74 - 75 - mpmu_base = ioremap(mpmu_phys, SZ_4K); 76 - if (!mpmu_base) { 77 - pr_err("error to ioremap MPMU base\n"); 78 - return; 79 - } 80 - 81 - apmu_base = ioremap(apmu_phys, SZ_4K); 82 - if (!apmu_base) { 83 - pr_err("error to ioremap APMU base\n"); 84 - return; 85 - } 86 - 87 - apbc_base = ioremap(apbc_phys, SZ_4K); 88 - if (!apbc_base) { 89 - pr_err("error to ioremap APBC base\n"); 90 - return; 91 - } 92 - 93 - clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); 94 - clk_register_clkdev(clk, "clk32", NULL); 95 - 96 - clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); 97 - clk_register_clkdev(clk, "vctcxo", NULL); 98 - 99 - clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); 100 - clk_register_clkdev(clk, "pll1", NULL); 101 - 102 - clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", 103 - CLK_SET_RATE_PARENT, 1, 2); 104 - clk_register_clkdev(clk, "pll1_2", NULL); 105 - 106 - clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", 107 - CLK_SET_RATE_PARENT, 1, 2); 108 - clk_register_clkdev(clk, "pll1_4", NULL); 109 - 110 - clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", 111 - CLK_SET_RATE_PARENT, 1, 2); 112 - clk_register_clkdev(clk, "pll1_8", NULL); 113 - 114 - clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", 115 - CLK_SET_RATE_PARENT, 1, 2); 116 - clk_register_clkdev(clk, "pll1_16", NULL); 117 - 118 - clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", 119 - CLK_SET_RATE_PARENT, 1, 3); 120 - clk_register_clkdev(clk, "pll1_6", NULL); 121 - 122 - clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", 123 - CLK_SET_RATE_PARENT, 1, 2); 124 - clk_register_clkdev(clk, "pll1_12", NULL); 125 - 126 - clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", 127 - CLK_SET_RATE_PARENT, 1, 2); 128 - clk_register_clkdev(clk, "pll1_24", NULL); 129 - 130 - clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", 131 - CLK_SET_RATE_PARENT, 1, 2); 132 - clk_register_clkdev(clk, "pll1_48", NULL); 133 - 134 - clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", 135 - CLK_SET_RATE_PARENT, 1, 2); 136 - clk_register_clkdev(clk, "pll1_96", NULL); 137 - 138 - clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", 139 - CLK_SET_RATE_PARENT, 1, 13); 140 - clk_register_clkdev(clk, "pll1_13", NULL); 141 - 142 - clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", 143 - CLK_SET_RATE_PARENT, 2, 3); 144 - clk_register_clkdev(clk, "pll1_13_1_5", NULL); 145 - 146 - clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", 147 - CLK_SET_RATE_PARENT, 2, 3); 148 - clk_register_clkdev(clk, "pll1_2_1_5", NULL); 149 - 150 - clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", 151 - CLK_SET_RATE_PARENT, 3, 16); 152 - clk_register_clkdev(clk, "pll1_3_16", NULL); 153 - 154 - uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, 155 - mpmu_base + MPMU_UART_PLL, 156 - &uart_factor_masks, uart_factor_tbl, 157 - ARRAY_SIZE(uart_factor_tbl), &clk_lock); 158 - clk_set_rate(uart_pll, 14745600); 159 - clk_register_clkdev(uart_pll, "uart_pll", NULL); 160 - 161 - clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", 162 - apbc_base + APBC_TWSI0, 10, 0, &clk_lock); 163 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); 164 - 165 - clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", 166 - apbc_base + APBC_TWSI1, 10, 0, &clk_lock); 167 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); 168 - 169 - clk = mmp_clk_register_apbc("gpio", "vctcxo", 170 - apbc_base + APBC_GPIO, 10, 0, &clk_lock); 171 - clk_register_clkdev(clk, NULL, "mmp-gpio"); 172 - 173 - clk = mmp_clk_register_apbc("kpc", "clk32", 174 - apbc_base + APBC_KPC, 10, 0, &clk_lock); 175 - clk_register_clkdev(clk, NULL, "pxa27x-keypad"); 176 - 177 - clk = mmp_clk_register_apbc("rtc", "clk32", 178 - apbc_base + APBC_RTC, 10, 0, &clk_lock); 179 - clk_register_clkdev(clk, NULL, "sa1100-rtc"); 180 - 181 - clk = mmp_clk_register_apbc("pwm0", "pll1_48", 182 - apbc_base + APBC_PWM0, 10, 0, &clk_lock); 183 - clk_register_clkdev(clk, NULL, "pxa168-pwm.0"); 184 - 185 - clk = mmp_clk_register_apbc("pwm1", "pll1_48", 186 - apbc_base + APBC_PWM1, 10, 0, &clk_lock); 187 - clk_register_clkdev(clk, NULL, "pxa168-pwm.1"); 188 - 189 - clk = mmp_clk_register_apbc("pwm2", "pll1_48", 190 - apbc_base + APBC_PWM2, 10, 0, &clk_lock); 191 - clk_register_clkdev(clk, NULL, "pxa168-pwm.2"); 192 - 193 - clk = mmp_clk_register_apbc("pwm3", "pll1_48", 194 - apbc_base + APBC_PWM3, 10, 0, &clk_lock); 195 - clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); 196 - 197 - clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 198 - ARRAY_SIZE(uart_parent), 199 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 200 - apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 201 - clk_set_parent(clk, uart_pll); 202 - clk_register_clkdev(clk, "uart_mux.0", NULL); 203 - 204 - clk = mmp_clk_register_apbc("uart0", "uart0_mux", 205 - apbc_base + APBC_UART0, 10, 0, &clk_lock); 206 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 207 - 208 - clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 209 - ARRAY_SIZE(uart_parent), 210 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 211 - apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 212 - clk_set_parent(clk, uart_pll); 213 - clk_register_clkdev(clk, "uart_mux.1", NULL); 214 - 215 - clk = mmp_clk_register_apbc("uart1", "uart1_mux", 216 - apbc_base + APBC_UART1, 10, 0, &clk_lock); 217 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 218 - 219 - clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 220 - ARRAY_SIZE(uart_parent), 221 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 222 - apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); 223 - clk_set_parent(clk, uart_pll); 224 - clk_register_clkdev(clk, "uart_mux.2", NULL); 225 - 226 - clk = mmp_clk_register_apbc("uart2", "uart2_mux", 227 - apbc_base + APBC_UART2, 10, 0, &clk_lock); 228 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 229 - 230 - clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 231 - ARRAY_SIZE(ssp_parent), 232 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 233 - apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 234 - clk_register_clkdev(clk, "uart_mux.0", NULL); 235 - 236 - clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, 237 - 10, 0, &clk_lock); 238 - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 239 - 240 - clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 241 - ARRAY_SIZE(ssp_parent), 242 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 243 - apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 244 - clk_register_clkdev(clk, "ssp_mux.1", NULL); 245 - 246 - clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, 247 - 10, 0, &clk_lock); 248 - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 249 - 250 - clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, 251 - ARRAY_SIZE(ssp_parent), 252 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 253 - apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); 254 - clk_register_clkdev(clk, "ssp_mux.2", NULL); 255 - 256 - clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, 257 - 10, 0, &clk_lock); 258 - clk_register_clkdev(clk, NULL, "mmp-ssp.2"); 259 - 260 - clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, 261 - ARRAY_SIZE(ssp_parent), 262 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 263 - apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); 264 - clk_register_clkdev(clk, "ssp_mux.3", NULL); 265 - 266 - clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, 267 - 10, 0, &clk_lock); 268 - clk_register_clkdev(clk, NULL, "mmp-ssp.3"); 269 - 270 - clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, 271 - ARRAY_SIZE(ssp_parent), 272 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 273 - apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); 274 - clk_register_clkdev(clk, "ssp_mux.4", NULL); 275 - 276 - clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, 277 - 10, 0, &clk_lock); 278 - clk_register_clkdev(clk, NULL, "mmp-ssp.4"); 279 - 280 - clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, 281 - 0x19b, &clk_lock); 282 - clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); 283 - 284 - clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, 285 - ARRAY_SIZE(sdh_parent), 286 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 287 - apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); 288 - clk_register_clkdev(clk, "sdh0_mux", NULL); 289 - 290 - clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, 291 - 0x1b, &clk_lock); 292 - clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); 293 - 294 - clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, 295 - ARRAY_SIZE(sdh_parent), 296 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 297 - apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); 298 - clk_register_clkdev(clk, "sdh1_mux", NULL); 299 - 300 - clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, 301 - 0x1b, &clk_lock); 302 - clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); 303 - 304 - clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, 305 - 0x9, &clk_lock); 306 - clk_register_clkdev(clk, "usb_clk", NULL); 307 - 308 - clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, 309 - 0x12, &clk_lock); 310 - clk_register_clkdev(clk, "sph_clk", NULL); 311 - 312 - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 313 - ARRAY_SIZE(disp_parent), 314 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 315 - apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); 316 - clk_register_clkdev(clk, "disp_mux.0", NULL); 317 - 318 - clk = mmp_clk_register_apmu("disp0", "disp0_mux", 319 - apmu_base + APMU_DISP0, 0x1b, &clk_lock); 320 - clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); 321 - 322 - clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", 323 - apmu_base + APMU_DISP0, 0x24, &clk_lock); 324 - clk_register_clkdev(clk, "hclk", "mmp-disp.0"); 325 - 326 - clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 327 - ARRAY_SIZE(ccic_parent), 328 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 329 - apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); 330 - clk_register_clkdev(clk, "ccic_mux.0", NULL); 331 - 332 - clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", 333 - apmu_base + APMU_CCIC0, 0x1b, &clk_lock); 334 - clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); 335 - 336 - clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, 337 - ARRAY_SIZE(ccic_phy_parent), 338 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 339 - apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); 340 - clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); 341 - 342 - clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", 343 - apmu_base + APMU_CCIC0, 0x24, &clk_lock); 344 - clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); 345 - 346 - clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", 347 - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 348 - 10, 5, 0, &clk_lock); 349 - clk_register_clkdev(clk, "sphyclk_div", NULL); 350 - 351 - clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", 352 - apmu_base + APMU_CCIC0, 0x300, &clk_lock); 353 - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); 354 - }

-325

drivers/clk/mmp/clk-pxa910.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * pxa910 clock framework source file 4 - * 5 - * Copyright (C) 2012 Marvell 6 - * Chao Xie <xiechao.mail@gmail.com> 7 - */ 8 - 9 - #include <linux/clk.h> 10 - #include <linux/clk/mmp.h> 11 - #include <linux/module.h> 12 - #include <linux/kernel.h> 13 - #include <linux/spinlock.h> 14 - #include <linux/io.h> 15 - #include <linux/delay.h> 16 - #include <linux/err.h> 17 - 18 - #include "clk.h" 19 - 20 - #define APBC_RTC 0x28 21 - #define APBC_TWSI0 0x2c 22 - #define APBC_KPC 0x18 23 - #define APBC_UART0 0x0 24 - #define APBC_UART1 0x4 25 - #define APBC_GPIO 0x8 26 - #define APBC_PWM0 0xc 27 - #define APBC_PWM1 0x10 28 - #define APBC_PWM2 0x14 29 - #define APBC_PWM3 0x18 30 - #define APBC_SSP0 0x1c 31 - #define APBC_SSP1 0x20 32 - #define APBC_SSP2 0x4c 33 - #define APBCP_TWSI1 0x28 34 - #define APBCP_UART2 0x1c 35 - #define APMU_SDH0 0x54 36 - #define APMU_SDH1 0x58 37 - #define APMU_USB 0x5c 38 - #define APMU_DISP0 0x4c 39 - #define APMU_CCIC0 0x50 40 - #define APMU_DFC 0x60 41 - #define MPMU_UART_PLL 0x14 42 - 43 - static DEFINE_SPINLOCK(clk_lock); 44 - 45 - static struct mmp_clk_factor_masks uart_factor_masks = { 46 - .factor = 2, 47 - .num_mask = 0x1fff, 48 - .den_mask = 0x1fff, 49 - .num_shift = 16, 50 - .den_shift = 0, 51 - }; 52 - 53 - static struct mmp_clk_factor_tbl uart_factor_tbl[] = { 54 - {.num = 8125, .den = 1536}, /*14.745MHZ */ 55 - }; 56 - 57 - static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; 58 - static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; 59 - static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; 60 - static const char *disp_parent[] = {"pll1_2", "pll1_12"}; 61 - static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; 62 - static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; 63 - 64 - void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys, 65 - phys_addr_t apbc_phys, phys_addr_t apbcp_phys) 66 - { 67 - struct clk *clk; 68 - struct clk *uart_pll; 69 - void __iomem *mpmu_base; 70 - void __iomem *apmu_base; 71 - void __iomem *apbcp_base; 72 - void __iomem *apbc_base; 73 - 74 - mpmu_base = ioremap(mpmu_phys, SZ_4K); 75 - if (!mpmu_base) { 76 - pr_err("error to ioremap MPMU base\n"); 77 - return; 78 - } 79 - 80 - apmu_base = ioremap(apmu_phys, SZ_4K); 81 - if (!apmu_base) { 82 - pr_err("error to ioremap APMU base\n"); 83 - return; 84 - } 85 - 86 - apbcp_base = ioremap(apbcp_phys, SZ_4K); 87 - if (!apbcp_base) { 88 - pr_err("error to ioremap APBC extension base\n"); 89 - return; 90 - } 91 - 92 - apbc_base = ioremap(apbc_phys, SZ_4K); 93 - if (!apbc_base) { 94 - pr_err("error to ioremap APBC base\n"); 95 - return; 96 - } 97 - 98 - clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); 99 - clk_register_clkdev(clk, "clk32", NULL); 100 - 101 - clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); 102 - clk_register_clkdev(clk, "vctcxo", NULL); 103 - 104 - clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); 105 - clk_register_clkdev(clk, "pll1", NULL); 106 - 107 - clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", 108 - CLK_SET_RATE_PARENT, 1, 2); 109 - clk_register_clkdev(clk, "pll1_2", NULL); 110 - 111 - clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", 112 - CLK_SET_RATE_PARENT, 1, 2); 113 - clk_register_clkdev(clk, "pll1_4", NULL); 114 - 115 - clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", 116 - CLK_SET_RATE_PARENT, 1, 2); 117 - clk_register_clkdev(clk, "pll1_8", NULL); 118 - 119 - clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", 120 - CLK_SET_RATE_PARENT, 1, 2); 121 - clk_register_clkdev(clk, "pll1_16", NULL); 122 - 123 - clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", 124 - CLK_SET_RATE_PARENT, 1, 3); 125 - clk_register_clkdev(clk, "pll1_6", NULL); 126 - 127 - clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", 128 - CLK_SET_RATE_PARENT, 1, 2); 129 - clk_register_clkdev(clk, "pll1_12", NULL); 130 - 131 - clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", 132 - CLK_SET_RATE_PARENT, 1, 2); 133 - clk_register_clkdev(clk, "pll1_24", NULL); 134 - 135 - clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", 136 - CLK_SET_RATE_PARENT, 1, 2); 137 - clk_register_clkdev(clk, "pll1_48", NULL); 138 - 139 - clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", 140 - CLK_SET_RATE_PARENT, 1, 2); 141 - clk_register_clkdev(clk, "pll1_96", NULL); 142 - 143 - clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", 144 - CLK_SET_RATE_PARENT, 1, 13); 145 - clk_register_clkdev(clk, "pll1_13", NULL); 146 - 147 - clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", 148 - CLK_SET_RATE_PARENT, 2, 3); 149 - clk_register_clkdev(clk, "pll1_13_1_5", NULL); 150 - 151 - clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", 152 - CLK_SET_RATE_PARENT, 2, 3); 153 - clk_register_clkdev(clk, "pll1_2_1_5", NULL); 154 - 155 - clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", 156 - CLK_SET_RATE_PARENT, 3, 16); 157 - clk_register_clkdev(clk, "pll1_3_16", NULL); 158 - 159 - uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, 160 - mpmu_base + MPMU_UART_PLL, 161 - &uart_factor_masks, uart_factor_tbl, 162 - ARRAY_SIZE(uart_factor_tbl), &clk_lock); 163 - clk_set_rate(uart_pll, 14745600); 164 - clk_register_clkdev(uart_pll, "uart_pll", NULL); 165 - 166 - clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", 167 - apbc_base + APBC_TWSI0, 10, 0, &clk_lock); 168 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); 169 - 170 - clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", 171 - apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock); 172 - clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); 173 - 174 - clk = mmp_clk_register_apbc("gpio", "vctcxo", 175 - apbc_base + APBC_GPIO, 10, 0, &clk_lock); 176 - clk_register_clkdev(clk, NULL, "mmp-gpio"); 177 - 178 - clk = mmp_clk_register_apbc("kpc", "clk32", 179 - apbc_base + APBC_KPC, 10, 0, &clk_lock); 180 - clk_register_clkdev(clk, NULL, "pxa27x-keypad"); 181 - 182 - clk = mmp_clk_register_apbc("rtc", "clk32", 183 - apbc_base + APBC_RTC, 10, 0, &clk_lock); 184 - clk_register_clkdev(clk, NULL, "sa1100-rtc"); 185 - 186 - clk = mmp_clk_register_apbc("pwm0", "pll1_48", 187 - apbc_base + APBC_PWM0, 10, 0, &clk_lock); 188 - clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); 189 - 190 - clk = mmp_clk_register_apbc("pwm1", "pll1_48", 191 - apbc_base + APBC_PWM1, 10, 0, &clk_lock); 192 - clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); 193 - 194 - clk = mmp_clk_register_apbc("pwm2", "pll1_48", 195 - apbc_base + APBC_PWM2, 10, 0, &clk_lock); 196 - clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); 197 - 198 - clk = mmp_clk_register_apbc("pwm3", "pll1_48", 199 - apbc_base + APBC_PWM3, 10, 0, &clk_lock); 200 - clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); 201 - 202 - clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 203 - ARRAY_SIZE(uart_parent), 204 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 205 - apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 206 - clk_set_parent(clk, uart_pll); 207 - clk_register_clkdev(clk, "uart_mux.0", NULL); 208 - 209 - clk = mmp_clk_register_apbc("uart0", "uart0_mux", 210 - apbc_base + APBC_UART0, 10, 0, &clk_lock); 211 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 212 - 213 - clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 214 - ARRAY_SIZE(uart_parent), 215 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 216 - apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 217 - clk_set_parent(clk, uart_pll); 218 - clk_register_clkdev(clk, "uart_mux.1", NULL); 219 - 220 - clk = mmp_clk_register_apbc("uart1", "uart1_mux", 221 - apbc_base + APBC_UART1, 10, 0, &clk_lock); 222 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 223 - 224 - clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 225 - ARRAY_SIZE(uart_parent), 226 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 227 - apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); 228 - clk_set_parent(clk, uart_pll); 229 - clk_register_clkdev(clk, "uart_mux.2", NULL); 230 - 231 - clk = mmp_clk_register_apbc("uart2", "uart2_mux", 232 - apbcp_base + APBCP_UART2, 10, 0, &clk_lock); 233 - clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 234 - 235 - clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 236 - ARRAY_SIZE(ssp_parent), 237 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 238 - apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 239 - clk_register_clkdev(clk, "uart_mux.0", NULL); 240 - 241 - clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", 242 - apbc_base + APBC_SSP0, 10, 0, &clk_lock); 243 - clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 244 - 245 - clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 246 - ARRAY_SIZE(ssp_parent), 247 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 248 - apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 249 - clk_register_clkdev(clk, "ssp_mux.1", NULL); 250 - 251 - clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", 252 - apbc_base + APBC_SSP1, 10, 0, &clk_lock); 253 - clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 254 - 255 - clk = mmp_clk_register_apmu("dfc", "pll1_4", 256 - apmu_base + APMU_DFC, 0x19b, &clk_lock); 257 - clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); 258 - 259 - clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, 260 - ARRAY_SIZE(sdh_parent), 261 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 262 - apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); 263 - clk_register_clkdev(clk, "sdh0_mux", NULL); 264 - 265 - clk = mmp_clk_register_apmu("sdh0", "sdh_mux", 266 - apmu_base + APMU_SDH0, 0x1b, &clk_lock); 267 - clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); 268 - 269 - clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, 270 - ARRAY_SIZE(sdh_parent), 271 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 272 - apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); 273 - clk_register_clkdev(clk, "sdh1_mux", NULL); 274 - 275 - clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", 276 - apmu_base + APMU_SDH1, 0x1b, &clk_lock); 277 - clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); 278 - 279 - clk = mmp_clk_register_apmu("usb", "usb_pll", 280 - apmu_base + APMU_USB, 0x9, &clk_lock); 281 - clk_register_clkdev(clk, "usb_clk", NULL); 282 - 283 - clk = mmp_clk_register_apmu("sph", "usb_pll", 284 - apmu_base + APMU_USB, 0x12, &clk_lock); 285 - clk_register_clkdev(clk, "sph_clk", NULL); 286 - 287 - clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 288 - ARRAY_SIZE(disp_parent), 289 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 290 - apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); 291 - clk_register_clkdev(clk, "disp_mux.0", NULL); 292 - 293 - clk = mmp_clk_register_apmu("disp0", "disp0_mux", 294 - apmu_base + APMU_DISP0, 0x1b, &clk_lock); 295 - clk_register_clkdev(clk, NULL, "mmp-disp.0"); 296 - 297 - clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 298 - ARRAY_SIZE(ccic_parent), 299 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 300 - apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); 301 - clk_register_clkdev(clk, "ccic_mux.0", NULL); 302 - 303 - clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", 304 - apmu_base + APMU_CCIC0, 0x1b, &clk_lock); 305 - clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); 306 - 307 - clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, 308 - ARRAY_SIZE(ccic_phy_parent), 309 - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 310 - apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); 311 - clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); 312 - 313 - clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", 314 - apmu_base + APMU_CCIC0, 0x24, &clk_lock); 315 - clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); 316 - 317 - clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", 318 - CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 319 - 10, 5, 0, &clk_lock); 320 - clk_register_clkdev(clk, "sphyclk_div", NULL); 321 - 322 - clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", 323 - apmu_base + APMU_CCIC0, 0x300, &clk_lock); 324 - clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); 325 - }

-18

include/linux/clk/mmp.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - #ifndef __CLK_MMP_H 3 - #define __CLK_MMP_H 4 - 5 - #include <linux/types.h> 6 - 7 - extern void pxa168_clk_init(phys_addr_t mpmu_phys, 8 - phys_addr_t apmu_phys, 9 - phys_addr_t apbc_phys); 10 - extern void pxa910_clk_init(phys_addr_t mpmu_phys, 11 - phys_addr_t apmu_phys, 12 - phys_addr_t apbc_phys, 13 - phys_addr_t apbcp_phys); 14 - extern void mmp2_clk_init(phys_addr_t mpmu_phys, 15 - phys_addr_t apmu_phys, 16 - phys_addr_t apbc_phys); 17 - 18 - #endif

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