Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v5.13-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers
devapc:
- add missing MODULE_DEVICE_TABLE to fix modalias
mkt-pm-domains:
- register smi node as regmap and not as syscon
- prepare-enable and unprepare-disable dependent clocks
pwrap:
- add support for MT8195
* tag 'v5.13-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC
dt-bindings: mediatek: add compatible for MT8195 pwrap
soc: mtk-pm-domains: Fix the clock prepared issue
soc: mtk-pm-domains: do not register smi node as syscon
soc: mediatek: add missing MODULE_DEVICE_TABLE
Link: https://lore.kernel.org/r/479ec9ad-95d3-ce91-8243-63596c4c6676@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
+53
-26
+1
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+1
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
···
27
27
"mediatek,mt8135-pwrap" for MT8135 SoCs
28
28
"mediatek,mt8173-pwrap" for MT8173 SoCs
29
29
"mediatek,mt8183-pwrap" for MT8183 SoCs
30
+
"mediatek,mt8195-pwrap" for MT8195 SoCs
30
31
"mediatek,mt8516-pwrap" for MT8516 SoCs
31
32
- interrupts: IRQ for pwrap in SOC
32
33
- reg-names: Must include the following entries:
+1
drivers/soc/mediatek/mtk-devapc.c
+1
drivers/soc/mediatek/mtk-devapc.c
+16
-26
drivers/soc/mediatek/mtk-pm-domains.c
+16
-26
drivers/soc/mediatek/mtk-pm-domains.c
···
211
211
if (ret)
212
212
return ret;
213
213
214
-
ret = clk_bulk_enable(pd->num_clks, pd->clks);
214
+
ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks);
215
215
if (ret)
216
216
goto err_reg;
217
217
···
229
229
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
230
230
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
231
231
232
-
ret = clk_bulk_enable(pd->num_subsys_clks, pd->subsys_clks);
232
+
ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks);
233
233
if (ret)
234
234
goto err_pwr_ack;
235
235
···
246
246
err_disable_sram:
247
247
scpsys_sram_disable(pd);
248
248
err_disable_subsys_clks:
249
-
clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks);
249
+
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
250
250
err_pwr_ack:
251
-
clk_bulk_disable(pd->num_clks, pd->clks);
251
+
clk_bulk_disable_unprepare(pd->num_clks, pd->clks);
252
252
err_reg:
253
253
scpsys_regulator_disable(pd->supply);
254
254
return ret;
···
269
269
if (ret < 0)
270
270
return ret;
271
271
272
-
clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks);
272
+
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
273
273
274
274
/* subsys power off */
275
275
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
···
284
284
if (ret < 0)
285
285
return ret;
286
286
287
-
clk_bulk_disable(pd->num_clks, pd->clks);
287
+
clk_bulk_disable_unprepare(pd->num_clks, pd->clks);
288
288
289
289
scpsys_regulator_disable(pd->supply);
290
290
···
297
297
const struct scpsys_domain_data *domain_data;
298
298
struct scpsys_domain *pd;
299
299
struct device_node *root_node = scpsys->dev->of_node;
300
+
struct device_node *smi_node;
300
301
struct property *prop;
301
302
const char *clk_name;
302
303
int i, ret, num_clks;
···
353
352
if (IS_ERR(pd->infracfg))
354
353
return ERR_CAST(pd->infracfg);
355
354
356
-
pd->smi = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,smi");
357
-
if (IS_ERR(pd->smi))
358
-
return ERR_CAST(pd->smi);
355
+
smi_node = of_parse_phandle(node, "mediatek,smi", 0);
356
+
if (smi_node) {
357
+
pd->smi = device_node_to_regmap(smi_node);
358
+
of_node_put(smi_node);
359
+
if (IS_ERR(pd->smi))
360
+
return ERR_CAST(pd->smi);
361
+
}
359
362
360
363
num_clks = of_clk_get_parent_count(node);
361
364
if (num_clks > 0) {
···
410
405
pd->subsys_clks[i].clk = clk;
411
406
}
412
407
413
-
ret = clk_bulk_prepare(pd->num_clks, pd->clks);
414
-
if (ret)
415
-
goto err_put_subsys_clocks;
416
-
417
-
ret = clk_bulk_prepare(pd->num_subsys_clks, pd->subsys_clks);
418
-
if (ret)
419
-
goto err_unprepare_clocks;
420
-
421
408
/*
422
409
* Initially turn on all domains to make the domains usable
423
410
* with !CONFIG_PM and to get the hardware in sync with the
···
424
427
ret = scpsys_power_on(&pd->genpd);
425
428
if (ret < 0) {
426
429
dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret);
427
-
goto err_unprepare_clocks;
430
+
goto err_put_subsys_clocks;
428
431
}
429
432
}
430
433
···
432
435
ret = -EINVAL;
433
436
dev_err(scpsys->dev,
434
437
"power domain with id %d already exists, check your device-tree\n", id);
435
-
goto err_unprepare_subsys_clocks;
438
+
goto err_put_subsys_clocks;
436
439
}
437
440
438
441
if (!pd->data->name)
···
452
455
453
456
return scpsys->pd_data.domains[id];
454
457
455
-
err_unprepare_subsys_clocks:
456
-
clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks);
457
-
err_unprepare_clocks:
458
-
clk_bulk_unprepare(pd->num_clks, pd->clks);
459
458
err_put_subsys_clocks:
460
459
clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks);
461
460
err_put_clocks:
···
530
537
"failed to remove domain '%s' : %d - state may be inconsistent\n",
531
538
pd->genpd.name, ret);
532
539
533
-
clk_bulk_unprepare(pd->num_clks, pd->clks);
534
540
clk_bulk_put(pd->num_clks, pd->clks);
535
-
536
-
clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks);
537
541
clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks);
538
542
}
539
543
+35
drivers/soc/mediatek/mtk-pmic-wrap.c
+35
drivers/soc/mediatek/mtk-pmic-wrap.c
···
961
961
[PWRAP_WACS2_VLDCLR] = 0xC28,
962
962
};
963
963
964
+
static int mt8195_regs[] = {
965
+
[PWRAP_INIT_DONE2] = 0x0,
966
+
[PWRAP_STAUPD_CTRL] = 0x4C,
967
+
[PWRAP_TIMER_EN] = 0x3E4,
968
+
[PWRAP_INT_EN] = 0x420,
969
+
[PWRAP_INT_FLG] = 0x428,
970
+
[PWRAP_INT_CLR] = 0x42C,
971
+
[PWRAP_INT1_EN] = 0x450,
972
+
[PWRAP_INT1_FLG] = 0x458,
973
+
[PWRAP_INT1_CLR] = 0x45C,
974
+
[PWRAP_WACS2_CMD] = 0x880,
975
+
[PWRAP_SWINF_2_WDATA_31_0] = 0x884,
976
+
[PWRAP_SWINF_2_RDATA_31_0] = 0x894,
977
+
[PWRAP_WACS2_VLDCLR] = 0x8A4,
978
+
[PWRAP_WACS2_RDATA] = 0x8A8,
979
+
};
980
+
964
981
static int mt8516_regs[] = {
965
982
[PWRAP_MUX_SEL] = 0x0,
966
983
[PWRAP_WRAP_EN] = 0x4,
···
1083
1066
PWRAP_MT8135,
1084
1067
PWRAP_MT8173,
1085
1068
PWRAP_MT8183,
1069
+
PWRAP_MT8195,
1086
1070
PWRAP_MT8516,
1087
1071
};
1088
1072
···
1543
1525
break;
1544
1526
case PWRAP_MT6873:
1545
1527
case PWRAP_MT8183:
1528
+
case PWRAP_MT8195:
1546
1529
break;
1547
1530
}
1548
1531
···
2044
2025
.init_soc_specific = pwrap_mt8183_init_soc_specific,
2045
2026
};
2046
2027
2028
+
static struct pmic_wrapper_type pwrap_mt8195 = {
2029
+
.regs = mt8195_regs,
2030
+
.type = PWRAP_MT8195,
2031
+
.arb_en_all = 0x777f, /* NEED CONFIRM */
2032
+
.int_en_all = 0x180000, /* NEED CONFIRM */
2033
+
.int1_en_all = 0,
2034
+
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2035
+
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2036
+
.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,
2037
+
.init_reg_clock = pwrap_common_init_reg_clock,
2038
+
.init_soc_specific = NULL,
2039
+
};
2040
+
2047
2041
static struct pmic_wrapper_type pwrap_mt8516 = {
2048
2042
.regs = mt8516_regs,
2049
2043
.type = PWRAP_MT8516,
···
2097
2065
}, {
2098
2066
.compatible = "mediatek,mt8183-pwrap",
2099
2067
.data = &pwrap_mt8183,
2068
+
}, {
2069
+
.compatible = "mediatek,mt8195-pwrap",
2070
+
.data = &pwrap_mt8195,
2100
2071
}, {
2101
2072
.compatible = "mediatek,mt8516-pwrap",
2102
2073
.data = &pwrap_mt8516,