Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6745/1: kprobes insn decoding fix
ARM: tlb: move noMMU tlb_flush() to asm/tlb.h
ARM: tlb: delay page freeing for SMP and ARMv7 CPUs
ARM: Keep exit text/data around for SMP_ON_UP
ARM: Ensure predictable endian state on signal handler entry
ARM: 6740/1: Place correctly notes section in the linker script
ARM: 6700/1: SPEAr: Correct SOC config base address for spear320
ARM: 6722/1: SPEAr: sp810: switch to slow mode before reset
ARM: 6712/1: SPEAr: replace readl(), writel() with relaxed versions in uncompress.h
ARM: 6720/1: SPEAr: Append UL to VMALLOC_END
ARM: 6676/1: Correct the cpu_architecture() function for ARMv7
ARM: 6739/1: update .gitignore for boot/compressed
ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of broadcasted operation
ARM: 6742/1: pmu: avoid setting IRQ affinity on UP systems
ARM: 6741/1: errata: pl310 cache sync operation may be faulty
+175
-37
+25
arch/arm/Kconfig
+25
arch/arm/Kconfig
···
1177
1177
visible impact on the overall performance or power consumption of the
1178
1178
processor.
1179
1179
1180
+
config ARM_ERRATA_751472
1181
+
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1182
+
depends on CPU_V7 && SMP
1183
+
help
1184
+
This option enables the workaround for the 751472 Cortex-A9 (prior
1185
+
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1186
+
completion of a following broadcasted operation if the second
1187
+
operation is received by a CPU before the ICIALLUIS has completed,
1188
+
potentially leading to corrupted entries in the cache or TLB.
1189
+
1190
+
config ARM_ERRATA_753970
1191
+
bool "ARM errata: cache sync operation may be faulty"
1192
+
depends on CACHE_PL310
1193
+
help
1194
+
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1195
+
1196
+
Under some condition the effect of cache sync operation on
1197
+
the store buffer still remains when the operation completes.
1198
+
This means that the store buffer is always asked to drain and
1199
+
this prevents it from merging any further writes. The workaround
1200
+
is to replace the normal offset of cache sync operation (0x730)
1201
+
by another offset targeting an unmapped PL310 register 0x740.
1202
+
This has the same effect as the cache sync operation: store buffer
1203
+
drain and waiting for all buffers empty.
1204
+
1180
1205
endmenu
1181
1206
1182
1207
source "arch/arm/common/Kconfig"
+1
-1
arch/arm/Makefile
+1
-1
arch/arm/Makefile
···
15
15
LDFLAGS_vmlinux += --be8
16
16
endif
17
17
18
-
OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
18
+
OBJCOPYFLAGS :=-O binary -R .comment -S
19
19
GZFLAGS :=-9
20
20
#KBUILD_CFLAGS +=-pipe
21
21
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
+5
-1
arch/arm/boot/compressed/.gitignore
+5
-1
arch/arm/boot/compressed/.gitignore
+1
arch/arm/include/asm/hardware/cache-l2x0.h
+1
arch/arm/include/asm/hardware/cache-l2x0.h
+3
arch/arm/include/asm/hardware/sp810.h
+3
arch/arm/include/asm/hardware/sp810.h
+92
-13
arch/arm/include/asm/tlb.h
+92
-13
arch/arm/include/asm/tlb.h
···
18
18
#define __ASMARM_TLB_H
19
19
20
20
#include <asm/cacheflush.h>
21
-
#include <asm/tlbflush.h>
22
21
23
22
#ifndef CONFIG_MMU
24
23
25
24
#include <linux/pagemap.h>
25
+
26
+
#define tlb_flush(tlb) ((void) tlb)
27
+
26
28
#include <asm-generic/tlb.h>
27
29
28
30
#else /* !CONFIG_MMU */
29
31
32
+
#include <linux/swap.h>
30
33
#include <asm/pgalloc.h>
34
+
#include <asm/tlbflush.h>
35
+
36
+
/*
37
+
* We need to delay page freeing for SMP as other CPUs can access pages
38
+
* which have been removed but not yet had their TLB entries invalidated.
39
+
* Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
40
+
* we need to apply this same delaying tactic to ensure correct operation.
41
+
*/
42
+
#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
43
+
#define tlb_fast_mode(tlb) 0
44
+
#define FREE_PTE_NR 500
45
+
#else
46
+
#define tlb_fast_mode(tlb) 1
47
+
#define FREE_PTE_NR 0
48
+
#endif
31
49
32
50
/*
33
51
* TLB handling. This allows us to remove pages from the page
···
54
36
struct mmu_gather {
55
37
struct mm_struct *mm;
56
38
unsigned int fullmm;
39
+
struct vm_area_struct *vma;
57
40
unsigned long range_start;
58
41
unsigned long range_end;
42
+
unsigned int nr;
43
+
struct page *pages[FREE_PTE_NR];
59
44
};
60
45
61
46
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
47
+
48
+
/*
49
+
* This is unnecessarily complex. There's three ways the TLB shootdown
50
+
* code is used:
51
+
* 1. Unmapping a range of vmas. See zap_page_range(), unmap_region().
52
+
* tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
53
+
* tlb->vma will be non-NULL.
54
+
* 2. Unmapping all vmas. See exit_mmap().
55
+
* tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
56
+
* tlb->vma will be non-NULL. Additionally, page tables will be freed.
57
+
* 3. Unmapping argument pages. See shift_arg_pages().
58
+
* tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
59
+
* tlb->vma will be NULL.
60
+
*/
61
+
static inline void tlb_flush(struct mmu_gather *tlb)
62
+
{
63
+
if (tlb->fullmm || !tlb->vma)
64
+
flush_tlb_mm(tlb->mm);
65
+
else if (tlb->range_end > 0) {
66
+
flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
67
+
tlb->range_start = TASK_SIZE;
68
+
tlb->range_end = 0;
69
+
}
70
+
}
71
+
72
+
static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
73
+
{
74
+
if (!tlb->fullmm) {
75
+
if (addr < tlb->range_start)
76
+
tlb->range_start = addr;
77
+
if (addr + PAGE_SIZE > tlb->range_end)
78
+
tlb->range_end = addr + PAGE_SIZE;
79
+
}
80
+
}
81
+
82
+
static inline void tlb_flush_mmu(struct mmu_gather *tlb)
83
+
{
84
+
tlb_flush(tlb);
85
+
if (!tlb_fast_mode(tlb)) {
86
+
free_pages_and_swap_cache(tlb->pages, tlb->nr);
87
+
tlb->nr = 0;
88
+
}
89
+
}
62
90
63
91
static inline struct mmu_gather *
64
92
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
···
113
49
114
50
tlb->mm = mm;
115
51
tlb->fullmm = full_mm_flush;
52
+
tlb->vma = NULL;
53
+
tlb->nr = 0;
116
54
117
55
return tlb;
118
56
}
···
122
56
static inline void
123
57
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
124
58
{
125
-
if (tlb->fullmm)
126
-
flush_tlb_mm(tlb->mm);
59
+
tlb_flush_mmu(tlb);
127
60
128
61
/* keep the page table cache within bounds */
129
62
check_pgt_cache();
···
136
71
static inline void
137
72
tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
138
73
{
139
-
if (!tlb->fullmm) {
140
-
if (addr < tlb->range_start)
141
-
tlb->range_start = addr;
142
-
if (addr + PAGE_SIZE > tlb->range_end)
143
-
tlb->range_end = addr + PAGE_SIZE;
144
-
}
74
+
tlb_add_flush(tlb, addr);
145
75
}
146
76
147
77
/*
···
149
89
{
150
90
if (!tlb->fullmm) {
151
91
flush_cache_range(vma, vma->vm_start, vma->vm_end);
92
+
tlb->vma = vma;
152
93
tlb->range_start = TASK_SIZE;
153
94
tlb->range_end = 0;
154
95
}
···
158
97
static inline void
159
98
tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
160
99
{
161
-
if (!tlb->fullmm && tlb->range_end > 0)
162
-
flush_tlb_range(vma, tlb->range_start, tlb->range_end);
100
+
if (!tlb->fullmm)
101
+
tlb_flush(tlb);
163
102
}
164
103
165
-
#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
166
-
#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
104
+
static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
105
+
{
106
+
if (tlb_fast_mode(tlb)) {
107
+
free_page_and_swap_cache(page);
108
+
} else {
109
+
tlb->pages[tlb->nr++] = page;
110
+
if (tlb->nr >= FREE_PTE_NR)
111
+
tlb_flush_mmu(tlb);
112
+
}
113
+
}
114
+
115
+
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
116
+
unsigned long addr)
117
+
{
118
+
pgtable_page_dtor(pte);
119
+
tlb_add_flush(tlb, addr);
120
+
tlb_remove_page(tlb, pte);
121
+
}
122
+
123
+
#define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr)
167
124
#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
168
125
169
126
#define tlb_migrate_finish(mm) do { } while (0)
+1
-6
arch/arm/include/asm/tlbflush.h
+1
-6
arch/arm/include/asm/tlbflush.h
+1
-1
arch/arm/kernel/kprobes-decode.c
+1
-1
arch/arm/kernel/kprobes-decode.c
+14
-8
arch/arm/kernel/pmu.c
+14
-8
arch/arm/kernel/pmu.c
···
97
97
irq, cpu);
98
98
return err;
99
99
#else
100
-
return 0;
100
+
return -EINVAL;
101
101
#endif
102
102
}
103
103
104
104
static int
105
105
init_cpu_pmu(void)
106
106
{
107
-
int i, err = 0;
107
+
int i, irqs, err = 0;
108
108
struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
109
109
110
-
if (!pdev) {
111
-
err = -ENODEV;
112
-
goto out;
113
-
}
110
+
if (!pdev)
111
+
return -ENODEV;
114
112
115
-
for (i = 0; i < pdev->num_resources; ++i) {
113
+
irqs = pdev->num_resources;
114
+
115
+
/*
116
+
* If we have a single PMU interrupt that we can't shift, assume that
117
+
* we're running on a uniprocessor machine and continue.
118
+
*/
119
+
if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
120
+
return 0;
121
+
122
+
for (i = 0; i < irqs; ++i) {
116
123
err = set_irq_affinity(platform_get_irq(pdev, i), i);
117
124
if (err)
118
125
break;
119
126
}
120
127
121
-
out:
122
128
return err;
123
129
}
124
130
+2
-2
arch/arm/kernel/setup.c
+2
-2
arch/arm/kernel/setup.c
···
226
226
* Register 0 and check for VMSAv7 or PMSAv7 */
227
227
asm("mrc p15, 0, %0, c0, c1, 4"
228
228
: "=r" (mmfr0));
229
-
if ((mmfr0 & 0x0000000f) == 0x00000003 ||
230
-
(mmfr0 & 0x000000f0) == 0x00000030)
229
+
if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
230
+
(mmfr0 & 0x000000f0) >= 0x00000030)
231
231
cpu_arch = CPU_ARCH_ARMv7;
232
232
else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
233
233
(mmfr0 & 0x000000f0) == 0x00000020)
+3
-1
arch/arm/kernel/signal.c
+3
-1
arch/arm/kernel/signal.c
···
474
474
unsigned long handler = (unsigned long)ka->sa.sa_handler;
475
475
unsigned long retcode;
476
476
int thumb = 0;
477
-
unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
477
+
unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
478
+
479
+
cpsr |= PSR_ENDSTATE;
478
480
479
481
/*
480
482
* Maybe we need to deliver a 32-bit signal to a 26-bit task.
+11
arch/arm/kernel/vmlinux.lds.S
+11
arch/arm/kernel/vmlinux.lds.S
···
21
21
#define ARM_CPU_KEEP(x)
22
22
#endif
23
23
24
+
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
25
+
#define ARM_EXIT_KEEP(x) x
26
+
#else
27
+
#define ARM_EXIT_KEEP(x)
28
+
#endif
29
+
24
30
OUTPUT_ARCH(arm)
25
31
ENTRY(stext)
26
32
···
49
43
_sinittext = .;
50
44
HEAD_TEXT
51
45
INIT_TEXT
46
+
ARM_EXIT_KEEP(EXIT_TEXT)
52
47
_einittext = .;
53
48
ARM_CPU_DISCARD(PROC_INFO)
54
49
__arch_info_begin = .;
···
74
67
#ifndef CONFIG_XIP_KERNEL
75
68
__init_begin = _stext;
76
69
INIT_DATA
70
+
ARM_EXIT_KEEP(EXIT_DATA)
77
71
#endif
78
72
}
79
73
···
170
162
. = ALIGN(PAGE_SIZE);
171
163
__init_begin = .;
172
164
INIT_DATA
165
+
ARM_EXIT_KEEP(EXIT_DATA)
173
166
. = ALIGN(PAGE_SIZE);
174
167
__init_end = .;
175
168
#endif
···
255
246
__tcm_end = .;
256
247
}
257
248
#endif
249
+
250
+
NOTES
258
251
259
252
BSS_SECTION(0, 0, 0)
260
253
_end = .;
+1
-1
arch/arm/mach-spear3xx/include/mach/spear320.h
+1
-1
arch/arm/mach-spear3xx/include/mach/spear320.h
···
62
62
#define SPEAR320_SMII1_BASE 0xAB000000
63
63
#define SPEAR320_SMII1_SIZE 0x01000000
64
64
65
-
#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
65
+
#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
66
66
#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
67
67
/* Interrupt registers offsets and masks */
68
68
#define INT_STS_MASK_REG 0x04
+6
arch/arm/mm/cache-l2x0.c
+6
arch/arm/mm/cache-l2x0.c
···
49
49
static inline void cache_sync(void)
50
50
{
51
51
void __iomem *base = l2x0_base;
52
+
53
+
#ifdef CONFIG_ARM_ERRATA_753970
54
+
/* write to an unmmapped register */
55
+
writel_relaxed(0, base + L2X0_DUMMY_REG);
56
+
#else
52
57
writel_relaxed(0, base + L2X0_CACHE_SYNC);
58
+
#endif
53
59
cache_wait(base + L2X0_CACHE_SYNC, 1);
54
60
}
55
61
+6
arch/arm/mm/proc-v7.S
+6
arch/arm/mm/proc-v7.S
···
264
264
orreq r10, r10, #1 << 6 @ set bit #6
265
265
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
266
266
#endif
267
+
#ifdef CONFIG_ARM_ERRATA_751472
268
+
cmp r6, #0x30 @ present prior to r3p0
269
+
mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
270
+
orrlt r10, r10, #1 << 11 @ set bit #11
271
+
mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
272
+
#endif
267
273
268
274
3: mov r10, #0
269
275
#ifdef HARVARD_CACHE
+2
-2
arch/arm/plat-spear/include/plat/uncompress.h
+2
-2
arch/arm/plat-spear/include/plat/uncompress.h
···
24
24
{
25
25
void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
26
26
27
-
while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
27
+
while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF)
28
28
barrier();
29
29
30
-
writel(c, base + UART01x_DR);
30
+
writel_relaxed(c, base + UART01x_DR);
31
31
}
32
32
33
33
static inline void flush(void)