tjh.dev / kernel
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: fix page flip finish vs. prepare on plane B
drm/i915: change default panel fitting mode to preserve aspect ratio
drm/i915: fix uninitialized variable warning in i915_setup_compression()
drm/i915: take struct_mutex in i915_dma_cleanup()
drm/i915: Fix CRT hotplug regression in 2.6.35-rc1
i915: fix ironlake edp panel setup (v4)
drm/i915: don't access FW_BLC_SELF on 965G
drm/i915: Account for space on the ring buffer consumed whilst wrapping.
drm/i915: gen3 page flipping fixes
drm/i915: don't queue flips during a flip pending event
drm/i915: Fix incorrect intel_ring_begin size in BSD ringbuffer.
drm/i915: Turn on 945 self-refresh only if single CRTC is active
drm/i915/gen4: Fix interrupt setup ordering
drm/i915: Use RSEN instead of HTPLG for tfp410 monitor detection.
drm/i915: Move non-phys cursors into the GTT
Revert "drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on)."

(Included the "fix page flip finish vs. prepare on plane B" patch from
Jesse on top of the pull request from Eric. -- Linus)

Linus Torvalds 97e02140 82645698

+140 -64
+1 -1
drivers/gpu/drm/i915/dvo_tfp410.c
··· 208 208 uint8_t ctl2; 209 209 210 210 if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { 211 - if (ctl2 & TFP410_CTL_2_HTPLG) 211 + if (ctl2 & TFP410_CTL_2_RSEN) 212 212 ret = connector_status_connected; 213 213 else 214 214 ret = connector_status_disconnected;
+1 -1
drivers/gpu/drm/i915/i915_debugfs.c
··· 620 620 drm_i915_private_t *dev_priv = dev->dev_private; 621 621 bool sr_enabled = false; 622 622 623 - if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev)) 623 + if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev)) 624 624 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 625 625 else if (IS_I915GM(dev)) 626 626 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
+7 -1
drivers/gpu/drm/i915/i915_dma.c
··· 128 128 if (dev->irq_enabled) 129 129 drm_irq_uninstall(dev); 130 130 131 + mutex_lock(&dev->struct_mutex); 131 132 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); 132 133 if (HAS_BSD(dev)) 133 134 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); 135 + mutex_unlock(&dev->struct_mutex); 134 136 135 137 /* Clear the HWS virtual address at teardown */ 136 138 if (I915_NEED_GFX_HWS(dev)) ··· 1231 1229 static void i915_setup_compression(struct drm_device *dev, int size) 1232 1230 { 1233 1231 struct drm_i915_private *dev_priv = dev->dev_private; 1234 - struct drm_mm_node *compressed_fb, *compressed_llb; 1232 + struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb); 1235 1233 unsigned long cfb_base; 1236 1234 unsigned long ll_base = 0; 1237 1235 ··· 1411 1409 i915_switcheroo_can_switch); 1412 1410 if (ret) 1413 1411 goto cleanup_vga_client; 1412 + 1413 + /* IIR "flip pending" bit means done if this bit is set */ 1414 + if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) 1415 + dev_priv->flip_pending_is_done = true; 1414 1416 1415 1417 intel_modeset_init(dev); 1416 1418
+2 -1
drivers/gpu/drm/i915/i915_drv.h
··· 596 596 struct drm_crtc *plane_to_crtc_mapping[2]; 597 597 struct drm_crtc *pipe_to_crtc_mapping[2]; 598 598 wait_queue_head_t pending_flip_queue; 599 + bool flip_pending_is_done; 599 600 600 601 /* Reclocking support */ 601 602 bool render_reclock_avail; ··· 1077 1076 drm_i915_private_t *dev_priv = dev->dev_private; \ 1078 1077 if (I915_VERBOSE) \ 1079 1078 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ 1080 - intel_ring_begin(dev, &dev_priv->render_ring, 4*(n)); \ 1079 + intel_ring_begin(dev, &dev_priv->render_ring, (n)); \ 1081 1080 } while (0) 1082 1081 1083 1082
+45 -31
drivers/gpu/drm/i915/i915_irq.c
··· 940 940 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) 941 941 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); 942 942 943 - if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) 943 + if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 944 944 intel_prepare_page_flip(dev, 0); 945 + if (dev_priv->flip_pending_is_done) 946 + intel_finish_page_flip_plane(dev, 0); 947 + } 945 948 946 - if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) 949 + if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 947 950 intel_prepare_page_flip(dev, 1); 951 + if (dev_priv->flip_pending_is_done) 952 + intel_finish_page_flip_plane(dev, 1); 953 + } 948 954 949 955 if (pipea_stats & vblank_status) { 950 956 vblank++; 951 957 drm_handle_vblank(dev, 0); 952 - intel_finish_page_flip(dev, 0); 958 + if (!dev_priv->flip_pending_is_done) 959 + intel_finish_page_flip(dev, 0); 953 960 } 954 961 955 962 if (pipeb_stats & vblank_status) { 956 963 vblank++; 957 964 drm_handle_vblank(dev, 1); 958 - intel_finish_page_flip(dev, 1); 965 + if (!dev_priv->flip_pending_is_done) 966 + intel_finish_page_flip(dev, 1); 959 967 } 960 968 961 969 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) || ··· 1395 1387 dev_priv->pipestat[1] = 0; 1396 1388 1397 1389 if (I915_HAS_HOTPLUG(dev)) { 1398 - u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1399 - 1400 - /* Note HDMI and DP share bits */ 1401 - if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 1402 - hotplug_en |= HDMIB_HOTPLUG_INT_EN; 1403 - if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 1404 - hotplug_en |= HDMIC_HOTPLUG_INT_EN; 1405 - if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 1406 - hotplug_en |= HDMID_HOTPLUG_INT_EN; 1407 - if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) 1408 - hotplug_en |= SDVOC_HOTPLUG_INT_EN; 1409 - if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) 1410 - hotplug_en |= SDVOB_HOTPLUG_INT_EN; 1411 - if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) 1412 - hotplug_en |= CRT_HOTPLUG_INT_EN; 1413 - /* Ignore TV since it's buggy */ 1414 - 1415 - I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 1416 - 1417 1390 /* Enable in IER... */ 1418 1391 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1419 1392 /* and unmask in IMR */ 1420 - i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); 1393 + dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; 1421 1394 } 1422 1395 1423 1396 /* ··· 1416 1427 } 1417 1428 I915_WRITE(EMR, error_mask); 1418 1429 1419 - /* Disable pipe interrupt enables, clear pending pipe status */ 1420 - I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); 1421 - I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); 1422 - /* Clear pending interrupt status */ 1423 - I915_WRITE(IIR, I915_READ(IIR)); 1424 - 1425 - I915_WRITE(IER, enable_mask); 1426 1430 I915_WRITE(IMR, dev_priv->irq_mask_reg); 1431 + I915_WRITE(IER, enable_mask); 1427 1432 (void) I915_READ(IER); 1433 + 1434 + if (I915_HAS_HOTPLUG(dev)) { 1435 + u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1436 + 1437 + /* Note HDMI and DP share bits */ 1438 + if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 1439 + hotplug_en |= HDMIB_HOTPLUG_INT_EN; 1440 + if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 1441 + hotplug_en |= HDMIC_HOTPLUG_INT_EN; 1442 + if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 1443 + hotplug_en |= HDMID_HOTPLUG_INT_EN; 1444 + if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) 1445 + hotplug_en |= SDVOC_HOTPLUG_INT_EN; 1446 + if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) 1447 + hotplug_en |= SDVOB_HOTPLUG_INT_EN; 1448 + if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 1449 + hotplug_en |= CRT_HOTPLUG_INT_EN; 1450 + 1451 + /* Programming the CRT detection parameters tends 1452 + to generate a spurious hotplug event about three 1453 + seconds later. So just do it once. 1454 + */ 1455 + if (IS_G4X(dev)) 1456 + hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1457 + hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1458 + } 1459 + 1460 + /* Ignore TV since it's buggy */ 1461 + 1462 + I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 1463 + } 1428 1464 1429 1465 opregion_enable_asle(dev); 1430 1466
+4 -1
drivers/gpu/drm/i915/i915_reg.h
··· 178 178 #define MI_OVERLAY_OFF (0x2<<21) 179 179 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 180 180 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 181 + #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 181 182 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 182 183 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 183 184 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ ··· 369 368 #define CM0_RC_OP_FLUSH_DISABLE (1<<0) 370 369 #define BB_ADDR 0x02140 /* 8 bytes */ 371 370 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 371 + #define ECOSKPD 0x021d0 372 + #define ECO_GATING_CX_ONLY (1<<3) 373 + #define ECO_FLIP_DONE (1<<0) 372 374 373 375 /* GEN6 interrupt control */ 374 376 #define GEN6_RENDER_HWSTAM 0x2098 ··· 1134 1130 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1135 1131 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1136 1132 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1137 - #define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ 1138 1133 1139 1134 #define PORT_HOTPLUG_STAT 0x61114 1140 1135 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
-6
drivers/gpu/drm/i915/intel_crt.c
··· 234 234 else 235 235 tries = 1; 236 236 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 237 - hotplug_en &= CRT_HOTPLUG_MASK; 238 237 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 239 - 240 - if (IS_G4X(dev)) 241 - hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 242 - 243 - hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 244 238 245 239 for (i = 0; i < tries ; i++) { 246 240 unsigned long timeout;
+47 -13
drivers/gpu/drm/i915/intel_display.c
··· 2970 2970 if (srwm < 0) 2971 2971 srwm = 1; 2972 2972 srwm &= 0x3f; 2973 - I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2973 + if (IS_I965GM(dev)) 2974 + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 2974 2975 } else { 2975 2976 /* Turn off self refresh if both pipes are enabled */ 2976 - I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 2977 - & ~FW_BLC_SELF_EN); 2977 + if (IS_I965GM(dev)) 2978 + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 2979 + & ~FW_BLC_SELF_EN); 2978 2980 } 2979 2981 2980 2982 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", ··· 4485 4483 struct drm_device *dev = dev_priv->dev; 4486 4484 struct drm_crtc *crtc; 4487 4485 struct intel_crtc *intel_crtc; 4486 + int enabled = 0; 4488 4487 4489 4488 if (!i915_powersave) 4490 4489 return; ··· 4494 4491 4495 4492 i915_update_gfx_val(dev_priv); 4496 4493 4497 - if (IS_I945G(dev) || IS_I945GM(dev)) { 4498 - DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); 4499 - I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 4500 - } 4501 - 4502 4494 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 4503 4495 /* Skip inactive CRTCs */ 4504 4496 if (!crtc->fb) 4505 4497 continue; 4506 4498 4499 + enabled++; 4507 4500 intel_crtc = to_intel_crtc(crtc); 4508 4501 if (!intel_crtc->busy) 4509 4502 intel_decrease_pllclock(crtc); 4503 + } 4504 + 4505 + if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { 4506 + DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); 4507 + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 4510 4508 } 4511 4509 4512 4510 mutex_unlock(&dev->struct_mutex); ··· 4605 4601 kfree(work); 4606 4602 } 4607 4603 4608 - void intel_finish_page_flip(struct drm_device *dev, int pipe) 4604 + static void do_intel_finish_page_flip(struct drm_device *dev, 4605 + struct drm_crtc *crtc) 4609 4606 { 4610 4607 drm_i915_private_t *dev_priv = dev->dev_private; 4611 - struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 4612 4608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4613 4609 struct intel_unpin_work *work; 4614 4610 struct drm_i915_gem_object *obj_priv; ··· 4652 4648 schedule_work(&work->work); 4653 4649 } 4654 4650 4651 + void intel_finish_page_flip(struct drm_device *dev, int pipe) 4652 + { 4653 + drm_i915_private_t *dev_priv = dev->dev_private; 4654 + struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 4655 + 4656 + do_intel_finish_page_flip(dev, crtc); 4657 + } 4658 + 4659 + void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 4660 + { 4661 + drm_i915_private_t *dev_priv = dev->dev_private; 4662 + struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 4663 + 4664 + do_intel_finish_page_flip(dev, crtc); 4665 + } 4666 + 4655 4667 void intel_prepare_page_flip(struct drm_device *dev, int plane) 4656 4668 { 4657 4669 drm_i915_private_t *dev_priv = dev->dev_private; ··· 4698 4678 unsigned long flags; 4699 4679 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; 4700 4680 int ret, pipesrc; 4681 + u32 flip_mask; 4701 4682 4702 4683 work = kzalloc(sizeof *work, GFP_KERNEL); 4703 4684 if (work == NULL) ··· 4752 4731 atomic_inc(&obj_priv->pending_flip); 4753 4732 work->pending_flip_obj = obj; 4754 4733 4734 + if (intel_crtc->plane) 4735 + flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 4736 + else 4737 + flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; 4738 + 4739 + /* Wait for any previous flip to finish */ 4740 + if (IS_GEN3(dev)) 4741 + while (I915_READ(ISR) & flip_mask) 4742 + ; 4743 + 4755 4744 BEGIN_LP_RING(4); 4756 - OUT_RING(MI_DISPLAY_FLIP | 4757 - MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 4758 - OUT_RING(fb->pitch); 4759 4745 if (IS_I965G(dev)) { 4746 + OUT_RING(MI_DISPLAY_FLIP | 4747 + MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 4748 + OUT_RING(fb->pitch); 4760 4749 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); 4761 4750 pipesrc = I915_READ(pipesrc_reg); 4762 4751 OUT_RING(pipesrc & 0x0fff0fff); 4763 4752 } else { 4753 + OUT_RING(MI_DISPLAY_FLIP_I915 | 4754 + MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 4755 + OUT_RING(fb->pitch); 4764 4756 OUT_RING(obj_priv->gtt_offset); 4765 4757 OUT_RING(MI_NOOP); 4766 4758 }
+24 -3
drivers/gpu/drm/i915/intel_dp.c
··· 136 136 } 137 137 138 138 static int 139 + intel_dp_max_data_rate(int max_link_clock, int max_lanes) 140 + { 141 + return (max_link_clock * max_lanes * 8) / 10; 142 + } 143 + 144 + static int 139 145 intel_dp_mode_valid(struct drm_connector *connector, 140 146 struct drm_display_mode *mode) 141 147 { ··· 150 144 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder)); 151 145 int max_lanes = intel_dp_max_lane_count(intel_encoder); 152 146 153 - if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock) 154 - > max_link_clock * max_lanes) 147 + /* only refuse the mode on non eDP since we have seen some wierd eDP panels 148 + which are outside spec tolerances but somehow work by magic */ 149 + if (!IS_eDP(intel_encoder) && 150 + (intel_dp_link_required(connector->dev, intel_encoder, mode->clock) 151 + > intel_dp_max_data_rate(max_link_clock, max_lanes))) 155 152 return MODE_CLOCK_HIGH; 156 153 157 154 if (mode->clock < 10000) ··· 515 506 516 507 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 517 508 for (clock = 0; clock <= max_clock; clock++) { 518 - int link_avail = intel_dp_link_clock(bws[clock]) * lane_count; 509 + int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 519 510 520 511 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock) 521 512 <= link_avail) { ··· 529 520 return true; 530 521 } 531 522 } 523 + } 524 + 525 + if (IS_eDP(intel_encoder)) { 526 + /* okay we failed just pick the highest */ 527 + dp_priv->lane_count = max_lane_count; 528 + dp_priv->link_bw = bws[max_clock]; 529 + adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 530 + DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 531 + "count %d clock %d\n", 532 + dp_priv->link_bw, dp_priv->lane_count, 533 + adjusted_mode->clock); 534 + return true; 532 535 } 533 536 return false; 534 537 }
+1
drivers/gpu/drm/i915/intel_drv.h
··· 224 224 225 225 extern void intel_prepare_page_flip(struct drm_device *dev, int plane); 226 226 extern void intel_finish_page_flip(struct drm_device *dev, int pipe); 227 + extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 227 228 228 229 extern void intel_setup_overlay(struct drm_device *dev); 229 230 extern void intel_cleanup_overlay(struct drm_device *dev);
+2 -2
drivers/gpu/drm/i915/intel_lvds.c
··· 983 983 984 984 drm_connector_attach_property(&intel_connector->base, 985 985 dev->mode_config.scaling_mode_property, 986 - DRM_MODE_SCALE_FULLSCREEN); 987 - lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN; 986 + DRM_MODE_SCALE_ASPECT); 987 + lvds_priv->fitting_mode = DRM_MODE_SCALE_ASPECT; 988 988 /* 989 989 * LVDS discovery: 990 990 * 1) check for EDID on DDC
+6 -4
drivers/gpu/drm/i915/intel_ringbuffer.c
··· 94 94 #if WATCH_EXEC 95 95 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); 96 96 #endif 97 - intel_ring_begin(dev, ring, 8); 97 + intel_ring_begin(dev, ring, 2); 98 98 intel_ring_emit(dev, ring, cmd); 99 99 intel_ring_emit(dev, ring, MI_NOOP); 100 100 intel_ring_advance(dev, ring); ··· 358 358 u32 invalidate_domains, 359 359 u32 flush_domains) 360 360 { 361 - intel_ring_begin(dev, ring, 8); 361 + intel_ring_begin(dev, ring, 2); 362 362 intel_ring_emit(dev, ring, MI_FLUSH); 363 363 intel_ring_emit(dev, ring, MI_NOOP); 364 364 intel_ring_advance(dev, ring); ··· 687 687 *virt++ = MI_NOOP; 688 688 689 689 ring->tail = 0; 690 + ring->space = ring->head - 8; 690 691 691 692 return 0; 692 693 } ··· 722 721 } 723 722 724 723 void intel_ring_begin(struct drm_device *dev, 725 - struct intel_ring_buffer *ring, int n) 724 + struct intel_ring_buffer *ring, int num_dwords) 726 725 { 726 + int n = 4*num_dwords; 727 727 if (unlikely(ring->tail + n > ring->size)) 728 728 intel_wrap_ring_buffer(dev, ring); 729 729 if (unlikely(ring->space < n)) ··· 754 752 { 755 753 unsigned int *virt = ring->virtual_start + ring->tail; 756 754 BUG_ON((len&~(4-1)) != 0); 757 - intel_ring_begin(dev, ring, len); 755 + intel_ring_begin(dev, ring, len/4); 758 756 memcpy(virt, data, len); 759 757 ring->tail += len; 760 758 ring->tail &= ring->size - 1;