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Merge tag 'mlx5-updates-2023-08-16' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux

Saeed Mahameed says:

====================
mlx5-updates-2023-08-16

1) aRFS ethtool stats

Improve aRFS observability by adding new set of counters. Each Rx
ring will have this set of counters listed below.
These counters are exposed through ethtool -S.

1.1) arfs_add: number of times a new rule has been created.
1.2) arfs_request_in: number of times a rule was requested to move from
its current Rx ring to a new Rx ring (incremented on the destination
Rx ring).
1.3) arfs_request_out: number of times a rule was requested to move out
from its current Rx ring (incremented on source/current Rx ring).
1.4) arfs_expired: number of times a rule has been expired by the
kernel and removed from HW.
1.5) arfs_err: number of times a rule creation or modification has
failed.

2) Supporting inline WQE when possible in SW steering

3) Misc cleanups and fixups to net-next branch

* tag 'mlx5-updates-2023-08-16' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux:
net/mlx5: Devcom, only use devcom after NULL check in mlx5_devcom_send_event()
net/mlx5: DR, Supporting inline WQE when possible
net/mlx5: Rename devlink port ops struct for PFs/VFs
net/mlx5: Remove VPORT_UPLINK handling from devlink_port.c
net/mlx5: Call mlx5_esw_offloads_rep_load/unload() for uplink port directly
net/mlx5: Update dead links in Kconfig documentation
net/mlx5: Remove health syndrome enum duplication
net/mlx5: DR, Remove unneeded local variable
net/mlx5: DR, Fix code indentation
net/mlx5: IRQ, consolidate irq and affinity mask allocation
net/mlx5e: Fix spelling mistake "Faided" -> "Failed"
net/mlx5e: aRFS, Introduce ethtool stats
net/mlx5e: aRFS, Warn if aRFS table does not exist for aRFS rule
net/mlx5e: aRFS, Prevent repeated kernel rule migrations requests
====================

Link: https://lore.kernel.org/r/20230821175739.81188-1-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 98173633 504fc6f4

+208 -95
+18 -5
Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst
··· 346 346 - The number of receive packets with CQE compression on ring i [#accel]_. 347 347 - Acceleration 348 348 349 + * - `rx[i]_arfs_add` 350 + - The number of aRFS flow rules added to the device for direct RQ steering 351 + on ring i [#accel]_. 352 + - Acceleration 353 + 354 + * - `rx[i]_arfs_request_in` 355 + - Number of flow rules that have been requested to move into ring i for 356 + direct RQ steering [#accel]_. 357 + - Acceleration 358 + 359 + * - `rx[i]_arfs_request_out` 360 + - Number of flow rules that have been requested to move out of ring i [#accel]_. 361 + - Acceleration 362 + 363 + * - `rx[i]_arfs_expired` 364 + - Number of flow rules that have been expired and removed [#accel]_. 365 + - Acceleration 366 + 349 367 * - `rx[i]_arfs_err` 350 368 - Number of flow rules that failed to be added to the flow table. 351 369 - Error ··· 461 443 * - `rx[i]_xsk_buff_alloc_err` 462 444 - The number of times allocating an skb or XSK buffer failed in the XSK RQ 463 445 context. 464 - - Error 465 - 466 - * - `rx[i]_xsk_arfs_err` 467 - - aRFS (accelerated Receive Flow Steering) does not occur in the XSK RQ 468 - context, so this counter should never increment. 469 446 - Error 470 447 471 448 * - `rx[i]_xdp_tx_xmit`
+7 -7
Documentation/networking/device_drivers/ethernet/mellanox/mlx5/kconfig.rst
··· 36 36 37 37 **CONFIG_MLX5_CORE_EN_DCB=(y/n)**: 38 38 39 - | Enables `Data Center Bridging (DCB) Support <https://community.mellanox.com/s/article/howto-auto-config-pfc-and-ets-on-connectx-4-via-lldp-dcbx>`_. 39 + | Enables `Data Center Bridging (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-connectx-4-via-lldp-dcbx>`_. 40 40 41 41 42 42 **CONFIG_MLX5_CORE_IPOIB=(y/n)** ··· 59 59 **CONFIG_MLX5_EN_ARFS=(y/n)** 60 60 61 61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering. 62 - | https://community.mellanox.com/s/article/howto-configure-arfs-on-connectx-4 62 + | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4 63 63 64 64 65 65 **CONFIG_MLX5_EN_IPSEC=(y/n)** 66 66 67 - | Enables `IPSec XFRM cryptography-offload acceleration <https://support.mellanox.com/s/article/ConnectX-6DX-Bluefield-2-IPsec-HW-Full-Offload-Configuration-Guide>`_. 67 + | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`. 68 68 69 69 70 70 **CONFIG_MLX5_EN_MACSEC=(y/n)** ··· 87 87 88 88 | Ethernet SRIOV E-Switch support in ConnectX NIC. E-Switch provides internal SRIOV packet steering 89 89 | and switching for the enabled VFs and PF in two available modes: 90 - | 1) `Legacy SRIOV mode (L2 mac vlan steering based) <https://community.mellanox.com/s/article/howto-configure-sr-iov-for-connectx-4-connectx-5-with-kvm--ethernet-x>`_. 91 - | 2) `Switchdev mode (eswitch offloads) <https://www.mellanox.com/related-docs/prod_software/ASAP2_Hardware_Offloading_for_vSwitches_User_Manual_v4.4.pdf>`_. 90 + | 1) `Legacy SRIOV mode (L2 mac vlan steering based) <https://enterprise-support.nvidia.com/s/article/HowTo-Configure-SR-IOV-for-ConnectX-4-ConnectX-5-ConnectX-6-with-KVM-Ethernet>`_. 91 + | 2) :ref:`Switchdev mode (eswitch offloads) <switchdev>`. 92 92 93 93 94 94 **CONFIG_MLX5_FPGA=(y/n)** ··· 101 101 102 102 **CONFIG_MLX5_INFINIBAND=(y/n/m)** (module mlx5_ib.ko) 103 103 104 - | Provides low-level InfiniBand/RDMA and `RoCE <https://community.mellanox.com/s/article/recommended-network-configuration-examples-for-roce-deployment>`_ support. 104 + | Provides low-level InfiniBand/RDMA and `RoCE <https://enterprise-support.nvidia.com/s/article/recommended-network-configuration-examples-for-roce-deployment>`_ support. 105 105 106 106 107 107 **CONFIG_MLX5_MPFS=(y/n)** 108 108 109 109 | Ethernet Multi-Physical Function Switch (MPFS) support in ConnectX NIC. 110 - | MPFs is required for when `Multi-Host <http://www.mellanox.com/page/multihost>`_ configuration is enabled to allow passing 110 + | MPFs is required for when `Multi-Host <https://www.nvidia.com/en-us/networking/multi-host/>`_ configuration is enabled to allow passing 111 111 | user configured unicast MAC addresses to the requesting PF. 112 112 113 113
+1
Documentation/networking/xfrm_device.rst
··· 1 1 .. SPDX-License-Identifier: GPL-2.0 2 + .. _xfrm_device: 2 3 3 4 =============================================== 4 5 XFRM device - offloading the IPsec computations
+17 -4
drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c
··· 432 432 } 433 433 spin_unlock_bh(&arfs->arfs_lock); 434 434 hlist_for_each_entry_safe(arfs_rule, htmp, &del_list, hlist) { 435 - if (arfs_rule->rule) 435 + if (arfs_rule->rule) { 436 436 mlx5_del_flow_rules(arfs_rule->rule); 437 + priv->channel_stats[arfs_rule->rxq]->rq.arfs_expired++; 438 + } 437 439 hlist_del(&arfs_rule->hlist); 438 440 kfree(arfs_rule); 439 441 } ··· 511 509 512 510 spec = kvzalloc(sizeof(*spec), GFP_KERNEL); 513 511 if (!spec) { 512 + priv->channel_stats[arfs_rule->rxq]->rq.arfs_err++; 514 513 err = -ENOMEM; 515 514 goto out; 516 515 } ··· 522 519 ntohs(tuple->etype)); 523 520 arfs_table = arfs_get_table(arfs, tuple->ip_proto, tuple->etype); 524 521 if (!arfs_table) { 522 + WARN_ONCE(1, "arfs table does not exist for etype %u and ip_proto %u\n", 523 + tuple->etype, tuple->ip_proto); 525 524 err = -EINVAL; 526 525 goto out; 527 526 } ··· 605 600 dst.type = MLX5_FLOW_DESTINATION_TYPE_TIR; 606 601 dst.tir_num = mlx5e_rx_res_get_tirn_direct(priv->rx_res, rxq); 607 602 err = mlx5_modify_rule_destination(rule, &dst, NULL); 608 - if (err) 603 + if (err) { 604 + priv->channel_stats[rxq]->rq.arfs_err++; 609 605 netdev_warn(priv->netdev, 610 606 "Failed to modify aRFS rule destination to rq=%d\n", rxq); 607 + } 611 608 } 612 609 613 610 static void arfs_handle_work(struct work_struct *work) ··· 639 632 if (IS_ERR(rule)) 640 633 goto out; 641 634 arfs_rule->rule = rule; 635 + priv->channel_stats[arfs_rule->rxq]->rq.arfs_add++; 642 636 } else { 643 637 arfs_modify_rule_rq(priv, arfs_rule->rule, 644 638 arfs_rule->rxq); ··· 658 650 struct arfs_tuple *tuple; 659 651 660 652 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 661 - if (!rule) 653 + if (!rule) { 654 + priv->channel_stats[rxq]->rq.arfs_err++; 662 655 return NULL; 656 + } 663 657 664 658 rule->priv = priv; 665 659 rule->rxq = rxq; ··· 750 740 spin_lock_bh(&arfs->arfs_lock); 751 741 arfs_rule = arfs_find_rule(arfs_t, &fk); 752 742 if (arfs_rule) { 753 - if (arfs_rule->rxq == rxq_index) { 743 + if (arfs_rule->rxq == rxq_index || work_busy(&arfs_rule->arfs_work)) { 754 744 spin_unlock_bh(&arfs->arfs_lock); 755 745 return arfs_rule->filter_id; 756 746 } 747 + 748 + priv->channel_stats[rxq_index]->rq.arfs_request_in++; 749 + priv->channel_stats[arfs_rule->rxq]->rq.arfs_request_out++; 757 750 arfs_rule->rxq = rxq_index; 758 751 } else { 759 752 arfs_rule = arfs_alloc_rule(priv, arfs_t, &fk, rxq_index, flow_id);
+18 -4
drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
··· 180 180 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) }, 181 181 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) }, 182 182 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) }, 183 + #ifdef CONFIG_MLX5_EN_ARFS 184 + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_add) }, 185 + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_in) }, 186 + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_out) }, 187 + { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_expired) }, 183 188 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) }, 189 + #endif 184 190 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_recover) }, 185 191 #ifdef CONFIG_PAGE_POOL_STATS 186 192 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_fast) }, ··· 237 231 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_blks) }, 238 232 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_pkts) }, 239 233 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_congst_umr) }, 240 - { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_arfs_err) }, 241 234 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_xmit) }, 242 235 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_mpwqe) }, 243 236 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_inlnw) }, ··· 326 321 s->rx_xsk_cqe_compress_blks += xskrq_stats->cqe_compress_blks; 327 322 s->rx_xsk_cqe_compress_pkts += xskrq_stats->cqe_compress_pkts; 328 323 s->rx_xsk_congst_umr += xskrq_stats->congst_umr; 329 - s->rx_xsk_arfs_err += xskrq_stats->arfs_err; 330 324 } 331 325 332 326 static void mlx5e_stats_grp_sw_update_stats_rq_stats(struct mlx5e_sw_stats *s, ··· 358 354 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; 359 355 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; 360 356 s->rx_congst_umr += rq_stats->congst_umr; 357 + #ifdef CONFIG_MLX5_EN_ARFS 358 + s->rx_arfs_add += rq_stats->arfs_add; 359 + s->rx_arfs_request_in += rq_stats->arfs_request_in; 360 + s->rx_arfs_request_out += rq_stats->arfs_request_out; 361 + s->rx_arfs_expired += rq_stats->arfs_expired; 361 362 s->rx_arfs_err += rq_stats->arfs_err; 363 + #endif 362 364 s->rx_recover += rq_stats->recover; 363 365 #ifdef CONFIG_PAGE_POOL_STATS 364 366 s->rx_pp_alloc_fast += rq_stats->pp_alloc_fast; ··· 2000 1990 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 2001 1991 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 2002 1992 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) }, 1993 + #ifdef CONFIG_MLX5_EN_ARFS 1994 + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_add) }, 1995 + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_in) }, 1996 + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_out) }, 1997 + { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_expired) }, 2003 1998 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) }, 1999 + #endif 2004 2000 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, recover) }, 2005 2001 #ifdef CONFIG_PAGE_POOL_STATS 2006 2002 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_fast) }, ··· 2108 2092 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 2109 2093 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 2110 2094 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, congst_umr) }, 2111 - { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, arfs_err) }, 2112 2095 }; 2113 2096 2114 2097 static const struct counter_desc xsksq_stats_desc[] = { ··· 2183 2168 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) }, 2184 2169 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) }, 2185 2170 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, congst_umr) }, 2186 - { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, arfs_err) }, 2187 2171 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, recover) }, 2188 2172 }; 2189 2173
+12 -1
drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
··· 194 194 u64 rx_cqe_compress_blks; 195 195 u64 rx_cqe_compress_pkts; 196 196 u64 rx_congst_umr; 197 + #ifdef CONFIG_MLX5_EN_ARFS 198 + u64 rx_arfs_add; 199 + u64 rx_arfs_request_in; 200 + u64 rx_arfs_request_out; 201 + u64 rx_arfs_expired; 197 202 u64 rx_arfs_err; 203 + #endif 198 204 u64 rx_recover; 199 205 u64 ch_events; 200 206 u64 ch_poll; ··· 262 256 u64 rx_xsk_cqe_compress_blks; 263 257 u64 rx_xsk_cqe_compress_pkts; 264 258 u64 rx_xsk_congst_umr; 265 - u64 rx_xsk_arfs_err; 266 259 u64 tx_xsk_xmit; 267 260 u64 tx_xsk_mpwqe; 268 261 u64 tx_xsk_inlnw; ··· 363 358 u64 cqe_compress_blks; 364 359 u64 cqe_compress_pkts; 365 360 u64 congst_umr; 361 + #ifdef CONFIG_MLX5_EN_ARFS 362 + u64 arfs_add; 363 + u64 arfs_request_in; 364 + u64 arfs_request_out; 365 + u64 arfs_expired; 366 366 u64 arfs_err; 367 + #endif 367 368 u64 recover; 368 369 #ifdef CONFIG_PAGE_POOL_STATS 369 370 u64 pp_alloc_fast;
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/esw/ipsec_fs.c
··· 316 316 err = mlx5_esw_ipsec_modify_flow_dests(esw, flow); 317 317 if (err) 318 318 mlx5_core_warn_once(mdev, 319 - "Faided to modify flow dests for IPsec"); 319 + "Failed to modify flow dests for IPsec"); 320 320 } 321 321 rhashtable_walk_stop(&iter); 322 322 rhashtable_walk_exit(&iter);
+8 -12
drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
··· 2542 2542 if (esw->mode != MLX5_ESWITCH_OFFLOADS) 2543 2543 return 0; 2544 2544 2545 - if (vport_num != MLX5_VPORT_UPLINK) { 2546 - err = mlx5_esw_offloads_devlink_port_register(esw, vport_num); 2547 - if (err) 2548 - return err; 2549 - } 2545 + err = mlx5_esw_offloads_devlink_port_register(esw, vport_num); 2546 + if (err) 2547 + return err; 2550 2548 2551 2549 err = mlx5_esw_offloads_rep_load(esw, vport_num); 2552 2550 if (err) ··· 2552 2554 return err; 2553 2555 2554 2556 load_err: 2555 - if (vport_num != MLX5_VPORT_UPLINK) 2556 - mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); 2557 + mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); 2557 2558 return err; 2558 2559 } 2559 2560 ··· 2563 2566 2564 2567 mlx5_esw_offloads_rep_unload(esw, vport_num); 2565 2568 2566 - if (vport_num != MLX5_VPORT_UPLINK) 2567 - mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); 2569 + mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); 2568 2570 } 2569 2571 2570 2572 static int esw_set_slave_root_fdb(struct mlx5_core_dev *master, ··· 3467 3471 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN; 3468 3472 3469 3473 /* Uplink vport rep must load first. */ 3470 - err = mlx5_esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK); 3474 + err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK); 3471 3475 if (err) 3472 3476 goto err_uplink; 3473 3477 ··· 3478 3482 return 0; 3479 3483 3480 3484 err_vports: 3481 - mlx5_esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK); 3485 + mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK); 3482 3486 err_uplink: 3483 3487 esw_offloads_steering_cleanup(esw); 3484 3488 err_steering_init: ··· 3516 3520 void esw_offloads_disable(struct mlx5_eswitch *esw) 3517 3521 { 3518 3522 mlx5_eswitch_disable_pf_vf_vports(esw); 3519 - mlx5_esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK); 3523 + mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK); 3520 3524 esw_set_passing_vport_metadata(esw, false); 3521 3525 esw_offloads_steering_cleanup(esw); 3522 3526 mapping_destroy(esw->offloads.reg_c0_obj_pool);
+11 -25
drivers/net/ethernet/mellanox/mlx5/core/health.c
··· 50 50 }; 51 51 52 52 enum { 53 - MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 54 - MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 55 - MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 56 - MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 57 - MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 58 - MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 59 - MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 60 - MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 61 - MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 62 - MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 63 - MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10 64 - }; 65 - 66 - enum { 67 53 MLX5_DROP_HEALTH_WORK, 68 54 }; 69 55 ··· 343 357 static const char *hsynd_str(u8 synd) 344 358 { 345 359 switch (synd) { 346 - case MLX5_HEALTH_SYNDR_FW_ERR: 360 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR: 347 361 return "firmware internal error"; 348 - case MLX5_HEALTH_SYNDR_IRISC_ERR: 362 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC: 349 363 return "irisc not responding"; 350 - case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR: 364 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR: 351 365 return "unrecoverable hardware error"; 352 - case MLX5_HEALTH_SYNDR_CRC_ERR: 366 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR: 353 367 return "firmware CRC error"; 354 - case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR: 368 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR: 355 369 return "ICM fetch PCI error"; 356 - case MLX5_HEALTH_SYNDR_HW_FTL_ERR: 370 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR: 357 371 return "HW fatal error\n"; 358 - case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR: 372 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN: 359 373 return "async EQ buffer overrun"; 360 - case MLX5_HEALTH_SYNDR_EQ_ERR: 374 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR: 361 375 return "EQ error"; 362 - case MLX5_HEALTH_SYNDR_EQ_INV: 376 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV: 363 377 return "Invalid EQ referenced"; 364 - case MLX5_HEALTH_SYNDR_FFSER_ERR: 378 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR: 365 379 return "FFSER error"; 366 - case MLX5_HEALTH_SYNDR_HIGH_TEMP: 380 + case MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR: 367 381 return "High temperature"; 368 382 default: 369 383 return "unrecognized error";
+2 -1
drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c
··· 256 256 int event, int rollback_event, 257 257 void *event_data) 258 258 { 259 - struct mlx5_devcom_comp *comp = devcom->comp; 260 259 struct mlx5_devcom_comp_dev *pos; 260 + struct mlx5_devcom_comp *comp; 261 261 int err = 0; 262 262 void *data; 263 263 264 264 if (IS_ERR_OR_NULL(devcom)) 265 265 return -ENODEV; 266 266 267 + comp = devcom->comp; 267 268 down_write(&comp->sem); 268 269 list_for_each_entry(pos, &comp->comp_dev_list_head, list) { 269 270 data = rcu_dereference_protected(pos->data, lockdep_is_held(&comp->sem));
+6 -8
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
··· 259 259 int err; 260 260 261 261 irq = kzalloc(sizeof(*irq), GFP_KERNEL); 262 - if (!irq) 262 + if (!irq || !zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) { 263 + kfree(irq); 263 264 return ERR_PTR(-ENOMEM); 265 + } 266 + 264 267 if (!i || !pci_msix_can_alloc_dyn(dev->pdev)) { 265 268 /* The vector at index 0 is always statically allocated. If 266 269 * dynamic irq is not supported all vectors are statically ··· 300 297 mlx5_core_err(dev, "Failed to request irq. err = %d\n", err); 301 298 goto err_req_irq; 302 299 } 303 - if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) { 304 - mlx5_core_warn(dev, "zalloc_cpumask_var failed\n"); 305 - err = -ENOMEM; 306 - goto err_cpumask; 307 - } 300 + 308 301 if (af_desc) { 309 302 cpumask_copy(irq->mask, &af_desc->mask); 310 303 irq_set_affinity_and_hint(irq->map.virq, irq->mask); ··· 318 319 err_xa: 319 320 if (af_desc) 320 321 irq_update_affinity_hint(irq->map.virq, NULL); 321 - free_cpumask_var(irq->mask); 322 - err_cpumask: 323 322 free_irq(irq->map.virq, &irq->nh); 324 323 err_req_irq: 325 324 #ifdef CONFIG_RFS_ACCEL ··· 330 333 if (i && pci_msix_can_alloc_dyn(dev->pdev)) 331 334 pci_msix_free_irq(dev->pdev, irq->map); 332 335 err_alloc_irq: 336 + free_cpumask_var(irq->mask); 333 337 kfree(irq); 334 338 return ERR_PTR(err); 335 339 }
-1
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c
··· 1422 1422 case DR_ACTION_TYP_TNL_L3_TO_L2: 1423 1423 { 1424 1424 u8 *hw_actions; 1425 - int ret; 1426 1425 1427 1426 hw_actions = kzalloc(DR_ACTION_CACHE_LINE_SIZE, GFP_KERNEL); 1428 1427 if (!hw_actions)
+102 -13
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c
··· 52 52 u32 cqn; 53 53 u32 pdn; 54 54 u32 max_send_wr; 55 + u32 max_send_sge; 55 56 struct mlx5_uars_page *uar; 56 57 u8 isolate_vl_tc:1; 57 58 }; ··· 247 246 return err == CQ_POLL_ERR ? err : npolled; 248 247 } 249 248 249 + static int dr_qp_get_args_update_send_wqe_size(struct dr_qp_init_attr *attr) 250 + { 251 + return roundup_pow_of_two(sizeof(struct mlx5_wqe_ctrl_seg) + 252 + sizeof(struct mlx5_wqe_flow_update_ctrl_seg) + 253 + sizeof(struct mlx5_wqe_header_modify_argument_update_seg)); 254 + } 255 + 256 + /* We calculate for specific RC QP with the required functionality */ 257 + static int dr_qp_calc_rc_send_wqe(struct dr_qp_init_attr *attr) 258 + { 259 + int update_arg_size; 260 + int inl_size = 0; 261 + int tot_size; 262 + int size; 263 + 264 + update_arg_size = dr_qp_get_args_update_send_wqe_size(attr); 265 + 266 + size = sizeof(struct mlx5_wqe_ctrl_seg) + 267 + sizeof(struct mlx5_wqe_raddr_seg); 268 + inl_size = size + ALIGN(sizeof(struct mlx5_wqe_inline_seg) + 269 + DR_STE_SIZE, 16); 270 + 271 + size += attr->max_send_sge * sizeof(struct mlx5_wqe_data_seg); 272 + 273 + size = max(size, update_arg_size); 274 + 275 + tot_size = max(size, inl_size); 276 + 277 + return ALIGN(tot_size, MLX5_SEND_WQE_BB); 278 + } 279 + 250 280 static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev, 251 281 struct dr_qp_init_attr *attr) 252 282 { ··· 285 253 u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {}; 286 254 struct mlx5_wq_param wqp; 287 255 struct mlx5dr_qp *dr_qp; 256 + int wqe_size; 288 257 int inlen; 289 258 void *qpc; 290 259 void *in; ··· 365 332 if (err) 366 333 goto err_in; 367 334 dr_qp->uar = attr->uar; 335 + wqe_size = dr_qp_calc_rc_send_wqe(attr); 336 + dr_qp->max_inline_data = min(wqe_size - 337 + (sizeof(struct mlx5_wqe_ctrl_seg) + 338 + sizeof(struct mlx5_wqe_raddr_seg) + 339 + sizeof(struct mlx5_wqe_inline_seg)), 340 + (2 * MLX5_SEND_WQE_BB - 341 + (sizeof(struct mlx5_wqe_ctrl_seg) + 342 + sizeof(struct mlx5_wqe_raddr_seg) + 343 + sizeof(struct mlx5_wqe_inline_seg)))); 368 344 369 345 return dr_qp; 370 346 ··· 437 395 MLX5_SEND_WQE_DS; 438 396 } 439 397 398 + static int dr_set_data_inl_seg(struct mlx5dr_qp *dr_qp, 399 + struct dr_data_seg *data_seg, void *wqe) 400 + { 401 + int inline_header_size = sizeof(struct mlx5_wqe_ctrl_seg) + 402 + sizeof(struct mlx5_wqe_raddr_seg) + 403 + sizeof(struct mlx5_wqe_inline_seg); 404 + struct mlx5_wqe_inline_seg *seg; 405 + int left_space; 406 + int inl = 0; 407 + void *addr; 408 + int len; 409 + int idx; 410 + 411 + seg = wqe; 412 + wqe += sizeof(*seg); 413 + addr = (void *)(unsigned long)(data_seg->addr); 414 + len = data_seg->length; 415 + inl += len; 416 + left_space = MLX5_SEND_WQE_BB - inline_header_size; 417 + 418 + if (likely(len > left_space)) { 419 + memcpy(wqe, addr, left_space); 420 + len -= left_space; 421 + addr += left_space; 422 + idx = (dr_qp->sq.pc + 1) & (dr_qp->sq.wqe_cnt - 1); 423 + wqe = mlx5_wq_cyc_get_wqe(&dr_qp->wq.sq, idx); 424 + } 425 + 426 + memcpy(wqe, addr, len); 427 + 428 + if (likely(inl)) { 429 + seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 430 + return DIV_ROUND_UP(inl + sizeof(seg->byte_count), 431 + MLX5_SEND_WQE_DS); 432 + } else { 433 + return 0; 434 + } 435 + } 436 + 440 437 static void 441 - dr_rdma_handle_icm_write_segments(struct mlx5_wqe_ctrl_seg *wq_ctrl, 438 + dr_rdma_handle_icm_write_segments(struct mlx5dr_qp *dr_qp, 439 + struct mlx5_wqe_ctrl_seg *wq_ctrl, 442 440 u64 remote_addr, 443 441 u32 rkey, 444 442 struct dr_data_seg *data_seg, ··· 494 412 wq_raddr->reserved = 0; 495 413 496 414 wq_dseg = (void *)(wq_raddr + 1); 415 + /* WQE ctrl segment + WQE remote addr segment */ 416 + *size = (sizeof(*wq_ctrl) + sizeof(*wq_raddr)) / MLX5_SEND_WQE_DS; 497 417 498 - wq_dseg->byte_count = cpu_to_be32(data_seg->length); 499 - wq_dseg->lkey = cpu_to_be32(data_seg->lkey); 500 - wq_dseg->addr = cpu_to_be64(data_seg->addr); 501 - 502 - *size = (sizeof(*wq_ctrl) + /* WQE ctrl segment */ 503 - sizeof(*wq_dseg) + /* WQE data segment */ 504 - sizeof(*wq_raddr)) / /* WQE remote addr segment */ 505 - MLX5_SEND_WQE_DS; 418 + if (data_seg->send_flags & IB_SEND_INLINE) { 419 + *size += dr_set_data_inl_seg(dr_qp, data_seg, wq_dseg); 420 + } else { 421 + wq_dseg->byte_count = cpu_to_be32(data_seg->length); 422 + wq_dseg->lkey = cpu_to_be32(data_seg->lkey); 423 + wq_dseg->addr = cpu_to_be64(data_seg->addr); 424 + *size += sizeof(*wq_dseg) / MLX5_SEND_WQE_DS; /* WQE data segment */ 425 + } 506 426 } 507 427 508 428 static void dr_set_ctrl_seg(struct mlx5_wqe_ctrl_seg *wq_ctrl, ··· 535 451 switch (opcode) { 536 452 case MLX5_OPCODE_RDMA_READ: 537 453 case MLX5_OPCODE_RDMA_WRITE: 538 - dr_rdma_handle_icm_write_segments(wq_ctrl, remote_addr, 454 + dr_rdma_handle_icm_write_segments(dr_qp, wq_ctrl, remote_addr, 539 455 rkey, data_seg, &size); 540 456 break; 541 457 case MLX5_OPCODE_FLOW_TBL_ACCESS: ··· 656 572 if (send_ring->pending_wqe % send_ring->signal_th == 0) 657 573 send_info->write.send_flags |= IB_SEND_SIGNALED; 658 574 else 659 - send_info->write.send_flags = 0; 575 + send_info->write.send_flags &= ~IB_SEND_SIGNALED; 660 576 } 661 577 662 578 static void dr_fill_write_icm_segs(struct mlx5dr_domain *dmn, ··· 680 596 } 681 597 682 598 send_ring->pending_wqe++; 599 + if (!send_info->write.lkey) 600 + send_info->write.send_flags |= IB_SEND_INLINE; 683 601 684 602 if (send_ring->pending_wqe % send_ring->signal_th == 0) 685 603 send_info->write.send_flags |= IB_SEND_SIGNALED; 604 + else 605 + send_info->write.send_flags &= ~IB_SEND_SIGNALED; 686 606 687 607 send_ring->pending_wqe++; 688 608 send_info->read.length = send_info->write.length; ··· 696 608 send_info->read.lkey = send_ring->sync_mr->mkey; 697 609 698 610 if (send_ring->pending_wqe % send_ring->signal_th == 0) 699 - send_info->read.send_flags = IB_SEND_SIGNALED; 611 + send_info->read.send_flags |= IB_SEND_SIGNALED; 700 612 else 701 - send_info->read.send_flags = 0; 613 + send_info->read.send_flags &= ~IB_SEND_SIGNALED; 702 614 } 703 615 704 616 static void dr_fill_data_segs(struct mlx5dr_domain *dmn, ··· 1345 1257 dmn->send_ring->cq->qp = dmn->send_ring->qp; 1346 1258 1347 1259 dmn->info.max_send_wr = QUEUE_SIZE; 1260 + init_attr.max_send_sge = 1; 1348 1261 dmn->info.max_inline_size = min(dmn->send_ring->qp->max_inline_data, 1349 1262 DR_STE_SIZE); 1350 1263
+1 -1
drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c
··· 336 336 if (fte->action.pkt_reformat->owner == MLX5_FLOW_RESOURCE_OWNER_FW) { 337 337 err = -EINVAL; 338 338 mlx5dr_err(domain, "FW-owned reformat can't be used in SW rule\n"); 339 - goto free_actions; 339 + goto free_actions; 340 340 } 341 341 342 342 is_decap = fte->action.pkt_reformat->reformat_type ==