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pinctrl: qcom: add sdm670 lpi tlmm

The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

authored by

Richard Acayan and committed by
Linus Walleij
9826035a 72102fda

+177
+10
drivers/pinctrl/qcom/Kconfig
··· 99 99 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI 100 100 (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform. 101 101 102 + config PINCTRL_SDM670_LPASS_LPI 103 + tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver" 104 + depends on GPIOLIB 105 + depends on ARM64 || COMPILE_TEST 106 + depends on PINCTRL_LPASS_LPI 107 + help 108 + This is the pinctrl, pinmux, pinconf and gpiolib driver for the 109 + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI 110 + (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform. 111 + 102 112 config PINCTRL_SM6115_LPASS_LPI 103 113 tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver" 104 114 depends on ARM64 || COMPILE_TEST
+1
drivers/pinctrl/qcom/Makefile
··· 51 51 obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o 52 52 obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o 53 53 obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o 54 + obj-$(CONFIG_PINCTRL_SDM670_LPASS_LPI) += pinctrl-sdm670-lpass-lpi.o 54 55 obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o 55 56 obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o 56 57 obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
+166
drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2023-2026, Richard Acayan. All rights reserved. 4 + */ 5 + 6 + #include <linux/kernel.h> 7 + #include <linux/module.h> 8 + #include <linux/of.h> 9 + #include <linux/platform_device.h> 10 + #include <linux/pinctrl/pinctrl.h> 11 + 12 + #include "pinctrl-lpass-lpi.h" 13 + 14 + enum lpass_lpi_functions { 15 + LPI_MUX_comp_rx, 16 + LPI_MUX_dmic1_clk, 17 + LPI_MUX_dmic1_data, 18 + LPI_MUX_dmic2_clk, 19 + LPI_MUX_dmic2_data, 20 + LPI_MUX_i2s1_clk, 21 + LPI_MUX_i2s1_data, 22 + LPI_MUX_i2s1_ws, 23 + LPI_MUX_lpi_cdc_rst, 24 + LPI_MUX_mclk0, 25 + LPI_MUX_pdm_rx, 26 + LPI_MUX_pdm_sync, 27 + LPI_MUX_pdm_tx, 28 + LPI_MUX_slimbus_clk, 29 + LPI_MUX_gpio, 30 + LPI_MUX__, 31 + }; 32 + 33 + static const struct pinctrl_pin_desc sdm670_lpi_pinctrl_pins[] = { 34 + PINCTRL_PIN(0, "gpio0"), 35 + PINCTRL_PIN(1, "gpio1"), 36 + PINCTRL_PIN(2, "gpio2"), 37 + PINCTRL_PIN(3, "gpio3"), 38 + PINCTRL_PIN(4, "gpio4"), 39 + PINCTRL_PIN(5, "gpio5"), 40 + PINCTRL_PIN(6, "gpio6"), 41 + PINCTRL_PIN(7, "gpio7"), 42 + PINCTRL_PIN(8, "gpio8"), 43 + PINCTRL_PIN(9, "gpio9"), 44 + PINCTRL_PIN(10, "gpio10"), 45 + PINCTRL_PIN(11, "gpio11"), 46 + PINCTRL_PIN(12, "gpio12"), 47 + PINCTRL_PIN(13, "gpio13"), 48 + PINCTRL_PIN(14, "gpio14"), 49 + PINCTRL_PIN(15, "gpio15"), 50 + PINCTRL_PIN(16, "gpio16"), 51 + PINCTRL_PIN(17, "gpio17"), 52 + PINCTRL_PIN(18, "gpio18"), 53 + PINCTRL_PIN(19, "gpio19"), 54 + PINCTRL_PIN(20, "gpio20"), 55 + PINCTRL_PIN(21, "gpio21"), 56 + PINCTRL_PIN(22, "gpio22"), 57 + PINCTRL_PIN(23, "gpio23"), 58 + PINCTRL_PIN(24, "gpio24"), 59 + PINCTRL_PIN(25, "gpio25"), 60 + PINCTRL_PIN(26, "gpio26"), 61 + PINCTRL_PIN(27, "gpio27"), 62 + PINCTRL_PIN(28, "gpio28"), 63 + PINCTRL_PIN(29, "gpio29"), 64 + PINCTRL_PIN(30, "gpio30"), 65 + PINCTRL_PIN(31, "gpio31"), 66 + }; 67 + 68 + static const char * const comp_rx_groups[] = { "gpio22", "gpio24" }; 69 + static const char * const dmic1_clk_groups[] = { "gpio26" }; 70 + static const char * const dmic1_data_groups[] = { "gpio27" }; 71 + static const char * const dmic2_clk_groups[] = { "gpio28" }; 72 + static const char * const dmic2_data_groups[] = { "gpio29" }; 73 + static const char * const i2s1_clk_groups[] = { "gpio8" }; 74 + static const char * const i2s1_ws_groups[] = { "gpio9" }; 75 + static const char * const i2s1_data_groups[] = { "gpio10", "gpio11" }; 76 + static const char * const lpi_cdc_rst_groups[] = { "gpio29" }; 77 + static const char * const mclk0_groups[] = { "gpio19" }; 78 + static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" }; 79 + static const char * const pdm_sync_groups[] = { "gpio19" }; 80 + static const char * const pdm_tx_groups[] = { "gpio20" }; 81 + static const char * const slimbus_clk_groups[] = { "gpio18" }; 82 + 83 + const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = { 84 + LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), 85 + LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), 86 + LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), 87 + LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _), 88 + LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _), 89 + LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _), 90 + LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _), 91 + LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _), 92 + LPI_PINGROUP(8, LPI_NO_SLEW, _, _, i2s1_clk, _), 93 + LPI_PINGROUP(9, LPI_NO_SLEW, _, _, i2s1_ws, _), 94 + LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, i2s1_data), 95 + LPI_PINGROUP(11, LPI_NO_SLEW, _, i2s1_data, _, _), 96 + LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _), 97 + LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _), 98 + LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _), 99 + LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _), 100 + LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _), 101 + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), 102 + LPI_PINGROUP(18, LPI_NO_SLEW, _, slimbus_clk, _, _), 103 + LPI_PINGROUP(19, LPI_NO_SLEW, mclk0, _, pdm_sync, _), 104 + LPI_PINGROUP(20, LPI_NO_SLEW, _, pdm_tx, _, _), 105 + LPI_PINGROUP(21, LPI_NO_SLEW, _, pdm_rx, _, _), 106 + LPI_PINGROUP(22, LPI_NO_SLEW, _, comp_rx, _, _), 107 + LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _), 108 + LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _), 109 + LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _), 110 + LPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _), 111 + LPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _), 112 + LPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _), 113 + LPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, lpi_cdc_rst, _, _), 114 + LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _), 115 + LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), 116 + }; 117 + 118 + const struct lpi_function sdm670_lpi_pinctrl_functions[] = { 119 + LPI_FUNCTION(comp_rx), 120 + LPI_FUNCTION(dmic1_clk), 121 + LPI_FUNCTION(dmic1_data), 122 + LPI_FUNCTION(dmic2_clk), 123 + LPI_FUNCTION(dmic2_data), 124 + LPI_FUNCTION(i2s1_clk), 125 + LPI_FUNCTION(i2s1_data), 126 + LPI_FUNCTION(i2s1_ws), 127 + LPI_FUNCTION(lpi_cdc_rst), 128 + LPI_FUNCTION(mclk0), 129 + LPI_FUNCTION(pdm_tx), 130 + LPI_FUNCTION(pdm_rx), 131 + LPI_FUNCTION(pdm_sync), 132 + LPI_FUNCTION(slimbus_clk), 133 + }; 134 + 135 + static const struct lpi_pinctrl_variant_data sdm670_lpi_pinctrl_data = { 136 + .pins = sdm670_lpi_pinctrl_pins, 137 + .npins = ARRAY_SIZE(sdm670_lpi_pinctrl_pins), 138 + .groups = sdm670_lpi_pinctrl_groups, 139 + .ngroups = ARRAY_SIZE(sdm670_lpi_pinctrl_groups), 140 + .functions = sdm670_lpi_pinctrl_functions, 141 + .nfunctions = ARRAY_SIZE(sdm670_lpi_pinctrl_functions), 142 + .flags = LPI_FLAG_SLEW_RATE_SAME_REG, 143 + }; 144 + 145 + static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = { 146 + { 147 + .compatible = "qcom,sdm670-lpass-lpi-pinctrl", 148 + .data = &sdm670_lpi_pinctrl_data, 149 + }, 150 + { } 151 + }; 152 + MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match); 153 + 154 + static struct platform_driver sdm670_lpi_pinctrl_driver = { 155 + .driver = { 156 + .name = "qcom-sdm670-lpass-lpi-pinctrl", 157 + .of_match_table = sdm670_lpi_pinctrl_of_match, 158 + }, 159 + .probe = lpi_pinctrl_probe, 160 + .remove = lpi_pinctrl_remove, 161 + }; 162 + module_platform_driver(sdm670_lpi_pinctrl_driver); 163 + 164 + MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>"); 165 + MODULE_DESCRIPTION("QTI SDM670 LPI GPIO pin control driver"); 166 + MODULE_LICENSE("GPL");