Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add SPI clocks and resets on Renesas RZ/G3E
- Add PCIe clocks and resets on Renesas RZ/V2N, RZ/V2H(P), and RZ/G3E
- Enable watchdog reset on Renesas RZ/N1D
- Remove clocks for watchdogs meant for other CPU cores on Renesas RZ/V2N
- Handle critical clock during system resume on Renesas RZ/G2L, RZ/G2UL, and
RZ/G3S
- Add initial support for the Renesas RZ/G3L (R9A08G046) SoC
* tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: Add support for RZ/G3L SoC
dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
clk: renesas: rzg2l: Re-enable critical module clocks during resume
clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
clk: renesas: rzg2l: Add helper for mod clock enable/disable
clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
clk: renesas: rzg2l: Add support for critical resets
clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
clk: renesas: r9a06g032: Enable watchdog reset sources
clk: renesas: cpg-mssr: Use struct_size() helper
clk: renesas: r9a09g047: Add PCIe clocks and reset
clk: renesas: r9a09g057: Add PCIe clocks and reset
clk: renesas: r9a09g056: Add PCIe clocks and reset
clk: renesas: r9a09g047: Add entries for the RSPIs
+698
-38
+35
-5
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+35
-5
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
···
28
28
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
29
29
- renesas,r9a07g054-cpg # RZ/V2L
30
30
- renesas,r9a08g045-cpg # RZ/G3S
31
+
- renesas,r9a08g046-cpg # RZ/G3L
31
32
- renesas,r9a09g011-cpg # RZ/V2M
32
33
33
34
reg:
34
35
maxItems: 1
35
36
36
37
clocks:
37
-
maxItems: 1
38
+
minItems: 1
39
+
items:
40
+
- description: Clock source to CPG can be either from external clock
41
+
input (EXCLK) or crystal oscillator (XIN/XOUT).
42
+
- description: ETH0 TXC clock input
43
+
- description: ETH0 RXC clock input
44
+
- description: ETH1 TXC clock input
45
+
- description: ETH1 RXC clock input
38
46
39
47
clock-names:
40
-
description:
41
-
Clock source to CPG can be either from external clock input (EXCLK) or
42
-
crystal oscillator (XIN/XOUT).
43
-
const: extal
48
+
minItems: 1
49
+
items:
50
+
- const: extal
51
+
- const: eth0_txc_tx_clk
52
+
- const: eth0_rxc_rx_clk
53
+
- const: eth1_txc_tx_clk
54
+
- const: eth1_rxc_rx_clk
44
55
45
56
'#clock-cells':
46
57
description: |
···
84
73
- '#clock-cells'
85
74
- '#power-domain-cells'
86
75
- '#reset-cells'
76
+
77
+
allOf:
78
+
- if:
79
+
properties:
80
+
compatible:
81
+
contains:
82
+
const: renesas,r9a08g046-cpg
83
+
then:
84
+
properties:
85
+
clocks:
86
+
minItems: 5
87
+
clock-names:
88
+
minItems: 5
89
+
else:
90
+
properties:
91
+
clocks:
92
+
maxItems: 1
93
+
clock-names:
94
+
maxItems: 1
87
95
88
96
additionalProperties: false
89
97
+6
-1
drivers/clk/renesas/Kconfig
+6
-1
drivers/clk/renesas/Kconfig
···
39
39
select CLK_R9A07G044 if ARCH_R9A07G044
40
40
select CLK_R9A07G054 if ARCH_R9A07G054
41
41
select CLK_R9A08G045 if ARCH_R9A08G045
42
+
select CLK_R9A08G046 if ARCH_R9A08G046
42
43
select CLK_R9A09G011 if ARCH_R9A09G011
43
44
select CLK_R9A09G047 if ARCH_R9A09G047
44
45
select CLK_R9A09G056 if ARCH_R9A09G056
···
195
194
bool "RZ/G3S clock support" if COMPILE_TEST
196
195
select CLK_RZG2L
197
196
197
+
config CLK_R9A08G046
198
+
bool "RZ/G3L clock support" if COMPILE_TEST
199
+
select CLK_RZG2L
200
+
198
201
config CLK_R9A09G011
199
202
bool "RZ/V2M clock support" if COMPILE_TEST
200
203
select CLK_RZG2L
···
255
250
This is a driver for R-Car USB2 clock selector
256
251
257
252
config CLK_RZG2L
258
-
bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
253
+
bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST
259
254
select RESET_CONTROLLER
260
255
261
256
config CLK_RZV2H
+1
drivers/clk/renesas/Makefile
+1
drivers/clk/renesas/Makefile
···
36
36
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
37
37
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
38
38
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
39
+
obj-$(CONFIG_CLK_R9A08G046) += r9a08g046-cpg.o
39
40
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
40
41
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
41
42
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
+3
-2
drivers/clk/renesas/r9a06g032-clocks.c
+3
-2
drivers/clk/renesas/r9a06g032-clocks.c
···
1342
1342
/* Clear potentially pending resets */
1343
1343
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
1344
1344
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
1345
-
/* Allow software reset */
1346
-
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1345
+
/* Allow watchdog and software resets */
1346
+
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 |
1347
+
R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1347
1348
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
1348
1349
1349
1350
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
+9
drivers/clk/renesas/r9a07g043-cpg.c
+9
drivers/clk/renesas/r9a07g043-cpg.c
···
379
379
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
380
380
};
381
381
382
+
static const unsigned int r9a07g043_crit_resets[] = {
383
+
R9A07G043_DMAC_ARESETN,
384
+
R9A07G043_DMAC_RST_ASYNC,
385
+
};
386
+
382
387
#ifdef CONFIG_ARM64
383
388
static const unsigned int r9a07g043_no_pm_mod_clks[] = {
384
389
MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
···
424
419
#ifdef CONFIG_RISCV
425
420
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
426
421
#endif
422
+
423
+
/* Critical Resets */
424
+
.crit_resets = r9a07g043_crit_resets,
425
+
.num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),
427
426
428
427
.has_clk_mon_regs = true,
429
428
};
+13
drivers/clk/renesas/r9a07g044-cpg.c
+13
drivers/clk/renesas/r9a07g044-cpg.c
···
489
489
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
490
490
};
491
491
492
+
static const unsigned int r9a07g044_crit_resets[] = {
493
+
R9A07G044_DMAC_ARESETN,
494
+
R9A07G044_DMAC_RST_ASYNC,
495
+
};
496
+
492
497
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
493
498
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
494
499
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
···
524
519
.resets = r9a07g044_resets,
525
520
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
526
521
522
+
/* Critical Resets */
523
+
.crit_resets = r9a07g044_crit_resets,
524
+
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
525
+
527
526
.has_clk_mon_regs = true,
528
527
};
529
528
#endif
···
556
547
/* Resets */
557
548
.resets = r9a07g044_resets,
558
549
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
550
+
551
+
/* Critical Resets */
552
+
.crit_resets = r9a07g044_crit_resets,
553
+
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
559
554
560
555
.has_clk_mon_regs = true,
561
556
};
+9
drivers/clk/renesas/r9a08g045-cpg.c
+9
drivers/clk/renesas/r9a08g045-cpg.c
···
361
361
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
362
362
};
363
363
364
+
static const unsigned int r9a08g045_crit_resets[] = {
365
+
R9A08G045_DMAC_ARESETN,
366
+
R9A08G045_DMAC_RST_ASYNC,
367
+
};
368
+
364
369
static const unsigned int r9a08g045_no_pm_mod_clks[] = {
365
370
MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
366
371
};
···
393
388
/* Resets */
394
389
.resets = r9a08g045_resets,
395
390
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
391
+
392
+
/* Critical Resets */
393
+
.crit_resets = r9a08g045_crit_resets,
394
+
.num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),
396
395
397
396
.has_clk_mon_regs = true,
398
397
};
+153
drivers/clk/renesas/r9a08g046-cpg.c
+153
drivers/clk/renesas/r9a08g046-cpg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* RZ/G3L CPG driver
4
+
*
5
+
* Copyright (C) 2026 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/device.h>
10
+
#include <linux/init.h>
11
+
#include <linux/kernel.h>
12
+
13
+
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
14
+
15
+
#include "rzg2l-cpg.h"
16
+
17
+
/* RZ/G3L Specific registers. */
18
+
#define G3L_CPG_PL2_DDIV (0x204)
19
+
#define G3L_CPG_PL3_DDIV (0x208)
20
+
#define G3L_CLKDIVSTATUS (0x280)
21
+
22
+
/* RZ/G3L Specific division configuration. */
23
+
#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
24
+
#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
25
+
#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
26
+
27
+
/* RZ/G3L Clock status configuration. */
28
+
#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
29
+
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
30
+
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
31
+
32
+
enum clk_ids {
33
+
/* Core Clock Outputs exported to DT */
34
+
LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
35
+
36
+
/* External Input Clocks */
37
+
CLK_EXTAL,
38
+
CLK_ETH0_TXC_TX_CLK_IN,
39
+
CLK_ETH0_RXC_RX_CLK_IN,
40
+
CLK_ETH1_TXC_TX_CLK_IN,
41
+
CLK_ETH1_RXC_RX_CLK_IN,
42
+
43
+
/* Internal Core Clocks */
44
+
CLK_PLL2,
45
+
CLK_PLL2_DIV2,
46
+
CLK_PLL3,
47
+
CLK_PLL3_DIV2,
48
+
49
+
/* Module Clocks */
50
+
MOD_CLK_BASE,
51
+
};
52
+
53
+
/* Divider tables */
54
+
static const struct clk_div_table dtable_4_128[] = {
55
+
{ 0, 4 },
56
+
{ 1, 8 },
57
+
{ 2, 16 },
58
+
{ 3, 128 },
59
+
{ 0, 0 },
60
+
};
61
+
62
+
static const struct clk_div_table dtable_8_256[] = {
63
+
{ 0, 8 },
64
+
{ 1, 16 },
65
+
{ 2, 32 },
66
+
{ 3, 256 },
67
+
{ 0, 0 },
68
+
};
69
+
70
+
static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
71
+
/* External Clock Inputs */
72
+
DEF_INPUT("extal", CLK_EXTAL),
73
+
DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
74
+
DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
75
+
DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
76
+
DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
77
+
78
+
/* Internal Core Clocks */
79
+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
80
+
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
81
+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
82
+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
83
+
84
+
/* Core output clk */
85
+
DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
86
+
dtable_8_256, 0, 0, 0, NULL),
87
+
DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
88
+
dtable_4_128, 0, 0, 0, NULL),
89
+
DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
90
+
dtable_4_128, 0, 0, 0, NULL),
91
+
};
92
+
93
+
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
94
+
DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, 0,
95
+
MSTOP(BUS_PERI_COM, BIT(12))),
96
+
DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0,
97
+
MSTOP(BUS_PERI_CPU, BIT(13))),
98
+
DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1,
99
+
MSTOP(BUS_PERI_CPU, BIT(13))),
100
+
DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0,
101
+
MSTOP(BUS_REG1, BIT(2))),
102
+
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
103
+
MSTOP(BUS_REG1, BIT(3))),
104
+
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
105
+
MSTOP(BUS_MCPU2, BIT(1))),
106
+
};
107
+
108
+
static const struct rzg2l_reset r9a08g046_resets[] = {
109
+
DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0),
110
+
DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1),
111
+
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
112
+
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
113
+
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
114
+
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
115
+
};
116
+
117
+
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
118
+
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
119
+
MOD_CLK_BASE + R9A08G046_IA55_CLK,
120
+
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
121
+
};
122
+
123
+
static const unsigned int r9a08g046_crit_resets[] = {
124
+
R9A08G046_DMAC_ARESETN,
125
+
R9A08G046_DMAC_RST_ASYNC,
126
+
};
127
+
128
+
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
129
+
/* Core Clocks */
130
+
.core_clks = r9a08g046_core_clks,
131
+
.num_core_clks = ARRAY_SIZE(r9a08g046_core_clks),
132
+
.last_dt_core_clk = LAST_DT_CORE_CLK,
133
+
.num_total_core_clks = MOD_CLK_BASE,
134
+
135
+
/* Critical Module Clocks */
136
+
.crit_mod_clks = r9a08g046_crit_mod_clks,
137
+
.num_crit_mod_clks = ARRAY_SIZE(r9a08g046_crit_mod_clks),
138
+
139
+
/* Module Clocks */
140
+
.mod_clks = r9a08g046_mod_clks,
141
+
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
142
+
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
143
+
144
+
/* Resets */
145
+
.resets = r9a08g046_resets,
146
+
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
147
+
148
+
/* Critical Resets */
149
+
.crit_resets = r9a08g046_crit_resets,
150
+
.num_crit_resets = ARRAY_SIZE(r9a08g046_crit_resets),
151
+
152
+
.has_clk_mon_regs = true,
153
+
};
+29
drivers/clk/renesas/r9a09g047-cpg.c
+29
drivers/clk/renesas/r9a09g047-cpg.c
···
224
224
BUS_MSTOP(5, BIT(13))),
225
225
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
226
226
BUS_MSTOP(5, BIT(13))),
227
+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
228
+
BUS_MSTOP(11, BIT(0))),
229
+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
230
+
BUS_MSTOP(11, BIT(0))),
231
+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
232
+
BUS_MSTOP(11, BIT(0))),
233
+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
234
+
BUS_MSTOP(11, BIT(1))),
235
+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
236
+
BUS_MSTOP(11, BIT(1))),
237
+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
238
+
BUS_MSTOP(11, BIT(1))),
239
+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
240
+
BUS_MSTOP(11, BIT(2))),
241
+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
242
+
BUS_MSTOP(11, BIT(2))),
243
+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
244
+
BUS_MSTOP(11, BIT(2))),
227
245
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
228
246
BUS_MSTOP(11, BIT(3))),
229
247
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
···
442
424
BUS_MSTOP(8, BIT(6))),
443
425
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
444
426
BUS_MSTOP(8, BIT(6))),
427
+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
428
+
BUS_MSTOP(1, BIT(15))),
429
+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
430
+
BUS_MSTOP(1, BIT(15))),
445
431
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
446
432
BUS_MSTOP(9, BIT(4))),
447
433
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
479
457
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
480
458
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
481
459
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
460
+
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
461
+
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
462
+
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
463
+
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
464
+
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
465
+
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
482
466
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
483
467
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
484
468
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
···
531
503
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
532
504
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
533
505
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
506
+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
534
507
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
535
508
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
536
509
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+5
-15
drivers/clk/renesas/r9a09g056-cpg.c
+5
-15
drivers/clk/renesas/r9a09g056-cpg.c
···
273
273
BUS_MSTOP(11, BIT(15))),
274
274
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
275
275
BUS_MSTOP(12, BIT(0))),
276
-
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
277
-
BUS_MSTOP(3, BIT(10))),
278
-
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
279
-
BUS_MSTOP(3, BIT(10))),
280
276
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
281
277
BUS_MSTOP(1, BIT(0))),
282
278
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
283
279
BUS_MSTOP(1, BIT(0))),
284
-
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
285
-
BUS_MSTOP(5, BIT(12))),
286
-
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
287
-
BUS_MSTOP(5, BIT(12))),
288
-
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
289
-
BUS_MSTOP(5, BIT(13))),
290
-
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
291
-
BUS_MSTOP(5, BIT(13))),
292
280
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
293
281
BUS_MSTOP(3, BIT(11) | BIT(12))),
294
282
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
···
493
505
BUS_MSTOP(8, BIT(6))),
494
506
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
495
507
BUS_MSTOP(8, BIT(6))),
508
+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
509
+
BUS_MSTOP(1, BIT(15))),
510
+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
511
+
BUS_MSTOP(1, BIT(15))),
496
512
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
497
513
BUS_MSTOP(9, BIT(4))),
498
514
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
563
571
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
564
572
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
565
573
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
566
-
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
567
574
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
568
-
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
569
-
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
570
575
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
571
576
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
572
577
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
···
617
628
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
618
629
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
619
630
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
631
+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
620
632
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
621
633
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
622
634
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+5
drivers/clk/renesas/r9a09g057-cpg.c
+5
drivers/clk/renesas/r9a09g057-cpg.c
···
508
508
BUS_MSTOP(8, BIT(6))),
509
509
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
510
510
BUS_MSTOP(8, BIT(6))),
511
+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
512
+
BUS_MSTOP(1, BIT(13) | BIT(15))),
513
+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
514
+
BUS_MSTOP(1, BIT(13) | BIT(15))),
511
515
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
512
516
BUS_MSTOP(9, BIT(4))),
513
517
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
646
642
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
647
643
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
648
644
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
645
+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
649
646
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
650
647
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
651
648
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
+2
-2
drivers/clk/renesas/renesas-cpg-mssr.c
+2
-2
drivers/clk/renesas/renesas-cpg-mssr.c
···
569
569
struct cpg_mssr_clk_domain {
570
570
struct generic_pm_domain genpd;
571
571
unsigned int num_core_pm_clks;
572
-
unsigned int core_pm_clks[];
572
+
unsigned int core_pm_clks[] __counted_by(num_core_pm_clks);
573
573
};
574
574
575
575
static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
···
667
667
size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
668
668
int ret;
669
669
670
-
pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
670
+
pd = devm_kzalloc(dev, struct_size(pd, core_pm_clks, num_core_pm_clks), GFP_KERNEL);
671
671
if (!pd)
672
672
return -ENOMEM;
673
673
+78
-13
drivers/clk/renesas/rzg2l-cpg.c
+78
-13
drivers/clk/renesas/rzg2l-cpg.c
···
1439
1439
}
1440
1440
DEFINE_SHOW_ATTRIBUTE(rzg2l_mod_clock_mstop);
1441
1441
1442
-
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
1442
+
static int rzg2l_mod_clock_endisable_helper(struct clk_hw *hw, bool enable,
1443
+
bool set_mstop_state)
1443
1444
{
1444
1445
struct mod_clock *clock = to_mod_clock(hw);
1445
1446
struct rzg2l_cpg_priv *priv = clock->priv;
···
1465
1464
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1466
1465
if (enable) {
1467
1466
writel(value, priv->base + CLK_ON_R(reg));
1468
-
rzg2l_mod_clock_module_set_state(clock, false);
1467
+
if (set_mstop_state)
1468
+
rzg2l_mod_clock_module_set_state(clock, false);
1469
1469
} else {
1470
-
rzg2l_mod_clock_module_set_state(clock, true);
1470
+
if (set_mstop_state)
1471
+
rzg2l_mod_clock_module_set_state(clock, true);
1471
1472
writel(value, priv->base + CLK_ON_R(reg));
1472
1473
}
1473
1474
}
···
1487
1484
CLK_ON_R(reg), hw->clk);
1488
1485
1489
1486
return error;
1487
+
}
1488
+
1489
+
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
1490
+
{
1491
+
return rzg2l_mod_clock_endisable_helper(hw, enable, true);
1490
1492
}
1491
1493
1492
1494
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
···
1594
1586
return NULL;
1595
1587
}
1596
1588
1589
+
static void rzg2l_mod_clock_init_mstop_helper(struct rzg2l_cpg_priv *priv,
1590
+
struct mod_clock *clk)
1591
+
{
1592
+
/*
1593
+
* Out of reset all modules are enabled. Set module state in case
1594
+
* associated clocks are disabled at probe/resume. Otherwise module
1595
+
* is in invalid HW state.
1596
+
*/
1597
+
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1598
+
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
1599
+
rzg2l_mod_clock_module_set_state(clk, true);
1600
+
}
1601
+
}
1602
+
1603
+
static void rzg2l_mod_enable_crit_clock_init_mstop(struct rzg2l_cpg_priv *priv)
1604
+
{
1605
+
struct mod_clock *clk;
1606
+
struct clk_hw *hw;
1607
+
1608
+
for_each_mod_clock(clk, hw, priv) {
1609
+
if ((clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) &&
1610
+
(!rzg2l_mod_clock_is_enabled(&clk->hw)))
1611
+
rzg2l_mod_clock_endisable_helper(&clk->hw, true, false);
1612
+
1613
+
if (clk->mstop)
1614
+
rzg2l_mod_clock_init_mstop_helper(priv, clk);
1615
+
}
1616
+
}
1617
+
1597
1618
static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv)
1598
1619
{
1599
1620
struct mod_clock *clk;
···
1632
1595
if (!clk->mstop)
1633
1596
continue;
1634
1597
1635
-
/*
1636
-
* Out of reset all modules are enabled. Set module state
1637
-
* in case associated clocks are disabled at probe. Otherwise
1638
-
* module is in invalid HW state.
1639
-
*/
1640
-
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
1641
-
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
1642
-
rzg2l_mod_clock_module_set_state(clk, true);
1643
-
}
1598
+
rzg2l_mod_clock_init_mstop_helper(priv, clk);
1644
1599
}
1645
1600
}
1646
1601
···
1794
1765
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
1795
1766
assert ? "assert" : "deassert", id, CLK_RST_R(reg));
1796
1767
1768
+
if (assert) {
1769
+
for (unsigned int i = 0; i < priv->info->num_crit_resets; i++) {
1770
+
if (id == priv->info->crit_resets[i])
1771
+
return 0;
1772
+
}
1773
+
}
1774
+
1797
1775
if (!assert)
1798
1776
value |= mask;
1799
1777
writel(value, priv->base + CLK_RST_R(reg));
···
1836
1800
unsigned long id)
1837
1801
{
1838
1802
return __rzg2l_cpg_assert(rcdev, id, false);
1803
+
}
1804
+
1805
+
static int rzg2l_cpg_deassert_crit_resets(struct reset_controller_dev *rcdev,
1806
+
const struct rzg2l_cpg_info *info)
1807
+
{
1808
+
int ret;
1809
+
1810
+
for (unsigned int i = 0; i < info->num_crit_resets; i++) {
1811
+
ret = rzg2l_cpg_deassert(rcdev, info->crit_resets[i]);
1812
+
if (ret)
1813
+
return ret;
1814
+
}
1815
+
1816
+
return 0;
1839
1817
}
1840
1818
1841
1819
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
···
2101
2051
if (error)
2102
2052
return error;
2103
2053
2054
+
error = rzg2l_cpg_deassert_crit_resets(&priv->rcdev, info);
2055
+
if (error)
2056
+
return error;
2057
+
2104
2058
debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fops);
2105
2059
return 0;
2106
2060
}
···
2112
2058
static int rzg2l_cpg_resume(struct device *dev)
2113
2059
{
2114
2060
struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
2061
+
int ret;
2115
2062
2116
-
rzg2l_mod_clock_init_mstop(priv);
2063
+
ret = rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info);
2064
+
if (ret)
2065
+
return ret;
2066
+
2067
+
rzg2l_mod_enable_crit_clock_init_mstop(priv);
2117
2068
2118
2069
return 0;
2119
2070
}
···
2150
2091
{
2151
2092
.compatible = "renesas,r9a08g045-cpg",
2152
2093
.data = &r9a08g045_cpg_info,
2094
+
},
2095
+
#endif
2096
+
#ifdef CONFIG_CLK_R9A08G046
2097
+
{
2098
+
.compatible = "renesas,r9a08g046-cpg",
2099
+
.data = &r9a08g046_cpg_info,
2153
2100
},
2154
2101
#endif
2155
2102
#ifdef CONFIG_CLK_R9A09G011
+8
drivers/clk/renesas/rzg2l-cpg.h
+8
drivers/clk/renesas/rzg2l-cpg.h
···
276
276
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
277
277
* should not be disabled without a knowledgeable driver
278
278
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
279
+
* @crit_resets: Array with Reset IDs of critical resets that should not be
280
+
* asserted without a knowledgeable driver
281
+
* @num_crit_resets: Number of entries in crit_resets[]
279
282
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
280
283
*/
281
284
struct rzg2l_cpg_info {
···
305
302
const unsigned int *crit_mod_clks;
306
303
unsigned int num_crit_mod_clks;
307
304
305
+
/* Critical Resets that should not be asserted */
306
+
const unsigned int *crit_resets;
307
+
unsigned int num_crit_resets;
308
+
308
309
bool has_clk_mon_regs;
309
310
};
310
311
···
316
309
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
317
310
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
318
311
extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
312
+
extern const struct rzg2l_cpg_info r9a08g046_cpg_info;
319
313
extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
320
314
321
315
int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);
+342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
+342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2026 Renesas Electronics Corp.
4
+
*/
5
+
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
6
+
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
7
+
8
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
+
10
+
/* R9A08G046 CPG Core Clocks */
11
+
#define R9A08G046_CLK_I 0
12
+
#define R9A08G046_CLK_IC0 1
13
+
#define R9A08G046_CLK_IC1 2
14
+
#define R9A08G046_CLK_IC2 3
15
+
#define R9A08G046_CLK_IC3 4
16
+
#define R9A08G046_CLK_P0 5
17
+
#define R9A08G046_CLK_P1 6
18
+
#define R9A08G046_CLK_P2 7
19
+
#define R9A08G046_CLK_P3 8
20
+
#define R9A08G046_CLK_P4 9
21
+
#define R9A08G046_CLK_P5 10
22
+
#define R9A08G046_CLK_P6 11
23
+
#define R9A08G046_CLK_P7 12
24
+
#define R9A08G046_CLK_P8 13
25
+
#define R9A08G046_CLK_P9 14
26
+
#define R9A08G046_CLK_P10 15
27
+
#define R9A08G046_CLK_P13 16
28
+
#define R9A08G046_CLK_P14 17
29
+
#define R9A08G046_CLK_P15 18
30
+
#define R9A08G046_CLK_P16 19
31
+
#define R9A08G046_CLK_P17 20
32
+
#define R9A08G046_CLK_P18 21
33
+
#define R9A08G046_CLK_P19 22
34
+
#define R9A08G046_CLK_P20 23
35
+
#define R9A08G046_CLK_M0 24
36
+
#define R9A08G046_CLK_M1 25
37
+
#define R9A08G046_CLK_M2 26
38
+
#define R9A08G046_CLK_M3 27
39
+
#define R9A08G046_CLK_M4 28
40
+
#define R9A08G046_CLK_M5 29
41
+
#define R9A08G046_CLK_M6 30
42
+
#define R9A08G046_CLK_AT 31
43
+
#define R9A08G046_CLK_B 32
44
+
#define R9A08G046_CLK_ETHTX01 33
45
+
#define R9A08G046_CLK_ETHTX02 34
46
+
#define R9A08G046_CLK_ETHRX01 35
47
+
#define R9A08G046_CLK_ETHRX02 36
48
+
#define R9A08G046_CLK_ETHRM0 37
49
+
#define R9A08G046_CLK_ETHTX11 38
50
+
#define R9A08G046_CLK_ETHTX12 39
51
+
#define R9A08G046_CLK_ETHRX11 40
52
+
#define R9A08G046_CLK_ETHRX12 41
53
+
#define R9A08G046_CLK_ETHRM1 42
54
+
#define R9A08G046_CLK_G 43
55
+
#define R9A08G046_CLK_HP 44
56
+
#define R9A08G046_CLK_SD0 45
57
+
#define R9A08G046_CLK_SD1 46
58
+
#define R9A08G046_CLK_SD2 47
59
+
#define R9A08G046_CLK_SPI0 48
60
+
#define R9A08G046_CLK_SPI1 49
61
+
#define R9A08G046_CLK_S0 50
62
+
#define R9A08G046_CLK_SWD 51
63
+
#define R9A08G046_OSCCLK 52
64
+
#define R9A08G046_OSCCLK2 53
65
+
#define R9A08G046_MIPI_DSI_PLLCLK 54
66
+
#define R9A08G046_USB_SCLK 55
67
+
68
+
/* R9A08G046 Module Clocks */
69
+
#define R9A08G046_CA55_SCLK 0
70
+
#define R9A08G046_CA55_PCLK 1
71
+
#define R9A08G046_CA55_ATCLK 2
72
+
#define R9A08G046_CA55_GICCLK 3
73
+
#define R9A08G046_CA55_PERICLK 4
74
+
#define R9A08G046_CA55_ACLK 5
75
+
#define R9A08G046_CA55_TSCLK 6
76
+
#define R9A08G046_CA55_CORECLK0 7
77
+
#define R9A08G046_CA55_CORECLK1 8
78
+
#define R9A08G046_CA55_CORECLK2 9
79
+
#define R9A08G046_CA55_CORECLK3 10
80
+
#define R9A08G046_SRAM_ACPU_ACLK0 11
81
+
#define R9A08G046_SRAM_ACPU_ACLK1 12
82
+
#define R9A08G046_SRAM_ACPU_ACLK2 13
83
+
#define R9A08G046_GIC600_GICCLK 14
84
+
#define R9A08G046_IA55_CLK 15
85
+
#define R9A08G046_IA55_PCLK 16
86
+
#define R9A08G046_MHU_PCLK 17
87
+
#define R9A08G046_SYC_CNT_CLK 18
88
+
#define R9A08G046_DMAC_ACLK 19
89
+
#define R9A08G046_DMAC_PCLK 20
90
+
#define R9A08G046_OSTM0_PCLK 21
91
+
#define R9A08G046_OSTM1_PCLK 22
92
+
#define R9A08G046_OSTM2_PCLK 23
93
+
#define R9A08G046_MTU_X_MCK_MTU3 24
94
+
#define R9A08G046_POE3_CLKM_POE 25
95
+
#define R9A08G046_GPT_PCLK 26
96
+
#define R9A08G046_POEG_A_CLKP 27
97
+
#define R9A08G046_POEG_B_CLKP 28
98
+
#define R9A08G046_POEG_C_CLKP 29
99
+
#define R9A08G046_POEG_D_CLKP 30
100
+
#define R9A08G046_WDT0_PCLK 31
101
+
#define R9A08G046_WDT0_CLK 32
102
+
#define R9A08G046_WDT1_PCLK 33
103
+
#define R9A08G046_WDT1_CLK 34
104
+
#define R9A08G046_WDT2_PCLK 35
105
+
#define R9A08G046_WDT2_CLK 36
106
+
#define R9A08G046_XSPI_HCLK 37
107
+
#define R9A08G046_XSPI_ACLK 38
108
+
#define R9A08G046_XSPI_CLK 39
109
+
#define R9A08G046_XSPI_CLKX2 40
110
+
#define R9A08G046_SDHI0_IMCLK 41
111
+
#define R9A08G046_SDHI0_IMCLK2 42
112
+
#define R9A08G046_SDHI0_CLK_HS 43
113
+
#define R9A08G046_SDHI0_IACLKS 44
114
+
#define R9A08G046_SDHI0_IACLKM 45
115
+
#define R9A08G046_SDHI1_IMCLK 46
116
+
#define R9A08G046_SDHI1_IMCLK2 47
117
+
#define R9A08G046_SDHI1_CLK_HS 48
118
+
#define R9A08G046_SDHI1_IACLKS 49
119
+
#define R9A08G046_SDHI1_IACLKM 50
120
+
#define R9A08G046_SDHI2_IMCLK 51
121
+
#define R9A08G046_SDHI2_IMCLK2 52
122
+
#define R9A08G046_SDHI2_CLK_HS 53
123
+
#define R9A08G046_SDHI2_IACLKS 54
124
+
#define R9A08G046_SDHI2_IACLKM 55
125
+
#define R9A08G046_GE3D_CLK 56
126
+
#define R9A08G046_GE3D_AXI_CLK 57
127
+
#define R9A08G046_GE3D_ACE_CLK 58
128
+
#define R9A08G046_ISU_ACLK 59
129
+
#define R9A08G046_ISU_PCLK 60
130
+
#define R9A08G046_H264_CLK_A 61
131
+
#define R9A08G046_H264_CLK_P 62
132
+
#define R9A08G046_CRU_SYSCLK 63
133
+
#define R9A08G046_CRU_VCLK 64
134
+
#define R9A08G046_CRU_PCLK 65
135
+
#define R9A08G046_CRU_ACLK 66
136
+
#define R9A08G046_MIPI_DSI_SYSCLK 67
137
+
#define R9A08G046_MIPI_DSI_ACLK 68
138
+
#define R9A08G046_MIPI_DSI_PCLK 69
139
+
#define R9A08G046_MIPI_DSI_VCLK 70
140
+
#define R9A08G046_MIPI_DSI_LPCLK 71
141
+
#define R9A08G046_LVDS_PLLCLK 72
142
+
#define R9A08G046_LVDS_CLK_DOT0 73
143
+
#define R9A08G046_LCDC_CLK_A 74
144
+
#define R9A08G046_LCDC_CLK_D 75
145
+
#define R9A08G046_LCDC_CLK_P 76
146
+
#define R9A08G046_SSI0_PCLK2 77
147
+
#define R9A08G046_SSI0_PCLK_SFR 78
148
+
#define R9A08G046_SSI1_PCLK2 79
149
+
#define R9A08G046_SSI1_PCLK_SFR 80
150
+
#define R9A08G046_SSI2_PCLK2 81
151
+
#define R9A08G046_SSI2_PCLK_SFR 82
152
+
#define R9A08G046_SSI3_PCLK2 83
153
+
#define R9A08G046_SSI3_PCLK_SFR 84
154
+
#define R9A08G046_USB_U2H0_HCLK 85
155
+
#define R9A08G046_USB_U2H1_HCLK 86
156
+
#define R9A08G046_USB_U2P0_EXR_CPUCLK 87
157
+
#define R9A08G046_USB_U2P1_EXR_CPUCLK 88
158
+
#define R9A08G046_USB_PCLK 89
159
+
#define R9A08G046_ETH0_CLK_AXI 90
160
+
#define R9A08G046_ETH0_CLK_CHI 91
161
+
#define R9A08G046_ETH0_CLK_TX_I 92
162
+
#define R9A08G046_ETH0_CLK_RX_I 93
163
+
#define R9A08G046_ETH0_CLK_TX_180_I 94
164
+
#define R9A08G046_ETH0_CLK_RX_180_I 95
165
+
#define R9A08G046_ETH0_CLK_RMII_I 96
166
+
#define R9A08G046_ETH0_CLK_PTP_REF_I 97
167
+
#define R9A08G046_ETH0_CLK_TX_I_RMII 98
168
+
#define R9A08G046_ETH0_CLK_RX_I_RMII 99
169
+
#define R9A08G046_ETH1_CLK_AXI 100
170
+
#define R9A08G046_ETH1_CLK_CHI 101
171
+
#define R9A08G046_ETH1_CLK_TX_I 102
172
+
#define R9A08G046_ETH1_CLK_RX_I 103
173
+
#define R9A08G046_ETH1_CLK_TX_180_I 104
174
+
#define R9A08G046_ETH1_CLK_RX_180_I 105
175
+
#define R9A08G046_ETH1_CLK_RMII_I 106
176
+
#define R9A08G046_ETH1_CLK_PTP_REF_I 107
177
+
#define R9A08G046_ETH1_CLK_TX_I_RMII 108
178
+
#define R9A08G046_ETH1_CLK_RX_I_RMII 109
179
+
#define R9A08G046_I2C0_PCLK 110
180
+
#define R9A08G046_I2C1_PCLK 111
181
+
#define R9A08G046_I2C2_PCLK 112
182
+
#define R9A08G046_I2C3_PCLK 113
183
+
#define R9A08G046_SCIF0_CLK_PCK 114
184
+
#define R9A08G046_SCIF1_CLK_PCK 115
185
+
#define R9A08G046_SCIF2_CLK_PCK 116
186
+
#define R9A08G046_SCIF3_CLK_PCK 117
187
+
#define R9A08G046_SCIF4_CLK_PCK 118
188
+
#define R9A08G046_SCIF5_CLK_PCK 119
189
+
#define R9A08G046_RSCI0_PCLK 120
190
+
#define R9A08G046_RSCI0_TCLK 121
191
+
#define R9A08G046_RSCI1_PCLK 122
192
+
#define R9A08G046_RSCI1_TCLK 123
193
+
#define R9A08G046_RSCI2_PCLK 124
194
+
#define R9A08G046_RSCI2_TCLK 125
195
+
#define R9A08G046_RSCI3_PCLK 126
196
+
#define R9A08G046_RSCI3_TCLK 127
197
+
#define R9A08G046_RSPI0_PCLK 128
198
+
#define R9A08G046_RSPI0_TCLK 129
199
+
#define R9A08G046_RSPI1_PCLK 130
200
+
#define R9A08G046_RSPI1_TCLK 131
201
+
#define R9A08G046_RSPI2_PCLK 132
202
+
#define R9A08G046_RSPI2_TCLK 133
203
+
#define R9A08G046_CANFD_PCLK 134
204
+
#define R9A08G046_CANFD_CLK_RAM 135
205
+
#define R9A08G046_GPIO_HCLK 136
206
+
#define R9A08G046_ADC0_ADCLK 137
207
+
#define R9A08G046_ADC0_PCLK 138
208
+
#define R9A08G046_ADC1_ADCLK 139
209
+
#define R9A08G046_ADC1_PCLK 140
210
+
#define R9A08G046_TSU_PCLK 141
211
+
#define R9A08G046_PDM_PCLK 142
212
+
#define R9A08G046_PDM_CCLK 143
213
+
#define R9A08G046_PCI_ACLK 144
214
+
#define R9A08G046_PCI_CLKL1PM 145
215
+
#define R9A08G046_PCI_CLK_PMU 146
216
+
#define R9A08G046_SPDIF_PCLK 147
217
+
#define R9A08G046_I3C_TCLK 148
218
+
#define R9A08G046_I3C_PCLK 149
219
+
#define R9A08G046_VBAT_BCLK 150
220
+
#define R9A08G046_BSC_X_BCK_BSC 151
221
+
222
+
/* R9A08G046 Resets */
223
+
#define R9A08G046_CA55_RST0_0 0
224
+
#define R9A08G046_CA55_RST0_1 1
225
+
#define R9A08G046_CA55_RST0_2 2
226
+
#define R9A08G046_CA55_RST0_3 3
227
+
#define R9A08G046_CA55_RST4_0 4
228
+
#define R9A08G046_CA55_RST4_1 5
229
+
#define R9A08G046_CA55_RST4_2 6
230
+
#define R9A08G046_CA55_RST4_3 7
231
+
#define R9A08G046_CA55_RST8 8
232
+
#define R9A08G046_CA55_RST9 9
233
+
#define R9A08G046_CA55_RST10 10
234
+
#define R9A08G046_CA55_RST11 11
235
+
#define R9A08G046_CA55_RST12 12
236
+
#define R9A08G046_CA55_RST13 13
237
+
#define R9A08G046_CA55_RST14 14
238
+
#define R9A08G046_CA55_RST15 15
239
+
#define R9A08G046_CA55_RST16 16
240
+
#define R9A08G046_SRAM_ACPU_ARESETN0 17
241
+
#define R9A08G046_SRAM_ACPU_ARESETN1 18
242
+
#define R9A08G046_SRAM_ACPU_ARESETN2 19
243
+
#define R9A08G046_GIC600_GICRESET_N 20
244
+
#define R9A08G046_GIC600_DBG_GICRESET_N 21
245
+
#define R9A08G046_IA55_RESETN 22
246
+
#define R9A08G046_MHU_RESETN 23
247
+
#define R9A08G046_SYC_RESETN 24
248
+
#define R9A08G046_DMAC_ARESETN 25
249
+
#define R9A08G046_DMAC_RST_ASYNC 26
250
+
#define R9A08G046_GTM0_PRESETZ 27
251
+
#define R9A08G046_GTM1_PRESETZ 28
252
+
#define R9A08G046_GTM2_PRESETZ 29
253
+
#define R9A08G046_MTU_X_PRESET_MTU3 30
254
+
#define R9A08G046_POE3_RST_M_REG 31
255
+
#define R9A08G046_GPT_RST_C 32
256
+
#define R9A08G046_POEG_A_RST 33
257
+
#define R9A08G046_POEG_B_RST 34
258
+
#define R9A08G046_POEG_C_RST 35
259
+
#define R9A08G046_POEG_D_RST 36
260
+
#define R9A08G046_WDT0_PRESETN 37
261
+
#define R9A08G046_WDT1_PRESETN 38
262
+
#define R9A08G046_WDT2_PRESETN 39
263
+
#define R9A08G046_XSPI_HRESETN 40
264
+
#define R9A08G046_XSPI_ARESETN 41
265
+
#define R9A08G046_SDHI0_IXRST 42
266
+
#define R9A08G046_SDHI1_IXRST 43
267
+
#define R9A08G046_SDHI2_IXRST 44
268
+
#define R9A08G046_SDHI0_IXRSTAXIM 45
269
+
#define R9A08G046_SDHI0_IXRSTAXIS 46
270
+
#define R9A08G046_SDHI1_IXRSTAXIM 47
271
+
#define R9A08G046_SDHI1_IXRSTAXIS 48
272
+
#define R9A08G046_SDHI2_IXRSTAXIM 49
273
+
#define R9A08G046_SDHI2_IXRSTAXIS 50
274
+
#define R9A08G046_GE3D_RESETN 51
275
+
#define R9A08G046_GE3D_AXI_RESETN 52
276
+
#define R9A08G046_GE3D_ACE_RESETN 53
277
+
#define R9A08G046_ISU_ARESETN 54
278
+
#define R9A08G046_ISU_PRESETN 55
279
+
#define R9A08G046_H264_X_RESET_VCP 56
280
+
#define R9A08G046_H264_CP_PRESET_P 57
281
+
#define R9A08G046_CRU_CMN_RSTB 58
282
+
#define R9A08G046_CRU_PRESETN 59
283
+
#define R9A08G046_CRU_ARESETN 60
284
+
#define R9A08G046_MIPI_DSI_CMN_RSTB 61
285
+
#define R9A08G046_MIPI_DSI_ARESET_N 62
286
+
#define R9A08G046_MIPI_DSI_PRESET_N 63
287
+
#define R9A08G046_LCDC_RESET_N 64
288
+
#define R9A08G046_SSI0_RST_M2_REG 65
289
+
#define R9A08G046_SSI1_RST_M2_REG 66
290
+
#define R9A08G046_SSI2_RST_M2_REG 67
291
+
#define R9A08G046_SSI3_RST_M2_REG 68
292
+
#define R9A08G046_USB_U2H0_HRESETN 69
293
+
#define R9A08G046_USB_U2H1_HRESETN 70
294
+
#define R9A08G046_USB_U2P0_EXL_SYSRST 71
295
+
#define R9A08G046_USB_PRESETN 72
296
+
#define R9A08G046_USB_U2P1_EXL_SYSRST 73
297
+
#define R9A08G046_ETH0_ARESET_N 74
298
+
#define R9A08G046_ETH1_ARESET_N 75
299
+
#define R9A08G046_I2C0_MRST 76
300
+
#define R9A08G046_I2C1_MRST 77
301
+
#define R9A08G046_I2C2_MRST 78
302
+
#define R9A08G046_I2C3_MRST 79
303
+
#define R9A08G046_SCIF0_RST_SYSTEM_N 80
304
+
#define R9A08G046_SCIF1_RST_SYSTEM_N 81
305
+
#define R9A08G046_SCIF2_RST_SYSTEM_N 82
306
+
#define R9A08G046_SCIF3_RST_SYSTEM_N 83
307
+
#define R9A08G046_SCIF4_RST_SYSTEM_N 84
308
+
#define R9A08G046_SCIF5_RST_SYSTEM_N 85
309
+
#define R9A08G046_RSPI0_PRESETN 86
310
+
#define R9A08G046_RSPI1_PRESETN 87
311
+
#define R9A08G046_RSPI2_PRESETN 88
312
+
#define R9A08G046_RSPI0_TRESETN 89
313
+
#define R9A08G046_RSPI1_TRESETN 90
314
+
#define R9A08G046_RSPI2_TRESETN 91
315
+
#define R9A08G046_CANFD_RSTP_N 92
316
+
#define R9A08G046_CANFD_RSTC_N 93
317
+
#define R9A08G046_GPIO_RSTN 94
318
+
#define R9A08G046_GPIO_PORT_RESETN 95
319
+
#define R9A08G046_GPIO_SPARE_RESETN 96
320
+
#define R9A08G046_ADC0_PRESETN 97
321
+
#define R9A08G046_ADC0_ADRST_N 98
322
+
#define R9A08G046_ADC1_PRESETN 99
323
+
#define R9A08G046_ADC1_ADRST_N 100
324
+
#define R9A08G046_TSU_PRESETN 101
325
+
#define R9A08G046_PDM_PRESETN 102
326
+
#define R9A08G046_PCI_ARESETN 103
327
+
#define R9A08G046_SPDIF_RST 104
328
+
#define R9A08G046_I3C_TRESETN 105
329
+
#define R9A08G046_I3C_PRESETN 106
330
+
#define R9A08G046_VBAT_BRESETN 107
331
+
#define R9A08G046_RSCI0_PRESETN 108
332
+
#define R9A08G046_RSCI1_PRESETN 109
333
+
#define R9A08G046_RSCI2_PRESETN 110
334
+
#define R9A08G046_RSCI3_PRESETN 111
335
+
#define R9A08G046_RSCI0_TRESETN 112
336
+
#define R9A08G046_RSCI1_TRESETN 113
337
+
#define R9A08G046_RSCI2_TRESETN 114
338
+
#define R9A08G046_RSCI3_TRESETN 115
339
+
#define R9A08G046_LVDS_RESET_N 116
340
+
#define R9A08G046_BSC_X_PRESET_BSC 117
341
+
342
+
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */