Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: adjust xcc logic for gfxhub v12_1
Adjust xcc_id logic to only use physical xcc_id when program
register, (use logic xcc_id by default), to fit for compute
partition.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Likun Gao
and committed by
Alex Deucher
98320bf3
1a856863
+33
-19
+33
-19
drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c
+33
-19
drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c
···
65
65
struct amdgpu_vmhub *hub;
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int i;
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-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
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+
for_each_inst(i, xcc_mask) {
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hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
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WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),
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regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
···
83
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uint32_t vmid,
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uint64_t page_table_base)
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{
86
+
uint32_t xcc_mask;
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+
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+
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
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gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, vmid, page_table_base,
87
-
adev->gfx.xcc_mask);
90
+
xcc_mask);
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}
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static void gfxhub_v12_1_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,
···
106
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/* If use GART for FB translation, vmid0 page table covers both
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* vram and system memory (gart)
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*/
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-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
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+
for_each_inst(i, xcc_mask) {
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if (adev->gmc.pdb0_bo) {
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WREG32_SOC15(GC, GET_INST(GC, i),
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regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
···
146
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uint32_t tmp;
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int i;
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-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
146
+
for_each_inst(i, xcc_mask) {
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/* Program the AGP BAR */
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WREG32_SOC15_RLC(GC, GET_INST(GC, i),
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regGCMC_VM_AGP_BASE_LO32, 0);
···
248
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uint32_t tmp;
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int i;
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251
-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
248
+
for_each_inst(i, xcc_mask) {
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/* Setup TLB control */
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tmp = RREG32_SOC15(GC, GET_INST(GC, i),
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regGCMC_VM_MX_L1_TLB_CNTL);
···
283
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uint32_t tmp;
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int i;
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-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
283
+
for_each_inst(i, xcc_mask) {
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/* Setup L2 cache */
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tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL);
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tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
···
344
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uint32_t tmp;
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int i;
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-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
344
+
for_each_inst(i, xcc_mask) {
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tmp = RREG32_SOC15(GC, GET_INST(GC, i),
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regGCVM_CONTEXT0_CNTL);
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tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
···
367
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{
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int i;
369
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370
-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
367
+
for_each_inst(i, xcc_mask) {
371
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WREG32_SOC15(GC, GET_INST(GC, i),
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regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
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0XFFFFFFFF);
···
403
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block_size = adev->vm_manager.block_size;
404
401
block_size -= 9;
405
402
406
-
for (j = 0; j < NUM_XCC(xcc_mask); j++) {
403
+
for_each_inst(j, xcc_mask) {
407
404
hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
408
405
for (i = 0; i <= 14; i++) {
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tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
···
461
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struct amdgpu_vmhub *hub;
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unsigned int i, j;
463
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-
for (j = 0; j < NUM_XCC(xcc_mask); j++) {
461
+
for_each_inst(j, xcc_mask) {
465
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hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
466
463
467
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for (i = 0 ; i < 18; ++i) {
···
484
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/* GCMC_VM_FB_LOCATION_BASE/TOP are VF copy registers
485
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* VBIO post does not program them at boot up phase
486
483
* Need driver to program them from guest side */
487
-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
484
+
for_each_inst(i, xcc_mask) {
488
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WREG32_SOC15(GC, GET_INST(GC, i),
489
486
regGCMC_VM_FB_LOCATION_BASE_LO32,
490
487
lower_32_bits(adev->gmc.vram_start >> 24));
···
517
514
518
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static int gfxhub_v12_1_gart_enable(struct amdgpu_device *adev)
519
516
{
520
-
return gfxhub_v12_1_xcc_gart_enable(adev,
521
-
adev->gfx.xcc_mask);
517
+
uint32_t xcc_mask;
518
+
519
+
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
520
+
return gfxhub_v12_1_xcc_gart_enable(adev, xcc_mask);
522
521
}
523
522
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523
static void gfxhub_v12_1_xcc_gart_disable(struct amdgpu_device *adev,
···
530
525
u32 tmp;
531
526
u32 i, j;
532
527
533
-
for (j = 0; j < NUM_XCC(xcc_mask); j++) {
528
+
for_each_inst(j, xcc_mask) {
534
529
hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
535
530
/* Disable all tables */
536
531
for (i = 0; i < 16; i++)
···
560
555
561
556
static void gfxhub_v12_1_gart_disable(struct amdgpu_device *adev)
562
557
{
563
-
gfxhub_v12_1_xcc_gart_disable(adev, adev->gfx.xcc_mask);
558
+
uint32_t xcc_mask;
559
+
560
+
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
561
+
gfxhub_v12_1_xcc_gart_disable(adev, xcc_mask);
564
562
}
565
563
566
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static void gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev,
···
572
564
u32 tmp;
573
565
int i;
574
566
575
-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
567
+
for_each_inst(i, xcc_mask) {
576
568
tmp = RREG32_SOC15(GC, GET_INST(GC, i),
577
569
regGCVM_L2_PROTECTION_FAULT_CNTL_LO32);
578
570
tmp = REG_SET_FIELD(tmp,
···
645
637
static void gfxhub_v12_1_set_fault_enable_default(struct amdgpu_device *adev,
646
638
bool value)
647
639
{
648
-
gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, adev->gfx.xcc_mask);
640
+
uint32_t xcc_mask;
641
+
642
+
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
643
+
gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, xcc_mask);
649
644
}
650
645
651
646
static uint32_t gfxhub_v12_1_get_invalidate_req(unsigned int vmid,
···
745
734
struct amdgpu_vmhub *hub;
746
735
int i;
747
736
748
-
for (i = 0; i < NUM_XCC(xcc_mask); i++) {
737
+
for_each_inst(i, xcc_mask) {
749
738
hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
750
739
751
740
hub->ctx0_ptb_addr_lo32 =
···
801
790
802
791
static void gfxhub_v12_1_init(struct amdgpu_device *adev)
803
792
{
804
-
gfxhub_v12_1_xcc_init(adev, adev->gfx.xcc_mask);
793
+
uint32_t xcc_mask;
794
+
795
+
xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
796
+
gfxhub_v12_1_xcc_init(adev, xcc_mask);
805
797
}
806
798
807
799
static int gfxhub_v12_1_get_xgmi_info(struct amdgpu_device *adev)