Merge tag 'spi-fix-v5.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

+1 -1

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml

··· 171 171 cs-gpios = <&gpio0 13 0>, 172 172 <&gpio0 14 0>; 173 173 rx-sample-delay-ns = <3>; 174 - spi-flash@1 { 174 + flash@1 { 175 175 compatible = "spi-nand"; 176 176 reg = <1>; 177 177 rx-sample-delay-ns = <7>;

+2 -2

drivers/spi/spi-atmel.c

··· 1301 1301 * DMA map early, for performance (empties dcache ASAP) and 1302 1302 * better fault reporting. 1303 1303 */ 1304 - if ((!master->cur_msg_mapped) 1304 + if ((!master->cur_msg->is_dma_mapped) 1305 1305 && as->use_pdc) { 1306 1306 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1307 1307 return -ENOMEM; ··· 1381 1381 } 1382 1382 } 1383 1383 1384 - if (!master->cur_msg_mapped 1384 + if (!master->cur_msg->is_dma_mapped 1385 1385 && as->use_pdc) 1386 1386 atmel_spi_dma_unmap_xfer(master, xfer); 1387 1387

+45 -32

drivers/spi/spi-bcm-qspi.c

··· 1250 1250 1251 1251 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi) 1252 1252 { 1253 + u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); 1254 + 1253 1255 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0); 1254 1256 if (has_bspi(qspi)) 1255 1257 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); 1256 1258 1259 + /* clear interrupt */ 1260 + bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1); 1257 1261 } 1258 1262 1259 1263 static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { ··· 1401 1397 if (!qspi->dev_ids) 1402 1398 return -ENOMEM; 1403 1399 1400 + /* 1401 + * Some SoCs integrate spi controller (e.g., its interrupt bits) 1402 + * in specific ways 1403 + */ 1404 + if (soc_intc) { 1405 + qspi->soc_intc = soc_intc; 1406 + soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); 1407 + } else { 1408 + qspi->soc_intc = NULL; 1409 + } 1410 + 1411 + if (qspi->clk) { 1412 + ret = clk_prepare_enable(qspi->clk); 1413 + if (ret) { 1414 + dev_err(dev, "failed to prepare clock\n"); 1415 + goto qspi_probe_err; 1416 + } 1417 + qspi->base_clk = clk_get_rate(qspi->clk); 1418 + } else { 1419 + qspi->base_clk = MSPI_BASE_FREQ; 1420 + } 1421 + 1422 + if (data->has_mspi_rev) { 1423 + rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); 1424 + /* some older revs do not have a MSPI_REV register */ 1425 + if ((rev & 0xff) == 0xff) 1426 + rev = 0; 1427 + } 1428 + 1429 + qspi->mspi_maj_rev = (rev >> 4) & 0xf; 1430 + qspi->mspi_min_rev = rev & 0xf; 1431 + qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk; 1432 + 1433 + qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); 1434 + 1435 + /* 1436 + * On SW resets it is possible to have the mask still enabled 1437 + * Need to disable the mask and clear the status while we init 1438 + */ 1439 + bcm_qspi_hw_uninit(qspi); 1440 + 1404 1441 for (val = 0; val < num_irqs; val++) { 1405 1442 irq = -1; 1406 1443 name = qspi_irq_tab[val].irq_name; ··· 1477 1432 ret = -EINVAL; 1478 1433 goto qspi_probe_err; 1479 1434 } 1480 - 1481 - /* 1482 - * Some SoCs integrate spi controller (e.g., its interrupt bits) 1483 - * in specific ways 1484 - */ 1485 - if (soc_intc) { 1486 - qspi->soc_intc = soc_intc; 1487 - soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); 1488 - } else { 1489 - qspi->soc_intc = NULL; 1490 - } 1491 - 1492 - ret = clk_prepare_enable(qspi->clk); 1493 - if (ret) { 1494 - dev_err(dev, "failed to prepare clock\n"); 1495 - goto qspi_probe_err; 1496 - } 1497 - 1498 - qspi->base_clk = clk_get_rate(qspi->clk); 1499 - 1500 - if (data->has_mspi_rev) { 1501 - rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); 1502 - /* some older revs do not have a MSPI_REV register */ 1503 - if ((rev & 0xff) == 0xff) 1504 - rev = 0; 1505 - } 1506 - 1507 - qspi->mspi_maj_rev = (rev >> 4) & 0xf; 1508 - qspi->mspi_min_rev = rev & 0xf; 1509 - qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk; 1510 - 1511 - qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); 1512 1435 1513 1436 bcm_qspi_hw_init(qspi); 1514 1437 init_completion(&qspi->mspi_done);

+36 -28

drivers/spi/spi-mt65xx.c

··· 233 233 return delay; 234 234 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 235 235 236 - setup = setup ? setup : 1; 237 - hold = hold ? hold : 1; 238 - inactive = inactive ? inactive : 1; 239 - 240 - reg_val = readl(mdata->base + SPI_CFG0_REG); 241 - if (mdata->dev_comp->enhance_timing) { 242 - hold = min_t(u32, hold, 0x10000); 243 - setup = min_t(u32, setup, 0x10000); 244 - reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 245 - reg_val |= (((hold - 1) & 0xffff) 246 - << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 247 - reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 248 - reg_val |= (((setup - 1) & 0xffff) 249 - << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 250 - } else { 251 - hold = min_t(u32, hold, 0x100); 252 - setup = min_t(u32, setup, 0x100); 253 - reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); 254 - reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 255 - reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); 256 - reg_val |= (((setup - 1) & 0xff) 257 - << SPI_CFG0_CS_SETUP_OFFSET); 236 + if (hold || setup) { 237 + reg_val = readl(mdata->base + SPI_CFG0_REG); 238 + if (mdata->dev_comp->enhance_timing) { 239 + if (hold) { 240 + hold = min_t(u32, hold, 0x10000); 241 + reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 242 + reg_val |= (((hold - 1) & 0xffff) 243 + << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 244 + } 245 + if (setup) { 246 + setup = min_t(u32, setup, 0x10000); 247 + reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 248 + reg_val |= (((setup - 1) & 0xffff) 249 + << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 250 + } 251 + } else { 252 + if (hold) { 253 + hold = min_t(u32, hold, 0x100); 254 + reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); 255 + reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 256 + } 257 + if (setup) { 258 + setup = min_t(u32, setup, 0x100); 259 + reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); 260 + reg_val |= (((setup - 1) & 0xff) 261 + << SPI_CFG0_CS_SETUP_OFFSET); 262 + } 263 + } 264 + writel(reg_val, mdata->base + SPI_CFG0_REG); 258 265 } 259 - writel(reg_val, mdata->base + SPI_CFG0_REG); 260 266 261 - inactive = min_t(u32, inactive, 0x100); 262 - reg_val = readl(mdata->base + SPI_CFG1_REG); 263 - reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 264 - reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 265 - writel(reg_val, mdata->base + SPI_CFG1_REG); 267 + if (inactive) { 268 + inactive = min_t(u32, inactive, 0x100); 269 + reg_val = readl(mdata->base + SPI_CFG1_REG); 270 + reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 271 + reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 272 + writel(reg_val, mdata->base + SPI_CFG1_REG); 273 + } 266 274 267 275 return 0; 268 276 }

+7

drivers/spi/spi-mux.c

··· 137 137 priv = spi_controller_get_devdata(ctlr); 138 138 priv->spi = spi; 139 139 140 + /* 141 + * Increase lockdep class as these lock are taken while the parent bus 142 + * already holds their instance's lock. 143 + */ 144 + lockdep_set_subclass(&ctlr->io_mutex, 1); 145 + lockdep_set_subclass(&ctlr->add_lock, 1); 146 + 140 147 priv->mux = devm_mux_control_get(&spi->dev, NULL); 141 148 if (IS_ERR(priv->mux)) { 142 149 ret = dev_err_probe(&spi->dev, PTR_ERR(priv->mux),

+7 -19

drivers/spi/spi-nxp-fspi.c

··· 33 33 34 34 #include <linux/acpi.h> 35 35 #include <linux/bitops.h> 36 + #include <linux/bitfield.h> 36 37 #include <linux/clk.h> 37 38 #include <linux/completion.h> 38 39 #include <linux/delay.h> ··· 316 315 #define NXP_FSPI_MIN_IOMAP SZ_4M 317 316 318 317 #define DCFG_RCWSR1 0x100 318 + #define SYS_PLL_RAT GENMASK(6, 2) 319 319 320 320 /* Access flash memory using IP bus only */ 321 321 #define FSPI_QUIRK_USE_IP_ONLY BIT(0) ··· 928 926 { .family = "QorIQ LS1028A" }, 929 927 { /* sentinel */ } 930 928 }; 931 - struct device_node *np; 932 929 struct regmap *map; 933 - u32 val = 0, sysclk = 0; 930 + u32 val, sys_pll_ratio; 934 931 int ret; 935 932 936 933 /* Check for LS1028A family */ ··· 938 937 return; 939 938 } 940 939 941 - /* Compute system clock frequency multiplier ratio */ 942 940 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 943 941 if (IS_ERR(map)) { 944 942 dev_err(f->dev, "No syscon regmap\n"); ··· 948 948 if (ret < 0) 949 949 goto err; 950 950 951 - /* Strap bits 6:2 define SYS_PLL_RAT i.e frequency multiplier ratio */ 952 - val = (val >> 2) & 0x1F; 953 - WARN(val == 0, "Strapping is zero: Cannot determine ratio"); 951 + sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val); 952 + dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); 954 953 955 - /* Compute system clock frequency */ 956 - np = of_find_node_by_name(NULL, "clock-sysclk"); 957 - if (!np) 958 - goto err; 959 - 960 - if (of_property_read_u32(np, "clock-frequency", &sysclk)) 961 - goto err; 962 - 963 - sysclk = (sysclk * val) / 1000000; /* Convert sysclk to Mhz */ 964 - dev_dbg(f->dev, "val: 0x%08x, sysclk: %dMhz\n", val, sysclk); 965 - 966 - /* Use IP bus only if PLL is 300MHz */ 967 - if (sysclk == 300) 954 + /* Use IP bus only if platform clock is 300MHz */ 955 + if (sys_pll_ratio == 3) 968 956 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 969 957 970 958 return;

+1 -3

drivers/spi/spi-tegra20-slink.c

··· 1182 1182 } 1183 1183 #endif 1184 1184 1185 - #ifdef CONFIG_PM 1186 - static int tegra_slink_runtime_suspend(struct device *dev) 1185 + static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev) 1187 1186 { 1188 1187 struct spi_master *master = dev_get_drvdata(dev); 1189 1188 struct tegra_slink_data *tspi = spi_master_get_devdata(master); ··· 1207 1208 } 1208 1209 return 0; 1209 1210 } 1210 - #endif /* CONFIG_PM */ 1211 1211 1212 1212 static const struct dev_pm_ops slink_pm_ops = { 1213 1213 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,

+11 -16

drivers/spi/spi.c

··· 478 478 */ 479 479 static DEFINE_MUTEX(board_lock); 480 480 481 - /* 482 - * Prevents addition of devices with same chip select and 483 - * addition of devices below an unregistering controller. 484 - */ 485 - static DEFINE_MUTEX(spi_add_lock); 486 - 487 481 /** 488 482 * spi_alloc_device - Allocate a new SPI device 489 483 * @ctlr: Controller to which device is connected ··· 630 636 * chipselect **BEFORE** we call setup(), else we'll trash 631 637 * its configuration. Lock against concurrent add() calls. 632 638 */ 633 - mutex_lock(&spi_add_lock); 639 + mutex_lock(&ctlr->add_lock); 634 640 status = __spi_add_device(spi); 635 - mutex_unlock(&spi_add_lock); 641 + mutex_unlock(&ctlr->add_lock); 636 642 return status; 637 643 } 638 644 EXPORT_SYMBOL_GPL(spi_add_device); ··· 652 658 /* Set the bus ID string */ 653 659 spi_dev_set_name(spi); 654 660 655 - WARN_ON(!mutex_is_locked(&spi_add_lock)); 661 + WARN_ON(!mutex_is_locked(&ctlr->add_lock)); 656 662 return __spi_add_device(spi); 657 663 } 658 664 ··· 2547 2553 return NULL; 2548 2554 2549 2555 device_initialize(&ctlr->dev); 2556 + INIT_LIST_HEAD(&ctlr->queue); 2557 + spin_lock_init(&ctlr->queue_lock); 2558 + spin_lock_init(&ctlr->bus_lock_spinlock); 2559 + mutex_init(&ctlr->bus_lock_mutex); 2560 + mutex_init(&ctlr->io_mutex); 2561 + mutex_init(&ctlr->add_lock); 2550 2562 ctlr->bus_num = -1; 2551 2563 ctlr->num_chipselect = 1; 2552 2564 ctlr->slave = slave; ··· 2825 2825 return id; 2826 2826 ctlr->bus_num = id; 2827 2827 } 2828 - INIT_LIST_HEAD(&ctlr->queue); 2829 - spin_lock_init(&ctlr->queue_lock); 2830 - spin_lock_init(&ctlr->bus_lock_spinlock); 2831 - mutex_init(&ctlr->bus_lock_mutex); 2832 - mutex_init(&ctlr->io_mutex); 2833 2828 ctlr->bus_lock_flag = 0; 2834 2829 init_completion(&ctlr->xfer_completion); 2835 2830 if (!ctlr->max_dma_len) ··· 2961 2966 2962 2967 /* Prevent addition of new devices, unregister existing ones */ 2963 2968 if (IS_ENABLED(CONFIG_SPI_DYNAMIC)) 2964 - mutex_lock(&spi_add_lock); 2969 + mutex_lock(&ctlr->add_lock); 2965 2970 2966 2971 device_for_each_child(&ctlr->dev, NULL, __unregister); 2967 2972 ··· 2992 2997 mutex_unlock(&board_lock); 2993 2998 2994 2999 if (IS_ENABLED(CONFIG_SPI_DYNAMIC)) 2995 - mutex_unlock(&spi_add_lock); 3000 + mutex_unlock(&ctlr->add_lock); 2996 3001 } 2997 3002 EXPORT_SYMBOL_GPL(spi_unregister_controller); 2998 3003

+14

drivers/spi/spidev.c

··· 673 673 674 674 static struct class *spidev_class; 675 675 676 + static const struct spi_device_id spidev_spi_ids[] = { 677 + { .name = "dh2228fv" }, 678 + { .name = "ltc2488" }, 679 + { .name = "sx1301" }, 680 + { .name = "bk4" }, 681 + { .name = "dhcom-board" }, 682 + { .name = "m53cpld" }, 683 + { .name = "spi-petra" }, 684 + { .name = "spi-authenta" }, 685 + {}, 686 + }; 687 + MODULE_DEVICE_TABLE(spi, spidev_spi_ids); 688 + 676 689 #ifdef CONFIG_OF 677 690 static const struct of_device_id spidev_dt_ids[] = { 678 691 { .compatible = "rohm,dh2228fv" }, ··· 831 818 }, 832 819 .probe = spidev_probe, 833 820 .remove = spidev_remove, 821 + .id_table = spidev_spi_ids, 834 822 835 823 /* NOTE: suspend/resume methods are not necessary here. 836 824 * We don't do anything except pass the requests to/from

+3

include/linux/spi/spi.h

··· 531 531 /* I/O mutex */ 532 532 struct mutex io_mutex; 533 533 534 + /* Used to avoid adding the same CS twice */ 535 + struct mutex add_lock; 536 + 534 537 /* lock and mutex for SPI bus locking */ 535 538 spinlock_t bus_lock_spinlock; 536 539 struct mutex bus_lock_mutex;

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