tjh.dev / kernel
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drm/msm/dpu: Add CWB entry to catalog for SM8650

Add a new block for concurrent writeback mux to the SM8650 HW catalog

Signed-off-by: Esha Bharadwaj <quic_ebharadw@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/629219/
Link: https://lore.kernel.org/r/20241216-concurrent-wb-v4-9-fe220297a7f0@quicinc.com

authored by

Esha Bharadwaj and committed by
Dmitry Baryshkov 989412ed 835d1062

+34
+21
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
··· 352 352 }, 353 353 }; 354 354 355 + static const struct dpu_cwb_cfg sm8650_cwb[] = { 356 + { 357 + .name = "cwb_0", .id = CWB_0, 358 + .base = 0x66200, .len = 0x8, 359 + }, 360 + { 361 + .name = "cwb_1", .id = CWB_1, 362 + .base = 0x66600, .len = 0x8, 363 + }, 364 + { 365 + .name = "cwb_2", .id = CWB_2, 366 + .base = 0x7E200, .len = 0x8, 367 + }, 368 + { 369 + .name = "cwb_3", .id = CWB_3, 370 + .base = 0x7E600, .len = 0x8, 371 + }, 372 + }; 373 + 355 374 static const struct dpu_intf_cfg sm8650_intf[] = { 356 375 { 357 376 .name = "intf_0", .id = INTF_0, ··· 468 449 .merge_3d = sm8650_merge_3d, 469 450 .wb_count = ARRAY_SIZE(sm8650_wb), 470 451 .wb = sm8650_wb, 452 + .cwb_count = ARRAY_SIZE(sm8650_cwb), 453 + .cwb = sm8650_cwb, 471 454 .intf_count = ARRAY_SIZE(sm8650_intf), 472 455 .intf = sm8650_intf, 473 456 .vbif_count = ARRAY_SIZE(sm8650_vbif),
+13
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 613 613 enum dpu_clk_ctrl_type clk_ctrl; 614 614 }; 615 615 616 + /* 617 + * struct dpu_cwb_cfg : MDP CWB mux instance info 618 + * @id: enum identifying this block 619 + * @base: register base offset to mdss 620 + * @features bit mask identifying sub-blocks/features 621 + */ 622 + struct dpu_cwb_cfg { 623 + DPU_HW_BLK_INFO; 624 + }; 625 + 616 626 /** 617 627 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 618 628 * @pps pixel per seconds ··· 824 814 825 815 u32 dspp_count; 826 816 const struct dpu_dspp_cfg *dspp; 817 + 818 + u32 cwb_count; 819 + const struct dpu_cwb_cfg *cwb; 827 820 828 821 /* Add additional block data structures here */ 829 822