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mfd: Remove STA2x11 core driver

With commit dcbb01fbb7ae ("x86/pci: Remove old STA2x11 support"), the core
driver for STA2x11 is not needed and cannot be built anymore.

Remove the driver and its header file.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20250303100055.372689-1-lukas.bulwahn@redhat.com
Signed-off-by: Lee Jones <lee@kernel.org>

authored by

Lukas Bulwahn and committed by
Lee Jones 98cf2d50 0d084ee9

-1158
-6
drivers/mfd/Kconfig
··· 1508 1508 This is used to enable SPI interface of STMPE 1509 1509 endmenu 1510 1510 1511 - config MFD_STA2X11 1512 - bool "STMicroelectronics STA2X11" 1513 - depends on STA2X11 1514 - select MFD_CORE 1515 - select REGMAP_MMIO 1516 - 1517 1511 config MFD_SUN6I_PRCM 1518 1512 bool "Allwinner A31/A23/A33 PRCM controller" 1519 1513 depends on ARCH_SUNXI || COMPILE_TEST
-1
drivers/mfd/Makefile
··· 26 26 obj-$(CONFIG_MFD_TI_LP87565) += lp87565.o 27 27 obj-$(CONFIG_MFD_TI_AM335X_TSCADC) += ti_am335x_tscadc.o 28 28 29 - obj-$(CONFIG_MFD_STA2X11) += sta2x11-mfd.o 30 29 obj-$(CONFIG_MFD_STMPE) += stmpe.o 31 30 obj-$(CONFIG_STMPE_I2C) += stmpe-i2c.o 32 31 obj-$(CONFIG_STMPE_SPI) += stmpe-spi.o
-645
drivers/mfd/sta2x11-mfd.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * STA2x11 mfd for GPIO, SCTL and APBREG 4 - * 5 - * Copyright (c) 2009-2011 Wind River Systems, Inc. 6 - * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi) 7 - */ 8 - 9 - #include <linux/kernel.h> 10 - #include <linux/init.h> 11 - #include <linux/export.h> 12 - #include <linux/spinlock.h> 13 - #include <linux/errno.h> 14 - #include <linux/device.h> 15 - #include <linux/slab.h> 16 - #include <linux/list.h> 17 - #include <linux/io.h> 18 - #include <linux/ioport.h> 19 - #include <linux/pci.h> 20 - #include <linux/seq_file.h> 21 - #include <linux/platform_device.h> 22 - #include <linux/mfd/core.h> 23 - #include <linux/mfd/sta2x11-mfd.h> 24 - #include <linux/regmap.h> 25 - 26 - #include <asm/sta2x11.h> 27 - 28 - static inline int __reg_within_range(unsigned int r, 29 - unsigned int start, 30 - unsigned int end) 31 - { 32 - return ((r >= start) && (r <= end)); 33 - } 34 - 35 - /* This describes STA2X11 MFD chip for us, we may have several */ 36 - struct sta2x11_mfd { 37 - struct sta2x11_instance *instance; 38 - struct regmap *regmap[sta2x11_n_mfd_plat_devs]; 39 - spinlock_t lock[sta2x11_n_mfd_plat_devs]; 40 - struct list_head list; 41 - void __iomem *regs[sta2x11_n_mfd_plat_devs]; 42 - }; 43 - 44 - static LIST_HEAD(sta2x11_mfd_list); 45 - 46 - /* Three functions to act on the list */ 47 - static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev) 48 - { 49 - struct sta2x11_instance *instance; 50 - struct sta2x11_mfd *mfd; 51 - 52 - if (!pdev && !list_empty(&sta2x11_mfd_list)) { 53 - pr_warn("%s: Unspecified device, using first instance\n", 54 - __func__); 55 - return list_entry(sta2x11_mfd_list.next, 56 - struct sta2x11_mfd, list); 57 - } 58 - 59 - instance = sta2x11_get_instance(pdev); 60 - if (!instance) 61 - return NULL; 62 - list_for_each_entry(mfd, &sta2x11_mfd_list, list) { 63 - if (mfd->instance == instance) 64 - return mfd; 65 - } 66 - return NULL; 67 - } 68 - 69 - static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags) 70 - { 71 - int i; 72 - struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev); 73 - struct sta2x11_instance *instance; 74 - 75 - if (mfd) 76 - return -EBUSY; 77 - instance = sta2x11_get_instance(pdev); 78 - if (!instance) 79 - return -EINVAL; 80 - mfd = kzalloc(sizeof(*mfd), flags); 81 - if (!mfd) 82 - return -ENOMEM; 83 - INIT_LIST_HEAD(&mfd->list); 84 - for (i = 0; i < ARRAY_SIZE(mfd->lock); i++) 85 - spin_lock_init(&mfd->lock[i]); 86 - mfd->instance = instance; 87 - list_add(&mfd->list, &sta2x11_mfd_list); 88 - return 0; 89 - } 90 - 91 - /* This function is exported and is not expected to fail */ 92 - u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val, 93 - enum sta2x11_mfd_plat_dev index) 94 - { 95 - struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev); 96 - u32 r; 97 - unsigned long flags; 98 - void __iomem *regs; 99 - 100 - if (!mfd) { 101 - dev_warn(&pdev->dev, ": can't access sctl regs\n"); 102 - return 0; 103 - } 104 - 105 - regs = mfd->regs[index]; 106 - if (!regs) { 107 - dev_warn(&pdev->dev, ": system ctl not initialized\n"); 108 - return 0; 109 - } 110 - spin_lock_irqsave(&mfd->lock[index], flags); 111 - r = readl(regs + reg); 112 - r &= ~mask; 113 - r |= val; 114 - if (mask) 115 - writel(r, regs + reg); 116 - spin_unlock_irqrestore(&mfd->lock[index], flags); 117 - return r; 118 - } 119 - EXPORT_SYMBOL(__sta2x11_mfd_mask); 120 - 121 - int sta2x11_mfd_get_regs_data(struct platform_device *dev, 122 - enum sta2x11_mfd_plat_dev index, 123 - void __iomem **regs, 124 - spinlock_t **lock) 125 - { 126 - struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev); 127 - struct sta2x11_mfd *mfd; 128 - 129 - if (!pdev) 130 - return -ENODEV; 131 - mfd = sta2x11_mfd_find(pdev); 132 - if (!mfd) 133 - return -ENODEV; 134 - if (index >= sta2x11_n_mfd_plat_devs) 135 - return -ENODEV; 136 - *regs = mfd->regs[index]; 137 - *lock = &mfd->lock[index]; 138 - pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs); 139 - return *regs ? 0 : -ENODEV; 140 - } 141 - EXPORT_SYMBOL(sta2x11_mfd_get_regs_data); 142 - 143 - /* 144 - * Special sta2x11-mfd regmap lock/unlock functions 145 - */ 146 - 147 - static void sta2x11_regmap_lock(void *__lock) 148 - { 149 - spinlock_t *lock = __lock; 150 - spin_lock(lock); 151 - } 152 - 153 - static void sta2x11_regmap_unlock(void *__lock) 154 - { 155 - spinlock_t *lock = __lock; 156 - spin_unlock(lock); 157 - } 158 - 159 - /* OTP (one time programmable registers do not require locking */ 160 - static void sta2x11_regmap_nolock(void *__lock) 161 - { 162 - } 163 - 164 - static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = { 165 - [sta2x11_sctl] = STA2X11_MFD_SCTL_NAME, 166 - [sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME, 167 - [sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME, 168 - [sta2x11_scr] = STA2X11_MFD_SCR_NAME, 169 - }; 170 - 171 - static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg) 172 - { 173 - return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA); 174 - } 175 - 176 - static struct regmap_config sta2x11_sctl_regmap_config = { 177 - .reg_bits = 32, 178 - .reg_stride = 4, 179 - .val_bits = 32, 180 - .lock = sta2x11_regmap_lock, 181 - .unlock = sta2x11_regmap_unlock, 182 - .max_register = SCTL_SCRSTSTA, 183 - .writeable_reg = sta2x11_sctl_writeable_reg, 184 - }; 185 - 186 - static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg) 187 - { 188 - return (reg == STA2X11_SECR_CR) || 189 - __reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1); 190 - } 191 - 192 - static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg) 193 - { 194 - return false; 195 - } 196 - 197 - static struct regmap_config sta2x11_scr_regmap_config = { 198 - .reg_bits = 32, 199 - .reg_stride = 4, 200 - .val_bits = 32, 201 - .lock = sta2x11_regmap_nolock, 202 - .unlock = sta2x11_regmap_nolock, 203 - .max_register = STA2X11_SECR_FVR1, 204 - .readable_reg = sta2x11_scr_readable_reg, 205 - .writeable_reg = sta2x11_scr_writeable_reg, 206 - }; 207 - 208 - static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg) 209 - { 210 - /* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */ 211 - if (reg >= APBREG_BSR_SARAC) 212 - reg -= APBREG_BSR_SARAC; 213 - switch (reg) { 214 - case APBREG_BSR: 215 - case APBREG_PAER: 216 - case APBREG_PWAC: 217 - case APBREG_PRAC: 218 - case APBREG_PCG: 219 - case APBREG_PUR: 220 - case APBREG_EMU_PCG: 221 - return true; 222 - default: 223 - return false; 224 - } 225 - } 226 - 227 - static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg) 228 - { 229 - if (reg >= APBREG_BSR_SARAC) 230 - reg -= APBREG_BSR_SARAC; 231 - if (!sta2x11_apbreg_readable_reg(dev, reg)) 232 - return false; 233 - return reg != APBREG_PAER; 234 - } 235 - 236 - static struct regmap_config sta2x11_apbreg_regmap_config = { 237 - .reg_bits = 32, 238 - .reg_stride = 4, 239 - .val_bits = 32, 240 - .lock = sta2x11_regmap_lock, 241 - .unlock = sta2x11_regmap_unlock, 242 - .max_register = APBREG_EMU_PCG_SARAC, 243 - .readable_reg = sta2x11_apbreg_readable_reg, 244 - .writeable_reg = sta2x11_apbreg_writeable_reg, 245 - }; 246 - 247 - static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev, 248 - unsigned int reg) 249 - { 250 - return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG || 251 - __reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) || 252 - __reg_within_range(reg, MASTER_LOCK_REG, 253 - SYSTEM_CONFIG_STATUS_REG) || 254 - reg == MSP_CLK_CTRL_REG || 255 - __reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG); 256 - } 257 - 258 - static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev, 259 - unsigned int reg) 260 - { 261 - if (!sta2x11_apb_soc_regs_readable_reg(dev, reg)) 262 - return false; 263 - switch (reg) { 264 - case PCIE_COMMON_CLOCK_CONFIG_0_4_0: 265 - case SYSTEM_CONFIG_STATUS_REG: 266 - case COMPENSATION_REG1: 267 - case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG: 268 - case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4: 269 - return false; 270 - default: 271 - return true; 272 - } 273 - } 274 - 275 - static struct regmap_config sta2x11_apb_soc_regs_regmap_config = { 276 - .reg_bits = 32, 277 - .reg_stride = 4, 278 - .val_bits = 32, 279 - .lock = sta2x11_regmap_lock, 280 - .unlock = sta2x11_regmap_unlock, 281 - .max_register = TEST_CTL_REG, 282 - .readable_reg = sta2x11_apb_soc_regs_readable_reg, 283 - .writeable_reg = sta2x11_apb_soc_regs_writeable_reg, 284 - }; 285 - 286 - static struct regmap_config * 287 - sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = { 288 - [sta2x11_sctl] = &sta2x11_sctl_regmap_config, 289 - [sta2x11_apbreg] = &sta2x11_apbreg_regmap_config, 290 - [sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config, 291 - [sta2x11_scr] = &sta2x11_scr_regmap_config, 292 - }; 293 - 294 - /* Probe for the four platform devices */ 295 - 296 - static int sta2x11_mfd_platform_probe(struct platform_device *dev, 297 - enum sta2x11_mfd_plat_dev index) 298 - { 299 - struct pci_dev **pdev; 300 - struct sta2x11_mfd *mfd; 301 - struct resource *res; 302 - const char *name = sta2x11_mfd_names[index]; 303 - struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index]; 304 - 305 - pdev = dev_get_platdata(&dev->dev); 306 - mfd = sta2x11_mfd_find(*pdev); 307 - if (!mfd) 308 - return -ENODEV; 309 - if (!regmap_config) 310 - return -ENODEV; 311 - 312 - res = platform_get_resource(dev, IORESOURCE_MEM, 0); 313 - if (!res) 314 - return -ENOMEM; 315 - 316 - if (!request_mem_region(res->start, resource_size(res), name)) 317 - return -EBUSY; 318 - 319 - mfd->regs[index] = ioremap(res->start, resource_size(res)); 320 - if (!mfd->regs[index]) { 321 - release_mem_region(res->start, resource_size(res)); 322 - return -ENOMEM; 323 - } 324 - regmap_config->lock_arg = &mfd->lock; 325 - /* 326 - No caching, registers could be reached both via regmap and via 327 - void __iomem * 328 - */ 329 - regmap_config->cache_type = REGCACHE_NONE; 330 - mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index], 331 - regmap_config); 332 - WARN_ON(IS_ERR(mfd->regmap[index])); 333 - 334 - return 0; 335 - } 336 - 337 - static int sta2x11_sctl_probe(struct platform_device *dev) 338 - { 339 - return sta2x11_mfd_platform_probe(dev, sta2x11_sctl); 340 - } 341 - 342 - static int sta2x11_apbreg_probe(struct platform_device *dev) 343 - { 344 - return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg); 345 - } 346 - 347 - static int sta2x11_apb_soc_regs_probe(struct platform_device *dev) 348 - { 349 - return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs); 350 - } 351 - 352 - static int sta2x11_scr_probe(struct platform_device *dev) 353 - { 354 - return sta2x11_mfd_platform_probe(dev, sta2x11_scr); 355 - } 356 - 357 - /* The three platform drivers */ 358 - static struct platform_driver sta2x11_sctl_platform_driver = { 359 - .driver = { 360 - .name = STA2X11_MFD_SCTL_NAME, 361 - }, 362 - .probe = sta2x11_sctl_probe, 363 - }; 364 - 365 - static struct platform_driver sta2x11_platform_driver = { 366 - .driver = { 367 - .name = STA2X11_MFD_APBREG_NAME, 368 - }, 369 - .probe = sta2x11_apbreg_probe, 370 - }; 371 - 372 - static struct platform_driver sta2x11_apb_soc_regs_platform_driver = { 373 - .driver = { 374 - .name = STA2X11_MFD_APB_SOC_REGS_NAME, 375 - }, 376 - .probe = sta2x11_apb_soc_regs_probe, 377 - }; 378 - 379 - static struct platform_driver sta2x11_scr_platform_driver = { 380 - .driver = { 381 - .name = STA2X11_MFD_SCR_NAME, 382 - }, 383 - .probe = sta2x11_scr_probe, 384 - }; 385 - 386 - static struct platform_driver * const drivers[] = { 387 - &sta2x11_platform_driver, 388 - &sta2x11_sctl_platform_driver, 389 - &sta2x11_apb_soc_regs_platform_driver, 390 - &sta2x11_scr_platform_driver, 391 - }; 392 - 393 - static int __init sta2x11_drivers_init(void) 394 - { 395 - return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 396 - } 397 - 398 - /* 399 - * What follows are the PCI devices that host the above pdevs. 400 - * Each logic block is 4kB and they are all consecutive: we use this info. 401 - */ 402 - 403 - /* Mfd 0 device */ 404 - 405 - /* Mfd 0, Bar 0 */ 406 - enum mfd0_bar0_cells { 407 - STA2X11_GPIO_0 = 0, 408 - STA2X11_GPIO_1, 409 - STA2X11_GPIO_2, 410 - STA2X11_GPIO_3, 411 - STA2X11_SCTL, 412 - STA2X11_SCR, 413 - STA2X11_TIME, 414 - }; 415 - /* Mfd 0 , Bar 1 */ 416 - enum mfd0_bar1_cells { 417 - STA2X11_APBREG = 0, 418 - }; 419 - #define CELL_4K(_name, _cell) { \ 420 - .name = _name, \ 421 - .start = _cell * 4096, .end = _cell * 4096 + 4095, \ 422 - .flags = IORESOURCE_MEM, \ 423 - } 424 - 425 - static const struct resource gpio_resources[] = { 426 - { 427 - /* 4 consecutive cells, 1 driver */ 428 - .name = STA2X11_MFD_GPIO_NAME, 429 - .start = 0, 430 - .end = (4 * 4096) - 1, 431 - .flags = IORESOURCE_MEM, 432 - } 433 - }; 434 - static const struct resource sctl_resources[] = { 435 - CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL), 436 - }; 437 - static const struct resource scr_resources[] = { 438 - CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR), 439 - }; 440 - static const struct resource time_resources[] = { 441 - CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME), 442 - }; 443 - 444 - static const struct resource apbreg_resources[] = { 445 - CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG), 446 - }; 447 - 448 - #define DEV(_name, _r) \ 449 - { .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, } 450 - 451 - static struct mfd_cell sta2x11_mfd0_bar0[] = { 452 - /* offset 0: we add pdata later */ 453 - DEV(STA2X11_MFD_GPIO_NAME, gpio_resources), 454 - DEV(STA2X11_MFD_SCTL_NAME, sctl_resources), 455 - DEV(STA2X11_MFD_SCR_NAME, scr_resources), 456 - DEV(STA2X11_MFD_TIME_NAME, time_resources), 457 - }; 458 - 459 - static struct mfd_cell sta2x11_mfd0_bar1[] = { 460 - DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources), 461 - }; 462 - 463 - /* Mfd 1 devices */ 464 - 465 - /* Mfd 1, Bar 0 */ 466 - enum mfd1_bar0_cells { 467 - STA2X11_VIC = 0, 468 - }; 469 - 470 - /* Mfd 1, Bar 1 */ 471 - enum mfd1_bar1_cells { 472 - STA2X11_APB_SOC_REGS = 0, 473 - }; 474 - 475 - static const struct resource vic_resources[] = { 476 - CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC), 477 - }; 478 - 479 - static const struct resource apb_soc_regs_resources[] = { 480 - CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS), 481 - }; 482 - 483 - static struct mfd_cell sta2x11_mfd1_bar0[] = { 484 - DEV(STA2X11_MFD_VIC_NAME, vic_resources), 485 - }; 486 - 487 - static struct mfd_cell sta2x11_mfd1_bar1[] = { 488 - DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources), 489 - }; 490 - 491 - 492 - static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state) 493 - { 494 - pci_save_state(pdev); 495 - pci_disable_device(pdev); 496 - pci_set_power_state(pdev, pci_choose_state(pdev, state)); 497 - 498 - return 0; 499 - } 500 - 501 - static int sta2x11_mfd_resume(struct pci_dev *pdev) 502 - { 503 - int err; 504 - 505 - pci_set_power_state(pdev, PCI_D0); 506 - err = pci_enable_device(pdev); 507 - if (err) 508 - return err; 509 - pci_restore_state(pdev); 510 - 511 - return 0; 512 - } 513 - 514 - struct sta2x11_mfd_bar_setup_data { 515 - struct mfd_cell *cells; 516 - int ncells; 517 - }; 518 - 519 - struct sta2x11_mfd_setup_data { 520 - struct sta2x11_mfd_bar_setup_data bars[2]; 521 - }; 522 - 523 - #define STA2X11_MFD0 0 524 - #define STA2X11_MFD1 1 525 - 526 - static struct sta2x11_mfd_setup_data mfd_setup_data[] = { 527 - /* Mfd 0: gpio, sctl, scr, timers / apbregs */ 528 - [STA2X11_MFD0] = { 529 - .bars = { 530 - [0] = { 531 - .cells = sta2x11_mfd0_bar0, 532 - .ncells = ARRAY_SIZE(sta2x11_mfd0_bar0), 533 - }, 534 - [1] = { 535 - .cells = sta2x11_mfd0_bar1, 536 - .ncells = ARRAY_SIZE(sta2x11_mfd0_bar1), 537 - }, 538 - }, 539 - }, 540 - /* Mfd 1: vic / apb-soc-regs */ 541 - [STA2X11_MFD1] = { 542 - .bars = { 543 - [0] = { 544 - .cells = sta2x11_mfd1_bar0, 545 - .ncells = ARRAY_SIZE(sta2x11_mfd1_bar0), 546 - }, 547 - [1] = { 548 - .cells = sta2x11_mfd1_bar1, 549 - .ncells = ARRAY_SIZE(sta2x11_mfd1_bar1), 550 - }, 551 - }, 552 - }, 553 - }; 554 - 555 - static void sta2x11_mfd_setup(struct pci_dev *pdev, 556 - struct sta2x11_mfd_setup_data *sd) 557 - { 558 - int i, j; 559 - for (i = 0; i < ARRAY_SIZE(sd->bars); i++) 560 - for (j = 0; j < sd->bars[i].ncells; j++) { 561 - sd->bars[i].cells[j].pdata_size = sizeof(pdev); 562 - sd->bars[i].cells[j].platform_data = &pdev; 563 - } 564 - } 565 - 566 - static int sta2x11_mfd_probe(struct pci_dev *pdev, 567 - const struct pci_device_id *pci_id) 568 - { 569 - int err, i; 570 - struct sta2x11_mfd_setup_data *setup_data; 571 - 572 - dev_info(&pdev->dev, "%s\n", __func__); 573 - 574 - err = pci_enable_device(pdev); 575 - if (err) { 576 - dev_err(&pdev->dev, "Can't enable device.\n"); 577 - return err; 578 - } 579 - 580 - err = pci_enable_msi(pdev); 581 - if (err) 582 - dev_info(&pdev->dev, "Enable msi failed\n"); 583 - 584 - setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ? 585 - &mfd_setup_data[STA2X11_MFD0] : 586 - &mfd_setup_data[STA2X11_MFD1]; 587 - 588 - /* platform data is the pci device for all of them */ 589 - sta2x11_mfd_setup(pdev, setup_data); 590 - 591 - /* Record this pdev before mfd_add_devices: their probe looks for it */ 592 - if (!sta2x11_mfd_find(pdev)) 593 - sta2x11_mfd_add(pdev, GFP_KERNEL); 594 - 595 - /* Just 2 bars for all mfd's at present */ 596 - for (i = 0; i < 2; i++) { 597 - err = mfd_add_devices(&pdev->dev, -1, 598 - setup_data->bars[i].cells, 599 - setup_data->bars[i].ncells, 600 - &pdev->resource[i], 601 - 0, NULL); 602 - if (err) { 603 - dev_err(&pdev->dev, 604 - "mfd_add_devices[%d] failed: %d\n", i, err); 605 - goto err_disable; 606 - } 607 - } 608 - 609 - return 0; 610 - 611 - err_disable: 612 - mfd_remove_devices(&pdev->dev); 613 - pci_disable_device(pdev); 614 - pci_disable_msi(pdev); 615 - return err; 616 - } 617 - 618 - static const struct pci_device_id sta2x11_mfd_tbl[] = { 619 - {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)}, 620 - {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)}, 621 - {0,}, 622 - }; 623 - 624 - static struct pci_driver sta2x11_mfd_driver = { 625 - .name = "sta2x11-mfd", 626 - .id_table = sta2x11_mfd_tbl, 627 - .probe = sta2x11_mfd_probe, 628 - .suspend = sta2x11_mfd_suspend, 629 - .resume = sta2x11_mfd_resume, 630 - }; 631 - 632 - static int __init sta2x11_mfd_init(void) 633 - { 634 - pr_info("%s\n", __func__); 635 - return pci_register_driver(&sta2x11_mfd_driver); 636 - } 637 - 638 - /* 639 - * All of this must be ready before "normal" devices like MMCI appear. 640 - * But MFD (the pci device) can't be too early. The following choice 641 - * prepares platform drivers very early and probe the PCI device later, 642 - * but before other PCI devices. 643 - */ 644 - subsys_initcall(sta2x11_drivers_init); 645 - rootfs_initcall(sta2x11_mfd_init);
-506
include/linux/mfd/sta2x11-mfd.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only */ 2 - /* 3 - * Copyright (c) 2009-2011 Wind River Systems, Inc. 4 - * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini) 5 - * 6 - * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated 7 - * functions in one PCI endpoint functions. This driver simply 8 - * registers the platform devices in this iomemregion and exports a few 9 - * functions to access common registers 10 - */ 11 - 12 - #ifndef __STA2X11_MFD_H 13 - #define __STA2X11_MFD_H 14 - #include <linux/types.h> 15 - #include <linux/pci.h> 16 - 17 - enum sta2x11_mfd_plat_dev { 18 - sta2x11_sctl = 0, 19 - sta2x11_gpio, 20 - sta2x11_scr, 21 - sta2x11_time, 22 - sta2x11_apbreg, 23 - sta2x11_apb_soc_regs, 24 - sta2x11_vic, 25 - sta2x11_n_mfd_plat_devs, 26 - }; 27 - 28 - #define STA2X11_MFD_SCTL_NAME "sta2x11-sctl" 29 - #define STA2X11_MFD_GPIO_NAME "sta2x11-gpio" 30 - #define STA2X11_MFD_SCR_NAME "sta2x11-scr" 31 - #define STA2X11_MFD_TIME_NAME "sta2x11-time" 32 - #define STA2X11_MFD_APBREG_NAME "sta2x11-apbreg" 33 - #define STA2X11_MFD_APB_SOC_REGS_NAME "sta2x11-apb-soc-regs" 34 - #define STA2X11_MFD_VIC_NAME "sta2x11-vic" 35 - 36 - extern u32 37 - __sta2x11_mfd_mask(struct pci_dev *, u32, u32, u32, enum sta2x11_mfd_plat_dev); 38 - 39 - /* 40 - * The MFD PCI block includes the GPIO peripherals and other register blocks. 41 - * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".) 42 - */ 43 - #define GSTA_GPIO_PER_BLOCK 32 44 - #define GSTA_NR_BLOCKS 4 45 - #define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS) 46 - 47 - /* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */ 48 - struct sta2x11_gpio_pdata { 49 - unsigned pinconfig[GSTA_NR_GPIO]; 50 - }; 51 - 52 - /* Macros below lifted from sh_pfc.h, with minor differences */ 53 - #define PINMUX_TYPE_NONE 0 54 - #define PINMUX_TYPE_FUNCTION 1 55 - #define PINMUX_TYPE_OUTPUT_LOW 2 56 - #define PINMUX_TYPE_OUTPUT_HIGH 3 57 - #define PINMUX_TYPE_INPUT 4 58 - #define PINMUX_TYPE_INPUT_PULLUP 5 59 - #define PINMUX_TYPE_INPUT_PULLDOWN 6 60 - 61 - /* Give names to GPIO pins, like PXA does, taken from the manual */ 62 - #define STA2X11_GPIO0 0 63 - #define STA2X11_GPIO1 1 64 - #define STA2X11_GPIO2 2 65 - #define STA2X11_GPIO3 3 66 - #define STA2X11_GPIO4 4 67 - #define STA2X11_GPIO5 5 68 - #define STA2X11_GPIO6 6 69 - #define STA2X11_GPIO7 7 70 - #define STA2X11_GPIO8_RGBOUT_RED7 8 71 - #define STA2X11_GPIO9_RGBOUT_RED6 9 72 - #define STA2X11_GPIO10_RGBOUT_RED5 10 73 - #define STA2X11_GPIO11_RGBOUT_RED4 11 74 - #define STA2X11_GPIO12_RGBOUT_RED3 12 75 - #define STA2X11_GPIO13_RGBOUT_RED2 13 76 - #define STA2X11_GPIO14_RGBOUT_RED1 14 77 - #define STA2X11_GPIO15_RGBOUT_RED0 15 78 - #define STA2X11_GPIO16_RGBOUT_GREEN7 16 79 - #define STA2X11_GPIO17_RGBOUT_GREEN6 17 80 - #define STA2X11_GPIO18_RGBOUT_GREEN5 18 81 - #define STA2X11_GPIO19_RGBOUT_GREEN4 19 82 - #define STA2X11_GPIO20_RGBOUT_GREEN3 20 83 - #define STA2X11_GPIO21_RGBOUT_GREEN2 21 84 - #define STA2X11_GPIO22_RGBOUT_GREEN1 22 85 - #define STA2X11_GPIO23_RGBOUT_GREEN0 23 86 - #define STA2X11_GPIO24_RGBOUT_BLUE7 24 87 - #define STA2X11_GPIO25_RGBOUT_BLUE6 25 88 - #define STA2X11_GPIO26_RGBOUT_BLUE5 26 89 - #define STA2X11_GPIO27_RGBOUT_BLUE4 27 90 - #define STA2X11_GPIO28_RGBOUT_BLUE3 28 91 - #define STA2X11_GPIO29_RGBOUT_BLUE2 29 92 - #define STA2X11_GPIO30_RGBOUT_BLUE1 30 93 - #define STA2X11_GPIO31_RGBOUT_BLUE0 31 94 - #define STA2X11_GPIO32_RGBOUT_VSYNCH 32 95 - #define STA2X11_GPIO33_RGBOUT_HSYNCH 33 96 - #define STA2X11_GPIO34_RGBOUT_DEN 34 97 - #define STA2X11_GPIO35_ETH_CRS_DV 35 98 - #define STA2X11_GPIO36_ETH_TXD1 36 99 - #define STA2X11_GPIO37_ETH_TXD0 37 100 - #define STA2X11_GPIO38_ETH_TX_EN 38 101 - #define STA2X11_GPIO39_MDIO 39 102 - #define STA2X11_GPIO40_ETH_REF_CLK 40 103 - #define STA2X11_GPIO41_ETH_RXD1 41 104 - #define STA2X11_GPIO42_ETH_RXD0 42 105 - #define STA2X11_GPIO43_MDC 43 106 - #define STA2X11_GPIO44_CAN_TX 44 107 - #define STA2X11_GPIO45_CAN_RX 45 108 - #define STA2X11_GPIO46_MLB_DAT 46 109 - #define STA2X11_GPIO47_MLB_SIG 47 110 - #define STA2X11_GPIO48_SPI0_CLK 48 111 - #define STA2X11_GPIO49_SPI0_TXD 49 112 - #define STA2X11_GPIO50_SPI0_RXD 50 113 - #define STA2X11_GPIO51_SPI0_FRM 51 114 - #define STA2X11_GPIO52_SPI1_CLK 52 115 - #define STA2X11_GPIO53_SPI1_TXD 53 116 - #define STA2X11_GPIO54_SPI1_RXD 54 117 - #define STA2X11_GPIO55_SPI1_FRM 55 118 - #define STA2X11_GPIO56_SPI2_CLK 56 119 - #define STA2X11_GPIO57_SPI2_TXD 57 120 - #define STA2X11_GPIO58_SPI2_RXD 58 121 - #define STA2X11_GPIO59_SPI2_FRM 59 122 - #define STA2X11_GPIO60_I2C0_SCL 60 123 - #define STA2X11_GPIO61_I2C0_SDA 61 124 - #define STA2X11_GPIO62_I2C1_SCL 62 125 - #define STA2X11_GPIO63_I2C1_SDA 63 126 - #define STA2X11_GPIO64_I2C2_SCL 64 127 - #define STA2X11_GPIO65_I2C2_SDA 65 128 - #define STA2X11_GPIO66_I2C3_SCL 66 129 - #define STA2X11_GPIO67_I2C3_SDA 67 130 - #define STA2X11_GPIO68_MSP0_RCK 68 131 - #define STA2X11_GPIO69_MSP0_RXD 69 132 - #define STA2X11_GPIO70_MSP0_RFS 70 133 - #define STA2X11_GPIO71_MSP0_TCK 71 134 - #define STA2X11_GPIO72_MSP0_TXD 72 135 - #define STA2X11_GPIO73_MSP0_TFS 73 136 - #define STA2X11_GPIO74_MSP0_SCK 74 137 - #define STA2X11_GPIO75_MSP1_CK 75 138 - #define STA2X11_GPIO76_MSP1_RXD 76 139 - #define STA2X11_GPIO77_MSP1_FS 77 140 - #define STA2X11_GPIO78_MSP1_TXD 78 141 - #define STA2X11_GPIO79_MSP2_CK 79 142 - #define STA2X11_GPIO80_MSP2_RXD 80 143 - #define STA2X11_GPIO81_MSP2_FS 81 144 - #define STA2X11_GPIO82_MSP2_TXD 82 145 - #define STA2X11_GPIO83_MSP3_CK 83 146 - #define STA2X11_GPIO84_MSP3_RXD 84 147 - #define STA2X11_GPIO85_MSP3_FS 85 148 - #define STA2X11_GPIO86_MSP3_TXD 86 149 - #define STA2X11_GPIO87_MSP4_CK 87 150 - #define STA2X11_GPIO88_MSP4_RXD 88 151 - #define STA2X11_GPIO89_MSP4_FS 89 152 - #define STA2X11_GPIO90_MSP4_TXD 90 153 - #define STA2X11_GPIO91_MSP5_CK 91 154 - #define STA2X11_GPIO92_MSP5_RXD 92 155 - #define STA2X11_GPIO93_MSP5_FS 93 156 - #define STA2X11_GPIO94_MSP5_TXD 94 157 - #define STA2X11_GPIO95_SDIO3_DAT3 95 158 - #define STA2X11_GPIO96_SDIO3_DAT2 96 159 - #define STA2X11_GPIO97_SDIO3_DAT1 97 160 - #define STA2X11_GPIO98_SDIO3_DAT0 98 161 - #define STA2X11_GPIO99_SDIO3_CLK 99 162 - #define STA2X11_GPIO100_SDIO3_CMD 100 163 - #define STA2X11_GPIO101 101 164 - #define STA2X11_GPIO102 102 165 - #define STA2X11_GPIO103 103 166 - #define STA2X11_GPIO104 104 167 - #define STA2X11_GPIO105_SDIO2_DAT3 105 168 - #define STA2X11_GPIO106_SDIO2_DAT2 106 169 - #define STA2X11_GPIO107_SDIO2_DAT1 107 170 - #define STA2X11_GPIO108_SDIO2_DAT0 108 171 - #define STA2X11_GPIO109_SDIO2_CLK 109 172 - #define STA2X11_GPIO110_SDIO2_CMD 110 173 - #define STA2X11_GPIO111 111 174 - #define STA2X11_GPIO112 112 175 - #define STA2X11_GPIO113 113 176 - #define STA2X11_GPIO114 114 177 - #define STA2X11_GPIO115_SDIO1_DAT3 115 178 - #define STA2X11_GPIO116_SDIO1_DAT2 116 179 - #define STA2X11_GPIO117_SDIO1_DAT1 117 180 - #define STA2X11_GPIO118_SDIO1_DAT0 118 181 - #define STA2X11_GPIO119_SDIO1_CLK 119 182 - #define STA2X11_GPIO120_SDIO1_CMD 120 183 - #define STA2X11_GPIO121 121 184 - #define STA2X11_GPIO122 122 185 - #define STA2X11_GPIO123 123 186 - #define STA2X11_GPIO124 124 187 - #define STA2X11_GPIO125_UART2_TXD 125 188 - #define STA2X11_GPIO126_UART2_RXD 126 189 - #define STA2X11_GPIO127_UART3_TXD 127 190 - 191 - /* 192 - * The APB bridge has its own registers, needed by our users as well. 193 - * They are accessed with the following read/mask/write function. 194 - */ 195 - static inline u32 196 - sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) 197 - { 198 - return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg); 199 - } 200 - 201 - /* CAN and MLB */ 202 - #define APBREG_BSR 0x00 /* Bridge Status Reg */ 203 - #define APBREG_PAER 0x08 /* Peripherals Address Error Reg */ 204 - #define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */ 205 - #define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */ 206 - #define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */ 207 - #define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */ 208 - #define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */ 209 - 210 - #define APBREG_CAN (1 << 1) 211 - #define APBREG_MLB (1 << 3) 212 - 213 - /* SARAC */ 214 - #define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */ 215 - #define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */ 216 - #define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */ 217 - #define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */ 218 - #define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */ 219 - #define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */ 220 - #define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */ 221 - 222 - #define APBREG_SARAC (1 << 2) 223 - 224 - /* 225 - * The system controller has its own registers. Some of these are accessed 226 - * by out users as well, using the following read/mask/write/function 227 - */ 228 - static inline 229 - u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) 230 - { 231 - return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl); 232 - } 233 - 234 - #define SCTL_SCCTL 0x00 /* System controller control register */ 235 - #define SCTL_ARMCFG 0x04 /* ARM configuration register */ 236 - #define SCTL_SCPLLCTL 0x08 /* PLL control status register */ 237 - 238 - #define SCTL_SCPLLCTL_AUDIO_PLL_PD BIT(1) 239 - #define SCTL_SCPLLCTL_FRAC_CONTROL BIT(3) 240 - #define SCTL_SCPLLCTL_STRB_BYPASS BIT(6) 241 - #define SCTL_SCPLLCTL_STRB_INPUT BIT(8) 242 - 243 - #define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */ 244 - 245 - #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_MASK 0xff 246 - #define SCTL_SCPLLFCTRL_AUDIO_PLL_NDIV_SHIFT 10 247 - #define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_MASK 7 248 - #define SCTL_SCPLLFCTRL_AUDIO_PLL_IDF_SHIFT 21 249 - #define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_MASK 7 250 - #define SCTL_SCPLLFCTRL_AUDIO_PLL_ODF_SHIFT 18 251 - #define SCTL_SCPLLFCTRL_DITHER_DISABLE_MASK 0x03 252 - #define SCTL_SCPLLFCTRL_DITHER_DISABLE_SHIFT 4 253 - 254 - 255 - #define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */ 256 - 257 - #define SCTL_SCRESFRACT_MASK 0x0000ffff 258 - 259 - 260 - #define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */ 261 - #define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */ 262 - #define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */ 263 - #define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */ 264 - #define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */ 265 - #define SCTL_SCGRST 0x28 /* Peripheral global reset */ 266 - #define SCTL_SCPCIECSBRST 0x2c /* PCIe PAB CSB reset status register */ 267 - #define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */ 268 - #define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */ 269 - #define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */ 270 - #define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */ 271 - #define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */ 272 - #define SCTL_SCINTREN 0x44 /* Interrupt enable */ 273 - #define SCTL_SCRISR 0x48 /* RAW interrupt status */ 274 - #define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */ 275 - #define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */ 276 - #define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */ 277 - #define SCTL_SCRSTSTA 0x58 /* Reset status register */ 278 - 279 - #define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0) 280 - #define SCTL_SCRESCTRL1_USB_OTG (1 << 1) 281 - #define SCTL_SCRESCTRL1_USB_HRST (1 << 2) 282 - #define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3) 283 - #define SCTL_SCRESCTRL1_SATAII (1 << 4) 284 - #define SCTL_SCRESCTRL1_VIP (1 << 5) 285 - #define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6) 286 - #define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7) 287 - #define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8) 288 - #define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9) 289 - #define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10) 290 - #define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11) 291 - #define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12) 292 - #define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13) 293 - #define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14) 294 - #define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15) 295 - #define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16) 296 - #define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17) 297 - #define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18) 298 - #define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19) 299 - #define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20) 300 - #define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21) 301 - #define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22) 302 - #define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23) 303 - #define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24) 304 - #define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25) 305 - #define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26) 306 - #define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27) 307 - #define SCTL_SCRESCTRL1_PER_MMC (1 << 28) 308 - #define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29) 309 - #define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30) 310 - #define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31) 311 - 312 - #define SCTL_SCPEREN0_UART0 (1 << 0) 313 - #define SCTL_SCPEREN0_UART1 (1 << 1) 314 - #define SCTL_SCPEREN0_UART2 (1 << 2) 315 - #define SCTL_SCPEREN0_UART3 (1 << 3) 316 - #define SCTL_SCPEREN0_MSP0 (1 << 4) 317 - #define SCTL_SCPEREN0_MSP1 (1 << 5) 318 - #define SCTL_SCPEREN0_MSP2 (1 << 6) 319 - #define SCTL_SCPEREN0_MSP3 (1 << 7) 320 - #define SCTL_SCPEREN0_MSP4 (1 << 8) 321 - #define SCTL_SCPEREN0_MSP5 (1 << 9) 322 - #define SCTL_SCPEREN0_SPI0 (1 << 10) 323 - #define SCTL_SCPEREN0_SPI1 (1 << 11) 324 - #define SCTL_SCPEREN0_SPI2 (1 << 12) 325 - #define SCTL_SCPEREN0_I2C0 (1 << 13) 326 - #define SCTL_SCPEREN0_I2C1 (1 << 14) 327 - #define SCTL_SCPEREN0_I2C2 (1 << 15) 328 - #define SCTL_SCPEREN0_I2C3 (1 << 16) 329 - #define SCTL_SCPEREN0_SVDO_LVDS (1 << 17) 330 - #define SCTL_SCPEREN0_USB_HOST (1 << 18) 331 - #define SCTL_SCPEREN0_USB_OTG (1 << 19) 332 - #define SCTL_SCPEREN0_MCI0 (1 << 20) 333 - #define SCTL_SCPEREN0_MCI1 (1 << 21) 334 - #define SCTL_SCPEREN0_MCI2 (1 << 22) 335 - #define SCTL_SCPEREN0_MCI3 (1 << 23) 336 - #define SCTL_SCPEREN0_SATA (1 << 24) 337 - #define SCTL_SCPEREN0_ETHERNET (1 << 25) 338 - #define SCTL_SCPEREN0_VIC (1 << 26) 339 - #define SCTL_SCPEREN0_DMA_AUDIO (1 << 27) 340 - #define SCTL_SCPEREN0_DMA_SOC (1 << 28) 341 - #define SCTL_SCPEREN0_RAM (1 << 29) 342 - #define SCTL_SCPEREN0_VIP (1 << 30) 343 - #define SCTL_SCPEREN0_ARM (1 << 31) 344 - 345 - #define SCTL_SCPEREN1_UART0 (1 << 0) 346 - #define SCTL_SCPEREN1_UART1 (1 << 1) 347 - #define SCTL_SCPEREN1_UART2 (1 << 2) 348 - #define SCTL_SCPEREN1_UART3 (1 << 3) 349 - #define SCTL_SCPEREN1_MSP0 (1 << 4) 350 - #define SCTL_SCPEREN1_MSP1 (1 << 5) 351 - #define SCTL_SCPEREN1_MSP2 (1 << 6) 352 - #define SCTL_SCPEREN1_MSP3 (1 << 7) 353 - #define SCTL_SCPEREN1_MSP4 (1 << 8) 354 - #define SCTL_SCPEREN1_MSP5 (1 << 9) 355 - #define SCTL_SCPEREN1_SPI0 (1 << 10) 356 - #define SCTL_SCPEREN1_SPI1 (1 << 11) 357 - #define SCTL_SCPEREN1_SPI2 (1 << 12) 358 - #define SCTL_SCPEREN1_I2C0 (1 << 13) 359 - #define SCTL_SCPEREN1_I2C1 (1 << 14) 360 - #define SCTL_SCPEREN1_I2C2 (1 << 15) 361 - #define SCTL_SCPEREN1_I2C3 (1 << 16) 362 - #define SCTL_SCPEREN1_USB_PHY (1 << 17) 363 - 364 - /* 365 - * APB-SOC registers 366 - */ 367 - static inline 368 - u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) 369 - { 370 - return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs); 371 - } 372 - 373 - #define PCIE_EP1_FUNC3_0_INTR_REG 0x000 374 - #define PCIE_EP1_FUNC7_4_INTR_REG 0x004 375 - #define PCIE_EP2_FUNC3_0_INTR_REG 0x008 376 - #define PCIE_EP2_FUNC7_4_INTR_REG 0x00c 377 - #define PCIE_EP3_FUNC3_0_INTR_REG 0x010 378 - #define PCIE_EP3_FUNC7_4_INTR_REG 0x014 379 - #define PCIE_EP4_FUNC3_0_INTR_REG 0x018 380 - #define PCIE_EP4_FUNC7_4_INTR_REG 0x01c 381 - #define PCIE_INTR_ENABLE0_REG 0x020 382 - #define PCIE_INTR_ENABLE1_REG 0x024 383 - #define PCIE_EP1_FUNC_TC_REG 0x028 384 - #define PCIE_EP2_FUNC_TC_REG 0x02c 385 - #define PCIE_EP3_FUNC_TC_REG 0x030 386 - #define PCIE_EP4_FUNC_TC_REG 0x034 387 - #define PCIE_EP1_FUNC_F_REG 0x038 388 - #define PCIE_EP2_FUNC_F_REG 0x03c 389 - #define PCIE_EP3_FUNC_F_REG 0x040 390 - #define PCIE_EP4_FUNC_F_REG 0x044 391 - #define PCIE_PAB_AMBA_SW_RST_REG 0x048 392 - #define PCIE_PM_STATUS_0_PORT_0_4 0x04c 393 - #define PCIE_PM_STATUS_7_0_EP1 0x050 394 - #define PCIE_PM_STATUS_7_0_EP2 0x054 395 - #define PCIE_PM_STATUS_7_0_EP3 0x058 396 - #define PCIE_PM_STATUS_7_0_EP4 0x05c 397 - #define PCIE_DEV_ID_0_EP1_REG 0x060 398 - #define PCIE_CC_REV_ID_0_EP1_REG 0x064 399 - #define PCIE_DEV_ID_1_EP1_REG 0x068 400 - #define PCIE_CC_REV_ID_1_EP1_REG 0x06c 401 - #define PCIE_DEV_ID_2_EP1_REG 0x070 402 - #define PCIE_CC_REV_ID_2_EP1_REG 0x074 403 - #define PCIE_DEV_ID_3_EP1_REG 0x078 404 - #define PCIE_CC_REV_ID_3_EP1_REG 0x07c 405 - #define PCIE_DEV_ID_4_EP1_REG 0x080 406 - #define PCIE_CC_REV_ID_4_EP1_REG 0x084 407 - #define PCIE_DEV_ID_5_EP1_REG 0x088 408 - #define PCIE_CC_REV_ID_5_EP1_REG 0x08c 409 - #define PCIE_DEV_ID_6_EP1_REG 0x090 410 - #define PCIE_CC_REV_ID_6_EP1_REG 0x094 411 - #define PCIE_DEV_ID_7_EP1_REG 0x098 412 - #define PCIE_CC_REV_ID_7_EP1_REG 0x09c 413 - #define PCIE_DEV_ID_0_EP2_REG 0x0a0 414 - #define PCIE_CC_REV_ID_0_EP2_REG 0x0a4 415 - #define PCIE_DEV_ID_1_EP2_REG 0x0a8 416 - #define PCIE_CC_REV_ID_1_EP2_REG 0x0ac 417 - #define PCIE_DEV_ID_2_EP2_REG 0x0b0 418 - #define PCIE_CC_REV_ID_2_EP2_REG 0x0b4 419 - #define PCIE_DEV_ID_3_EP2_REG 0x0b8 420 - #define PCIE_CC_REV_ID_3_EP2_REG 0x0bc 421 - #define PCIE_DEV_ID_4_EP2_REG 0x0c0 422 - #define PCIE_CC_REV_ID_4_EP2_REG 0x0c4 423 - #define PCIE_DEV_ID_5_EP2_REG 0x0c8 424 - #define PCIE_CC_REV_ID_5_EP2_REG 0x0cc 425 - #define PCIE_DEV_ID_6_EP2_REG 0x0d0 426 - #define PCIE_CC_REV_ID_6_EP2_REG 0x0d4 427 - #define PCIE_DEV_ID_7_EP2_REG 0x0d8 428 - #define PCIE_CC_REV_ID_7_EP2_REG 0x0dC 429 - #define PCIE_DEV_ID_0_EP3_REG 0x0e0 430 - #define PCIE_CC_REV_ID_0_EP3_REG 0x0e4 431 - #define PCIE_DEV_ID_1_EP3_REG 0x0e8 432 - #define PCIE_CC_REV_ID_1_EP3_REG 0x0ec 433 - #define PCIE_DEV_ID_2_EP3_REG 0x0f0 434 - #define PCIE_CC_REV_ID_2_EP3_REG 0x0f4 435 - #define PCIE_DEV_ID_3_EP3_REG 0x0f8 436 - #define PCIE_CC_REV_ID_3_EP3_REG 0x0fc 437 - #define PCIE_DEV_ID_4_EP3_REG 0x100 438 - #define PCIE_CC_REV_ID_4_EP3_REG 0x104 439 - #define PCIE_DEV_ID_5_EP3_REG 0x108 440 - #define PCIE_CC_REV_ID_5_EP3_REG 0x10c 441 - #define PCIE_DEV_ID_6_EP3_REG 0x110 442 - #define PCIE_CC_REV_ID_6_EP3_REG 0x114 443 - #define PCIE_DEV_ID_7_EP3_REG 0x118 444 - #define PCIE_CC_REV_ID_7_EP3_REG 0x11c 445 - #define PCIE_DEV_ID_0_EP4_REG 0x120 446 - #define PCIE_CC_REV_ID_0_EP4_REG 0x124 447 - #define PCIE_DEV_ID_1_EP4_REG 0x128 448 - #define PCIE_CC_REV_ID_1_EP4_REG 0x12c 449 - #define PCIE_DEV_ID_2_EP4_REG 0x130 450 - #define PCIE_CC_REV_ID_2_EP4_REG 0x134 451 - #define PCIE_DEV_ID_3_EP4_REG 0x138 452 - #define PCIE_CC_REV_ID_3_EP4_REG 0x13c 453 - #define PCIE_DEV_ID_4_EP4_REG 0x140 454 - #define PCIE_CC_REV_ID_4_EP4_REG 0x144 455 - #define PCIE_DEV_ID_5_EP4_REG 0x148 456 - #define PCIE_CC_REV_ID_5_EP4_REG 0x14c 457 - #define PCIE_DEV_ID_6_EP4_REG 0x150 458 - #define PCIE_CC_REV_ID_6_EP4_REG 0x154 459 - #define PCIE_DEV_ID_7_EP4_REG 0x158 460 - #define PCIE_CC_REV_ID_7_EP4_REG 0x15c 461 - #define PCIE_SUBSYS_VEN_ID_REG 0x160 462 - #define PCIE_COMMON_CLOCK_CONFIG_0_4_0 0x164 463 - #define PCIE_MIPHYP_SSC_EN_REG 0x168 464 - #define PCIE_MIPHYP_ADDR_REG 0x16c 465 - #define PCIE_L1_ASPM_READY_REG 0x170 466 - #define PCIE_EXT_CFG_RDY_REG 0x174 467 - #define PCIE_SoC_INT_ROUTER_STATUS0_REG 0x178 468 - #define PCIE_SoC_INT_ROUTER_STATUS1_REG 0x17c 469 - #define PCIE_SoC_INT_ROUTER_STATUS2_REG 0x180 470 - #define PCIE_SoC_INT_ROUTER_STATUS3_REG 0x184 471 - #define DMA_IP_CTRL_REG 0x324 472 - #define DISP_BRIDGE_PU_PD_CTRL_REG 0x328 473 - #define VIP_PU_PD_CTRL_REG 0x32c 474 - #define USB_MLB_PU_PD_CTRL_REG 0x330 475 - #define SDIO_PU_PD_MISCFUNC_CTRL_REG1 0x334 476 - #define SDIO_PU_PD_MISCFUNC_CTRL_REG2 0x338 477 - #define UART_PU_PD_CTRL_REG 0x33c 478 - #define ARM_Lock 0x340 479 - #define SYS_IO_CHAR_REG1 0x344 480 - #define SYS_IO_CHAR_REG2 0x348 481 - #define SATA_CORE_ID_REG 0x34c 482 - #define SATA_CTRL_REG 0x350 483 - #define I2C_HSFIX_MISC_REG 0x354 484 - #define SPARE2_RESERVED 0x358 485 - #define SPARE3_RESERVED 0x35c 486 - #define MASTER_LOCK_REG 0x368 487 - #define SYSTEM_CONFIG_STATUS_REG 0x36c 488 - #define MSP_CLK_CTRL_REG 0x39c 489 - #define COMPENSATION_REG1 0x3c4 490 - #define COMPENSATION_REG2 0x3c8 491 - #define COMPENSATION_REG3 0x3cc 492 - #define TEST_CTL_REG 0x3d0 493 - 494 - /* 495 - * SECR (OTP) registers 496 - */ 497 - #define STA2X11_SECR_CR 0x00 498 - #define STA2X11_SECR_FVR0 0x10 499 - #define STA2X11_SECR_FVR1 0x14 500 - 501 - extern int sta2x11_mfd_get_regs_data(struct platform_device *pdev, 502 - enum sta2x11_mfd_plat_dev index, 503 - void __iomem **regs, 504 - spinlock_t **lock); 505 - 506 - #endif /* __STA2X11_MFD_H */