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arm64: dts: marvell: fix interrupt-map property for Armada CP110 PCIe controller

The interrupt-map property used in the description of the Marvell
Armada 7K/8K PCIe controllers has a bogus extraneous 0 that causes the
interrupt conversion to not be done properly. This causes the PCIe PME
and AER root port service drivers to fail their initialization:

[ 5.019900] genirq: Setting trigger mode 7 for irq 114 failed (irq_chip_set_type_parent+0x0/0x30)
[ 5.028821] pcie_pme: probe of 0001:00:00.0:pcie001 failed with error -22
[ 5.035687] genirq: Setting trigger mode 7 for irq 114 failed (irq_chip_set_type_parent+0x0/0x30)
[ 5.044614] aer: probe of 0001:00:00.0:pcie002 failed with error -22

This problem was introduced when the interrupt description was
switched from using the GIC directly to using the ICU interrupt
controller. Indeed, the GIC has address-cells = <1>, which requires a
parent unit address, while the ICU has address-cells = <0>.

Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

authored by

Thomas Petazzoni and committed by
Gregory CLEMENT 98f7d577 9e7460fc

+6 -6
+3 -3
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
··· 336 336 /* non-prefetchable memory */ 337 337 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 338 338 interrupt-map-mask = <0 0 0 0>; 339 - interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 339 + interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 340 340 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 341 341 num-lanes = <1>; 342 342 clocks = <&cpm_clk 1 13>; ··· 362 362 /* non-prefetchable memory */ 363 363 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; 364 364 interrupt-map-mask = <0 0 0 0>; 365 - interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 365 + interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 366 366 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 367 367 368 368 num-lanes = <1>; ··· 389 389 /* non-prefetchable memory */ 390 390 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; 391 391 interrupt-map-mask = <0 0 0 0>; 392 - interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 392 + interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 393 393 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 394 394 395 395 num-lanes = <1>;
+3 -3
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
··· 335 335 /* non-prefetchable memory */ 336 336 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; 337 337 interrupt-map-mask = <0 0 0 0>; 338 - interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 338 + interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 339 339 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; 340 340 num-lanes = <1>; 341 341 clocks = <&cps_clk 1 13>; ··· 361 361 /* non-prefetchable memory */ 362 362 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; 363 363 interrupt-map-mask = <0 0 0 0>; 364 - interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 364 + interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 365 365 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; 366 366 367 367 num-lanes = <1>; ··· 388 388 /* non-prefetchable memory */ 389 389 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; 390 390 interrupt-map-mask = <0 0 0 0>; 391 - interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 391 + interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 392 392 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; 393 393 394 394 num-lanes = <1>;