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ASoC: fsl_mqs: Distinguish different modules by system manager indices

On i.MX94, the MQS2 also needs to be configured by SCMI interface, add
sm_index variable in struct fsl_mqs_soc_data to distinguish the MQS1 and
MQS2 on this platform.

Add the system manager indices for i.MX94 in the header file.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20250620055229.965942-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shengjiu Wang and committed by
Mark Brown 9931d289 b27a58ec

+16 -3
+8
include/linux/firmware/imx/sm.h
··· 18 18 #define SCMI_IMX_CTRL_SAI4_MCLK 4 /* WAKE SAI4 MCLK */ 19 19 #define SCMI_IMX_CTRL_SAI5_MCLK 5 /* WAKE SAI5 MCLK */ 20 20 21 + #define SCMI_IMX94_CTRL_PDM_CLK_SEL 0U /*!< AON PDM clock sel */ 22 + #define SCMI_IMX94_CTRL_MQS1_SETTINGS 1U /*!< AON MQS settings */ 23 + #define SCMI_IMX94_CTRL_MQS2_SETTINGS 2U /*!< WAKE MQS settings */ 24 + #define SCMI_IMX94_CTRL_SAI1_MCLK 3U /*!< AON SAI1 MCLK */ 25 + #define SCMI_IMX94_CTRL_SAI2_MCLK 4U /*!< WAKE SAI2 MCLK */ 26 + #define SCMI_IMX94_CTRL_SAI3_MCLK 5U /*!< WAKE SAI3 MCLK */ 27 + #define SCMI_IMX94_CTRL_SAI4_MCLK 6U /*!< WAKE SAI4 MCLK */ 28 + 21 29 int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val); 22 30 int scmi_imx_misc_ctrl_set(u32 id, u32 val); 23 31
+8 -3
sound/soc/fsl/fsl_mqs.c
··· 39 39 * struct fsl_mqs_soc_data - soc specific data 40 40 * 41 41 * @type: control register space type 42 + * @sm_index: index from definition in system manager 42 43 * @ctrl_off: control register offset 43 44 * @en_mask: enable bit mask 44 45 * @en_shift: enable bit shift ··· 52 51 */ 53 52 struct fsl_mqs_soc_data { 54 53 enum reg_type type; 54 + int sm_index; 55 55 int ctrl_off; 56 56 int en_mask; 57 57 int en_shift; ··· 84 82 85 83 if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) && 86 84 mqs_priv->soc->ctrl_off == reg) 87 - return scmi_imx_misc_ctrl_get(SCMI_IMX_CTRL_MQS1_SETTINGS, &num, val); 85 + return scmi_imx_misc_ctrl_get(mqs_priv->soc->sm_index, &num, val); 88 86 89 87 return -EINVAL; 90 88 }; ··· 95 93 96 94 if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) && 97 95 mqs_priv->soc->ctrl_off == reg) 98 - return scmi_imx_misc_ctrl_set(SCMI_IMX_CTRL_MQS1_SETTINGS, val); 96 + return scmi_imx_misc_ctrl_set(mqs_priv->soc->sm_index, val); 99 97 100 98 return -EINVAL; 101 99 }; ··· 388 386 389 387 static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = { 390 388 .type = TYPE_REG_SM, 389 + .sm_index = SCMI_IMX_CTRL_MQS1_SETTINGS, 391 390 .ctrl_off = 0x88, 392 391 .en_mask = BIT(1), 393 392 .en_shift = 1, ··· 415 412 416 413 static const struct fsl_mqs_soc_data fsl_mqs_imx943_aon_data = { 417 414 .type = TYPE_REG_SM, 415 + .sm_index = SCMI_IMX94_CTRL_MQS1_SETTINGS, 418 416 .ctrl_off = 0x88, 419 417 .en_mask = BIT(1), 420 418 .en_shift = 1, ··· 428 424 }; 429 425 430 426 static const struct fsl_mqs_soc_data fsl_mqs_imx943_wakeup_data = { 431 - .type = TYPE_REG_GPR, 427 + .type = TYPE_REG_SM, 428 + .sm_index = SCMI_IMX94_CTRL_MQS2_SETTINGS, 432 429 .ctrl_off = 0x10, 433 430 .en_mask = BIT(1), 434 431 .en_shift = 1,