Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iio-for-7.0a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
Jonathan writes:
IIO: New device support, features and cleanup for the 6.20/7.0 cycle.
Slightly messier than normal unfortunately due to some conflicts
and build config bugs related to I3C drivers.
One last minute Kconfig fix right at the top after a linux-next report.
I've simplified the Kconfig and made it match other instances in the kernel
so that should be safe enough despite short soak time in front of build bots.
Merge of an immutable branch from I3C to get some stubs that were missing
and caused build issues with dual I2C / I3C drivers. This also brought in a
drop of some deprecated interfaces so there is also one patch to update a
new driver to not use those.
We are having another go at using cleanup.h magic with the IIO mode claim
functions after backing out last try at this. This time we have wrappers
around the new ACQUIRE() and ACQUIRE_ERR() macros.
Having been burnt once, we will be taking it a bit more slowly this time
wrt to wide adoption of these! Thanks in particular to Kurt for taking
on this core IIO work.
New Device Support
==================
adi,ad18113
- New driver to support the AD18113 amplifier - an interesting device due
to the external bypass paths where we need to describe what gain those
paths have in DT. Longer term it will be interesting to see if this
simplistic description is enough for real deployments.
adi,ad4062
- New driver for the AD4060 and AD4052 SAR ADCs including trigger, event
and GPIO controller support. Follow up patch replaced use of some
deprecated I3C interfaces prior to the I3C immutable branch merge as
that includes dropping them.
adi,ad4134
- New driver for the AD4134 24bit 4 channel simultaneous sampling ADC.
adi,ad7768-1,
- Add support for the ADAQ767-1, ADAQ7768-1 and ADAQ7769-1 ADCs after some
rework to enable the driver to support multiple device types.
adi,ad9467
- Add support for the similar ad9211 ADC to this existing driver.
- Make the selection of 2s comp mode explicit for normal operation and
switch to offset binary when entering calibration mode.
honeywell,abp2
- New driver to support this huge family (100+) of board mount pressure and
temperature sensors.
maxim,max22007
- New drier for this 4 channel DAC.
memsic,mmc5633
- New driver for this I2C/I3C magnetometer. Follow on patches fixed up
issues related to single driver supporting both bus types.
microchip,mcp747feb02
- New driver for the Microchip MCP47F(E/V)B(0/1/2)1,
MCP47F(E/V)B(0/1/2)2, MCP47F(E/V)B(0/1/2)4 and MCP47F(E/V)B(0/1/2)8
buffered voltage output DACs.
nxp,sar-adc
- New driver support ADCs found on s32g2 and s32g3 platforms.
ti,ads1018
- New drier for the ADS1018 and ADS1118 SPI ADCs.
ti,ads131m02
- New driver supporting ADS131M(02/03/04/06/08)24-bit simultaneous sampling
ADCs.
Features
========
iio-core
- New IIO_DEV_ACQUIRE_DIRECT_MODE() / IIO_DEV_ACQUIRE_FAILED() +
equivalents for the much rarer case where the mode needs pinning
whether or not it is in direct mode. These use the ACQUIRE()
/ ACQUIRE_ERR() infrastructure underneath to provide both simple
checks on whether we got the requested mode and to provide scope
based release. Applied in a few initial drivers.
adi,ad9467
- Support calibbias control
adi,adf4377
- Add support to act as a clock provider.
adi,adxl380
- Support low power 1KHz sampling frequency mode. Required rework of
how events and filters were configured, plus applying of constraints
when in this mode.
rf-digital,rfd77402
- Add interrupt support as alternative to polling for completion.
st,lsm6dsx
- Tap event detection (after considerable driver rework)
Cleanup and Minor Fixes
=======================
More minor cleanup such as typos, white space etc not called out except
where they were applied to a lot of drivers.
Various drivers.
- Use of dev_err_probe() to cleanup error handling.
- Introduce local struct device and struct device_node variables to
reduce duplication of getting them from containing structs.
- Ensure uses of iio_trigger_generic_data_rdy_poll() set IRQF_NO_THREAD
as that function calls non threaded child interrupt handlers.
- Replace IRQF_ONESHOT in not thread interrupt handlers with
IRQF_NO_THREAD to ensure they run as intended. Drop one unnecessary case.
iio-sw-device/trigger.
- Constify configs_group_operations structures.
iio-buffer-dma / buffer-dma-engine
- Use lockdep_assert_held() to replace WARN_ON() to check lock is
correctly held.
- Make use of cleanup.h magic to simplify various code paths.
- Make iio_dma_buffer_init() return void rather than always success.
adi,ad7766
- Replace custom interrupt handler with iio_trigger_generic_data_rdy_poll()
adi,ad9832
- Drop legacy platform_data support.
adi,ade9000
- Add a maintainer entry.
adi,adt7316
- Move to EXPORT_GPL_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() so the compiler
can cleanly drop unused pm structures and callbacks.
adi,adxl345
- Relax build constraint vs the driver that is in input so both may be
built as modules and selection made at runtime.
adi,adxl380
- Make sure we don't read tail entries in the hardware fifo if a partial
new scan has been written.
- Move to a single larger regmap_noinc_read() to read the hardware fifo.
aspeed,ast2600
- Add missing interrupts property to DT binding.
bosch,bmi270_i2c
- Add missing MODULE_DEVICE_TABLE() macros so auto probing of modules can
work.
bosch,smi330
- Drop duplicate assignment of IIO_TYPE in smi330_read_avail()
- Use new common field_get() and field_prep() helpers to replace local
version.
honeywell,mprls0025pa
Fixes delayed to merge window as late in cycle and we didn't want to delay
the rest of the series.
- Allow Kconfig selection of specific bus sub-drivers rather than tying that
to the buses themselves being supported.
- Zero spi_transfer structure to avoid chance of unintentionally set fields
effecting transfer.
- Fix a potential timing violation wrt to the chip select to first clock
edge timing.
- As recent driver, take risk inherent in dropping interrupt direction from
driver as that should be set by firmware.
- Fix wrong reported number of data bits for channel.
- Fix a pressure channel calculation bug.
- Rework to allow embedding the tx buffer in the iio_priv() structure rather
than requiring separate allocation.
- Move the buffer clearing to the shared core bringing it into affect for
SPI as well as I2C.
- Stricter checks for status byte.
- Greatly simplify the measurement sequence.
- Add a copyright entry to reflect Petre's continued work on this driver.
intersil,isl29018
- Switch from spritnf to sysfs_emit_at() to make it clear overflow can't
occur.
invensense,icm42600
- Allow sysfs access to temperature when buffered capture in use as it
does not impact other sensor data paths.
invensense,itg3200
- Check unused return value in read_raw() callback.
men,z188
- Drop now duplicated module alias.
rf-digital,rfd77402
- Add DT binding doc and explicit of_device_id table.
- Poll for timeout with times as on datasheet, then replace opencoded
version with read_poll_timeout().
sensiron,scd4x
- Add missing timestamp channel. The code to push it to the buffer was there
but there was no way to turn it on.
vti,sca3000
- Fix resource leak if iio_device_register() fails.
* tag 'iio-for-7.0a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio: (144 commits)
iio: magn: mmc5633: Fix Kconfig for combination of I3C as module and driver builtin
iio: sca3000: Fix a resource leak in sca3000_probe()
iio: proximity: rfd77402: Add interrupt handling support
iio: proximity: rfd77402: Document device private data structure
iio: proximity: rfd77402: Use devm-managed mutex initialization
iio: proximity: rfd77402: Use kernel helper for result polling
iio: proximity: rfd77402: Align polling timeout with datasheet
iio: cros_ec: Allow enabling/disabling calibration mode
iio: frequency: ad9523: correct kernel-doc bad line warning
iio: buffer: buffer_impl.h: fix kernel-doc warnings
iio: gyro: itg3200: Fix unchecked return value in read_raw
MAINTAINERS: add entry for ADE9000 driver
iio: accel: sca3000: remove unused last_timestamp field
iio: accel: adxl372: remove unused int2_bitmask field
iio: adc: ad7766: Use iio_trigger_generic_data_rdy_poll()
iio: magnetometer: Remove IRQF_ONESHOT
iio: Replace IRQF_ONESHOT with IRQF_NO_THREAD
iio: Use IRQF_NO_THREAD
iio: dac: Add MAX22007 DAC driver support
dt-bindings: iio: dac: Add max22007
...
+12096
-1227
+11
Documentation/ABI/testing/sysfs-bus-i3c
+11
Documentation/ABI/testing/sysfs-bus-i3c
···
161
161
Description:
162
162
These directories are just symbolic links to
163
163
/sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>.
164
+
165
+
What: /sys/bus/i3c/devices/i3c-<bus-id>/<bus-id>-<device-pid>/dev_nack_retry_count
166
+
KernelVersion: 6.18
167
+
Contact: linux-i3c@vger.kernel.org
168
+
Description:
169
+
Expose the dev_nak_retry_count which controls the number of
170
+
automatic retries that will be performed by the controller when
171
+
the target device returns a NACK response. A value of 0 disables
172
+
the automatic retries. Exist only when I3C constroller supports
173
+
this retry on nack feature.
174
+
+6
-3
Documentation/ABI/testing/sysfs-bus-iio-cros-ec
+6
-3
Documentation/ABI/testing/sysfs-bus-iio-cros-ec
···
3
3
KernelVersion: 4.7
4
4
Contact: linux-iio@vger.kernel.org
5
5
Description:
6
-
Writing '1' will perform a FOC (Fast Online Calibration). The
7
-
corresponding calibration offsets can be read from `*_calibbias`
8
-
entries.
6
+
Writing '1' either perform a FOC (Fast Online Calibration) or
7
+
enter calibration mode.
8
+
Writing '0` exits calibration mode. It is a NOP for FOC enabled
9
+
sensors.
10
+
The corresponding calibration offsets can be read from `*_calibbias`
11
+
entries.
9
12
10
13
What: /sys/bus/iio/devices/iio:deviceX/id
11
14
Date: September 2017
+120
Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml
+120
Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright 2025 Analog Devices Inc.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/iio/adc/adi,ad4062.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Analog Devices AD4062 ADC family device driver
9
+
10
+
maintainers:
11
+
- Jorge Marques <jorge.marques@analog.com>
12
+
13
+
description: |
14
+
Analog Devices AD4062 Single Channel Precision SAR ADC family
15
+
16
+
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4060.pdf
17
+
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4062.pdf
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- adi,ad4060
23
+
- adi,ad4062
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
interrupts:
29
+
description:
30
+
Two pins are available that can be configured as either a general purpose
31
+
digital output, device enable signal (used to synchronise other parts of
32
+
the signal chain with ADC sampling), device ready (GP1 only) or various
33
+
interrupt signals. If intended for use as a GPIO or device enable, will not
34
+
present here.
35
+
minItems: 1
36
+
items:
37
+
- description:
38
+
GP0 pin, cannot be configured as DEV_RDY.
39
+
- description:
40
+
GP1 pin, can be configured to any setting.
41
+
42
+
interrupt-names:
43
+
minItems: 1
44
+
items:
45
+
- const: gp0
46
+
- const: gp1
47
+
48
+
gpio-controller:
49
+
description:
50
+
Marks the device node as a GPIO controller. GPs not listed as interrupts
51
+
are exposed as a GPO.
52
+
53
+
'#gpio-cells':
54
+
const: 2
55
+
description:
56
+
The first cell is the GPIO number and the second cell specifies
57
+
GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
58
+
59
+
vdd-supply:
60
+
description: Analog power supply.
61
+
62
+
vio-supply:
63
+
description: Digital interface logic power supply.
64
+
65
+
ref-supply:
66
+
description:
67
+
Reference voltage to set the ADC full-scale range. If not present,
68
+
vdd-supply is used as the reference voltage.
69
+
70
+
required:
71
+
- compatible
72
+
- reg
73
+
- vdd-supply
74
+
- vio-supply
75
+
76
+
allOf:
77
+
- $ref: /schemas/i3c/i3c.yaml#
78
+
79
+
unevaluatedProperties: false
80
+
81
+
examples:
82
+
- |
83
+
#include <dt-bindings/gpio/gpio.h>
84
+
#include <dt-bindings/interrupt-controller/irq.h>
85
+
86
+
i3c {
87
+
#address-cells = <3>;
88
+
#size-cells = <0>;
89
+
90
+
adc@0,2ee007c0000 {
91
+
reg = <0x0 0x2ee 0x7c0000>;
92
+
vdd-supply = <&vdd>;
93
+
vio-supply = <&vio>;
94
+
ref-supply = <&ref>;
95
+
96
+
interrupt-parent = <&gpio>;
97
+
interrupts = <0 0 IRQ_TYPE_EDGE_RISING>,
98
+
<0 1 IRQ_TYPE_EDGE_FALLING>;
99
+
interrupt-names = "gp0", "gp1";
100
+
};
101
+
};
102
+
103
+
- |
104
+
#include <dt-bindings/gpio/gpio.h>
105
+
#include <dt-bindings/interrupt-controller/irq.h>
106
+
107
+
i3c {
108
+
#address-cells = <3>;
109
+
#size-cells = <0>;
110
+
111
+
adc@0,2ee007c0000 {
112
+
reg = <0x0 0x2ee 0x7c0000>;
113
+
vdd-supply = <&vdd>;
114
+
vio-supply = <&vio>;
115
+
ref-supply = <&ref>;
116
+
117
+
gpio-controller;
118
+
#gpio-cells = <2>;
119
+
};
120
+
};
+191
Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
+191
Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/adi,ad4134.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Analog Devices AD4134 ADC
8
+
9
+
maintainers:
10
+
- Marcelo Schmitt <marcelo.schmitt@analog.com>
11
+
12
+
description: |
13
+
The AD4134 is a quad channel, low noise, simultaneous sampling, precision
14
+
analog-to-digital converter (ADC).
15
+
Specifications can be found at:
16
+
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4134.pdf
17
+
18
+
$ref: /schemas/spi/spi-peripheral-props.yaml#
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- adi,ad4134
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
spi-max-frequency:
29
+
maximum: 50000000
30
+
31
+
avdd5-supply:
32
+
description: A 5V supply that powers the chip's analog circuitry.
33
+
34
+
dvdd5-supply:
35
+
description: A 5V supply that powers the chip's digital circuitry.
36
+
37
+
iovdd-supply:
38
+
description:
39
+
A 1.8V supply that sets the logic levels for the digital interface pins.
40
+
41
+
refin-supply:
42
+
description:
43
+
A 4.096V or 5V supply that serves as reference for ADC conversions.
44
+
45
+
avdd1v8-supply:
46
+
description: A 1.8V supply used by the analog circuitry.
47
+
48
+
dvdd1v8-supply:
49
+
description: A 1.8V supply used by the digital circuitry.
50
+
51
+
clkvdd-supply:
52
+
description: A 1.8V supply for the chip's clock management circuit.
53
+
54
+
ldoin-supply:
55
+
description:
56
+
A 2.6V to 5.5V supply that generates 1.8V for AVDD1V8, DVDD1V8, and CLKVDD
57
+
pins.
58
+
59
+
clocks:
60
+
maxItems: 1
61
+
description:
62
+
Required external clock source. Can specify either a crystal or CMOS clock
63
+
source. If an external crystal is set, connect the CLKSEL pin to IOVDD.
64
+
Otherwise, connect the CLKSEL pin to IOGND and the external CMOS clock
65
+
signal to the XTAL2/CLKIN pin.
66
+
67
+
clock-names:
68
+
enum:
69
+
- xtal
70
+
- clkin
71
+
default: clkin
72
+
73
+
'#clock-cells':
74
+
const: 0
75
+
76
+
clock-output-names:
77
+
maxItems: 1
78
+
79
+
regulators:
80
+
type: object
81
+
description:
82
+
list of regulators provided by this controller.
83
+
84
+
properties:
85
+
vcm-output:
86
+
$ref: /schemas/regulator/regulator.yaml#
87
+
type: object
88
+
unevaluatedProperties: false
89
+
90
+
additionalProperties: false
91
+
92
+
reset-gpios:
93
+
maxItems: 1
94
+
95
+
powerdown-gpios:
96
+
description:
97
+
Active low GPIO connected to the /PDN pin. Forces the device into full
98
+
power-down mode when brought low. Pull this input to IOVDD for normal
99
+
operation.
100
+
maxItems: 1
101
+
102
+
odr-gpios:
103
+
description:
104
+
GPIO connected to ODR pin. Used to sample ADC data in minimum I/O mode.
105
+
maxItems: 1
106
+
107
+
adi,asrc-mode:
108
+
$ref: /schemas/types.yaml#/definitions/string
109
+
description:
110
+
Asynchronous Sample Rate Converter (ASRC) operation mode control input.
111
+
Describes whether the MODE pin is set to a high level (for master mode
112
+
operation) or to a low level (for slave mode operation).
113
+
enum: [ high, low ]
114
+
default: low
115
+
116
+
adi,dclkio:
117
+
description:
118
+
DCLK pin I/O direction control for when the device operates in Pin Control
119
+
Slave Mode or in SPI Control Mode. Describes if DEC0/DCLKIO pin is at a
120
+
high level (which configures DCLK as an output) or to set to a low level
121
+
(configuring DCLK for input).
122
+
enum: [ out, in ]
123
+
default: in
124
+
125
+
adi,dclkmode:
126
+
description:
127
+
DCLK mode control for when the device operates in Pin Control Slave Mode
128
+
or in SPI Control Mode. Describes whether the DEC1/DCLKMODE pin is set to
129
+
a high level (configuring the DCLK to operate in free running mode) or
130
+
to a low level (to configure DCLK to operate in gated mode).
131
+
enum: [ free-running, gated ]
132
+
default: gated
133
+
134
+
required:
135
+
- compatible
136
+
- reg
137
+
- avdd5-supply
138
+
- dvdd5-supply
139
+
- iovdd-supply
140
+
- refin-supply
141
+
- clocks
142
+
- clock-names
143
+
144
+
oneOf:
145
+
- required:
146
+
- ldoin-supply
147
+
- required:
148
+
- avdd1v8-supply
149
+
- dvdd1v8-supply
150
+
- clkvdd-supply
151
+
152
+
unevaluatedProperties: false
153
+
154
+
examples:
155
+
- |
156
+
#include <dt-bindings/gpio/gpio.h>
157
+
158
+
spi {
159
+
#address-cells = <1>;
160
+
#size-cells = <0>;
161
+
162
+
adc@0 {
163
+
compatible = "adi,ad4134";
164
+
reg = <0>;
165
+
166
+
spi-max-frequency = <1000000>;
167
+
168
+
reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
169
+
odr-gpios = <&gpio0 87 GPIO_ACTIVE_HIGH>;
170
+
powerdown-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
171
+
172
+
clocks = <&sys_clk>;
173
+
clock-names = "clkin";
174
+
175
+
avdd5-supply = <&avdd5>;
176
+
dvdd5-supply = <&dvdd5>;
177
+
iovdd-supply = <&iovdd>;
178
+
refin-supply = <&refin>;
179
+
avdd1v8-supply = <&avdd1v8>;
180
+
dvdd1v8-supply = <&dvdd1v8>;
181
+
clkvdd-supply = <&clkvdd>;
182
+
183
+
regulators {
184
+
vcm_reg: vcm-output {
185
+
regulator-name = "ad4134-vcm";
186
+
};
187
+
};
188
+
189
+
};
190
+
};
191
+
...
+60
-4
Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
+60
-4
Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
···
4
4
$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Analog Devices AD7768-1 ADC device driver
7
+
title: Analog Devices AD7768-1 ADC family
8
8
9
9
maintainers:
10
10
- Michael Hennerich <michael.hennerich@analog.com>
11
11
12
12
description: |
13
-
Datasheet at:
14
-
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
13
+
Analog Devices AD7768-1 24-Bit Single Channel Low Power sigma-delta ADC family
14
+
15
+
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
16
+
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7767-1.pdf
17
+
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7768-1.pdf
18
+
https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7769-1.pdf
15
19
16
20
properties:
17
21
compatible:
18
-
const: adi,ad7768-1
22
+
enum:
23
+
- adi,ad7768-1
24
+
- adi,adaq7767-1
25
+
- adi,adaq7768-1
26
+
- adi,adaq7769-1
19
27
20
28
reg:
21
29
maxItems: 1
···
65
57
vref-supply:
66
58
description:
67
59
ADC reference voltage supply
60
+
61
+
adi,aaf-gain-bp:
62
+
description: |
63
+
Specifies the gain applied by the Analog Anti-Aliasing Filter (AAF)
64
+
to the ADC input in basis points (one hundredth of a percent).
65
+
The hardware gain is determined by which input pin(s) the signal goes
66
+
through into the AAF. The possible connections are:
67
+
* For the ADAQ7767-1: Input connected to IN1±, IN2± or IN3±.
68
+
* For the ADAQ7769-1: OUT_PGA pin connected to IN1_AAF+, IN2_AAF+,
69
+
or IN3_AAF+.
70
+
enum: [1430, 3640, 10000]
71
+
default: 10000
72
+
73
+
pga-gpios:
74
+
description:
75
+
GAIN 0, GAIN1 and GAIN2 pins for gain selection. For devices that have
76
+
PGA configuration input pins, pga-gpios must be defined.
77
+
minItems: 3
78
+
maxItems: 3
68
79
69
80
adi,sync-in-gpios:
70
81
maxItems: 1
···
173
146
174
147
allOf:
175
148
- $ref: /schemas/spi/spi-peripheral-props.yaml#
149
+
150
+
# AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices
151
+
- if:
152
+
properties:
153
+
compatible:
154
+
contains:
155
+
enum:
156
+
- adi,adaq7767-1
157
+
- adi,adaq7769-1
158
+
then:
159
+
required:
160
+
- adi,aaf-gain-bp
161
+
else:
162
+
properties:
163
+
adi,aaf-gain-bp: false
164
+
165
+
- if:
166
+
properties:
167
+
compatible:
168
+
contains:
169
+
enum:
170
+
- adi,adaq7768-1
171
+
- adi,adaq7769-1
172
+
then:
173
+
required:
174
+
- pga-gpios
175
+
else:
176
+
properties:
177
+
pga-gpios: false
176
178
177
179
unevaluatedProperties: false
178
180
+2
Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
+2
Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml
···
18
18
All the parts support the register map described by Application Note AN-877
19
19
https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
20
20
21
+
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9211.pdf
21
22
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9265.pdf
22
23
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf
23
24
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf
···
26
25
properties:
27
26
compatible:
28
27
enum:
28
+
- adi,ad9211
29
29
- adi,ad9265
30
30
- adi,ad9434
31
31
- adi,ad9467
+3
Documentation/devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml
+3
Documentation/devicetree/bindings/iio/adc/aspeed,ast2600-adc.yaml
+63
Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
+63
Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP Successive Approximation ADC
8
+
9
+
description:
10
+
The NXP SAR ADC provides fast and accurate analog-to-digital
11
+
conversion using the Successive Approximation Register (SAR) method.
12
+
It has 12-bit resolution with 8 input channels. Conversions can be
13
+
launched in software or using hardware triggers. It supports
14
+
continuous and one-shot modes with separate registers.
15
+
16
+
maintainers:
17
+
- Daniel Lezcano <daniel.lezcano@kernel.org>
18
+
19
+
properties:
20
+
compatible:
21
+
oneOf:
22
+
- const: nxp,s32g2-sar-adc
23
+
- items:
24
+
- const: nxp,s32g3-sar-adc
25
+
- const: nxp,s32g2-sar-adc
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
clocks:
34
+
maxItems: 1
35
+
36
+
dmas:
37
+
maxItems: 1
38
+
39
+
dma-names:
40
+
const: rx
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- interrupts
46
+
- clocks
47
+
- dmas
48
+
- dma-names
49
+
50
+
additionalProperties: false
51
+
52
+
examples:
53
+
- |
54
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
55
+
56
+
adc@401f8000 {
57
+
compatible = "nxp,s32g2-sar-adc";
58
+
reg = <0x401f8000 0x1000>;
59
+
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
60
+
clocks = <&clks 0x41>;
61
+
dmas = <&edma0 0 32>;
62
+
dma-names = "rx";
63
+
};
+82
Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml
+82
Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/ti,ads1018.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI ADS1018/ADS1118 SPI analog to digital converter
8
+
9
+
maintainers:
10
+
- Kurt Borja <kuurtb@gmail.com>
11
+
12
+
description: |
13
+
The ADS1018/ADS1118 is a precision, low-power, 12-bit/16-bit, analog to
14
+
digital converter (ADC). It integrates a programmable gain amplifier (PGA),
15
+
internal voltage reference, oscillator and high-accuracy temperature sensor.
16
+
17
+
Datasheets:
18
+
- ADS1018: https://www.ti.com/lit/ds/symlink/ads1018.pdf
19
+
- ADS1118: https://www.ti.com/lit/ds/symlink/ads1118.pdf
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- ti,ads1018
25
+
- ti,ads1118
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
vdd-supply: true
31
+
32
+
spi-max-frequency:
33
+
maximum: 4000000
34
+
35
+
spi-cpha: true
36
+
37
+
interrupts:
38
+
description: DOUT/DRDY (Data Out/Data Ready) line.
39
+
maxItems: 1
40
+
41
+
drdy-gpios:
42
+
description:
43
+
Extra GPIO line connected to DOUT/DRDY (Data Out/Data Ready). This allows
44
+
distinguishing between interrupts triggered by the data-ready signal and
45
+
interrupts triggered by an SPI transfer.
46
+
maxItems: 1
47
+
48
+
'#io-channel-cells':
49
+
const: 1
50
+
51
+
required:
52
+
- compatible
53
+
- reg
54
+
- vdd-supply
55
+
56
+
allOf:
57
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
58
+
59
+
unevaluatedProperties: false
60
+
61
+
examples:
62
+
- |
63
+
#include <dt-bindings/interrupt-controller/irq.h>
64
+
#include <dt-bindings/gpio/gpio.h>
65
+
66
+
spi {
67
+
#address-cells = <1>;
68
+
#size-cells = <0>;
69
+
70
+
adc@0 {
71
+
compatible = "ti,ads1118";
72
+
reg = <0>;
73
+
74
+
spi-max-frequency = <4000000>;
75
+
spi-cpha;
76
+
77
+
vdd-supply = <&vdd_3v3_reg>;
78
+
79
+
interrupts-extended = <&gpio 14 IRQ_TYPE_EDGE_FALLING>;
80
+
drdy-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
81
+
};
82
+
};
+208
Documentation/devicetree/bindings/iio/adc/ti,ads131m02.yaml
+208
Documentation/devicetree/bindings/iio/adc/ti,ads131m02.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/adc/ti,ads131m02.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments ADS131M0x 2-, 3-, 4-, 6- and 8-Channel ADCs
8
+
9
+
maintainers:
10
+
- Oleksij Rempel <o.rempel@pengutronix.de>
11
+
12
+
description: |
13
+
The ADS131M0x are a family of multichannel, simultaneous sampling,
14
+
24-bit, delta-sigma, analog-to-digital converters (ADCs) with a
15
+
built-in programmable gain amplifier (PGA) and internal reference.
16
+
Communication with the ADC chip is via SPI.
17
+
18
+
Datasheets:
19
+
- ADS131M02: https://www.ti.com/lit/ds/symlink/ads131m02.pdf
20
+
- ADS131M03: https://www.ti.com/lit/ds/symlink/ads131m03.pdf
21
+
- ADS131M04: https://www.ti.com/lit/ds/symlink/ads131m04.pdf
22
+
- ADS131M06: https://www.ti.com/lit/ds/symlink/ads131m06.pdf
23
+
- ADS131M08: https://www.ti.com/lit/ds/symlink/ads131m08.pdf
24
+
25
+
properties:
26
+
compatible:
27
+
enum:
28
+
- ti,ads131m02
29
+
- ti,ads131m03
30
+
- ti,ads131m04
31
+
- ti,ads131m06
32
+
- ti,ads131m08
33
+
34
+
reg:
35
+
description: SPI chip select number.
36
+
37
+
clocks:
38
+
description:
39
+
Phandle to the external clock source required by the ADC's CLKIN pin.
40
+
The datasheet recommends specific frequencies based on the desired power
41
+
mode (e.g., 8.192 MHz for High-Resolution mode).
42
+
maxItems: 1
43
+
44
+
avdd-supply:
45
+
description: Analog power supply (AVDD).
46
+
47
+
dvdd-supply:
48
+
description: Digital power supply (DVDD).
49
+
50
+
interrupts:
51
+
description: DRDY (Data Ready) output signal.
52
+
maxItems: 1
53
+
54
+
reset-gpios:
55
+
description: Optional RESET signal.
56
+
maxItems: 1
57
+
58
+
clock-names:
59
+
description:
60
+
Indicates if a crystal oscillator (XTAL) or CMOS signal is connected
61
+
(CLKIN). Note that XTAL mode is only supported on ADS131M06 and ADS131M08.
62
+
enum: [xtal, clkin]
63
+
64
+
refin-supply:
65
+
description: Optional external reference supply (REFIN).
66
+
67
+
'#address-cells':
68
+
const: 1
69
+
70
+
'#size-cells':
71
+
const: 0
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
- clocks
77
+
- clock-names
78
+
- avdd-supply
79
+
- dvdd-supply
80
+
81
+
patternProperties:
82
+
"^channel@[0-7]$":
83
+
type: object
84
+
$ref: /schemas/iio/adc/adc.yaml#
85
+
description: Properties for a single ADC channel.
86
+
87
+
properties:
88
+
reg:
89
+
description: The channel index (0-7).
90
+
minimum: 0
91
+
maximum: 7 # Max channels on ADS131M08
92
+
93
+
label: true
94
+
95
+
required:
96
+
- reg
97
+
98
+
unevaluatedProperties: false
99
+
100
+
allOf:
101
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
102
+
103
+
- if:
104
+
# 20-pin devices: M02, M03, M04
105
+
# These do not support XTAL or REFIN.
106
+
properties:
107
+
compatible:
108
+
enum:
109
+
- ti,ads131m02
110
+
- ti,ads131m03
111
+
- ti,ads131m04
112
+
then:
113
+
properties:
114
+
clock-names:
115
+
const: clkin
116
+
refin-supply: false
117
+
118
+
- if:
119
+
# ADS131M02: 2 channels max (0-1)
120
+
properties:
121
+
compatible:
122
+
contains:
123
+
const: ti,ads131m02
124
+
then:
125
+
patternProperties:
126
+
"^channel@[0-1]$":
127
+
properties:
128
+
reg:
129
+
maximum: 1
130
+
"^channel@[2-7]$": false
131
+
132
+
- if:
133
+
# ADS131M03: 3 channels max (0-2)
134
+
properties:
135
+
compatible:
136
+
contains:
137
+
const: ti,ads131m03
138
+
then:
139
+
patternProperties:
140
+
"^channel@[0-2]$":
141
+
properties:
142
+
reg:
143
+
maximum: 2
144
+
"^channel@[3-7]$": false
145
+
146
+
- if:
147
+
# ADS131M04: 4 channels max (0-3)
148
+
properties:
149
+
compatible:
150
+
contains:
151
+
const: ti,ads131m04
152
+
then:
153
+
patternProperties:
154
+
"^channel@[0-3]$":
155
+
properties:
156
+
reg:
157
+
maximum: 3
158
+
"^channel@[4-7]$": false
159
+
160
+
- if:
161
+
# ADS131M06: 6 channels max (0-5)
162
+
properties:
163
+
compatible:
164
+
contains:
165
+
const: ti,ads131m06
166
+
then:
167
+
patternProperties:
168
+
"^channel@[0-5]$":
169
+
properties:
170
+
reg:
171
+
maximum: 5
172
+
"^channel@[6-7]$": false
173
+
174
+
unevaluatedProperties: false
175
+
176
+
examples:
177
+
- |
178
+
#include <dt-bindings/clock/stm32mp1-clks.h>
179
+
180
+
spi1 {
181
+
#address-cells = <1>;
182
+
#size-cells = <0>;
183
+
184
+
adc@0 {
185
+
compatible = "ti,ads131m02";
186
+
reg = <0>;
187
+
spi-max-frequency = <8000000>;
188
+
189
+
clocks = <&rcc CK_MCO2>;
190
+
clock-names = "clkin";
191
+
192
+
avdd-supply = <&vdd_ana>;
193
+
dvdd-supply = <&vdd_dig>;
194
+
195
+
#address-cells = <1>;
196
+
#size-cells = <0>;
197
+
198
+
channel@0 {
199
+
reg = <0>;
200
+
label = "input_voltage";
201
+
};
202
+
203
+
channel@1 {
204
+
reg = <1>;
205
+
label = "input_current";
206
+
};
207
+
};
208
+
};
+87
Documentation/devicetree/bindings/iio/amplifiers/adi,adl8113.yaml
+87
Documentation/devicetree/bindings/iio/amplifiers/adi,adl8113.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/amplifiers/adi,adl8113.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Analog Devices ADL8113 Low Noise Amplifier with integrated bypass switches
8
+
9
+
maintainers:
10
+
- Antoniu Miclaus <antoniu.miclaus@analog.com>
11
+
12
+
description: |
13
+
The ADL8113 is a 10MHz to 12GHz Low Noise Amplifier with integrated bypass
14
+
switches controlled by two GPIO pins (VA and VB). The device supports four
15
+
operation modes:
16
+
- Internal Amplifier: VA=0, VB=0 - Signal passes through the internal LNA
17
+
- Internal Bypass: VA=1, VB=1 - Signal bypasses through internal path
18
+
- External Bypass A: VA=0, VB=1 - Signal routes from RFIN to OUT_A and from IN_A to RFOUT
19
+
- External Bypass B: VA=1, VB=0 - Signal routes from RFIN to OUT_B and from IN_B to RFOUT
20
+
21
+
https://www.analog.com/en/products/adl8113.html
22
+
23
+
properties:
24
+
compatible:
25
+
const: adi,adl8113
26
+
27
+
vdd1-supply: true
28
+
29
+
vdd2-supply: true
30
+
31
+
vss2-supply: true
32
+
33
+
ctrl-gpios:
34
+
items:
35
+
- description: VA control pin
36
+
- description: VB control pin
37
+
38
+
adi,external-bypass-a-gain-db:
39
+
description:
40
+
Gain in dB of external amplifier connected to bypass path A (OUT_A/IN_A).
41
+
When specified, this gain value becomes selectable via the hardwaregain
42
+
attribute and automatically routes through the external A path.
43
+
44
+
adi,external-bypass-b-gain-db:
45
+
description:
46
+
Gain in dB of external amplifier connected to bypass path B (OUT_B/IN_B).
47
+
When specified, this gain value becomes selectable via the hardwaregain
48
+
attribute and automatically routes through the external B path.
49
+
50
+
required:
51
+
- compatible
52
+
- ctrl-gpios
53
+
- vdd1-supply
54
+
- vdd2-supply
55
+
- vss2-supply
56
+
57
+
additionalProperties: false
58
+
59
+
examples:
60
+
- |
61
+
#include <dt-bindings/gpio/gpio.h>
62
+
63
+
/* Basic configuration with only internal paths */
64
+
amplifier {
65
+
compatible = "adi,adl8113";
66
+
ctrl-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>,
67
+
<&gpio 23 GPIO_ACTIVE_HIGH>;
68
+
vdd1-supply = <&vdd1_5v>;
69
+
vdd2-supply = <&vdd2_3v3>;
70
+
vss2-supply = <&vss2_neg>;
71
+
};
72
+
73
+
- |
74
+
#include <dt-bindings/gpio/gpio.h>
75
+
76
+
/* Configuration with external bypass amplifiers */
77
+
amplifier {
78
+
compatible = "adi,adl8113";
79
+
ctrl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>,
80
+
<&gpio 25 GPIO_ACTIVE_HIGH>;
81
+
vdd1-supply = <&vdd1_5v>;
82
+
vdd2-supply = <&vdd2_3v3>;
83
+
vss2-supply = <&vss2_neg>;
84
+
adi,external-bypass-a-gain-db = <20>; /* 20dB external amp on path A */
85
+
adi,external-bypass-b-gain-db = <6>; /* 6dB external amp on path B */
86
+
};
87
+
...
+120
Documentation/devicetree/bindings/iio/dac/adi,max22007.yaml
+120
Documentation/devicetree/bindings/iio/dac/adi,max22007.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/dac/adi,max22007.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Analog Devices MAX22007 DAC
8
+
9
+
maintainers:
10
+
- Janani Sunil <janani.sunil@analog.com>
11
+
12
+
description:
13
+
The MAX22007 is a quad-channel, 12-bit digital-to-analog converter (DAC)
14
+
with integrated precision output amplifiers and current output capability.
15
+
Each channel can be independently configured for voltage or current output.
16
+
Datasheet available at https://www.analog.com/en/products/max22007.html
17
+
18
+
$ref: /schemas/spi/spi-peripheral-props.yaml#
19
+
20
+
properties:
21
+
compatible:
22
+
const: adi,max22007
23
+
24
+
reg:
25
+
maxItems: 1
26
+
27
+
spi-max-frequency:
28
+
maximum: 500000
29
+
30
+
'#address-cells':
31
+
const: 1
32
+
33
+
'#size-cells':
34
+
const: 0
35
+
36
+
vdd-supply:
37
+
description: Low-Voltage Power Supply from +2.7V to +5.5V.
38
+
39
+
hvdd-supply:
40
+
description:
41
+
Positive High-Voltage Power Supply from +8V to (HVSS +24V) for
42
+
the Output Channels.
43
+
44
+
hvss-supply:
45
+
description:
46
+
Optional Negative High-Voltage Power Supply from -2V to 0V for the Output
47
+
Channels. For most applications HVSS can be connected to GND (0V), but for
48
+
applications requiring output down to true 0V or 0mA, connect to a -2V supply.
49
+
50
+
reset-gpios:
51
+
maxItems: 1
52
+
description:
53
+
Active low GPIO.
54
+
55
+
patternProperties:
56
+
"^channel@[0-3]$":
57
+
$ref: /schemas/iio/dac/dac.yaml#
58
+
type: object
59
+
description:
60
+
Represents the external channels which are connected to the DAC.
61
+
62
+
properties:
63
+
reg:
64
+
description: Channel number
65
+
items:
66
+
minimum: 0
67
+
maximum: 3
68
+
69
+
adi,ch-func:
70
+
description:
71
+
Channel output type. Use CH_FUNC_VOLTAGE_OUTPUT for voltage
72
+
output or CH_FUNC_CURRENT_OUTPUT for current output.
73
+
$ref: /schemas/types.yaml#/definitions/uint32
74
+
enum: [1, 2]
75
+
76
+
required:
77
+
- reg
78
+
- adi,ch-func
79
+
80
+
unevaluatedProperties: false
81
+
82
+
required:
83
+
- compatible
84
+
- reg
85
+
- vdd-supply
86
+
- hvdd-supply
87
+
88
+
unevaluatedProperties: false
89
+
90
+
examples:
91
+
- |
92
+
#include <dt-bindings/gpio/gpio.h>
93
+
#include <dt-bindings/iio/addac/adi,ad74413r.h>
94
+
95
+
spi {
96
+
#address-cells = <1>;
97
+
#size-cells = <0>;
98
+
99
+
dac@0 {
100
+
compatible = "adi,max22007";
101
+
reg = <0>;
102
+
spi-max-frequency = <500000>;
103
+
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
104
+
vdd-supply = <&vdd_reg>;
105
+
hvdd-supply = <&hvdd_reg>;
106
+
#address-cells = <1>;
107
+
#size-cells = <0>;
108
+
109
+
channel@0 {
110
+
reg = <0>;
111
+
adi,ch-func = <CH_FUNC_VOLTAGE_OUTPUT>;
112
+
};
113
+
114
+
channel@1 {
115
+
reg = <1>;
116
+
adi,ch-func = <CH_FUNC_CURRENT_OUTPUT>;
117
+
};
118
+
};
119
+
};
120
+
...
+302
Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
+302
Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/dac/microchip,mcp47feb02.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Microchip MCP47F(E/V)B(0/1/2)(1/2/4/8) DAC with I2C Interface Families
8
+
9
+
maintainers:
10
+
- Ariana Lazar <ariana.lazar@microchip.com>
11
+
12
+
description: |
13
+
Datasheet for MCP47FEB01, MCP47FEB11, MCP47FEB21, MCP47FEB02, MCP47FEB12,
14
+
MCP47FEB22 can be found here:
15
+
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005375A.pdf
16
+
Datasheet for MCP47FVB01, MCP47FVB11, MCP47FVB21, MCP47FVB02, MCP47FVB12,
17
+
MCP47FVB22 can be found here:
18
+
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005405A.pdf
19
+
Datasheet for MCP47FEB04, MCP47FEB14, MCP47FEB24, MCP47FEB08, MCP47FEB18,
20
+
MCP47FEB28, MCP47FVB04, MCP47FVB14, MCP47FVB24, MCP47FVB08, MCP47FVB18,
21
+
MCP47FVB28 can be found here:
22
+
https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf
23
+
24
+
+------------+--------------+-------------+-------------+------------+
25
+
| Device | Resolution | Channels | Vref number | Memory |
26
+
|------------|--------------|-------------|-------------|------------|
27
+
| MCP47FEB01 | 8-bit | 1 | 1 | EEPROM |
28
+
| MCP47FEB11 | 10-bit | 1 | 1 | EEPROM |
29
+
| MCP47FEB21 | 12-bit | 1 | 1 | EEPROM |
30
+
|------------|--------------|-------------|-------------|------------|
31
+
| MCP47FEB02 | 8-bit | 2 | 1 | EEPROM |
32
+
| MCP47FEB12 | 10-bit | 2 | 1 | EEPROM |
33
+
| MCP47FEB22 | 12-bit | 2 | 1 | EEPROM |
34
+
|------------|--------------|-------------|-------------|------------|
35
+
| MCP47FVB01 | 8-bit | 1 | 1 | RAM |
36
+
| MCP47FVB11 | 10-bit | 1 | 1 | RAM |
37
+
| MCP47FVB21 | 12-bit | 1 | 1 | RAM |
38
+
|------------|--------------|-------------|-------------|------------|
39
+
| MCP47FVB02 | 8-bit | 2 | 1 | RAM |
40
+
| MCP47FVB12 | 10-bit | 2 | 1 | RAM |
41
+
| MCP47FVB22 | 12-bit | 2 | 1 | RAM |
42
+
|------------|--------------|-------------|-------------|------------|
43
+
| MCP47FVB04 | 8-bit | 4 | 2 | RAM |
44
+
| MCP47FVB14 | 10-bit | 4 | 2 | RAM |
45
+
| MCP47FVB24 | 12-bit | 4 | 2 | RAM |
46
+
|------------|--------------|-------------|-------------|------------|
47
+
| MCP47FVB08 | 8-bit | 8 | 2 | RAM |
48
+
| MCP47FVB18 | 10-bit | 8 | 2 | RAM |
49
+
| MCP47FVB28 | 12-bit | 8 | 2 | RAM |
50
+
|------------|--------------|-------------|-------------|------------|
51
+
| MCP47FEB04 | 8-bit | 4 | 2 | EEPROM |
52
+
| MCP47FEB14 | 10-bit | 4 | 2 | EEPROM |
53
+
| MCP47FEB24 | 12-bit | 4 | 2 | EEPROM |
54
+
|------------|--------------|-------------|-------------|------------|
55
+
| MCP47FEB08 | 8-bit | 8 | 2 | EEPROM |
56
+
| MCP47FEB18 | 10-bit | 8 | 2 | EEPROM |
57
+
| MCP47FEB28 | 12-bit | 8 | 2 | EEPROM |
58
+
+------------+--------------+-------------+-------------+------------+
59
+
60
+
properties:
61
+
compatible:
62
+
enum:
63
+
- microchip,mcp47feb01
64
+
- microchip,mcp47feb11
65
+
- microchip,mcp47feb21
66
+
- microchip,mcp47feb02
67
+
- microchip,mcp47feb12
68
+
- microchip,mcp47feb22
69
+
- microchip,mcp47fvb01
70
+
- microchip,mcp47fvb11
71
+
- microchip,mcp47fvb21
72
+
- microchip,mcp47fvb02
73
+
- microchip,mcp47fvb12
74
+
- microchip,mcp47fvb22
75
+
- microchip,mcp47fvb04
76
+
- microchip,mcp47fvb14
77
+
- microchip,mcp47fvb24
78
+
- microchip,mcp47fvb08
79
+
- microchip,mcp47fvb18
80
+
- microchip,mcp47fvb28
81
+
- microchip,mcp47feb04
82
+
- microchip,mcp47feb14
83
+
- microchip,mcp47feb24
84
+
- microchip,mcp47feb08
85
+
- microchip,mcp47feb18
86
+
- microchip,mcp47feb28
87
+
88
+
reg:
89
+
maxItems: 1
90
+
91
+
"#address-cells":
92
+
const: 1
93
+
94
+
"#size-cells":
95
+
const: 0
96
+
97
+
vdd-supply:
98
+
description:
99
+
Provides power to the chip and it could be used as reference voltage. The
100
+
voltage is used to calculate scale. For parts without EEPROM at powerup
101
+
this will be the selected as voltage reference.
102
+
103
+
vref-supply:
104
+
description: |
105
+
Vref pin (it could be found as Vref0 into the datasheet) may be used as a
106
+
voltage reference when this supply is specified. The internal reference
107
+
will be taken into account for voltage reference besides VDD if this supply
108
+
does not exist.
109
+
110
+
This supply will be voltage reference for the following outputs:
111
+
- for single-channel device: Vout0;
112
+
- for dual-channel device: Vout0, Vout1;
113
+
- for quad-channel device: Vout0, Vout2;
114
+
- for octal-channel device: Vout0, Vout2, Vout6, Vout8;
115
+
116
+
vref1-supply:
117
+
description: |
118
+
Vref1 pin may be used as a voltage reference when this supply is specified.
119
+
The internal reference will be taken into account for voltage reference
120
+
beside VDD if this supply does not exist.
121
+
122
+
This supply will be voltage reference for the following outputs:
123
+
- for quad-channel device: Vout1, Vout3;
124
+
- for octal-channel device: Vout1, Vout3, Vout5, Vout7;
125
+
126
+
lat-gpios:
127
+
description:
128
+
LAT pin to be used as a hardware trigger to synchronously update the DAC
129
+
channels. The pin is active Low. It could be also found as LAT0 in
130
+
datasheet.
131
+
maxItems: 1
132
+
133
+
lat1-gpios:
134
+
description:
135
+
LAT1 pin to be used as a hardware trigger to synchronously update the odd
136
+
DAC channels on devices with 4 and 8 channels. The pin is active Low.
137
+
maxItems: 1
138
+
139
+
microchip,vref-buffered:
140
+
type: boolean
141
+
description:
142
+
Enable buffering of the external Vref/Vref0 pin in cases where the
143
+
external reference voltage does not have sufficient current capability in
144
+
order not to drop it’s voltage when connected to the internal resistor
145
+
ladder circuit.
146
+
147
+
microchip,vref1-buffered:
148
+
type: boolean
149
+
description:
150
+
Enable buffering of the external Vref1 pin in cases where the external
151
+
reference voltage does not have sufficient current capability in order not
152
+
to drop it’s voltage when connected to the internal resistor ladder
153
+
circuit.
154
+
155
+
patternProperties:
156
+
"^channel@[0-7]$":
157
+
$ref: dac.yaml
158
+
type: object
159
+
description: Voltage output channel.
160
+
161
+
properties:
162
+
reg:
163
+
description: The channel number.
164
+
minItems: 1
165
+
maxItems: 8
166
+
167
+
label:
168
+
description: Unique name to identify which channel this is.
169
+
170
+
required:
171
+
- reg
172
+
173
+
unevaluatedProperties: false
174
+
175
+
required:
176
+
- compatible
177
+
- reg
178
+
- vdd-supply
179
+
180
+
allOf:
181
+
- if:
182
+
properties:
183
+
compatible:
184
+
contains:
185
+
enum:
186
+
- microchip,mcp47feb01
187
+
- microchip,mcp47feb11
188
+
- microchip,mcp47feb21
189
+
- microchip,mcp47fvb01
190
+
- microchip,mcp47fvb11
191
+
- microchip,mcp47fvb21
192
+
then:
193
+
properties:
194
+
lat1-gpios: false
195
+
vref1-supply: false
196
+
microchip,vref1-buffered: false
197
+
channel@0:
198
+
properties:
199
+
reg:
200
+
const: 0
201
+
patternProperties:
202
+
"^channel@[1-7]$": false
203
+
- if:
204
+
properties:
205
+
compatible:
206
+
contains:
207
+
enum:
208
+
- microchip,mcp47feb02
209
+
- microchip,mcp47feb12
210
+
- microchip,mcp47feb22
211
+
- microchip,mcp47fvb02
212
+
- microchip,mcp47fvb12
213
+
- microchip,mcp47fvb22
214
+
then:
215
+
properties:
216
+
lat1-gpios: false
217
+
vref1-supply: false
218
+
microchip,vref1-buffered: false
219
+
patternProperties:
220
+
"^channel@[0-1]$":
221
+
properties:
222
+
reg:
223
+
enum: [0, 1]
224
+
"^channel@[2-7]$": false
225
+
- if:
226
+
properties:
227
+
compatible:
228
+
contains:
229
+
enum:
230
+
- microchip,mcp47fvb04
231
+
- microchip,mcp47fvb14
232
+
- microchip,mcp47fvb24
233
+
- microchip,mcp47feb04
234
+
- microchip,mcp47feb14
235
+
- microchip,mcp47feb24
236
+
then:
237
+
patternProperties:
238
+
"^channel@[0-3]$":
239
+
properties:
240
+
reg:
241
+
enum: [0, 1, 2, 3]
242
+
"^channel@[4-7]$": false
243
+
- if:
244
+
properties:
245
+
compatible:
246
+
contains:
247
+
enum:
248
+
- microchip,mcp47fvb08
249
+
- microchip,mcp47fvb18
250
+
- microchip,mcp47fvb28
251
+
- microchip,mcp47feb08
252
+
- microchip,mcp47feb18
253
+
- microchip,mcp47feb28
254
+
then:
255
+
patternProperties:
256
+
"^channel@[0-7]$":
257
+
properties:
258
+
reg:
259
+
enum: [0, 1, 2, 3, 4, 5, 6, 7]
260
+
- if:
261
+
not:
262
+
required:
263
+
- vref-supply
264
+
then:
265
+
properties:
266
+
microchip,vref-buffered: false
267
+
- if:
268
+
not:
269
+
required:
270
+
- vref1-supply
271
+
then:
272
+
properties:
273
+
microchip,vref1-buffered: false
274
+
275
+
additionalProperties: false
276
+
277
+
examples:
278
+
- |
279
+
i2c {
280
+
281
+
#address-cells = <1>;
282
+
#size-cells = <0>;
283
+
dac@0 {
284
+
compatible = "microchip,mcp47feb02";
285
+
reg = <0>;
286
+
vdd-supply = <&vdac_vdd>;
287
+
vref-supply = <&vref_reg>;
288
+
289
+
#address-cells = <1>;
290
+
#size-cells = <0>;
291
+
channel@0 {
292
+
reg = <0>;
293
+
label = "Adjustable_voltage_ch0";
294
+
};
295
+
296
+
channel@1 {
297
+
reg = <0x1>;
298
+
label = "Adjustable_voltage_ch1";
299
+
};
300
+
};
301
+
};
302
+
...
+8
Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
+8
Documentation/devicetree/bindings/iio/frequency/adi,adf4377.yaml
···
40
40
items:
41
41
- const: ref_in
42
42
43
+
'#clock-cells':
44
+
const: 0
45
+
46
+
clock-output-names:
47
+
maxItems: 1
48
+
43
49
chip-enable-gpios:
44
50
description:
45
51
GPIO that controls the Chip Enable Pin.
···
103
97
spi-max-frequency = <10000000>;
104
98
clocks = <&adf4377_ref_in>;
105
99
clock-names = "ref_in";
100
+
#clock-cells = <0>;
101
+
clock-output-names = "adf4377";
106
102
};
107
103
};
108
104
...
+132
Documentation/devicetree/bindings/iio/pressure/honeywell,abp2030pa.yaml
+132
Documentation/devicetree/bindings/iio/pressure/honeywell,abp2030pa.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/pressure/honeywell,abp2030pa.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Honeywell abp2030pa pressure sensor
8
+
9
+
maintainers:
10
+
- Petre Rodan <petre.rodan@subdimension.ro>
11
+
12
+
description: |
13
+
Honeywell pressure sensor of model abp2030pa.
14
+
15
+
This sensor has an I2C and SPI interface.
16
+
17
+
There are many models with different pressure ranges available. The vendor
18
+
calls them "ABP2 series". All of them have an identical programming model and
19
+
differ in the pressure range and measurement unit.
20
+
21
+
To support different models one needs to specify its pressure triplet.
22
+
23
+
For custom silicon chips not covered by the Honeywell ABP2 series datasheet,
24
+
the pressure values can be specified manually via honeywell,pmin-pascal and
25
+
honeywell,pmax-pascal.
26
+
27
+
Specifications about the devices can be found at:
28
+
https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/basic-abp2-series/documents/sps-siot-abp2-series-datasheet-32350268-en.pdf
29
+
30
+
properties:
31
+
compatible:
32
+
const: honeywell,abp2030pa
33
+
34
+
reg:
35
+
maxItems: 1
36
+
37
+
interrupts:
38
+
description:
39
+
Optional interrupt for indicating end of conversion.
40
+
SPI variants of ABP2 chips do not provide this feature.
41
+
maxItems: 1
42
+
43
+
honeywell,pressure-triplet:
44
+
description: |
45
+
Case-sensitive five character string that defines pressure range, unit
46
+
and type as part of the device nomenclature. In the unlikely case of a
47
+
custom chip, unset and provide pmin-pascal and pmax-pascal instead.
48
+
enum: [001BA, 1.6BA, 2.5BA, 004BA, 006BA, 008BA, 010BA, 012BA, 001BD,
49
+
1.6BD, 2.5BD, 004BD, 001BG, 1.6BG, 2.5BG, 004BG, 006BG, 008BG,
50
+
010BG, 012BG, 001GG, 1.2GG, 100KA, 160KA, 250KA, 001KD, 1.6KD,
51
+
2.5KD, 004KD, 006KD, 010KD, 016KD, 025KD, 040KD, 060KD, 100KD,
52
+
160KD, 250KD, 400KD, 001KG, 1.6KG, 2.5KG, 004KG, 006KG, 010KG,
53
+
016KG, 025KG, 040KG, 060KG, 100KG, 160KG, 250KG, 400KG, 600KG,
54
+
800KG, 250LD, 600LD, 600LG, 2.5MD, 006MD, 010MD, 016MD, 025MD,
55
+
040MD, 060MD, 100MD, 160MD, 250MD, 400MD, 600MD, 006MG, 010MG,
56
+
016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG, 600MG,
57
+
001ND, 002ND, 004ND, 005ND, 010ND, 020ND, 030ND, 002NG, 004NG,
58
+
005NG, 010NG, 020NG, 030NG, 015PA, 030PA, 060PA, 100PA, 150PA,
59
+
175PA, 001PD, 005PD, 015PD, 030PD, 060PD, 001PG, 005PG, 015PG,
60
+
030PG, 060PG, 100PG, 150PG, 175PG]
61
+
$ref: /schemas/types.yaml#/definitions/string
62
+
63
+
honeywell,pmin-pascal:
64
+
description:
65
+
Minimum pressure value the sensor can measure in pascal.
66
+
67
+
honeywell,pmax-pascal:
68
+
description:
69
+
Maximum pressure value the sensor can measure in pascal.
70
+
71
+
spi-max-frequency:
72
+
maximum: 800000
73
+
74
+
vdd-supply: true
75
+
76
+
required:
77
+
- compatible
78
+
- reg
79
+
- vdd-supply
80
+
81
+
oneOf:
82
+
- required:
83
+
- honeywell,pressure-triplet
84
+
- required:
85
+
- honeywell,pmin-pascal
86
+
- honeywell,pmax-pascal
87
+
88
+
allOf:
89
+
- $ref: /schemas/spi/spi-peripheral-props.yaml
90
+
- if:
91
+
required:
92
+
- honeywell,pressure-triplet
93
+
then:
94
+
properties:
95
+
honeywell,pmin-pascal: false
96
+
honeywell,pmax-pascal: false
97
+
98
+
additionalProperties: false
99
+
100
+
examples:
101
+
- |
102
+
#include <dt-bindings/gpio/gpio.h>
103
+
#include <dt-bindings/interrupt-controller/irq.h>
104
+
i2c {
105
+
#address-cells = <1>;
106
+
#size-cells = <0>;
107
+
108
+
pressure@18 {
109
+
compatible = "honeywell,abp2030pa";
110
+
reg = <0x18>;
111
+
interrupt-parent = <&gpio3>;
112
+
interrupts = <21 IRQ_TYPE_EDGE_RISING>;
113
+
114
+
honeywell,pressure-triplet = "001BA";
115
+
vdd-supply = <&vcc_3v3>;
116
+
};
117
+
};
118
+
- |
119
+
spi {
120
+
#address-cells = <1>;
121
+
#size-cells = <0>;
122
+
123
+
pressure@0 {
124
+
compatible = "honeywell,abp2030pa";
125
+
reg = <0>;
126
+
spi-max-frequency = <800000>;
127
+
128
+
honeywell,pressure-triplet = "001PD";
129
+
vdd-supply = <&vcc_3v3>;
130
+
};
131
+
};
132
+
...
+53
Documentation/devicetree/bindings/iio/proximity/rfdigital,rfd77402.yaml
+53
Documentation/devicetree/bindings/iio/proximity/rfdigital,rfd77402.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/iio/proximity/rfdigital,rfd77402.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: RF Digital RFD77402 ToF sensor
8
+
9
+
maintainers:
10
+
- Shrikant Raskar <raskar.shree97@gmail.com>
11
+
12
+
description:
13
+
The RF Digital RFD77402 is a Time-of-Flight (ToF) proximity and distance
14
+
sensor providing up to 200 mm range measurement over an I2C interface.
15
+
16
+
properties:
17
+
compatible:
18
+
const: rfdigital,rfd77402
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
maxItems: 1
25
+
description:
26
+
Interrupt asserted when a new distance measurement is available.
27
+
28
+
vdd-supply:
29
+
description: Regulator that provides power to the sensor.
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- vdd-supply
35
+
36
+
additionalProperties: false
37
+
38
+
examples:
39
+
- |
40
+
#include <dt-bindings/interrupt-controller/irq.h>
41
+
i2c {
42
+
#address-cells = <1>;
43
+
#size-cells = <0>;
44
+
45
+
proximity@4c {
46
+
compatible = "rfdigital,rfd77402";
47
+
reg = <0x4c>;
48
+
vdd-supply = <&vdd_3v3>;
49
+
interrupt-parent = <&gpio>;
50
+
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
51
+
};
52
+
};
53
+
...
+4
Documentation/devicetree/bindings/trivial-devices.yaml
+4
Documentation/devicetree/bindings/trivial-devices.yaml
···
229
229
- meas,tsys01
230
230
# MEMSIC magnetometer
231
231
- memsic,mmc35240
232
+
# MEMSIC 3-axis magnetometer
233
+
- memsic,mmc5603
234
+
# MEMSIC 3-axis magnetometer (Support I3C HDR)
235
+
- memsic,mmc5633
232
236
# MEMSIC 3-axis accelerometer
233
237
- memsic,mxc4005
234
238
# MEMSIC 2-axis 8-bit digital accelerometer
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+148
Documentation/iio/ad4062.rst
+148
Documentation/iio/ad4062.rst
···
1
+
.. SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
=============
4
+
AD4062 driver
5
+
=============
6
+
7
+
ADC driver for Analog Devices Inc. AD4060/AD4062 devices. The module name is
8
+
``ad4062``.
9
+
10
+
Supported devices
11
+
=================
12
+
13
+
The following chips are supported by this driver:
14
+
15
+
* `AD4060 <https://www.analog.com/AD4060>`_
16
+
* `AD4062 <https://www.analog.com/AD4062>`_
17
+
18
+
Wiring modes
19
+
============
20
+
21
+
The ADC is interfaced through an I3C bus, and contains two programmable GPIOs.
22
+
23
+
The ADC convert-start happens on the SDA rising edge of the I3C stop (P) bit
24
+
at the end of the read command.
25
+
26
+
The two programmable GPIOS are optional and have a role assigned if present in
27
+
the devicetree ``interrupt-names`` property:
28
+
29
+
- GP0: Is assigned the role of Threshold Either signal.
30
+
- GP1: Is assigned the role of Data Ready signal.
31
+
32
+
If the property ``gpio-controller`` is present in the devicetree, then the GPO
33
+
not present in the ``interrupt-names`` is exposed as a GPO.
34
+
35
+
Device attributes
36
+
=================
37
+
38
+
The ADC contains only one channel with following attributes:
39
+
40
+
.. list-table:: Channel attributes
41
+
:header-rows: 1
42
+
43
+
* - Attribute
44
+
- Description
45
+
* - ``in_voltage_calibscale``
46
+
- Sets the gain scaling factor that the hardware applies to the sample,
47
+
to compensate for system gain error.
48
+
* - ``in_voltage_oversampling_ratio``
49
+
- Sets device's burst averaging mode to over sample using the
50
+
internal sample rate. Value 1 disable the burst averaging mode.
51
+
* - ``in_voltage_oversampling_ratio_available``
52
+
- List of available oversampling values.
53
+
* - ``in_voltage_raw``
54
+
- Returns the raw ADC voltage value.
55
+
* - ``in_voltage_scale``
56
+
- Returns the channel scale in reference to the reference voltage
57
+
``ref-supply`` or ``vdd-supply`` if the former not present.
58
+
59
+
Also contain the following device attributes:
60
+
61
+
.. list-table:: Device attributes
62
+
:header-rows: 1
63
+
64
+
* - Attribute
65
+
- Description
66
+
* - ``sampling_frequency``
67
+
- Sets the duration of a single scan, used in the burst averaging mode.
68
+
The duration is described by ``(n_avg - 1) / fosc + tconv``, where
69
+
``n_avg`` is the oversampling ratio, ``fosc`` is the internal sample
70
+
rate and ``tconv`` is the ADC conversion time.
71
+
* - ``sampling_frequency_available``
72
+
- Lists the available sampling frequencies, computed on the current
73
+
oversampling ratio. If the ratio is 1, the frequency is ``1/tconv``.
74
+
75
+
Interrupts
76
+
==========
77
+
78
+
The interrupts are mapped through the ``interrupt-names`` and ``interrupts``
79
+
properties.
80
+
81
+
The ``interrupt-names`` ``gp0`` entry sets the role of Threshold signal, and
82
+
entry ``gp1`` the role of Data Ready signal.
83
+
84
+
If each is not present, the driver fallback to enabling the same role as an
85
+
I3C IBI.
86
+
87
+
Low-power mode
88
+
==============
89
+
90
+
The device enters low-power mode on idle to save power. Enabling an event puts
91
+
the device out of the low-power since the ADC autonomously samples to assert
92
+
the event condition.
93
+
94
+
IIO trigger support
95
+
===================
96
+
97
+
An IIO trigger ``ad4062-devX`` is registered by the driver to be used by the
98
+
same device, to capture samples to a software buffer. It is required to attach
99
+
the trigger to the device by setting the ``current_trigger`` before enabling
100
+
and reading the buffer.
101
+
102
+
The acquisition is sequential and bounded by the protocol timings, software
103
+
latency and internal timings, the sample rate is not configurable. The burst
104
+
averaging mode does impact the effective sample rate, since it increases the
105
+
internal timing to output a single sample.
106
+
107
+
Threshold events
108
+
================
109
+
110
+
The ADC supports a monitoring mode to raise threshold events. The driver
111
+
supports a single interrupt for both rising and falling readings.
112
+
113
+
The feature is enabled/disabled by setting ``thresh_either_en``. During monitor
114
+
mode, the device continuously operates in autonomous mode. Any register access
115
+
puts the device back in configuration mode, due to this, any access disables
116
+
monitor mode.
117
+
118
+
The following event attributes are available:
119
+
120
+
.. list-table:: Event attributes
121
+
:header-rows: 1
122
+
123
+
* - Attribute
124
+
- Description
125
+
* - ``sampling_frequency``
126
+
- Frequency used in the monitoring mode, sets the device internal sample
127
+
rate when the mode is activated.
128
+
* - ``sampling_frequency_available``
129
+
- List of available sample rates.
130
+
* - ``thresh_either_en``
131
+
- Enable monitoring mode.
132
+
* - ``thresh_falling_hysteresis``
133
+
- Set the hysteresis value for the minimum threshold.
134
+
* - ``thresh_falling_value``
135
+
- Set the minimum threshold value.
136
+
* - ``thresh_rising_hysteresis``
137
+
- Set the hysteresis value for the maximum threshold.
138
+
* - ``thresh_rising_value``
139
+
- Set the maximum threshold value.
140
+
141
+
GPO controller support
142
+
======================
143
+
144
+
The device supports using GP0 and GP1 as GPOs. If the devicetree contains the
145
+
node ``gpio-controller```, the device is marked as a GPIO controller and the
146
+
GPs not listed in ``interrupt-names`` are exposed as a GPO. The GPIO index
147
+
matches the pin name, so if GP0 is not exposed but GP1 is, index 0 is masked
148
+
out and only index 1 can be set.
+1
Documentation/iio/index.rst
+1
Documentation/iio/index.rst
+53
MAINTAINERS
+53
MAINTAINERS
···
1435
1435
F: Documentation/iio/ad4030.rst
1436
1436
F: drivers/iio/adc/ad4030.c
1437
1437
1438
+
ANALOG DEVICES INC AD4062 DRIVER
1439
+
M: Jorge Marques <jorge.marques@analog.com>
1440
+
S: Supported
1441
+
W: https://ez.analog.com/linux-software-drivers
1442
+
F: Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml
1443
+
F: Documentation/iio/ad4062.rst
1444
+
F: drivers/iio/adc/ad4062.c
1445
+
1438
1446
ANALOG DEVICES INC AD4080 DRIVER
1439
1447
M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1440
1448
L: linux-iio@vger.kernel.org
···
1459
1451
F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130
1460
1452
F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml
1461
1453
F: drivers/iio/adc/ad4130.c
1454
+
1455
+
ANALOG DEVICES INC AD4134 DRIVER
1456
+
M: Marcelo Schmitt <marcelo.schmitt@analog.com>
1457
+
L: linux-iio@vger.kernel.org
1458
+
S: Supported
1459
+
W: https://ez.analog.com/linux-software-drivers
1460
+
F: Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml
1461
+
F: drivers/iio/adc/ad4134.c
1462
1462
1463
1463
ANALOG DEVICES INC AD4170-4 DRIVER
1464
1464
M: Marcelo Schmitt <marcelo.schmitt@analog.com>
···
1612
1596
F: Documentation/devicetree/bindings/iio/dac/adi,ad9739a.yaml
1613
1597
F: drivers/iio/dac/ad9739a.c
1614
1598
1599
+
ANALOG DEVICES INC MAX22007 DRIVER
1600
+
M: Janani Sunil <janani.sunil@analog.com>
1601
+
L: linux-iio@vger.kernel.org
1602
+
S: Supported
1603
+
W: https://ez.analog.com/linux-software-drivers
1604
+
F: Documentation/devicetree/bindings/iio/dac/adi,max22007.yaml
1605
+
F: drivers/iio/dac/max22007.c
1606
+
1615
1607
ANALOG DEVICES INC ADA4250 DRIVER
1616
1608
M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1617
1609
L: linux-iio@vger.kernel.org
···
1627
1603
W: https://ez.analog.com/linux-software-drivers
1628
1604
F: Documentation/devicetree/bindings/iio/amplifiers/adi,ada4250.yaml
1629
1605
F: drivers/iio/amplifiers/ada4250.c
1606
+
1607
+
ANALOG DEVICES INC ADE9000 DRIVER
1608
+
M: Antoniu Miclaus <antoniu.miclaus@analog.com>
1609
+
L: linux-iio@vger.kernel.org
1610
+
S: Supported
1611
+
W: https://ez.analog.com/linux-software-drivers
1612
+
F: Documentation/devicetree/bindings/iio/adc/adi,ade9000.yaml
1613
+
F: drivers/iio/adc/ade9000.c
1630
1614
1631
1615
ANALOG DEVICES INC ADF4377 DRIVER
1632
1616
M: Antoniu Miclaus <antoniu.miclaus@analog.com>
···
11547
11515
F: mm/hmm*
11548
11516
F: tools/testing/selftests/mm/*hmm*
11549
11517
11518
+
HONEYWELL ABP2030PA PRESSURE SENSOR SERIES IIO DRIVER
11519
+
M: Petre Rodan <petre.rodan@subdimension.ro>
11520
+
L: linux-iio@vger.kernel.org
11521
+
S: Maintained
11522
+
F: Documentation/devicetree/bindings/iio/pressure/honeywell,abp2030pa.yaml
11523
+
F: drivers/iio/pressure/abp2030pa*
11524
+
11550
11525
HONEYWELL HSC030PA PRESSURE SENSOR SERIES IIO DRIVER
11551
11526
M: Petre Rodan <petre.rodan@subdimension.ro>
11552
11527
L: linux-iio@vger.kernel.org
···
15701
15662
F: Documentation/ABI/testing/sysfs-bus-iio-potentiometer-mcp4531
15702
15663
F: drivers/iio/potentiometer/mcp4018.c
15703
15664
F: drivers/iio/potentiometer/mcp4531.c
15665
+
15666
+
MCP47FEB02 MICROCHIP DAC DRIVER
15667
+
M: Ariana Lazar <ariana.lazar@microchip.com>
15668
+
L: linux-iio@vger.kernel.org
15669
+
S: Supported
15670
+
F: Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml
15671
+
F: drivers/iio/dac/mcp47feb02.c
15704
15672
15705
15673
MCP4821 DAC DRIVER
15706
15674
M: Anshul Dalal <anshulusr@gmail.com>
···
26076
26030
S: Maintained
26077
26031
F: Documentation/devicetree/bindings/iio/adc/ti,ads1119.yaml
26078
26032
F: drivers/iio/adc/ti-ads1119.c
26033
+
26034
+
TI ADS1018 ADC DRIVER
26035
+
M: Kurt Borja <kuurtb@gmail.com>
26036
+
L: linux-iio@vger.kernel.org
26037
+
S: Maintained
26038
+
F: Documentation/devicetree/bindings/iio/adc/ti,ads1018.yaml
26039
+
F: drivers/iio/adc/ti-ads1018.c
26079
26040
26080
26041
TI ADS7924 ADC DRIVER
26081
26042
M: Hugo Villeneuve <hvilleneuve@dimonoff.com>
+41
-5
drivers/i3c/master.c
+41
-5
drivers/i3c/master.c
···
683
683
684
684
static DEVICE_ATTR_RW(hotjoin);
685
685
686
+
static ssize_t dev_nack_retry_count_show(struct device *dev,
687
+
struct device_attribute *attr, char *buf)
688
+
{
689
+
return sysfs_emit(buf, "%u\n", dev_to_i3cmaster(dev)->dev_nack_retry_count);
690
+
}
691
+
692
+
static ssize_t dev_nack_retry_count_store(struct device *dev,
693
+
struct device_attribute *attr,
694
+
const char *buf, size_t count)
695
+
{
696
+
struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
697
+
struct i3c_master_controller *master = dev_to_i3cmaster(dev);
698
+
unsigned long val;
699
+
int ret;
700
+
701
+
ret = kstrtoul(buf, 0, &val);
702
+
if (ret)
703
+
return ret;
704
+
705
+
i3c_bus_maintenance_lock(i3cbus);
706
+
ret = master->ops->set_dev_nack_retry(master, val);
707
+
i3c_bus_maintenance_unlock(i3cbus);
708
+
709
+
if (ret)
710
+
return ret;
711
+
712
+
master->dev_nack_retry_count = val;
713
+
714
+
return count;
715
+
}
716
+
717
+
static DEVICE_ATTR_RW(dev_nack_retry_count);
718
+
686
719
static struct attribute *i3c_masterdev_attrs[] = {
687
720
&dev_attr_mode.attr,
688
721
&dev_attr_current_master.attr,
···
2403
2370
{
2404
2371
struct device *dev = &master->dev;
2405
2372
struct device_node *i3cbus_np = dev->of_node;
2406
-
struct device_node *node;
2407
2373
int ret;
2408
2374
u32 val;
2409
2375
2410
2376
if (!i3cbus_np)
2411
2377
return 0;
2412
2378
2413
-
for_each_available_child_of_node(i3cbus_np, node) {
2379
+
for_each_available_child_of_node_scoped(i3cbus_np, node) {
2414
2380
ret = of_i3c_master_add_dev(master, node);
2415
-
if (ret) {
2416
-
of_node_put(node);
2381
+
if (ret)
2417
2382
return ret;
2418
-
}
2419
2383
}
2420
2384
2421
2385
/*
···
2989
2959
i3c_master_register_new_i3c_devs(master);
2990
2960
i3c_bus_normaluse_unlock(&master->bus);
2991
2961
2962
+
if (master->ops->set_dev_nack_retry)
2963
+
device_create_file(&master->dev, &dev_attr_dev_nack_retry_count);
2964
+
2992
2965
return 0;
2993
2966
2994
2967
err_del_dev:
···
3016
2983
void i3c_master_unregister(struct i3c_master_controller *master)
3017
2984
{
3018
2985
i3c_bus_notify(&master->bus, I3C_NOTIFY_BUS_REMOVE);
2986
+
2987
+
if (master->ops->set_dev_nack_retry)
2988
+
device_remove_file(&master->dev, &dev_attr_dev_nack_retry_count);
3019
2989
3020
2990
i3c_master_i2c_adapter_cleanup(master);
3021
2991
i3c_master_unregister_i3c_devs(master);
+53
-6
drivers/i3c/master/dw-i3c-master.c
+53
-6
drivers/i3c/master/dw-i3c-master.c
···
5
5
* Author: Vitor Soares <vitor.soares@synopsys.com>
6
6
*/
7
7
8
+
#include <linux/bitfield.h>
8
9
#include <linux/bitops.h>
9
10
#include <linux/clk.h>
10
11
#include <linux/completion.h>
···
205
204
#define EXTENDED_CAPABILITY 0xe8
206
205
#define SLAVE_CONFIG 0xec
207
206
207
+
#define DW_I3C_DEV_NACK_RETRY_CNT_MAX 0x3
208
+
#define DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK GENMASK(30, 29)
209
+
#define DEV_ADDR_TABLE_DYNAMIC_MASK GENMASK(23, 16)
210
+
#define DEV_ADDR_TABLE_STATIC_MASK GENMASK(6, 0)
208
211
#define DEV_ADDR_TABLE_IBI_MDB BIT(12)
209
212
#define DEV_ADDR_TABLE_SIR_REJECT BIT(13)
213
+
#define DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(x) \
214
+
FIELD_PREP(DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK, (x))
210
215
#define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
211
-
#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16))
212
-
#define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0))
216
+
#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_DYNAMIC_MASK, x)
217
+
#define DEV_ADDR_TABLE_STATIC_ADDR(x) FIELD_PREP(DEV_ADDR_TABLE_STATIC_MASK, x)
213
218
#define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2))
214
219
215
220
#define I3C_BUS_SDR1_SCL_RATE 8000000
···
1496
1489
return IRQ_HANDLED;
1497
1490
}
1498
1491
1492
+
static int dw_i3c_master_set_dev_nack_retry(struct i3c_master_controller *m,
1493
+
unsigned long dev_nack_retry_cnt)
1494
+
{
1495
+
struct dw_i3c_master *master = to_dw_i3c_master(m);
1496
+
u32 reg;
1497
+
int i;
1498
+
1499
+
if (dev_nack_retry_cnt > DW_I3C_DEV_NACK_RETRY_CNT_MAX) {
1500
+
dev_err(&master->base.dev,
1501
+
"Value %ld exceeds maximum %d\n",
1502
+
dev_nack_retry_cnt, DW_I3C_DEV_NACK_RETRY_CNT_MAX);
1503
+
return -ERANGE;
1504
+
}
1505
+
1506
+
/*
1507
+
* Update DAT entries for all currently attached devices.
1508
+
* We directly iterate through the master's device array.
1509
+
*/
1510
+
for (i = 0; i < master->maxdevs; i++) {
1511
+
/* Skip free/empty slots */
1512
+
if (master->free_pos & BIT(i))
1513
+
continue;
1514
+
1515
+
reg = readl(master->regs +
1516
+
DEV_ADDR_TABLE_LOC(master->datstartaddr, i));
1517
+
reg &= ~DEV_ADDR_TABLE_DEV_NACK_RETRY_MASK;
1518
+
reg |= DEV_ADDR_TABLE_DEV_NACK_RETRY_CNT(dev_nack_retry_cnt);
1519
+
writel(reg, master->regs +
1520
+
DEV_ADDR_TABLE_LOC(master->datstartaddr, i));
1521
+
}
1522
+
1523
+
return 0;
1524
+
}
1525
+
1499
1526
static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
1500
1527
.bus_init = dw_i3c_master_bus_init,
1501
1528
.bus_cleanup = dw_i3c_master_bus_cleanup,
···
1550
1509
.recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot,
1551
1510
.enable_hotjoin = dw_i3c_master_enable_hotjoin,
1552
1511
.disable_hotjoin = dw_i3c_master_disable_hotjoin,
1512
+
.set_dev_nack_retry = dw_i3c_master_set_dev_nack_retry,
1553
1513
};
1554
1514
1555
1515
/* default platform ops implementations */
···
1718
1676
if (master->free_pos & BIT(pos))
1719
1677
continue;
1720
1678
1721
-
if (master->devs[pos].is_i2c_addr)
1722
-
reg_val = DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1679
+
reg_val = readl(master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1680
+
1681
+
if (master->devs[pos].is_i2c_addr) {
1682
+
reg_val &= ~DEV_ADDR_TABLE_STATIC_MASK;
1683
+
reg_val |= DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1723
1684
DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr);
1724
-
else
1725
-
reg_val = DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
1685
+
} else {
1686
+
reg_val &= ~DEV_ADDR_TABLE_DYNAMIC_MASK;
1687
+
reg_val |= DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr);
1688
+
}
1726
1689
1727
1690
writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
1728
1691
}
+2
-2
drivers/i3c/master/svc-i3c-master.c
+2
-2
drivers/i3c/master/svc-i3c-master.c
···
533
533
static void svc_i3c_master_ibi_isr(struct svc_i3c_master *master)
534
534
{
535
535
struct svc_i3c_i2c_dev_data *data;
536
+
struct i3c_dev_desc *dev = NULL;
536
537
unsigned int ibitype, ibiaddr;
537
-
struct i3c_dev_desc *dev;
538
538
u32 status, val;
539
539
int ret;
540
540
···
627
627
* for the slave to interrupt again.
628
628
*/
629
629
if (svc_i3c_master_error(master)) {
630
-
if (master->ibi.tbq_slot) {
630
+
if (master->ibi.tbq_slot && dev) {
631
631
data = i3c_dev_get_master_data(dev);
632
632
i3c_generic_ibi_recycle_slot(data->ibi_pool,
633
633
master->ibi.tbq_slot);
+6
-4
drivers/iio/accel/Kconfig
+6
-4
drivers/iio/accel/Kconfig
···
64
64
65
65
config ADXL345_I2C
66
66
tristate "Analog Devices ADXL345 3-Axis Digital Accelerometer I2C Driver"
67
-
depends on INPUT_ADXL34X=n
67
+
depends on !INPUT_ADXL34X
68
68
depends on I2C
69
69
select ADXL345
70
70
select REGMAP_I2C
···
74
74
75
75
To compile this driver as a module, choose M here: the module
76
76
will be called adxl345_i2c and you will also get adxl345_core
77
-
for the core module.
77
+
for the core module. INPUT_ADXL34X share compatibles with this
78
+
driver, do not add both modules to the kernel.
78
79
79
80
config ADXL345_SPI
80
81
tristate "Analog Devices ADXL345 3-Axis Digital Accelerometer SPI Driver"
81
-
depends on INPUT_ADXL34X=n
82
+
depends on !INPUT_ADXL34X
82
83
depends on SPI
83
84
select ADXL345
84
85
select REGMAP_SPI
···
89
88
90
89
To compile this driver as a module, choose M here: the module
91
90
will be called adxl345_spi and you will also get adxl345_core
92
-
for the core module.
91
+
for the core module. INPUT_ADXL34X share compatibles with this
92
+
driver, do not add both modules to the kernel.
93
93
94
94
config ADXL355
95
95
tristate
+2
-3
drivers/iio/accel/adxl355_core.c
+2
-3
drivers/iio/accel/adxl355_core.c
···
768
768
data->dready_trig->ops = &adxl355_trigger_ops;
769
769
iio_trigger_set_drvdata(data->dready_trig, indio_dev);
770
770
771
-
ret = devm_request_irq(data->dev, irq,
772
-
&iio_trigger_generic_data_rdy_poll,
773
-
IRQF_ONESHOT, "adxl355_irq", data->dready_trig);
771
+
ret = devm_request_irq(data->dev, irq, &iio_trigger_generic_data_rdy_poll,
772
+
IRQF_NO_THREAD, "adxl355_irq", data->dready_trig);
774
773
if (ret)
775
774
return dev_err_probe(data->dev, ret, "request irq %d failed\n",
776
775
irq);
+4
-6
drivers/iio/accel/adxl372.c
+4
-6
drivers/iio/accel/adxl372.c
···
295
295
u32 inact_time_ms;
296
296
u8 fifo_set_size;
297
297
unsigned long int1_bitmask;
298
-
unsigned long int2_bitmask;
299
298
u16 watermark;
300
299
__be16 fifo_buf[ADXL372_FIFO_SIZE];
301
300
bool peak_fifo_mode_en;
···
1246
1247
1247
1248
indio_dev->trig = iio_trigger_get(st->dready_trig);
1248
1249
1249
-
ret = devm_request_threaded_irq(dev, st->irq,
1250
-
iio_trigger_generic_data_rdy_poll,
1251
-
NULL,
1252
-
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1253
-
indio_dev->name, st->dready_trig);
1250
+
ret = devm_request_irq(dev, st->irq,
1251
+
iio_trigger_generic_data_rdy_poll,
1252
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
1253
+
indio_dev->name, st->dready_trig);
1254
1254
if (ret < 0)
1255
1255
return ret;
1256
1256
}
+94
-44
drivers/iio/accel/adxl380.c
+94
-44
drivers/iio/accel/adxl380.c
···
232
232
}
233
233
EXPORT_SYMBOL_NS_GPL(adxl380_readable_noinc_reg, "IIO_ADXL380");
234
234
235
+
static int adxl380_act_inact_enabled(struct adxl380_state *st, bool *enabled)
236
+
{
237
+
unsigned int act_inact_ctl;
238
+
int ret;
239
+
240
+
if (!st->chip_info->has_low_power) {
241
+
*enabled = false;
242
+
return 0;
243
+
}
244
+
245
+
ret = regmap_read(st->regmap, ADXL380_ACT_INACT_CTL_REG, &act_inact_ctl);
246
+
if (ret)
247
+
return ret;
248
+
249
+
*enabled = FIELD_GET(ADXL380_ACT_EN_MSK, act_inact_ctl) ||
250
+
FIELD_GET(ADXL380_INACT_EN_MSK, act_inact_ctl);
251
+
252
+
return 0;
253
+
}
254
+
235
255
static int adxl380_set_measure_en(struct adxl380_state *st, bool en)
236
256
{
237
257
int ret;
238
-
unsigned int act_inact_ctl;
239
258
u8 op_mode = ADXL380_OP_MODE_STANDBY;
240
259
241
260
if (en) {
242
-
ret = regmap_read(st->regmap, ADXL380_ACT_INACT_CTL_REG, &act_inact_ctl);
261
+
bool act_inact_enabled;
262
+
263
+
ret = adxl380_act_inact_enabled(st, &act_inact_enabled);
243
264
if (ret)
244
265
return ret;
245
266
246
267
/*
247
268
* Activity/Inactivity detection available only in VLP/ULP
248
-
* mode and for devices that support low power modes. Otherwise
249
-
* go straight to measure mode (same bits as ADXL380_OP_MODE_HP).
269
+
* mode and for devices that support low power modes.
250
270
*/
251
-
if (st->chip_info->has_low_power &&
252
-
(FIELD_GET(ADXL380_ACT_EN_MSK, act_inact_ctl) ||
253
-
FIELD_GET(ADXL380_INACT_EN_MSK, act_inact_ctl)))
271
+
if (act_inact_enabled)
272
+
st->odr = ADXL380_ODR_VLP;
273
+
274
+
if (st->odr == ADXL380_ODR_VLP)
254
275
op_mode = ADXL380_OP_MODE_VLP;
255
276
else
256
277
op_mode = ADXL380_OP_MODE_HP;
···
438
417
439
418
static int adxl380_get_odr(struct adxl380_state *st, int *odr)
440
419
{
441
-
int ret;
442
-
unsigned int trig_cfg, odr_idx;
443
-
444
-
ret = regmap_read(st->regmap, ADXL380_TRIG_CFG_REG, &trig_cfg);
445
-
if (ret)
446
-
return ret;
447
-
448
-
odr_idx = (FIELD_GET(ADXL380_TRIG_CFG_SINC_RATE_MSK, trig_cfg) << 1) |
449
-
(FIELD_GET(ADXL380_TRIG_CFG_DEC_2X_MSK, trig_cfg) & 1);
450
-
451
-
*odr = st->chip_info->samp_freq_tbl[odr_idx];
420
+
*odr = st->chip_info->samp_freq_tbl[st->odr];
452
421
453
422
return 0;
454
423
}
···
499
488
if (ret)
500
489
return ret;
501
490
502
-
ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
503
-
ADXL380_TRIG_CFG_DEC_2X_MSK,
504
-
FIELD_PREP(ADXL380_TRIG_CFG_DEC_2X_MSK, odr & 1));
505
-
if (ret)
506
-
return ret;
491
+
if (odr >= ADXL380_ODR_DSM) {
492
+
u8 mul = odr - ADXL380_ODR_DSM;
493
+
u8 field;
507
494
508
-
ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
509
-
ADXL380_TRIG_CFG_SINC_RATE_MSK,
510
-
FIELD_PREP(ADXL380_TRIG_CFG_SINC_RATE_MSK, odr >> 1));
511
-
if (ret)
512
-
return ret;
495
+
field = FIELD_PREP(ADXL380_TRIG_CFG_DEC_2X_MSK, mul & 1);
496
+
ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
497
+
ADXL380_TRIG_CFG_DEC_2X_MSK, field);
498
+
if (ret)
499
+
return ret;
513
500
501
+
field = FIELD_PREP(ADXL380_TRIG_CFG_SINC_RATE_MSK, mul >> 1);
502
+
ret = regmap_update_bits(st->regmap, ADXL380_TRIG_CFG_REG,
503
+
ADXL380_TRIG_CFG_SINC_RATE_MSK, field);
504
+
if (ret)
505
+
return ret;
506
+
}
507
+
508
+
st->odr = odr;
514
509
ret = adxl380_set_measure_en(st, true);
515
510
if (ret)
516
511
return ret;
···
966
949
if (ret)
967
950
return IRQ_HANDLED;
968
951
969
-
for (i = 0; i < fifo_entries; i += st->fifo_set_size) {
970
-
ret = regmap_noinc_read(st->regmap, ADXL380_FIFO_DATA,
971
-
&st->fifo_buf[i],
972
-
2 * st->fifo_set_size);
973
-
if (ret)
974
-
return IRQ_HANDLED;
952
+
fifo_entries = rounddown(fifo_entries, st->fifo_set_size);
953
+
ret = regmap_noinc_read(st->regmap, ADXL380_FIFO_DATA, &st->fifo_buf,
954
+
sizeof(*st->fifo_buf) * fifo_entries);
955
+
if (ret)
956
+
return IRQ_HANDLED;
957
+
for (i = 0; i < fifo_entries; i += st->fifo_set_size)
975
958
iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
976
-
}
977
959
978
960
return IRQ_HANDLED;
979
961
}
···
1154
1138
.predisable = adxl380_buffer_predisable,
1155
1139
};
1156
1140
1141
+
static int adxl380_samp_freq_avail(struct adxl380_state *st, const int **vals,
1142
+
int *length)
1143
+
{
1144
+
bool act_inact_enabled;
1145
+
int ret;
1146
+
1147
+
if (!st->chip_info->has_low_power) {
1148
+
*vals = st->chip_info->samp_freq_tbl + ADXL380_ODR_DSM;
1149
+
*length = ADXL380_ODR_MAX - ADXL380_ODR_DSM;
1150
+
return 0;
1151
+
}
1152
+
1153
+
ret = adxl380_act_inact_enabled(st, &act_inact_enabled);
1154
+
if (ret)
1155
+
return 0;
1156
+
1157
+
/*
1158
+
* Motion detection is only functional in low-power mode, and this
1159
+
* affects the available sampling frequencies.
1160
+
*/
1161
+
*vals = st->chip_info->samp_freq_tbl;
1162
+
*length = act_inact_enabled ? ADXL380_ODR_DSM : ADXL380_ODR_MAX;
1163
+
1164
+
return 0;
1165
+
}
1166
+
1157
1167
static int adxl380_read_raw(struct iio_dev *indio_dev,
1158
1168
struct iio_chan_spec const *chan,
1159
1169
int *val, int *val2, long info)
···
1260
1218
long mask)
1261
1219
{
1262
1220
struct adxl380_state *st = iio_priv(indio_dev);
1221
+
int ret;
1263
1222
1264
1223
if (chan->type != IIO_ACCEL)
1265
1224
return -EINVAL;
···
1272
1229
*length = ARRAY_SIZE(st->chip_info->scale_tbl) * 2;
1273
1230
return IIO_AVAIL_LIST;
1274
1231
case IIO_CHAN_INFO_SAMP_FREQ:
1275
-
*vals = (const int *)st->chip_info->samp_freq_tbl;
1232
+
ret = adxl380_samp_freq_avail(st, vals, length);
1233
+
if (ret)
1234
+
return ret;
1235
+
1276
1236
*type = IIO_VAL_INT;
1277
-
*length = ARRAY_SIZE(st->chip_info->samp_freq_tbl);
1278
1237
return IIO_AVAIL_LIST;
1279
1238
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
1280
1239
*vals = (const int *)st->lpf_tbl;
···
1299
1254
int val, int val2, long info)
1300
1255
{
1301
1256
struct adxl380_state *st = iio_priv(indio_dev);
1302
-
int odr_index, lpf_index, hpf_index, range_index;
1257
+
const int *freq_vals;
1258
+
int odr_index, lpf_index, hpf_index, range_index, freq_count, ret;
1303
1259
1304
1260
switch (info) {
1305
1261
case IIO_CHAN_INFO_SAMP_FREQ:
1306
-
odr_index = adxl380_find_match_1d_tbl(st->chip_info->samp_freq_tbl,
1307
-
ARRAY_SIZE(st->chip_info->samp_freq_tbl),
1262
+
ret = adxl380_samp_freq_avail(st, &freq_vals, &freq_count);
1263
+
if (ret)
1264
+
return ret;
1265
+
1266
+
odr_index = adxl380_find_match_1d_tbl(freq_vals, freq_count,
1308
1267
val);
1309
1268
return adxl380_set_odr(st, odr_index);
1310
1269
case IIO_CHAN_INFO_CALIBBIAS:
···
1670
1621
[ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 },
1671
1622
[ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 },
1672
1623
},
1673
-
.samp_freq_tbl = { 8000, 16000, 32000 },
1624
+
.samp_freq_tbl = { 0, 8000, 16000, 32000 },
1674
1625
/*
1675
1626
* The datasheet defines an intercept of 550 LSB at 25 degC
1676
1627
* and a sensitivity of 10.2 LSB/C.
···
1688
1639
[ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 },
1689
1640
[ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 },
1690
1641
},
1691
-
.samp_freq_tbl = { 16000, 32000, 64000 },
1642
+
.samp_freq_tbl = { 0, 16000, 32000, 64000 },
1692
1643
/*
1693
1644
* The datasheet defines an intercept of 550 LSB at 25 degC
1694
1645
* and a sensitivity of 10.2 LSB/C.
···
1706
1657
[ADXL380_OP_MODE_8G_RANGE] = { 0, 2615434 },
1707
1658
[ADXL380_OP_MODE_16G_RANGE] = { 0, 5229886 },
1708
1659
},
1709
-
.samp_freq_tbl = { 8000, 16000, 32000 },
1660
+
.samp_freq_tbl = { 1000, 8000, 16000, 32000 },
1710
1661
/*
1711
1662
* The datasheet defines an intercept of 470 LSB at 25 degC
1712
1663
* and a sensitivity of 10.2 LSB/C.
···
1726
1677
[ADXL382_OP_MODE_30G_RANGE] = { 0, 9806650 },
1727
1678
[ADXL382_OP_MODE_60G_RANGE] = { 0, 19613300 },
1728
1679
},
1729
-
.samp_freq_tbl = { 16000, 32000, 64000 },
1680
+
.samp_freq_tbl = { 1000, 16000, 32000, 64000 },
1730
1681
/*
1731
1682
* The datasheet defines an intercept of 570 LSB at 25 degC
1732
1683
* and a sensitivity of 10.2 LSB/C.
···
1965
1916
st->dev = dev;
1966
1917
st->regmap = regmap;
1967
1918
st->chip_info = chip_info;
1919
+
st->odr = ADXL380_ODR_DSM;
1968
1920
1969
1921
mutex_init(&st->lock);
1970
1922
+9
-1
drivers/iio/accel/adxl380.h
+9
-1
drivers/iio/accel/adxl380.h
···
8
8
#ifndef _ADXL380_H_
9
9
#define _ADXL380_H_
10
10
11
+
enum adxl380_odr {
12
+
ADXL380_ODR_VLP,
13
+
ADXL380_ODR_DSM,
14
+
ADXL380_ODR_DSM_2X,
15
+
ADXL380_ODR_DSM_4X,
16
+
ADXL380_ODR_MAX
17
+
};
18
+
11
19
struct adxl380_chip_info {
12
20
const char *name;
13
21
const int scale_tbl[3][2];
14
-
const int samp_freq_tbl[3];
22
+
const int samp_freq_tbl[ADXL380_ODR_MAX];
15
23
const struct iio_info *info;
16
24
const int temp_offset;
17
25
const u16 chip_id;
+3
-2
drivers/iio/accel/bma180.c
+3
-2
drivers/iio/accel/bma180.c
···
986
986
}
987
987
988
988
ret = devm_request_irq(dev, client->irq,
989
-
iio_trigger_generic_data_rdy_poll, IRQF_TRIGGER_RISING,
990
-
"bma180_event", data->trig);
989
+
iio_trigger_generic_data_rdy_poll,
990
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
991
+
"bma180_event", data->trig);
991
992
if (ret) {
992
993
dev_err(dev, "unable to request IRQ\n");
993
994
goto err_trigger_free;
+4
-7
drivers/iio/accel/mxc4005.c
+4
-7
drivers/iio/accel/mxc4005.c
···
486
486
if (!data->dready_trig)
487
487
return -ENOMEM;
488
488
489
-
ret = devm_request_threaded_irq(&client->dev, client->irq,
490
-
iio_trigger_generic_data_rdy_poll,
491
-
NULL,
492
-
IRQF_TRIGGER_FALLING |
493
-
IRQF_ONESHOT,
494
-
"mxc4005_event",
495
-
data->dready_trig);
489
+
ret = devm_request_irq(&client->dev, client->irq,
490
+
iio_trigger_generic_data_rdy_poll,
491
+
IRQF_TRIGGER_FALLING | IRQF_NO_THREAD,
492
+
"mxc4005_event", data->dready_trig);
496
493
if (ret) {
497
494
dev_err(&client->dev,
498
495
"failed to init threaded irq\n");
+5
-3
drivers/iio/accel/sca3000.c
+5
-3
drivers/iio/accel/sca3000.c
···
153
153
* struct sca3000_state - device instance state information
154
154
* @us: the associated spi device
155
155
* @info: chip variant information
156
-
* @last_timestamp: the timestamp of the last event
157
156
* @mo_det_use_count: reference counter for the motion detection unit
158
157
* @lock: lock used to protect elements of sca3000_state
159
158
* and the underlying device state.
···
162
163
struct sca3000_state {
163
164
struct spi_device *us;
164
165
const struct sca3000_chip_info *info;
165
-
s64 last_timestamp;
166
166
int mo_det_use_count;
167
167
struct mutex lock;
168
168
/* Can these share a cacheline ? */
···
1487
1489
if (ret)
1488
1490
goto error_free_irq;
1489
1491
1490
-
return iio_device_register(indio_dev);
1492
+
ret = iio_device_register(indio_dev);
1493
+
if (ret)
1494
+
goto error_free_irq;
1495
+
1496
+
return 0;
1491
1497
1492
1498
error_free_irq:
1493
1499
if (spi->irq)
+4
-7
drivers/iio/accel/stk8ba50.c
+4
-7
drivers/iio/accel/stk8ba50.c
···
428
428
}
429
429
430
430
if (client->irq > 0) {
431
-
ret = devm_request_threaded_irq(&client->dev, client->irq,
432
-
stk8ba50_data_rdy_trig_poll,
433
-
NULL,
434
-
IRQF_TRIGGER_RISING |
435
-
IRQF_ONESHOT,
436
-
"stk8ba50_event",
437
-
indio_dev);
431
+
ret = devm_request_irq(&client->dev, client->irq,
432
+
stk8ba50_data_rdy_trig_poll,
433
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
434
+
"stk8ba50_event", indio_dev);
438
435
if (ret < 0) {
439
436
dev_err(&client->dev, "request irq %d failed\n",
440
437
client->irq);
+60
drivers/iio/adc/Kconfig
+60
drivers/iio/adc/Kconfig
···
70
70
To compile this driver as a module, choose M here: the module will be
71
71
called ad4030.
72
72
73
+
config AD4062
74
+
tristate "Analog Devices AD4062 Driver"
75
+
depends on I3C
76
+
select REGMAP_I3C
77
+
select IIO_BUFFER
78
+
select IIO_TRIGGERED_BUFFER
79
+
help
80
+
Say yes here to build support for Analog Devices AD4062 I3C analog
81
+
to digital converters (ADC).
82
+
83
+
To compile this driver as a module, choose M here: the module will be
84
+
called ad4062.
85
+
73
86
config AD4080
74
87
tristate "Analog Devices AD4080 high speed ADC"
75
88
depends on SPI
···
112
99
To compile this driver as a module, choose M here: the module will be
113
100
called ad4130.
114
101
102
+
config AD4134
103
+
tristate "Analog Device AD4134 ADC Driver"
104
+
depends on SPI
105
+
select REGMAP_SPI
106
+
select CRC8
107
+
help
108
+
Say yes here to build support for Analog Devices AD4134 SPI analog to
109
+
digital converters (ADC).
110
+
111
+
To compile this driver as a module, choose M here: the module will be
112
+
called ad4134_spi.
115
113
116
114
config AD4170_4
117
115
tristate "Analog Device AD4170-4 ADC Driver"
···
411
387
depends on SPI
412
388
select REGULATOR
413
389
select REGMAP_SPI
390
+
select RATIONAL
414
391
select IIO_BUFFER
415
392
select IIO_TRIGGER
416
393
select IIO_TRIGGERED_BUFFER
···
1247
1222
This driver can also be built as a module. If so, the module
1248
1223
will be called npcm_adc.
1249
1224
1225
+
config NXP_SAR_ADC
1226
+
tristate "NXP S32G SAR-ADC driver"
1227
+
depends on ARCH_S32 || COMPILE_TEST
1228
+
select IIO_BUFFER
1229
+
select IIO_TRIGGERED_BUFFER
1230
+
help
1231
+
Say yes here to build support for S32G platforms
1232
+
analog-to-digital converter.
1233
+
1234
+
This driver can also be built as a module. If so, the module will be
1235
+
called nxp_sar_adc.
1236
+
1250
1237
config PAC1921
1251
1238
tristate "Microchip Technology PAC1921 driver"
1252
1239
depends on I2C
···
1701
1664
This driver can also be built as a module. If so, the module will be
1702
1665
called ti-ads1015.
1703
1666
1667
+
config TI_ADS1018
1668
+
tristate "Texas Instruments ADS1018 ADC"
1669
+
depends on SPI
1670
+
select IIO_BUFFER
1671
+
select IIO_TRIGGERED_BUFFER
1672
+
help
1673
+
If you say yes here you get support for Texas Instruments ADS1018 and
1674
+
ADS1118 ADC chips.
1675
+
1676
+
This driver can also be built as a module. If so, the module will be
1677
+
called ti-ads1018.
1678
+
1704
1679
config TI_ADS1100
1705
1680
tristate "Texas Instruments ADS1100 and ADS1000 ADC"
1706
1681
depends on I2C
···
1770
1721
1771
1722
This driver can also be built as a module. If so, the module will be
1772
1723
called ti-ads131e08.
1724
+
1725
+
config TI_ADS131M02
1726
+
tristate "Texas Instruments ADS131M02"
1727
+
depends on SPI && REGULATOR
1728
+
select CRC_ITU_T
1729
+
help
1730
+
Say yes here to get support for Texas Instruments ADS131M02, ADS131M03,
1731
+
ADS131M04, ADS131M06 and ADS131M08 chips.
1732
+
1733
+
This driver can also be built as a module. If so, the module will be
1734
+
called ti-ads131m02.
1773
1735
1774
1736
config TI_ADS7138
1775
1737
tristate "Texas Instruments ADS7128 and ADS7138 ADC driver"
+5
drivers/iio/adc/Makefile
+5
drivers/iio/adc/Makefile
···
11
11
obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o
12
12
obj-$(CONFIG_AD4000) += ad4000.o
13
13
obj-$(CONFIG_AD4030) += ad4030.o
14
+
obj-$(CONFIG_AD4062) += ad4062.o
14
15
obj-$(CONFIG_AD4080) += ad4080.o
15
16
obj-$(CONFIG_AD4130) += ad4130.o
17
+
obj-$(CONFIG_AD4134) += ad4134.o
16
18
obj-$(CONFIG_AD4170_4) += ad4170-4.o
17
19
obj-$(CONFIG_AD4695) += ad4695.o
18
20
obj-$(CONFIG_AD4851) += ad4851.o
···
110
108
obj-$(CONFIG_NAU7802) += nau7802.o
111
109
obj-$(CONFIG_NCT7201) += nct7201.o
112
110
obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
111
+
obj-$(CONFIG_NXP_SAR_ADC) += nxp-sar-adc.o
113
112
obj-$(CONFIG_PAC1921) += pac1921.o
114
113
obj-$(CONFIG_PAC1934) += pac1934.o
115
114
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
···
148
145
obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
149
146
obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o
150
147
obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
148
+
obj-$(CONFIG_TI_ADS1018) += ti-ads1018.o
151
149
obj-$(CONFIG_TI_ADS1100) += ti-ads1100.o
152
150
obj-$(CONFIG_TI_ADS1119) += ti-ads1119.o
153
151
obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o
154
152
obj-$(CONFIG_TI_ADS1298) += ti-ads1298.o
155
153
obj-$(CONFIG_TI_ADS131E08) += ti-ads131e08.o
154
+
obj-$(CONFIG_TI_ADS131M02) += ti-ads131m02.o
156
155
obj-$(CONFIG_TI_ADS7138) += ti-ads7138.o
157
156
obj-$(CONFIG_TI_ADS7924) += ti-ads7924.o
158
157
obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o
+1609
drivers/iio/adc/ad4062.c
+1609
drivers/iio/adc/ad4062.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Analog Devices AD4062 I3C ADC driver
4
+
*
5
+
* Copyright 2025 Analog Devices Inc.
6
+
*/
7
+
#include <linux/array_size.h>
8
+
#include <linux/bitfield.h>
9
+
#include <linux/bitops.h>
10
+
#include <linux/completion.h>
11
+
#include <linux/delay.h>
12
+
#include <linux/devm-helpers.h>
13
+
#include <linux/err.h>
14
+
#include <linux/gpio/driver.h>
15
+
#include <linux/i3c/device.h>
16
+
#include <linux/i3c/master.h>
17
+
#include <linux/iio/buffer.h>
18
+
#include <linux/iio/events.h>
19
+
#include <linux/iio/iio.h>
20
+
#include <linux/iio/sysfs.h>
21
+
#include <linux/iio/trigger.h>
22
+
#include <linux/iio/trigger_consumer.h>
23
+
#include <linux/iio/triggered_buffer.h>
24
+
#include <linux/interrupt.h>
25
+
#include <linux/jiffies.h>
26
+
#include <linux/math.h>
27
+
#include <linux/minmax.h>
28
+
#include <linux/pm_runtime.h>
29
+
#include <linux/property.h>
30
+
#include <linux/regmap.h>
31
+
#include <linux/regulator/consumer.h>
32
+
#include <linux/string.h>
33
+
#include <linux/types.h>
34
+
#include <linux/units.h>
35
+
#include <linux/unaligned.h>
36
+
#include <linux/util_macros.h>
37
+
38
+
#define AD4062_REG_INTERFACE_CONFIG_A 0x00
39
+
#define AD4062_REG_DEVICE_CONFIG 0x02
40
+
#define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0)
41
+
#define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE 3
42
+
#define AD4062_REG_PROD_ID_1 0x05
43
+
#define AD4062_REG_DEVICE_GRADE 0x06
44
+
#define AD4062_REG_SCRATCH_PAD 0x0A
45
+
#define AD4062_REG_VENDOR_H 0x0D
46
+
#define AD4062_REG_STREAM_MODE 0x0E
47
+
#define AD4062_REG_INTERFACE_STATUS 0x11
48
+
#define AD4062_REG_MODE_SET 0x20
49
+
#define AD4062_REG_MODE_SET_ENTER_ADC BIT(0)
50
+
#define AD4062_REG_ADC_MODES 0x21
51
+
#define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0)
52
+
#define AD4062_REG_ADC_CONFIG 0x22
53
+
#define AD4062_REG_ADC_CONFIG_REF_EN_MSK BIT(5)
54
+
#define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4)
55
+
#define AD4062_REG_AVG_CONFIG 0x23
56
+
#define AD4062_REG_GP_CONF 0x24
57
+
#define AD4062_REG_GP_CONF_MODE_MSK_0 GENMASK(2, 0)
58
+
#define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4)
59
+
#define AD4062_REG_INTR_CONF 0x25
60
+
#define AD4062_REG_INTR_CONF_EN_MSK_0 GENMASK(1, 0)
61
+
#define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4)
62
+
#define AD4062_REG_TIMER_CONFIG 0x27
63
+
#define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4)
64
+
#define AD4062_REG_MAX_LIMIT 0x29
65
+
#define AD4062_REG_MIN_LIMIT 0x2B
66
+
#define AD4062_REG_MAX_HYST 0x2C
67
+
#define AD4062_REG_MIN_HYST 0x2D
68
+
#define AD4062_REG_MON_VAL 0x2F
69
+
#define AD4062_REG_ADC_IBI_EN 0x31
70
+
#define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2)
71
+
#define AD4062_REG_ADC_IBI_EN_MAX BIT(1)
72
+
#define AD4062_REG_ADC_IBI_EN_MIN BIT(0)
73
+
#define AD4062_REG_FUSE_CRC 0x40
74
+
#define AD4062_REG_DEVICE_STATUS 0x41
75
+
#define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6)
76
+
#define AD4062_REG_IBI_STATUS 0x48
77
+
#define AD4062_REG_CONV_READ_LSB 0x50
78
+
#define AD4062_REG_CONV_READ_16BITS 0x51
79
+
#define AD4062_REG_CONV_READ_32BITS 0x53
80
+
#define AD4062_REG_CONV_TRIGGER_16BITS 0x57
81
+
#define AD4062_REG_CONV_TRIGGER_32BITS 0x59
82
+
#define AD4062_REG_CONV_AUTO 0x61
83
+
#define AD4062_MAX_REG AD4062_REG_CONV_AUTO
84
+
85
+
#define AD4062_MON_VAL_MIDDLE_POINT 0x8000
86
+
87
+
#define AD4062_I3C_VENDOR 0x0177
88
+
#define AD4062_SOFT_RESET 0x81
89
+
#define AD4060_PROD_ID 0x7A
90
+
#define AD4062_PROD_ID 0x7C
91
+
92
+
#define AD4062_GP_DISABLED 0x0
93
+
#define AD4062_GP_INTR 0x1
94
+
#define AD4062_GP_DRDY 0x2
95
+
#define AD4062_GP_STATIC_LOW 0x5
96
+
#define AD4062_GP_STATIC_HIGH 0x6
97
+
98
+
#define AD4062_LIMIT_BITS 12
99
+
100
+
#define AD4062_INTR_EN_NEITHER 0x0
101
+
#define AD4062_INTR_EN_EITHER 0x3
102
+
103
+
#define AD4062_TCONV_NS 270
104
+
105
+
enum ad4062_operation_mode {
106
+
AD4062_SAMPLE_MODE = 0x0,
107
+
AD4062_BURST_AVERAGING_MODE = 0x1,
108
+
AD4062_MONITOR_MODE = 0x3,
109
+
};
110
+
111
+
struct ad4062_chip_info {
112
+
const struct iio_chan_spec channels[1];
113
+
const char *name;
114
+
u16 prod_id;
115
+
u16 avg_max;
116
+
};
117
+
118
+
enum {
119
+
AD4062_SCAN_TYPE_SAMPLE,
120
+
AD4062_SCAN_TYPE_BURST_AVG,
121
+
};
122
+
123
+
static const struct iio_scan_type ad4062_scan_type_12_s[] = {
124
+
[AD4062_SCAN_TYPE_SAMPLE] = {
125
+
.sign = 's',
126
+
.realbits = 12,
127
+
.storagebits = 16,
128
+
.endianness = IIO_BE,
129
+
},
130
+
[AD4062_SCAN_TYPE_BURST_AVG] = {
131
+
.sign = 's',
132
+
.realbits = 14,
133
+
.storagebits = 16,
134
+
.endianness = IIO_BE,
135
+
},
136
+
};
137
+
138
+
static const struct iio_scan_type ad4062_scan_type_16_s[] = {
139
+
[AD4062_SCAN_TYPE_SAMPLE] = {
140
+
.sign = 's',
141
+
.realbits = 16,
142
+
.storagebits = 16,
143
+
.endianness = IIO_BE,
144
+
},
145
+
[AD4062_SCAN_TYPE_BURST_AVG] = {
146
+
.sign = 's',
147
+
.realbits = 20,
148
+
.storagebits = 32,
149
+
.endianness = IIO_BE,
150
+
},
151
+
};
152
+
153
+
static const unsigned int ad4062_conversion_freqs[] = {
154
+
2000000, 1000000, 300000, 100000, /* 0 - 3 */
155
+
33300, 10000, 3000, 500, /* 4 - 7 */
156
+
333, 250, 200, 166, /* 8 - 11 */
157
+
140, 124, 111, /* 12 - 15 */
158
+
};
159
+
160
+
struct ad4062_state {
161
+
const struct ad4062_chip_info *chip;
162
+
const struct ad4062_bus_ops *ops;
163
+
enum ad4062_operation_mode mode;
164
+
struct work_struct trig_conv;
165
+
struct completion completion;
166
+
struct iio_trigger *trigger;
167
+
struct iio_dev *indio_dev;
168
+
struct i3c_device *i3cdev;
169
+
struct regmap *regmap;
170
+
bool wait_event;
171
+
int vref_uV;
172
+
unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)];
173
+
bool gpo_irq[2];
174
+
u16 sampling_frequency;
175
+
u16 events_frequency;
176
+
u8 oversamp_ratio;
177
+
u8 conv_sizeof;
178
+
u8 conv_addr;
179
+
union {
180
+
__be32 be32;
181
+
__be16 be16;
182
+
} buf __aligned(IIO_DMA_MINALIGN);
183
+
};
184
+
185
+
static const struct regmap_range ad4062_regmap_rd_ranges[] = {
186
+
regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE),
187
+
regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS),
188
+
regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN),
189
+
regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS),
190
+
regmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO),
191
+
};
192
+
193
+
static const struct regmap_access_table ad4062_regmap_rd_table = {
194
+
.yes_ranges = ad4062_regmap_rd_ranges,
195
+
.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_rd_ranges),
196
+
};
197
+
198
+
static const struct regmap_range ad4062_regmap_wr_ranges[] = {
199
+
regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG),
200
+
regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD),
201
+
regmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS),
202
+
regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN),
203
+
regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS),
204
+
};
205
+
206
+
static const struct regmap_access_table ad4062_regmap_wr_table = {
207
+
.yes_ranges = ad4062_regmap_wr_ranges,
208
+
.n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges),
209
+
};
210
+
211
+
static const struct iio_event_spec ad4062_events[] = {
212
+
{
213
+
.type = IIO_EV_TYPE_THRESH,
214
+
.dir = IIO_EV_DIR_EITHER,
215
+
.mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE),
216
+
},
217
+
{
218
+
.type = IIO_EV_TYPE_THRESH,
219
+
.dir = IIO_EV_DIR_RISING,
220
+
.mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) |
221
+
BIT(IIO_EV_INFO_HYSTERESIS),
222
+
},
223
+
{
224
+
.type = IIO_EV_TYPE_THRESH,
225
+
.dir = IIO_EV_DIR_FALLING,
226
+
.mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) |
227
+
BIT(IIO_EV_INFO_HYSTERESIS),
228
+
},
229
+
};
230
+
231
+
#define AD4062_CHAN(bits) { \
232
+
.type = IIO_VOLTAGE, \
233
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \
234
+
BIT(IIO_CHAN_INFO_SCALE) | \
235
+
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
236
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
237
+
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
238
+
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
239
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
240
+
.indexed = 1, \
241
+
.channel = 0, \
242
+
.event_spec = ad4062_events, \
243
+
.num_event_specs = ARRAY_SIZE(ad4062_events), \
244
+
.has_ext_scan_type = 1, \
245
+
.ext_scan_type = ad4062_scan_type_##bits##_s, \
246
+
.num_ext_scan_type = ARRAY_SIZE(ad4062_scan_type_##bits##_s), \
247
+
}
248
+
249
+
static const struct ad4062_chip_info ad4060_chip_info = {
250
+
.name = "ad4060",
251
+
.channels = { AD4062_CHAN(12) },
252
+
.prod_id = AD4060_PROD_ID,
253
+
.avg_max = 256,
254
+
};
255
+
256
+
static const struct ad4062_chip_info ad4062_chip_info = {
257
+
.name = "ad4062",
258
+
.channels = { AD4062_CHAN(16) },
259
+
.prod_id = AD4062_PROD_ID,
260
+
.avg_max = 4096,
261
+
};
262
+
263
+
static ssize_t sampling_frequency_show(struct device *dev,
264
+
struct device_attribute *attr, char *buf)
265
+
{
266
+
struct ad4062_state *st = iio_priv(dev_to_iio_dev(dev));
267
+
268
+
return sysfs_emit(buf, "%d\n", ad4062_conversion_freqs[st->events_frequency]);
269
+
}
270
+
271
+
static int sampling_frequency_store_dispatch(struct iio_dev *indio_dev,
272
+
const char *buf)
273
+
{
274
+
struct ad4062_state *st = iio_priv(indio_dev);
275
+
int val, ret;
276
+
277
+
if (st->wait_event)
278
+
return -EBUSY;
279
+
280
+
ret = kstrtoint(buf, 10, &val);
281
+
if (ret)
282
+
return ret;
283
+
284
+
st->events_frequency = find_closest_descending(val, ad4062_conversion_freqs,
285
+
ARRAY_SIZE(ad4062_conversion_freqs));
286
+
return 0;
287
+
}
288
+
289
+
static ssize_t sampling_frequency_store(struct device *dev,
290
+
struct device_attribute *attr,
291
+
const char *buf, size_t len)
292
+
{
293
+
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
294
+
int ret;
295
+
296
+
if (!iio_device_claim_direct(indio_dev))
297
+
return -EBUSY;
298
+
299
+
ret = sampling_frequency_store_dispatch(indio_dev, buf);
300
+
iio_device_release_direct(indio_dev);
301
+
return ret ?: len;
302
+
}
303
+
304
+
static IIO_DEVICE_ATTR_RW(sampling_frequency, 0);
305
+
306
+
static ssize_t sampling_frequency_available_show(struct device *dev,
307
+
struct device_attribute *attr,
308
+
char *buf)
309
+
{
310
+
int ret = 0;
311
+
312
+
for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++)
313
+
ret += sysfs_emit_at(buf, ret, "%d%s", ad4062_conversion_freqs[i],
314
+
i != (ARRAY_SIZE(ad4062_conversion_freqs) - 1) ? " " : "\n");
315
+
return ret;
316
+
}
317
+
318
+
static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0);
319
+
320
+
static struct attribute *ad4062_event_attributes[] = {
321
+
&iio_dev_attr_sampling_frequency.dev_attr.attr,
322
+
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
323
+
NULL
324
+
};
325
+
326
+
static const struct attribute_group ad4062_event_attribute_group = {
327
+
.attrs = ad4062_event_attributes,
328
+
};
329
+
330
+
static int ad4062_set_oversampling_ratio(struct ad4062_state *st, int val, int val2)
331
+
{
332
+
const u32 _max = st->chip->avg_max;
333
+
const u32 _min = 1;
334
+
int ret;
335
+
336
+
if (!in_range(val, _min, _max) || val2 != 0)
337
+
return -EINVAL;
338
+
339
+
/* 1 disables oversampling */
340
+
val = ilog2(val);
341
+
if (val == 0) {
342
+
st->mode = AD4062_SAMPLE_MODE;
343
+
} else {
344
+
st->mode = AD4062_BURST_AVERAGING_MODE;
345
+
ret = regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1);
346
+
if (ret)
347
+
return ret;
348
+
}
349
+
st->oversamp_ratio = val;
350
+
351
+
return 0;
352
+
}
353
+
354
+
static int ad4062_get_oversampling_ratio(struct ad4062_state *st, int *val)
355
+
{
356
+
int ret, buf;
357
+
358
+
if (st->mode == AD4062_SAMPLE_MODE) {
359
+
*val = 1;
360
+
return 0;
361
+
}
362
+
363
+
ret = regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf);
364
+
if (ret)
365
+
return ret;
366
+
367
+
*val = BIT(buf + 1);
368
+
return 0;
369
+
}
370
+
371
+
static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int oversamp_ratio)
372
+
{
373
+
/* From datasheet p.31: (n_avg - 1)/fosc + tconv */
374
+
u32 n_avg = BIT(oversamp_ratio) - 1;
375
+
u32 period_ns = NSEC_PER_SEC / fosc;
376
+
377
+
/* Result is less than 1 Hz */
378
+
if (n_avg >= fosc)
379
+
return 1;
380
+
381
+
return NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS);
382
+
}
383
+
384
+
static int ad4062_populate_sampling_frequency(struct ad4062_state *st)
385
+
{
386
+
for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++)
387
+
st->samp_freqs[i] =
388
+
ad4062_calc_sampling_frequency(ad4062_conversion_freqs[i],
389
+
st->oversamp_ratio);
390
+
return 0;
391
+
}
392
+
393
+
static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val)
394
+
{
395
+
int freq = ad4062_conversion_freqs[st->sampling_frequency];
396
+
397
+
*val = ad4062_calc_sampling_frequency(freq, st->oversamp_ratio);
398
+
return IIO_VAL_INT;
399
+
}
400
+
401
+
static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val, int val2)
402
+
{
403
+
int ret;
404
+
405
+
if (val2 != 0)
406
+
return -EINVAL;
407
+
408
+
ret = ad4062_populate_sampling_frequency(st);
409
+
if (ret)
410
+
return ret;
411
+
412
+
st->sampling_frequency =
413
+
find_closest_descending(val, st->samp_freqs,
414
+
ARRAY_SIZE(ad4062_conversion_freqs));
415
+
return 0;
416
+
}
417
+
418
+
static int ad4062_check_ids(struct ad4062_state *st)
419
+
{
420
+
struct device *dev = &st->i3cdev->dev;
421
+
int ret;
422
+
u16 val;
423
+
424
+
ret = regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1,
425
+
&st->buf.be16, sizeof(st->buf.be16));
426
+
if (ret)
427
+
return ret;
428
+
429
+
val = be16_to_cpu(st->buf.be16);
430
+
if (val != st->chip->prod_id)
431
+
dev_warn(dev, "Production ID x%x does not match known values", val);
432
+
433
+
ret = regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H,
434
+
&st->buf.be16, sizeof(st->buf.be16));
435
+
if (ret)
436
+
return ret;
437
+
438
+
val = be16_to_cpu(st->buf.be16);
439
+
if (val != AD4062_I3C_VENDOR) {
440
+
dev_err(dev, "Vendor ID x%x does not match expected value\n", val);
441
+
return -ENODEV;
442
+
}
443
+
444
+
return 0;
445
+
}
446
+
447
+
static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val)
448
+
{
449
+
return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG,
450
+
FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val));
451
+
}
452
+
453
+
static int ad4062_set_operation_mode(struct ad4062_state *st,
454
+
enum ad4062_operation_mode mode)
455
+
{
456
+
const unsigned int samp_freq = mode == AD4062_MONITOR_MODE ?
457
+
st->events_frequency : st->sampling_frequency;
458
+
int ret;
459
+
460
+
ret = ad4062_conversion_frequency_set(st, samp_freq);
461
+
if (ret)
462
+
return ret;
463
+
464
+
ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES,
465
+
AD4062_REG_ADC_MODES_MODE_MSK, mode);
466
+
if (ret)
467
+
return ret;
468
+
469
+
if (mode == AD4062_MONITOR_MODE) {
470
+
/* Change address pointer to enter monitor mode */
471
+
struct i3c_xfer xfer_trigger = {
472
+
.data.out = &st->conv_addr,
473
+
.len = sizeof(st->conv_addr),
474
+
.rnw = false,
475
+
};
476
+
st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS;
477
+
return i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR);
478
+
}
479
+
480
+
return regmap_write(st->regmap, AD4062_REG_MODE_SET,
481
+
AD4062_REG_MODE_SET_ENTER_ADC);
482
+
}
483
+
484
+
static int ad4062_soft_reset(struct ad4062_state *st)
485
+
{
486
+
u8 val = AD4062_SOFT_RESET;
487
+
int ret;
488
+
489
+
ret = regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val);
490
+
if (ret)
491
+
return ret;
492
+
493
+
/* Wait AD4062 treset time, datasheet p8 */
494
+
ndelay(60);
495
+
496
+
return 0;
497
+
}
498
+
499
+
static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
500
+
const bool *ref_sel)
501
+
{
502
+
struct ad4062_state *st = iio_priv(indio_dev);
503
+
const struct iio_scan_type *scan_type;
504
+
int ret;
505
+
506
+
scan_type = iio_get_current_scan_type(indio_dev, chan);
507
+
if (IS_ERR(scan_type))
508
+
return PTR_ERR(scan_type);
509
+
510
+
ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
511
+
AD4062_REG_GP_CONF_MODE_MSK_0,
512
+
FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0,
513
+
AD4062_GP_INTR));
514
+
if (ret)
515
+
return ret;
516
+
517
+
ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
518
+
AD4062_REG_GP_CONF_MODE_MSK_1,
519
+
FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1,
520
+
AD4062_GP_DRDY));
521
+
if (ret)
522
+
return ret;
523
+
524
+
ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG,
525
+
AD4062_REG_ADC_CONFIG_REF_EN_MSK,
526
+
FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK,
527
+
*ref_sel));
528
+
if (ret)
529
+
return ret;
530
+
531
+
ret = regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS,
532
+
AD4062_REG_DEVICE_STATUS_DEVICE_RESET);
533
+
if (ret)
534
+
return ret;
535
+
536
+
ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF,
537
+
AD4062_REG_INTR_CONF_EN_MSK_0,
538
+
FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_0,
539
+
AD4062_INTR_EN_EITHER));
540
+
if (ret)
541
+
return ret;
542
+
543
+
ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF,
544
+
AD4062_REG_INTR_CONF_EN_MSK_1,
545
+
FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1,
546
+
AD4062_INTR_EN_NEITHER));
547
+
if (ret)
548
+
return ret;
549
+
550
+
st->buf.be16 = cpu_to_be16(AD4062_MON_VAL_MIDDLE_POINT);
551
+
return regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL,
552
+
&st->buf.be16, sizeof(st->buf.be16));
553
+
}
554
+
555
+
static irqreturn_t ad4062_irq_handler_thresh(int irq, void *private)
556
+
{
557
+
struct iio_dev *indio_dev = private;
558
+
559
+
iio_push_event(indio_dev,
560
+
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
561
+
IIO_EV_TYPE_THRESH,
562
+
IIO_EV_DIR_EITHER),
563
+
iio_get_time_ns(indio_dev));
564
+
565
+
return IRQ_HANDLED;
566
+
}
567
+
568
+
static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private)
569
+
{
570
+
struct iio_dev *indio_dev = private;
571
+
struct ad4062_state *st = iio_priv(indio_dev);
572
+
573
+
if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))
574
+
iio_trigger_poll(st->trigger);
575
+
else
576
+
complete(&st->completion);
577
+
578
+
return IRQ_HANDLED;
579
+
}
580
+
581
+
static void ad4062_ibi_handler(struct i3c_device *i3cdev,
582
+
const struct i3c_ibi_payload *payload)
583
+
{
584
+
struct ad4062_state *st = i3cdev_get_drvdata(i3cdev);
585
+
586
+
if (st->wait_event) {
587
+
iio_push_event(st->indio_dev,
588
+
IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
589
+
IIO_EV_TYPE_THRESH,
590
+
IIO_EV_DIR_EITHER),
591
+
iio_get_time_ns(st->indio_dev));
592
+
return;
593
+
}
594
+
if (iio_buffer_enabled(st->indio_dev))
595
+
iio_trigger_poll_nested(st->trigger);
596
+
else
597
+
complete(&st->completion);
598
+
}
599
+
600
+
static void ad4062_trigger_work(struct work_struct *work)
601
+
{
602
+
struct ad4062_state *st =
603
+
container_of(work, struct ad4062_state, trig_conv);
604
+
int ret;
605
+
606
+
/*
607
+
* Read current conversion, if at reg CONV_READ, stop bit triggers
608
+
* next sample and does not need writing the address.
609
+
*/
610
+
struct i3c_xfer xfer_sample = {
611
+
.data.in = &st->buf.be32,
612
+
.len = st->conv_sizeof,
613
+
.rnw = true,
614
+
};
615
+
struct i3c_xfer xfer_trigger = {
616
+
.data.out = &st->conv_addr,
617
+
.len = sizeof(st->conv_addr),
618
+
.rnw = false,
619
+
};
620
+
621
+
ret = i3c_device_do_xfers(st->i3cdev, &xfer_sample, 1, I3C_SDR);
622
+
if (ret)
623
+
return;
624
+
625
+
iio_push_to_buffers_with_ts(st->indio_dev, &st->buf.be32, st->conv_sizeof,
626
+
iio_get_time_ns(st->indio_dev));
627
+
if (st->gpo_irq[1])
628
+
return;
629
+
630
+
i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR);
631
+
}
632
+
633
+
static irqreturn_t ad4062_poll_handler(int irq, void *p)
634
+
{
635
+
struct iio_poll_func *pf = p;
636
+
struct iio_dev *indio_dev = pf->indio_dev;
637
+
struct ad4062_state *st = iio_priv(indio_dev);
638
+
639
+
iio_trigger_notify_done(indio_dev->trig);
640
+
schedule_work(&st->trig_conv);
641
+
642
+
return IRQ_HANDLED;
643
+
}
644
+
645
+
static void ad4062_disable_ibi(void *data)
646
+
{
647
+
struct i3c_device *i3cdev = data;
648
+
649
+
i3c_device_disable_ibi(i3cdev);
650
+
}
651
+
652
+
static void ad4062_free_ibi(void *data)
653
+
{
654
+
struct i3c_device *i3cdev = data;
655
+
656
+
i3c_device_free_ibi(i3cdev);
657
+
}
658
+
659
+
static int ad4062_request_ibi(struct i3c_device *i3cdev)
660
+
{
661
+
const struct i3c_ibi_setup ibireq = {
662
+
.max_payload_len = 1,
663
+
.num_slots = 1,
664
+
.handler = ad4062_ibi_handler,
665
+
};
666
+
int ret;
667
+
668
+
ret = i3c_device_request_ibi(i3cdev, &ibireq);
669
+
if (ret)
670
+
return ret;
671
+
672
+
ret = devm_add_action_or_reset(&i3cdev->dev, ad4062_free_ibi, i3cdev);
673
+
if (ret)
674
+
return ret;
675
+
676
+
ret = i3c_device_enable_ibi(i3cdev);
677
+
if (ret)
678
+
return ret;
679
+
680
+
return devm_add_action_or_reset(&i3cdev->dev, ad4062_disable_ibi, i3cdev);
681
+
}
682
+
683
+
static int ad4062_request_irq(struct iio_dev *indio_dev)
684
+
{
685
+
struct ad4062_state *st = iio_priv(indio_dev);
686
+
struct device *dev = &st->i3cdev->dev;
687
+
int ret;
688
+
689
+
ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp0");
690
+
if (ret == -EPROBE_DEFER)
691
+
return ret;
692
+
693
+
if (ret < 0) {
694
+
st->gpo_irq[0] = false;
695
+
ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,
696
+
AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN,
697
+
AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN);
698
+
if (ret)
699
+
return ret;
700
+
} else {
701
+
st->gpo_irq[0] = true;
702
+
ret = devm_request_threaded_irq(dev, ret, NULL,
703
+
ad4062_irq_handler_thresh,
704
+
IRQF_ONESHOT, indio_dev->name,
705
+
indio_dev);
706
+
if (ret)
707
+
return ret;
708
+
}
709
+
710
+
ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1");
711
+
if (ret == -EPROBE_DEFER)
712
+
return ret;
713
+
714
+
if (ret < 0) {
715
+
st->gpo_irq[1] = false;
716
+
return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,
717
+
AD4062_REG_ADC_IBI_EN_CONV_TRIGGER,
718
+
AD4062_REG_ADC_IBI_EN_CONV_TRIGGER);
719
+
}
720
+
st->gpo_irq[1] = true;
721
+
722
+
return devm_request_threaded_irq(dev, ret,
723
+
ad4062_irq_handler_drdy,
724
+
NULL, IRQF_ONESHOT, indio_dev->name,
725
+
indio_dev);
726
+
}
727
+
728
+
static const struct iio_trigger_ops ad4062_trigger_ops = {
729
+
.validate_device = &iio_trigger_validate_own_device,
730
+
};
731
+
732
+
static int ad4062_request_trigger(struct iio_dev *indio_dev)
733
+
{
734
+
struct ad4062_state *st = iio_priv(indio_dev);
735
+
struct device *dev = &st->i3cdev->dev;
736
+
int ret;
737
+
738
+
st->trigger = devm_iio_trigger_alloc(dev, "%s-dev%d",
739
+
indio_dev->name,
740
+
iio_device_id(indio_dev));
741
+
if (!st->trigger)
742
+
return -ENOMEM;
743
+
744
+
st->trigger->ops = &ad4062_trigger_ops;
745
+
iio_trigger_set_drvdata(st->trigger, indio_dev);
746
+
747
+
ret = devm_iio_trigger_register(dev, st->trigger);
748
+
if (ret)
749
+
return ret;
750
+
751
+
indio_dev->trig = iio_trigger_get(st->trigger);
752
+
753
+
return 0;
754
+
}
755
+
756
+
static const int ad4062_oversampling_avail[] = {
757
+
1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */
758
+
256, 512, 1024, 2048, 4096, /* 8 - 12 */
759
+
};
760
+
761
+
static int ad4062_read_avail(struct iio_dev *indio_dev,
762
+
struct iio_chan_spec const *chan, const int **vals,
763
+
int *type, int *len, long mask)
764
+
{
765
+
struct ad4062_state *st = iio_priv(indio_dev);
766
+
int ret;
767
+
768
+
switch (mask) {
769
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
770
+
*vals = ad4062_oversampling_avail;
771
+
*len = ARRAY_SIZE(ad4062_oversampling_avail);
772
+
*len -= st->chip->avg_max == 256 ? 4 : 0;
773
+
*type = IIO_VAL_INT;
774
+
775
+
return IIO_AVAIL_LIST;
776
+
case IIO_CHAN_INFO_SAMP_FREQ:
777
+
ret = ad4062_populate_sampling_frequency(st);
778
+
if (ret)
779
+
return ret;
780
+
*vals = st->samp_freqs;
781
+
*len = st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1;
782
+
*type = IIO_VAL_INT;
783
+
784
+
return IIO_AVAIL_LIST;
785
+
default:
786
+
return -EINVAL;
787
+
}
788
+
}
789
+
790
+
static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int *val2)
791
+
{
792
+
struct ad4062_state *st = iio_priv(indio_dev);
793
+
const struct iio_scan_type *scan_type;
794
+
795
+
/*
796
+
* In burst averaging mode the averaging filter accumulates resulting
797
+
* in a sample with increased precision.
798
+
*/
799
+
scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels);
800
+
if (IS_ERR(scan_type))
801
+
return PTR_ERR(scan_type);
802
+
803
+
*val = (st->vref_uV * 2) / (MICRO / MILLI); /* signed */
804
+
*val2 = scan_type->realbits - 1;
805
+
806
+
return IIO_VAL_FRACTIONAL_LOG2;
807
+
}
808
+
809
+
static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2)
810
+
{
811
+
int ret;
812
+
813
+
ret = regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL,
814
+
&st->buf.be16, sizeof(st->buf.be16));
815
+
if (ret)
816
+
return ret;
817
+
818
+
/* From datasheet: code out = code in × mon_val/0x8000 */
819
+
*val = be16_to_cpu(st->buf.be16) * 2;
820
+
*val2 = 16;
821
+
822
+
return IIO_VAL_FRACTIONAL_LOG2;
823
+
}
824
+
825
+
static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_int,
826
+
int gain_frac)
827
+
{
828
+
/* Divide numerator and denumerator by known great common divider */
829
+
const u32 mon_val = AD4062_MON_VAL_MIDDLE_POINT / 64;
830
+
const u32 micro = MICRO / 64;
831
+
const u32 gain_fp = gain_int * MICRO + gain_frac;
832
+
const u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro);
833
+
int ret;
834
+
835
+
/* Checks if the gain is in range and the value fits the field */
836
+
if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1)
837
+
return -EINVAL;
838
+
839
+
st->buf.be16 = cpu_to_be16(reg_val);
840
+
ret = regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL,
841
+
&st->buf.be16, sizeof(st->buf.be16));
842
+
if (ret)
843
+
return ret;
844
+
845
+
/* Enable scale if gain is not equal to one */
846
+
return regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG,
847
+
AD4062_REG_ADC_CONFIG_SCALE_EN_MSK,
848
+
FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK,
849
+
!(gain_int == 1 && gain_frac == 0)));
850
+
}
851
+
852
+
static int ad4062_read_chan_raw(struct ad4062_state *st, int *val)
853
+
{
854
+
struct i3c_device *i3cdev = st->i3cdev;
855
+
struct i3c_xfer xfer_trigger = {
856
+
.data.out = &st->conv_addr,
857
+
.len = sizeof(st->conv_addr),
858
+
.rnw = false,
859
+
};
860
+
struct i3c_xfer xfer_sample = {
861
+
.data.in = &st->buf.be32,
862
+
.len = sizeof(st->buf.be32),
863
+
.rnw = true,
864
+
};
865
+
int ret;
866
+
867
+
PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);
868
+
ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
869
+
if (ret)
870
+
return ret;
871
+
872
+
ret = ad4062_set_operation_mode(st, st->mode);
873
+
if (ret)
874
+
return ret;
875
+
876
+
reinit_completion(&st->completion);
877
+
/* Change address pointer to trigger conversion */
878
+
st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS;
879
+
ret = i3c_device_do_xfers(i3cdev, &xfer_trigger, 1, I3C_SDR);
880
+
if (ret)
881
+
return ret;
882
+
/*
883
+
* Single sample read should be used only for oversampling and
884
+
* sampling frequency pairs that take less than 1 sec.
885
+
*/
886
+
ret = wait_for_completion_timeout(&st->completion,
887
+
msecs_to_jiffies(1000));
888
+
if (!ret)
889
+
return -ETIMEDOUT;
890
+
891
+
ret = i3c_device_do_xfers(i3cdev, &xfer_sample, 1, I3C_SDR);
892
+
if (ret)
893
+
return ret;
894
+
*val = be32_to_cpu(st->buf.be32);
895
+
return 0;
896
+
}
897
+
898
+
static int ad4062_read_raw_dispatch(struct ad4062_state *st,
899
+
int *val, int *val2, long info)
900
+
{
901
+
if (st->wait_event)
902
+
return -EBUSY;
903
+
904
+
switch (info) {
905
+
case IIO_CHAN_INFO_RAW:
906
+
return ad4062_read_chan_raw(st, val);
907
+
908
+
case IIO_CHAN_INFO_CALIBSCALE:
909
+
return ad4062_get_chan_calibscale(st, val, val2);
910
+
911
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
912
+
return ad4062_get_oversampling_ratio(st, val);
913
+
914
+
default:
915
+
return -EINVAL;
916
+
}
917
+
}
918
+
919
+
static int ad4062_read_raw(struct iio_dev *indio_dev,
920
+
struct iio_chan_spec const *chan,
921
+
int *val, int *val2, long info)
922
+
{
923
+
struct ad4062_state *st = iio_priv(indio_dev);
924
+
int ret;
925
+
926
+
switch (info) {
927
+
case IIO_CHAN_INFO_SCALE:
928
+
return ad4062_get_chan_scale(indio_dev, val, val2);
929
+
930
+
case IIO_CHAN_INFO_SAMP_FREQ:
931
+
return ad4062_get_sampling_frequency(st, val);
932
+
}
933
+
934
+
if (!iio_device_claim_direct(indio_dev))
935
+
return -EBUSY;
936
+
937
+
ret = ad4062_read_raw_dispatch(st, val, val2, info);
938
+
iio_device_release_direct(indio_dev);
939
+
return ret ?: IIO_VAL_INT;
940
+
}
941
+
942
+
static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int val2,
943
+
long info)
944
+
{
945
+
if (st->wait_event)
946
+
return -EBUSY;
947
+
948
+
switch (info) {
949
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
950
+
return ad4062_set_oversampling_ratio(st, val, val2);
951
+
952
+
case IIO_CHAN_INFO_CALIBSCALE:
953
+
return ad4062_set_chan_calibscale(st, val, val2);
954
+
955
+
default:
956
+
return -EINVAL;
957
+
}
958
+
};
959
+
960
+
static int ad4062_write_raw(struct iio_dev *indio_dev,
961
+
struct iio_chan_spec const *chan, int val,
962
+
int val2, long info)
963
+
{
964
+
struct ad4062_state *st = iio_priv(indio_dev);
965
+
int ret;
966
+
967
+
switch (info) {
968
+
case IIO_CHAN_INFO_SAMP_FREQ:
969
+
return ad4062_set_sampling_frequency(st, val, val2);
970
+
}
971
+
972
+
if (!iio_device_claim_direct(indio_dev))
973
+
return -EBUSY;
974
+
975
+
ret = ad4062_write_raw_dispatch(st, val, val2, info);
976
+
iio_device_release_direct(indio_dev);
977
+
return ret;
978
+
}
979
+
980
+
static int pm_ad4062_monitor_mode_enable(struct ad4062_state *st)
981
+
{
982
+
int ret;
983
+
984
+
PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);
985
+
ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
986
+
if (ret)
987
+
return ret;
988
+
989
+
return ad4062_set_operation_mode(st, AD4062_MONITOR_MODE);
990
+
}
991
+
992
+
static int ad4062_monitor_mode_enable(struct ad4062_state *st)
993
+
{
994
+
int ret;
995
+
996
+
ret = pm_ad4062_monitor_mode_enable(st);
997
+
if (ret)
998
+
return ret;
999
+
1000
+
pm_runtime_get_noresume(&st->i3cdev->dev);
1001
+
return 0;
1002
+
}
1003
+
1004
+
static int ad4062_monitor_mode_disable(struct ad4062_state *st)
1005
+
{
1006
+
pm_runtime_put_autosuspend(&st->i3cdev->dev);
1007
+
return 0;
1008
+
}
1009
+
1010
+
static int ad4062_read_event_config(struct iio_dev *indio_dev,
1011
+
const struct iio_chan_spec *chan,
1012
+
enum iio_event_type type,
1013
+
enum iio_event_direction dir)
1014
+
{
1015
+
struct ad4062_state *st = iio_priv(indio_dev);
1016
+
1017
+
return st->wait_event;
1018
+
}
1019
+
1020
+
static int ad4062_write_event_config_dispatch(struct iio_dev *indio_dev,
1021
+
bool state)
1022
+
{
1023
+
struct ad4062_state *st = iio_priv(indio_dev);
1024
+
int ret;
1025
+
1026
+
if (st->wait_event == state)
1027
+
ret = 0;
1028
+
else if (state)
1029
+
ret = ad4062_monitor_mode_enable(st);
1030
+
else
1031
+
ret = ad4062_monitor_mode_disable(st);
1032
+
if (ret)
1033
+
return ret;
1034
+
1035
+
st->wait_event = state;
1036
+
return 0;
1037
+
}
1038
+
1039
+
static int ad4062_write_event_config(struct iio_dev *indio_dev,
1040
+
const struct iio_chan_spec *chan,
1041
+
enum iio_event_type type,
1042
+
enum iio_event_direction dir,
1043
+
bool state)
1044
+
{
1045
+
int ret;
1046
+
1047
+
if (!iio_device_claim_direct(indio_dev))
1048
+
return -EBUSY;
1049
+
1050
+
ret = ad4062_write_event_config_dispatch(indio_dev, state);
1051
+
iio_device_release_direct(indio_dev);
1052
+
return ret;
1053
+
}
1054
+
1055
+
static int __ad4062_read_event_info_value(struct ad4062_state *st,
1056
+
enum iio_event_direction dir, int *val)
1057
+
{
1058
+
int ret;
1059
+
u8 reg;
1060
+
1061
+
if (dir == IIO_EV_DIR_RISING)
1062
+
reg = AD4062_REG_MAX_LIMIT;
1063
+
else
1064
+
reg = AD4062_REG_MIN_LIMIT;
1065
+
1066
+
ret = regmap_bulk_read(st->regmap, reg, &st->buf.be16,
1067
+
sizeof(st->buf.be16));
1068
+
if (ret)
1069
+
return ret;
1070
+
1071
+
*val = sign_extend32(be16_to_cpu(st->buf.be16), AD4062_LIMIT_BITS - 1);
1072
+
1073
+
return 0;
1074
+
}
1075
+
1076
+
static int __ad4062_read_event_info_hysteresis(struct ad4062_state *st,
1077
+
enum iio_event_direction dir, int *val)
1078
+
{
1079
+
u8 reg;
1080
+
1081
+
if (dir == IIO_EV_DIR_RISING)
1082
+
reg = AD4062_REG_MAX_HYST;
1083
+
else
1084
+
reg = AD4062_REG_MIN_HYST;
1085
+
return regmap_read(st->regmap, reg, val);
1086
+
}
1087
+
1088
+
static int ad4062_read_event_config_dispatch(struct iio_dev *indio_dev,
1089
+
enum iio_event_direction dir,
1090
+
enum iio_event_info info, int *val)
1091
+
{
1092
+
struct ad4062_state *st = iio_priv(indio_dev);
1093
+
1094
+
if (st->wait_event)
1095
+
return -EBUSY;
1096
+
1097
+
switch (info) {
1098
+
case IIO_EV_INFO_VALUE:
1099
+
return __ad4062_read_event_info_value(st, dir, val);
1100
+
case IIO_EV_INFO_HYSTERESIS:
1101
+
return __ad4062_read_event_info_hysteresis(st, dir, val);
1102
+
default:
1103
+
return -EINVAL;
1104
+
}
1105
+
}
1106
+
1107
+
static int ad4062_read_event_value(struct iio_dev *indio_dev,
1108
+
const struct iio_chan_spec *chan,
1109
+
enum iio_event_type type,
1110
+
enum iio_event_direction dir,
1111
+
enum iio_event_info info, int *val,
1112
+
int *val2)
1113
+
{
1114
+
int ret;
1115
+
1116
+
if (!iio_device_claim_direct(indio_dev))
1117
+
return -EBUSY;
1118
+
1119
+
ret = ad4062_read_event_config_dispatch(indio_dev, dir, info, val);
1120
+
iio_device_release_direct(indio_dev);
1121
+
return ret ?: IIO_VAL_INT;
1122
+
}
1123
+
1124
+
static int __ad4062_write_event_info_value(struct ad4062_state *st,
1125
+
enum iio_event_direction dir, int val)
1126
+
{
1127
+
u8 reg;
1128
+
1129
+
if (val != sign_extend32(val, AD4062_LIMIT_BITS - 1))
1130
+
return -EINVAL;
1131
+
if (dir == IIO_EV_DIR_RISING)
1132
+
reg = AD4062_REG_MAX_LIMIT;
1133
+
else
1134
+
reg = AD4062_REG_MIN_LIMIT;
1135
+
st->buf.be16 = cpu_to_be16(val);
1136
+
1137
+
return regmap_bulk_write(st->regmap, reg, &st->buf.be16,
1138
+
sizeof(st->buf.be16));
1139
+
}
1140
+
1141
+
static int __ad4062_write_event_info_hysteresis(struct ad4062_state *st,
1142
+
enum iio_event_direction dir, int val)
1143
+
{
1144
+
u8 reg;
1145
+
1146
+
if (val > BIT(7) - 1)
1147
+
return -EINVAL;
1148
+
if (dir == IIO_EV_DIR_RISING)
1149
+
reg = AD4062_REG_MAX_HYST;
1150
+
else
1151
+
reg = AD4062_REG_MIN_HYST;
1152
+
1153
+
return regmap_write(st->regmap, reg, val);
1154
+
}
1155
+
1156
+
static int ad4062_write_event_value_dispatch(struct iio_dev *indio_dev,
1157
+
enum iio_event_type type,
1158
+
enum iio_event_direction dir,
1159
+
enum iio_event_info info, int val)
1160
+
{
1161
+
struct ad4062_state *st = iio_priv(indio_dev);
1162
+
1163
+
if (st->wait_event)
1164
+
return -EBUSY;
1165
+
1166
+
switch (type) {
1167
+
case IIO_EV_TYPE_THRESH:
1168
+
switch (info) {
1169
+
case IIO_EV_INFO_VALUE:
1170
+
return __ad4062_write_event_info_value(st, dir, val);
1171
+
case IIO_EV_INFO_HYSTERESIS:
1172
+
return __ad4062_write_event_info_hysteresis(st, dir, val);
1173
+
default:
1174
+
return -EINVAL;
1175
+
}
1176
+
default:
1177
+
return -EINVAL;
1178
+
}
1179
+
}
1180
+
1181
+
static int ad4062_write_event_value(struct iio_dev *indio_dev,
1182
+
const struct iio_chan_spec *chan,
1183
+
enum iio_event_type type,
1184
+
enum iio_event_direction dir,
1185
+
enum iio_event_info info, int val,
1186
+
int val2)
1187
+
{
1188
+
int ret;
1189
+
1190
+
if (!iio_device_claim_direct(indio_dev))
1191
+
return -EBUSY;
1192
+
1193
+
ret = ad4062_write_event_value_dispatch(indio_dev, type, dir, info, val);
1194
+
iio_device_release_direct(indio_dev);
1195
+
return ret;
1196
+
}
1197
+
1198
+
/*
1199
+
* The AD4062 in burst averaging mode increases realbits from 16-bits to
1200
+
* 20-bits, increasing the storagebits from 16-bits to 32-bits.
1201
+
*/
1202
+
static inline size_t ad4062_sizeof_storagebits(struct ad4062_state *st)
1203
+
{
1204
+
const struct iio_scan_type *scan_type =
1205
+
iio_get_current_scan_type(st->indio_dev, st->chip->channels);
1206
+
1207
+
return BITS_TO_BYTES(scan_type->storagebits);
1208
+
}
1209
+
1210
+
/* Read registers only with realbits (no sign extension bytes) */
1211
+
static inline size_t ad4062_get_conv_addr(struct ad4062_state *st, size_t _sizeof)
1212
+
{
1213
+
if (st->gpo_irq[1])
1214
+
return _sizeof == sizeof(u32) ? AD4062_REG_CONV_READ_32BITS :
1215
+
AD4062_REG_CONV_READ_16BITS;
1216
+
return _sizeof == sizeof(u32) ? AD4062_REG_CONV_TRIGGER_32BITS :
1217
+
AD4062_REG_CONV_TRIGGER_16BITS;
1218
+
}
1219
+
1220
+
static int pm_ad4062_triggered_buffer_postenable(struct ad4062_state *st)
1221
+
{
1222
+
int ret;
1223
+
1224
+
PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm);
1225
+
ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
1226
+
if (ret)
1227
+
return ret;
1228
+
1229
+
if (st->wait_event)
1230
+
return -EBUSY;
1231
+
1232
+
ret = ad4062_set_operation_mode(st, st->mode);
1233
+
if (ret)
1234
+
return ret;
1235
+
1236
+
st->conv_sizeof = ad4062_sizeof_storagebits(st);
1237
+
st->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof);
1238
+
/* CONV_READ requires read to trigger first sample. */
1239
+
struct i3c_xfer xfer_sample[2] = {
1240
+
{
1241
+
.data.out = &st->conv_addr,
1242
+
.len = sizeof(st->conv_addr),
1243
+
.rnw = false,
1244
+
},
1245
+
{
1246
+
.data.in = &st->buf.be32,
1247
+
.len = sizeof(st->buf.be32),
1248
+
.rnw = true,
1249
+
}
1250
+
};
1251
+
1252
+
return i3c_device_do_xfers(st->i3cdev, xfer_sample,
1253
+
st->gpo_irq[1] ? 2 : 1, I3C_SDR);
1254
+
}
1255
+
1256
+
static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev)
1257
+
{
1258
+
struct ad4062_state *st = iio_priv(indio_dev);
1259
+
int ret;
1260
+
1261
+
ret = pm_ad4062_triggered_buffer_postenable(st);
1262
+
if (ret)
1263
+
return ret;
1264
+
1265
+
pm_runtime_get_noresume(&st->i3cdev->dev);
1266
+
return 0;
1267
+
}
1268
+
1269
+
static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev)
1270
+
{
1271
+
struct ad4062_state *st = iio_priv(indio_dev);
1272
+
1273
+
pm_runtime_put_autosuspend(&st->i3cdev->dev);
1274
+
return 0;
1275
+
}
1276
+
1277
+
static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops = {
1278
+
.postenable = &ad4062_triggered_buffer_postenable,
1279
+
.predisable = &ad4062_triggered_buffer_predisable,
1280
+
};
1281
+
1282
+
static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1283
+
unsigned int writeval, unsigned int *readval)
1284
+
{
1285
+
struct ad4062_state *st = iio_priv(indio_dev);
1286
+
1287
+
if (readval)
1288
+
return regmap_read(st->regmap, reg, readval);
1289
+
else
1290
+
return regmap_write(st->regmap, reg, writeval);
1291
+
}
1292
+
1293
+
static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev,
1294
+
const struct iio_chan_spec *chan)
1295
+
{
1296
+
struct ad4062_state *st = iio_priv(indio_dev);
1297
+
1298
+
return st->mode == AD4062_BURST_AVERAGING_MODE ?
1299
+
AD4062_SCAN_TYPE_BURST_AVG :
1300
+
AD4062_SCAN_TYPE_SAMPLE;
1301
+
}
1302
+
1303
+
static const struct iio_info ad4062_info = {
1304
+
.read_raw = ad4062_read_raw,
1305
+
.write_raw = ad4062_write_raw,
1306
+
.read_avail = ad4062_read_avail,
1307
+
.read_event_config = ad4062_read_event_config,
1308
+
.write_event_config = ad4062_write_event_config,
1309
+
.read_event_value = ad4062_read_event_value,
1310
+
.write_event_value = ad4062_write_event_value,
1311
+
.event_attrs = &ad4062_event_attribute_group,
1312
+
.get_current_scan_type = ad4062_get_current_scan_type,
1313
+
.debugfs_reg_access = ad4062_debugfs_reg_access,
1314
+
};
1315
+
1316
+
static const struct regmap_config ad4062_regmap_config = {
1317
+
.name = "ad4062",
1318
+
.reg_bits = 8,
1319
+
.val_bits = 8,
1320
+
.max_register = AD4062_MAX_REG,
1321
+
.rd_table = &ad4062_regmap_rd_table,
1322
+
.wr_table = &ad4062_regmap_wr_table,
1323
+
.can_sleep = true,
1324
+
};
1325
+
1326
+
static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel)
1327
+
{
1328
+
struct device *dev = &st->i3cdev->dev;
1329
+
int ret;
1330
+
1331
+
ret = devm_regulator_get_enable(dev, "vio");
1332
+
if (ret)
1333
+
return dev_err_probe(dev, ret, "Failed to enable vio voltage\n");
1334
+
1335
+
st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref");
1336
+
*ref_sel = st->vref_uV == -ENODEV;
1337
+
if (st->vref_uV < 0 && !*ref_sel)
1338
+
return dev_err_probe(dev, st->vref_uV,
1339
+
"Failed to enable and read ref voltage\n");
1340
+
1341
+
if (*ref_sel) {
1342
+
st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "vdd");
1343
+
if (st->vref_uV < 0)
1344
+
return dev_err_probe(dev, st->vref_uV,
1345
+
"Failed to enable and read vdd voltage\n");
1346
+
} else {
1347
+
ret = devm_regulator_get_enable(dev, "vdd");
1348
+
if (ret)
1349
+
return dev_err_probe(dev, ret,
1350
+
"Failed to enable vdd regulator\n");
1351
+
}
1352
+
1353
+
return 0;
1354
+
}
1355
+
1356
+
static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1357
+
{
1358
+
return GPIO_LINE_DIRECTION_OUT;
1359
+
}
1360
+
1361
+
static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1362
+
{
1363
+
struct ad4062_state *st = gpiochip_get_data(gc);
1364
+
unsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW;
1365
+
1366
+
if (offset)
1367
+
return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
1368
+
AD4062_REG_GP_CONF_MODE_MSK_1,
1369
+
FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val));
1370
+
else
1371
+
return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
1372
+
AD4062_REG_GP_CONF_MODE_MSK_0,
1373
+
FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val));
1374
+
}
1375
+
1376
+
static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset)
1377
+
{
1378
+
struct ad4062_state *st = gpiochip_get_data(gc);
1379
+
unsigned int reg_val;
1380
+
int ret;
1381
+
1382
+
ret = regmap_read(st->regmap, AD4062_REG_GP_CONF, ®_val);
1383
+
if (ret)
1384
+
return ret;
1385
+
1386
+
if (offset)
1387
+
reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val);
1388
+
else
1389
+
reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val);
1390
+
1391
+
return reg_val == AD4062_GP_STATIC_HIGH;
1392
+
}
1393
+
1394
+
static void ad4062_gpio_disable(void *data)
1395
+
{
1396
+
struct ad4062_state *st = data;
1397
+
u8 val = FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) |
1398
+
FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED);
1399
+
1400
+
regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
1401
+
AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0,
1402
+
val);
1403
+
}
1404
+
1405
+
static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc,
1406
+
unsigned long *valid_mask,
1407
+
unsigned int ngpios)
1408
+
{
1409
+
struct ad4062_state *st = gpiochip_get_data(gc);
1410
+
1411
+
bitmap_zero(valid_mask, ngpios);
1412
+
1413
+
for (unsigned int i = 0; i < ARRAY_SIZE(st->gpo_irq); i++)
1414
+
__assign_bit(i, valid_mask, !st->gpo_irq[i]);
1415
+
1416
+
return 0;
1417
+
}
1418
+
1419
+
static int ad4062_gpio_init(struct ad4062_state *st)
1420
+
{
1421
+
struct device *dev = &st->i3cdev->dev;
1422
+
struct gpio_chip *gc;
1423
+
u8 val, mask;
1424
+
int ret;
1425
+
1426
+
if (!device_property_read_bool(dev, "gpio-controller"))
1427
+
return 0;
1428
+
1429
+
gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1430
+
if (!gc)
1431
+
return -ENOMEM;
1432
+
1433
+
val = 0;
1434
+
mask = 0;
1435
+
if (!st->gpo_irq[0]) {
1436
+
mask |= AD4062_REG_GP_CONF_MODE_MSK_0;
1437
+
val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW);
1438
+
}
1439
+
if (!st->gpo_irq[1]) {
1440
+
mask |= AD4062_REG_GP_CONF_MODE_MSK_1;
1441
+
val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW);
1442
+
}
1443
+
1444
+
ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,
1445
+
mask, val);
1446
+
if (ret)
1447
+
return ret;
1448
+
1449
+
ret = devm_add_action_or_reset(dev, ad4062_gpio_disable, st);
1450
+
if (ret)
1451
+
return ret;
1452
+
1453
+
gc->parent = dev;
1454
+
gc->label = st->chip->name;
1455
+
gc->owner = THIS_MODULE;
1456
+
gc->base = -1;
1457
+
gc->ngpio = 2;
1458
+
gc->init_valid_mask = ad4062_gpio_init_valid_mask;
1459
+
gc->get_direction = ad4062_gpio_get_direction;
1460
+
gc->set = ad4062_gpio_set;
1461
+
gc->get = ad4062_gpio_get;
1462
+
gc->can_sleep = true;
1463
+
1464
+
ret = devm_gpiochip_add_data(dev, gc, st);
1465
+
if (ret)
1466
+
return dev_err_probe(dev, ret, "Unable to register GPIO chip\n");
1467
+
1468
+
return 0;
1469
+
}
1470
+
1471
+
static const struct i3c_device_id ad4062_id_table[] = {
1472
+
I3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info),
1473
+
I3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info),
1474
+
{ }
1475
+
};
1476
+
MODULE_DEVICE_TABLE(i3c, ad4062_id_table);
1477
+
1478
+
static int ad4062_probe(struct i3c_device *i3cdev)
1479
+
{
1480
+
const struct i3c_device_id *id = i3c_device_match_id(i3cdev, ad4062_id_table);
1481
+
const struct ad4062_chip_info *chip = id->data;
1482
+
struct device *dev = &i3cdev->dev;
1483
+
struct iio_dev *indio_dev;
1484
+
struct ad4062_state *st;
1485
+
bool ref_sel;
1486
+
int ret;
1487
+
1488
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1489
+
if (!indio_dev)
1490
+
return -ENOMEM;
1491
+
1492
+
st = iio_priv(indio_dev);
1493
+
st->i3cdev = i3cdev;
1494
+
i3cdev_set_drvdata(i3cdev, st);
1495
+
init_completion(&st->completion);
1496
+
1497
+
ret = ad4062_regulators_get(st, &ref_sel);
1498
+
if (ret)
1499
+
return ret;
1500
+
1501
+
st->regmap = devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config);
1502
+
if (IS_ERR(st->regmap))
1503
+
return dev_err_probe(dev, PTR_ERR(st->regmap),
1504
+
"Failed to initialize regmap\n");
1505
+
1506
+
st->mode = AD4062_SAMPLE_MODE;
1507
+
st->wait_event = false;
1508
+
st->chip = chip;
1509
+
st->sampling_frequency = 0;
1510
+
st->events_frequency = 0;
1511
+
st->oversamp_ratio = 0;
1512
+
st->indio_dev = indio_dev;
1513
+
1514
+
indio_dev->modes = INDIO_DIRECT_MODE;
1515
+
indio_dev->num_channels = 1;
1516
+
indio_dev->info = &ad4062_info;
1517
+
indio_dev->name = chip->name;
1518
+
indio_dev->channels = chip->channels;
1519
+
1520
+
ret = ad4062_soft_reset(st);
1521
+
if (ret)
1522
+
return dev_err_probe(dev, ret, "AD4062 failed to soft reset\n");
1523
+
1524
+
ret = ad4062_check_ids(st);
1525
+
if (ret)
1526
+
return ret;
1527
+
1528
+
ret = ad4062_setup(indio_dev, indio_dev->channels, &ref_sel);
1529
+
if (ret)
1530
+
return ret;
1531
+
1532
+
ret = ad4062_request_irq(indio_dev);
1533
+
if (ret)
1534
+
return ret;
1535
+
1536
+
ret = ad4062_request_trigger(indio_dev);
1537
+
if (ret)
1538
+
return ret;
1539
+
1540
+
ret = devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev,
1541
+
iio_pollfunc_store_time,
1542
+
ad4062_poll_handler,
1543
+
&ad4062_triggered_buffer_setup_ops);
1544
+
if (ret)
1545
+
return ret;
1546
+
1547
+
pm_runtime_set_active(dev);
1548
+
ret = devm_pm_runtime_enable(dev);
1549
+
if (ret)
1550
+
return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n");
1551
+
1552
+
pm_runtime_set_autosuspend_delay(dev, 1000);
1553
+
pm_runtime_use_autosuspend(dev);
1554
+
1555
+
ret = ad4062_request_ibi(i3cdev);
1556
+
if (ret)
1557
+
return dev_err_probe(dev, ret, "Failed to request i3c ibi\n");
1558
+
1559
+
ret = ad4062_gpio_init(st);
1560
+
if (ret)
1561
+
return ret;
1562
+
1563
+
ret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work);
1564
+
if (ret)
1565
+
return ret;
1566
+
1567
+
return devm_iio_device_register(dev, indio_dev);
1568
+
}
1569
+
1570
+
static int ad4062_runtime_suspend(struct device *dev)
1571
+
{
1572
+
struct ad4062_state *st = dev_get_drvdata(dev);
1573
+
1574
+
return regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG,
1575
+
FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK,
1576
+
AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE));
1577
+
}
1578
+
1579
+
static int ad4062_runtime_resume(struct device *dev)
1580
+
{
1581
+
struct ad4062_state *st = dev_get_drvdata(dev);
1582
+
int ret;
1583
+
1584
+
ret = regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG,
1585
+
AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK);
1586
+
if (ret)
1587
+
return ret;
1588
+
1589
+
/* Wait device functional blocks to power up */
1590
+
fsleep(3 * USEC_PER_MSEC);
1591
+
return 0;
1592
+
}
1593
+
1594
+
static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops,
1595
+
ad4062_runtime_suspend, ad4062_runtime_resume, NULL);
1596
+
1597
+
static struct i3c_driver ad4062_driver = {
1598
+
.driver = {
1599
+
.name = "ad4062",
1600
+
.pm = pm_ptr(&ad4062_pm_ops),
1601
+
},
1602
+
.probe = ad4062_probe,
1603
+
.id_table = ad4062_id_table,
1604
+
};
1605
+
module_i3c_driver(ad4062_driver);
1606
+
1607
+
MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>");
1608
+
MODULE_DESCRIPTION("Analog Devices AD4062");
1609
+
MODULE_LICENSE("GPL");
+500
drivers/iio/adc/ad4134.c
+500
drivers/iio/adc/ad4134.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (C) 2026 Analog Devices, Inc.
4
+
* Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
5
+
*/
6
+
7
+
#include <linux/array_size.h>
8
+
#include <linux/bitfield.h>
9
+
#include <linux/bitops.h>
10
+
#include <linux/clk.h>
11
+
#include <linux/crc8.h>
12
+
#include <linux/delay.h>
13
+
#include <linux/dev_printk.h>
14
+
#include <linux/err.h>
15
+
#include <linux/export.h>
16
+
#include <linux/gpio/consumer.h>
17
+
#include <linux/iio/iio.h>
18
+
#include <linux/iio/types.h>
19
+
#include <linux/module.h>
20
+
#include <linux/mod_devicetable.h>
21
+
#include <linux/regmap.h>
22
+
#include <linux/regulator/consumer.h>
23
+
#include <linux/reset.h>
24
+
#include <linux/spi/spi.h>
25
+
#include <linux/time.h>
26
+
#include <linux/types.h>
27
+
#include <linux/unaligned.h>
28
+
#include <linux/units.h>
29
+
30
+
#define AD4134_RESET_TIME_US (10 * USEC_PER_SEC)
31
+
32
+
#define AD4134_REG_READ_MASK BIT(7)
33
+
#define AD4134_SPI_MAX_XFER_LEN 3
34
+
35
+
#define AD4134_EXT_CLOCK_MHZ (48 * HZ_PER_MHZ)
36
+
37
+
#define AD4134_NUM_CHANNELS 4
38
+
#define AD4134_CHAN_PRECISION_BITS 24
39
+
40
+
#define AD4134_IFACE_CONFIG_A_REG 0x00
41
+
#define AD4134_IFACE_CONFIG_B_REG 0x01
42
+
#define AD4134_IFACE_CONFIG_B_SINGLE_INSTR BIT(7)
43
+
44
+
#define AD4134_DEVICE_CONFIG_REG 0x02
45
+
#define AD4134_DEVICE_CONFIG_POWER_MODE_MASK BIT(0)
46
+
#define AD4134_POWER_MODE_HIGH_PERF 0x1
47
+
48
+
#define AD4134_SILICON_REV_REG 0x07
49
+
#define AD4134_SCRATCH_PAD_REG 0x0A
50
+
#define AD4134_STREAM_MODE_REG 0x0E
51
+
#define AD4134_SDO_PIN_SRC_SEL_REG 0x10
52
+
#define AD4134_SDO_PIN_SRC_SEL_SDO_SEL_MASK BIT(2)
53
+
54
+
#define AD4134_DATA_PACKET_CONFIG_REG 0x11
55
+
#define AD4134_DATA_PACKET_CONFIG_FRAME_MASK GENMASK(5, 4)
56
+
#define AD4134_DATA_PACKET_24BIT_FRAME 0x2
57
+
58
+
#define AD4134_DIG_IF_CFG_REG 0x12
59
+
#define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0)
60
+
#define AD4134_DATA_FORMAT_SINGLE_CH_MODE 0x0
61
+
62
+
#define AD4134_PW_DOWN_CTRL_REG 0x13
63
+
#define AD4134_DEVICE_STATUS_REG 0x15
64
+
#define AD4134_ODR_VAL_INT_LSB_REG 0x16
65
+
#define AD4134_CH3_OFFSET_MSB_REG 0x3E
66
+
#define AD4134_AIN_OR_ERROR_REG 0x48
67
+
68
+
/*
69
+
* AD4134 register map ends at address 0x48 and there is no register for
70
+
* retrieving ADC sample data. Though, to make use of Linux regmap API both
71
+
* for register access and sample read, we define one virtual register for each
72
+
* ADC channel. AD4134_CH_VREG(x) maps a channel number to it's virtual register
73
+
* address while AD4134_VREG_CH(x) tells which channel given the address.
74
+
*/
75
+
#define AD4134_CH_VREG(x) ((x) + 0x50)
76
+
#define AD4134_VREG_CH(x) ((x) - 0x50)
77
+
78
+
#define AD4134_SPI_CRC_POLYNOM 0x07
79
+
#define AD4134_SPI_CRC_INIT_VALUE 0xA5
80
+
static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE];
81
+
82
+
#define AD4134_CHANNEL(_index) { \
83
+
.type = IIO_VOLTAGE, \
84
+
.indexed = 1, \
85
+
.channel = (_index), \
86
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
87
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
88
+
}
89
+
90
+
static const struct iio_chan_spec ad4134_chan_set[] = {
91
+
AD4134_CHANNEL(0),
92
+
AD4134_CHANNEL(1),
93
+
AD4134_CHANNEL(2),
94
+
AD4134_CHANNEL(3),
95
+
};
96
+
97
+
struct ad4134_state {
98
+
struct spi_device *spi;
99
+
struct regmap *regmap;
100
+
unsigned long sys_clk_hz;
101
+
struct gpio_desc *odr_gpio;
102
+
int refin_mv;
103
+
/*
104
+
* DMA (thus cache coherency maintenance) requires the transfer buffers
105
+
* to live in their own cache lines.
106
+
*/
107
+
u8 rx_buf[AD4134_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
108
+
u8 tx_buf[AD4134_SPI_MAX_XFER_LEN];
109
+
};
110
+
111
+
static const struct regmap_range ad4134_regmap_rd_range[] = {
112
+
regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_SILICON_REV_REG),
113
+
regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_PW_DOWN_CTRL_REG),
114
+
regmap_reg_range(AD4134_DEVICE_STATUS_REG, AD4134_AIN_OR_ERROR_REG),
115
+
regmap_reg_range(AD4134_CH_VREG(0), AD4134_CH_VREG(AD4134_NUM_CHANNELS)),
116
+
};
117
+
118
+
static const struct regmap_range ad4134_regmap_wr_range[] = {
119
+
regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_DEVICE_CONFIG_REG),
120
+
regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_SCRATCH_PAD_REG),
121
+
regmap_reg_range(AD4134_STREAM_MODE_REG, AD4134_PW_DOWN_CTRL_REG),
122
+
regmap_reg_range(AD4134_ODR_VAL_INT_LSB_REG, AD4134_CH3_OFFSET_MSB_REG),
123
+
};
124
+
125
+
static const struct regmap_access_table ad4134_regmap_rd_table = {
126
+
.yes_ranges = ad4134_regmap_rd_range,
127
+
.n_yes_ranges = ARRAY_SIZE(ad4134_regmap_rd_range),
128
+
};
129
+
130
+
static const struct regmap_access_table ad4134_regmap_wr_table = {
131
+
.yes_ranges = ad4134_regmap_wr_range,
132
+
.n_yes_ranges = ARRAY_SIZE(ad4134_regmap_wr_range),
133
+
};
134
+
135
+
static int ad4134_calc_spi_crc(u8 inst, u8 data)
136
+
{
137
+
u8 buf[] = { inst, data };
138
+
139
+
return crc8(ad4134_spi_crc_table, buf, ARRAY_SIZE(buf),
140
+
AD4134_SPI_CRC_INIT_VALUE);
141
+
}
142
+
143
+
static void ad4134_prepare_spi_tx_buf(u8 inst, u8 data, u8 *buf)
144
+
{
145
+
buf[0] = inst;
146
+
buf[1] = data;
147
+
buf[2] = ad4134_calc_spi_crc(inst, data);
148
+
}
149
+
150
+
static int ad4134_reg_write(void *context, unsigned int reg, unsigned int val)
151
+
{
152
+
struct ad4134_state *st = context;
153
+
struct spi_transfer xfer = {
154
+
.tx_buf = st->tx_buf,
155
+
.rx_buf = st->rx_buf,
156
+
.len = AD4134_SPI_MAX_XFER_LEN,
157
+
};
158
+
int ret;
159
+
160
+
ad4134_prepare_spi_tx_buf(reg, val, st->tx_buf);
161
+
162
+
ret = spi_sync_transfer(st->spi, &xfer, 1);
163
+
if (ret)
164
+
return ret;
165
+
166
+
if (st->rx_buf[2] != st->tx_buf[2])
167
+
dev_dbg(&st->spi->dev, "reg write CRC check failed\n");
168
+
169
+
return 0;
170
+
}
171
+
172
+
static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
173
+
unsigned int *val)
174
+
{
175
+
unsigned int i;
176
+
int ret;
177
+
178
+
/*
179
+
* To be able to read data from all 4 channels through a single line, we
180
+
* set DOUTx output format to 0 in the digital interface config register
181
+
* (0x12). With that, data from all four channels is serialized and
182
+
* output on DOUT0. During the probe, we also set SDO_PIN_SRC_SEL in
183
+
* DEVICE_CONFIG_1 register to duplicate DOUT0 on the SDO pin. Combined,
184
+
* those configurations enable ADC data read through a conventional SPI
185
+
* interface. Now we read data from all channels but keep only the bits
186
+
* from the requested one.
187
+
*/
188
+
for (i = 0; i < ARRAY_SIZE(ad4134_chan_set); i++) {
189
+
ret = spi_write_then_read(st->spi, NULL, 0, st->rx_buf,
190
+
BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS));
191
+
if (ret)
192
+
return ret;
193
+
194
+
/*
195
+
* AD4134 has a built-in feature that flags when data transfers
196
+
* don't run enough clock cycles to read the entire data frame.
197
+
* Clock out data from all channels to avoid that.
198
+
*/
199
+
if (i == AD4134_VREG_CH(reg))
200
+
*val = get_unaligned_be24(st->rx_buf);
201
+
}
202
+
203
+
return 0;
204
+
}
205
+
206
+
static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
207
+
unsigned int *val)
208
+
{
209
+
struct spi_transfer xfer = {
210
+
.tx_buf = st->tx_buf,
211
+
.rx_buf = st->rx_buf,
212
+
.len = AD4134_SPI_MAX_XFER_LEN,
213
+
};
214
+
unsigned int inst;
215
+
int ret;
216
+
217
+
inst = AD4134_REG_READ_MASK | reg;
218
+
ad4134_prepare_spi_tx_buf(inst, 0, st->tx_buf);
219
+
220
+
ret = spi_sync_transfer(st->spi, &xfer, 1);
221
+
if (ret)
222
+
return ret;
223
+
224
+
*val = st->rx_buf[1];
225
+
226
+
/* Check CRC */
227
+
if (st->rx_buf[2] != st->tx_buf[2])
228
+
dev_dbg(&st->spi->dev, "reg read CRC check failed\n");
229
+
230
+
return 0;
231
+
}
232
+
233
+
static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *val)
234
+
{
235
+
struct ad4134_state *st = context;
236
+
237
+
if (reg >= AD4134_CH_VREG(0))
238
+
return ad4134_data_read(st, reg, val);
239
+
240
+
return ad4134_register_read(st, reg, val);
241
+
}
242
+
243
+
static const struct regmap_config ad4134_regmap_config = {
244
+
.reg_read = ad4134_reg_read,
245
+
.reg_write = ad4134_reg_write,
246
+
.rd_table = &ad4134_regmap_rd_table,
247
+
.wr_table = &ad4134_regmap_wr_table,
248
+
.max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)),
249
+
};
250
+
251
+
static int ad4134_read_raw(struct iio_dev *indio_dev,
252
+
struct iio_chan_spec const *chan,
253
+
int *val, int *val2, long info)
254
+
{
255
+
struct ad4134_state *st = iio_priv(indio_dev);
256
+
int ret;
257
+
258
+
switch (info) {
259
+
case IIO_CHAN_INFO_RAW:
260
+
gpiod_set_value_cansleep(st->odr_gpio, 1);
261
+
/*
262
+
* For slave mode gated DCLK (data sheet page 11), the minimum
263
+
* ODR high time is 3 * tDIGCLK. The internal digital clock
264
+
* period is tDIGCLK = 1/fDIGCLK = 2/fSYSCLK.
265
+
* The System clock frequency (fSYSCLK) is typically 48 MHz.
266
+
* Thus, ODR high time = 3 * (2 / (48 * HZ_PER_MHZ))
267
+
* ODR high time = 0.000000125 s = 125 ns
268
+
* 1 micro second should be more than enough. Not worth it
269
+
* tweaking for shorter dealy since this is not a fast data path.
270
+
*/
271
+
fsleep(1);
272
+
gpiod_set_value_cansleep(st->odr_gpio, 0);
273
+
ret = regmap_read(st->regmap, AD4134_CH_VREG(chan->channel), val);
274
+
if (ret)
275
+
return ret;
276
+
277
+
return IIO_VAL_INT;
278
+
case IIO_CHAN_INFO_SCALE:
279
+
*val = st->refin_mv;
280
+
*val2 = AD4134_CHAN_PRECISION_BITS - 1;
281
+
282
+
return IIO_VAL_FRACTIONAL_LOG2;
283
+
default:
284
+
return -EINVAL;
285
+
}
286
+
}
287
+
288
+
static int ad4134_debugfs_reg_access(struct iio_dev *indio_dev,
289
+
unsigned int reg, unsigned int writeval,
290
+
unsigned int *readval)
291
+
{
292
+
struct ad4134_state *st = iio_priv(indio_dev);
293
+
294
+
if (readval)
295
+
return regmap_read(st->regmap, reg, readval);
296
+
297
+
return regmap_write(st->regmap, reg, writeval);
298
+
}
299
+
300
+
static int ad4134_min_io_mode_setup(struct ad4134_state *st)
301
+
{
302
+
struct device *dev = &st->spi->dev;
303
+
int ret;
304
+
305
+
st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
306
+
if (IS_ERR(st->odr_gpio))
307
+
return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
308
+
"failed to get ODR GPIO\n");
309
+
310
+
ret = regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG,
311
+
AD4134_DIF_IF_CFG_FORMAT_MASK,
312
+
FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK,
313
+
AD4134_DATA_FORMAT_SINGLE_CH_MODE));
314
+
if (ret)
315
+
return dev_err_probe(dev, ret,
316
+
"failed to set single channel mode\n");
317
+
318
+
ret = regmap_set_bits(st->regmap, AD4134_SDO_PIN_SRC_SEL_REG,
319
+
AD4134_SDO_PIN_SRC_SEL_SDO_SEL_MASK);
320
+
if (ret)
321
+
return dev_err_probe(dev, ret,
322
+
"failed to set SDO source selection\n");
323
+
324
+
return regmap_set_bits(st->regmap, AD4134_IFACE_CONFIG_B_REG,
325
+
AD4134_IFACE_CONFIG_B_SINGLE_INSTR);
326
+
}
327
+
328
+
static const struct iio_info ad4134_info = {
329
+
.read_raw = ad4134_read_raw,
330
+
.debugfs_reg_access = ad4134_debugfs_reg_access,
331
+
};
332
+
333
+
static const char * const ad4143_required_regulators[] = {
334
+
"avdd5", "dvdd5", "iovdd",
335
+
};
336
+
337
+
static const char * const ad4143_optional_regulators[] = {
338
+
"avdd1v8", "dvdd1v8", "clkvdd",
339
+
};
340
+
341
+
static int ad4134_regulator_setup(struct ad4134_state *st)
342
+
{
343
+
struct device *dev = &st->spi->dev;
344
+
int ret;
345
+
346
+
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4143_required_regulators),
347
+
ad4143_required_regulators);
348
+
if (ret)
349
+
return dev_err_probe(dev, ret, "failed to enable power supplies\n");
350
+
351
+
/* Required regulator that we need to read the voltage */
352
+
ret = devm_regulator_get_enable_read_voltage(dev, "refin");
353
+
if (ret < 0)
354
+
return dev_err_probe(dev, ret, "failed to get REFIN voltage.\n");
355
+
356
+
st->refin_mv = ret / (MICRO / MILLI);
357
+
358
+
ret = devm_regulator_get_enable_optional(dev, "ldoin");
359
+
if (ret < 0 && ret != -ENODEV)
360
+
return dev_err_probe(dev, ret, "failed to enable ldoin supply\n");
361
+
362
+
/* If ldoin was provided, then use the use the internal LDO regulators */
363
+
if (ret == 0)
364
+
return 0;
365
+
366
+
/*
367
+
* If ldoin is not provided, then avdd1v8, dvdd1v8, and clkvdd are
368
+
* required.
369
+
*/
370
+
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4143_optional_regulators),
371
+
ad4143_optional_regulators);
372
+
if (ret)
373
+
return dev_err_probe(dev, ret, "failed to enable 1V8 power supplies\n");
374
+
375
+
return 0;
376
+
}
377
+
378
+
static int ad4134_clock_select(struct ad4134_state *st)
379
+
{
380
+
struct device *dev = &st->spi->dev;
381
+
struct clk *xtal_clk, *clkin_clk;
382
+
383
+
/*
384
+
* AD4134 requires one external clock source and only one external clock
385
+
* source can be provided at a time. Try to get a crystal provided clock.
386
+
* If that fails, try to get a CMOS clock.
387
+
*/
388
+
xtal_clk = devm_clk_get_optional_enabled(dev, "xtal");
389
+
if (!xtal_clk)
390
+
xtal_clk = devm_clk_get_optional_enabled(dev, "xtal");
391
+
if (IS_ERR(xtal_clk))
392
+
return dev_err_probe(dev, PTR_ERR(xtal_clk),
393
+
"failed to get xtal\n");
394
+
395
+
clkin_clk = devm_clk_get_optional_enabled(dev, "clkin");
396
+
if (!clkin_clk)
397
+
clkin_clk = devm_clk_get_optional_enabled(dev, "clkin");
398
+
if (IS_ERR(clkin_clk))
399
+
return dev_err_probe(dev, PTR_ERR(clkin_clk),
400
+
"failed to get clkin\n");
401
+
402
+
st->sys_clk_hz = clk_get_rate(xtal_clk) | clk_get_rate(clkin_clk);
403
+
if (st->sys_clk_hz != AD4134_EXT_CLOCK_MHZ)
404
+
dev_warn(dev, "invalid external clock frequency %lu\n",
405
+
st->sys_clk_hz);
406
+
407
+
return 0;
408
+
}
409
+
410
+
static int ad4134_probe(struct spi_device *spi)
411
+
{
412
+
struct device *dev = &spi->dev;
413
+
struct reset_control *rst;
414
+
struct iio_dev *indio_dev;
415
+
struct ad4134_state *st;
416
+
int ret;
417
+
418
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
419
+
if (!indio_dev)
420
+
return -ENOMEM;
421
+
422
+
st = iio_priv(indio_dev);
423
+
st->spi = spi;
424
+
425
+
indio_dev->name = "ad4134";
426
+
indio_dev->channels = ad4134_chan_set;
427
+
indio_dev->num_channels = ARRAY_SIZE(ad4134_chan_set);
428
+
indio_dev->modes = INDIO_DIRECT_MODE;
429
+
indio_dev->info = &ad4134_info;
430
+
431
+
ret = ad4134_regulator_setup(st);
432
+
if (ret)
433
+
return ret;
434
+
435
+
ret = ad4134_clock_select(st);
436
+
if (ret)
437
+
return ret;
438
+
439
+
rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
440
+
if (IS_ERR(rst))
441
+
return dev_err_probe(dev, PTR_ERR(rst),
442
+
"failed to get and deassert reset\n");
443
+
444
+
crc8_populate_msb(ad4134_spi_crc_table, AD4134_SPI_CRC_POLYNOM);
445
+
446
+
st->regmap = devm_regmap_init(dev, NULL, st, &ad4134_regmap_config);
447
+
if (IS_ERR(st->regmap))
448
+
return dev_err_probe(dev, PTR_ERR(st->regmap),
449
+
"failed to initialize regmap");
450
+
451
+
ret = ad4134_min_io_mode_setup(st);
452
+
if (ret)
453
+
return dev_err_probe(dev, ret,
454
+
"failed to setup minimum I/O mode\n");
455
+
456
+
/* Bump precision to 24-bit */
457
+
ret = regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG,
458
+
AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
459
+
FIELD_PREP(AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
460
+
AD4134_DATA_PACKET_24BIT_FRAME));
461
+
if (ret)
462
+
return ret;
463
+
464
+
/* Set high performance power mode */
465
+
ret = regmap_update_bits(st->regmap, AD4134_DEVICE_CONFIG_REG,
466
+
AD4134_DEVICE_CONFIG_POWER_MODE_MASK,
467
+
FIELD_PREP(AD4134_DEVICE_CONFIG_POWER_MODE_MASK,
468
+
AD4134_POWER_MODE_HIGH_PERF));
469
+
if (ret)
470
+
return ret;
471
+
472
+
return devm_iio_device_register(dev, indio_dev);
473
+
}
474
+
475
+
static const struct spi_device_id ad4134_id[] = {
476
+
{ "ad4134" },
477
+
{ }
478
+
};
479
+
MODULE_DEVICE_TABLE(spi, ad4134_id);
480
+
481
+
static const struct of_device_id ad4134_of_match[] = {
482
+
{ .compatible = "adi,ad4134" },
483
+
{ }
484
+
};
485
+
MODULE_DEVICE_TABLE(of, ad4134_of_match);
486
+
487
+
static struct spi_driver ad4134_driver = {
488
+
.driver = {
489
+
.name = "ad4134",
490
+
.of_match_table = ad4134_of_match,
491
+
},
492
+
.probe = ad4134_probe,
493
+
.id_table = ad4134_id,
494
+
};
495
+
module_spi_driver(ad4134_driver);
496
+
497
+
MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
498
+
MODULE_DESCRIPTION("Analog Devices AD4134 SPI driver");
499
+
MODULE_LICENSE("GPL");
500
+
MODULE_IMPORT_NS("IIO_AD4134");
+1
-1
drivers/iio/adc/ad4170-4.c
+1
-1
drivers/iio/adc/ad4170-4.c
-1
drivers/iio/adc/ad7476.c
-1
drivers/iio/adc/ad7476.c
+1
-1
drivers/iio/adc/ad7606_spi.c
+1
-1
drivers/iio/adc/ad7606_spi.c
+2
-8
drivers/iio/adc/ad7766.c
+2
-8
drivers/iio/adc/ad7766.c
···
184
184
.read_raw = &ad7766_read_raw,
185
185
};
186
186
187
-
static irqreturn_t ad7766_irq(int irq, void *private)
188
-
{
189
-
iio_trigger_poll(private);
190
-
return IRQ_HANDLED;
191
-
}
192
-
193
187
static int ad7766_set_trigger_state(struct iio_trigger *trig, bool enable)
194
188
{
195
189
struct ad7766 *ad7766 = iio_trigger_get_drvdata(trig);
···
254
260
* Some platforms might not allow the option to power it down so
255
261
* don't enable the interrupt to avoid extra load on the system
256
262
*/
257
-
ret = devm_request_irq(&spi->dev, spi->irq, ad7766_irq,
258
-
IRQF_TRIGGER_FALLING | IRQF_NO_AUTOEN,
263
+
ret = devm_request_irq(&spi->dev, spi->irq, iio_trigger_generic_data_rdy_poll,
264
+
IRQF_TRIGGER_FALLING | IRQF_NO_AUTOEN | IRQF_NO_THREAD,
259
265
dev_name(&spi->dev),
260
266
ad7766->trig);
261
267
if (ret < 0)
+376
-54
drivers/iio/adc/ad7768-1.c
+376
-54
drivers/iio/adc/ad7768-1.c
···
6
6
*/
7
7
#include <linux/array_size.h>
8
8
#include <linux/bitfield.h>
9
+
#include <linux/cleanup.h>
9
10
#include <linux/clk.h>
10
11
#include <linux/completion.h>
11
12
#include <linux/delay.h>
···
15
14
#include <linux/gpio/driver.h>
16
15
#include <linux/gpio/consumer.h>
17
16
#include <linux/interrupt.h>
17
+
#include <linux/limits.h>
18
+
#include <linux/math.h>
18
19
#include <linux/minmax.h>
19
20
#include <linux/module.h>
21
+
#include <linux/mutex.h>
22
+
#include <linux/rational.h>
20
23
#include <linux/regmap.h>
21
24
#include <linux/regulator/consumer.h>
22
25
#include <linux/regulator/driver.h>
···
112
107
113
108
#define AD7768_VCM_OFF 0x07
114
109
110
+
#define ADAQ776X_GAIN_MAX_NANO (128 * NANO)
111
+
#define ADAQ776X_MAX_GAIN_MODES 8
112
+
115
113
#define AD7768_TRIGGER_SOURCE_SYNC_IDX 0
116
114
117
115
#define AD7768_MAX_CHANNELS 1
116
+
117
+
#define ADAQ7768_PGA_PINS 3
118
118
119
119
enum ad7768_conv_mode {
120
120
AD7768_CONTINUOUS,
···
161
151
enum ad7768_scan_type {
162
152
AD7768_SCAN_TYPE_NORMAL,
163
153
AD7768_SCAN_TYPE_HIGH_SPEED,
154
+
};
155
+
156
+
enum {
157
+
AD7768_PGA_GAIN_0,
158
+
AD7768_PGA_GAIN_1,
159
+
AD7768_PGA_GAIN_2,
160
+
AD7768_PGA_GAIN_3,
161
+
AD7768_PGA_GAIN_4,
162
+
AD7768_PGA_GAIN_5,
163
+
AD7768_PGA_GAIN_6,
164
+
AD7768_PGA_GAIN_7,
165
+
};
166
+
167
+
enum {
168
+
AD7768_AAF_IN1,
169
+
AD7768_AAF_IN2,
170
+
AD7768_AAF_IN3,
171
+
};
172
+
173
+
/* PGA and AAF gains in V/V */
174
+
static const int adaq7768_gains[] = {
175
+
[AD7768_PGA_GAIN_0] = 325, /* 0.325 */
176
+
[AD7768_PGA_GAIN_1] = 650, /* 0.650 */
177
+
[AD7768_PGA_GAIN_2] = 1300, /* 1.300 */
178
+
[AD7768_PGA_GAIN_3] = 2600, /* 2.600 */
179
+
[AD7768_PGA_GAIN_4] = 5200, /* 5.200 */
180
+
[AD7768_PGA_GAIN_5] = 10400, /* 10.400 */
181
+
[AD7768_PGA_GAIN_6] = 20800, /* 20.800 */
182
+
};
183
+
184
+
static const int adaq7769_gains[] = {
185
+
[AD7768_PGA_GAIN_0] = 1000, /* 1.000 */
186
+
[AD7768_PGA_GAIN_1] = 2000, /* 2.000 */
187
+
[AD7768_PGA_GAIN_2] = 4000, /* 4.000 */
188
+
[AD7768_PGA_GAIN_3] = 8000, /* 8.000 */
189
+
[AD7768_PGA_GAIN_4] = 16000, /* 16.000 */
190
+
[AD7768_PGA_GAIN_5] = 32000, /* 32.000 */
191
+
[AD7768_PGA_GAIN_6] = 64000, /* 64.000 */
192
+
[AD7768_PGA_GAIN_7] = 128000, /* 128.000 */
193
+
};
194
+
195
+
static const int ad7768_aaf_gains_bp[] = {
196
+
[AD7768_AAF_IN1] = 10000, /* 1.000 */
197
+
[AD7768_AAF_IN2] = 3640, /* 0.364 */
198
+
[AD7768_AAF_IN3] = 1430, /* 0.143 */
164
199
};
165
200
166
201
/* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */
···
268
213
},
269
214
};
270
215
216
+
struct ad7768_chip_info {
217
+
const char *name;
218
+
const struct iio_chan_spec *channel_spec;
219
+
int num_channels;
220
+
const int *pga_gains;
221
+
int num_pga_modes;
222
+
int default_pga_mode;
223
+
int pgia_mode2pin_offset;
224
+
bool has_pga;
225
+
bool has_variable_aaf;
226
+
bool has_vcm_regulator;
227
+
};
228
+
271
229
struct ad7768_state {
272
230
struct spi_device *spi;
273
231
struct regmap *regmap;
···
296
228
unsigned int samp_freq;
297
229
unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)];
298
230
unsigned int samp_freq_avail_len;
231
+
unsigned int pga_gain_mode;
232
+
unsigned int aaf_gain;
233
+
int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2];
299
234
struct completion completion;
300
235
struct iio_trigger *trig;
236
+
struct gpio_descs *pga_gpios;
301
237
struct gpio_desc *gpio_sync_in;
302
238
struct gpio_desc *gpio_reset;
303
239
const char *labels[AD7768_MAX_CHANNELS];
304
240
struct gpio_chip gpiochip;
241
+
const struct ad7768_chip_info *chip;
305
242
bool en_spi_sync;
243
+
struct mutex pga_lock; /* protect device internal state (PGA) */
306
244
/*
307
245
* DMA (thus cache coherency maintenance) may require the
308
246
* transfer buffers to live in their own cache lines.
···
531
457
return ret;
532
458
}
533
459
460
+
static void ad7768_fill_scale_tbl(struct iio_dev *dev)
461
+
{
462
+
struct ad7768_state *st = iio_priv(dev);
463
+
const struct iio_scan_type *scan_type;
464
+
int val, val2, tmp0, tmp1, i;
465
+
struct u32_fract fract;
466
+
unsigned long n, d;
467
+
u64 tmp2;
468
+
469
+
scan_type = iio_get_current_scan_type(dev, &dev->channels[0]);
470
+
if (scan_type->sign == 's')
471
+
val2 = scan_type->realbits - 1;
472
+
else
473
+
val2 = scan_type->realbits;
474
+
475
+
for (i = 0; i < st->chip->num_pga_modes; i++) {
476
+
/* Convert gain to a fraction format */
477
+
fract.numerator = st->chip->pga_gains[i];
478
+
fract.denominator = MILLI;
479
+
if (st->chip->has_variable_aaf) {
480
+
fract.numerator *= ad7768_aaf_gains_bp[st->aaf_gain];
481
+
fract.denominator *= PERMYRIAD;
482
+
}
483
+
484
+
rational_best_approximation(fract.numerator, fract.denominator,
485
+
INT_MAX, INT_MAX, &n, &d);
486
+
487
+
val = mult_frac(st->vref_uv, d, n);
488
+
/* Would multiply by NANO here, but value is already in milli */
489
+
tmp2 = ((u64)val * MICRO) >> val2;
490
+
tmp0 = div_u64_rem(tmp2, NANO, &tmp1);
491
+
st->scale_tbl[i][0] = tmp0; /* Integer part */
492
+
st->scale_tbl[i][1] = abs(tmp1); /* Fractional part */
493
+
}
494
+
}
495
+
534
496
static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st,
535
497
unsigned int dec_rate)
536
498
{
···
668
558
st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx];
669
559
}
670
560
561
+
/* Update scale table: scale values vary according to the precision */
562
+
ad7768_fill_scale_tbl(dev);
563
+
671
564
ad7768_fill_samp_freq_tbl(st);
672
565
673
566
/* A sync-in pulse is required after every configuration change */
674
567
return ad7768_send_sync_pulse(st);
568
+
}
569
+
570
+
static int ad7768_setup_pga(struct device *dev, struct ad7768_state *st)
571
+
{
572
+
st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW);
573
+
if (IS_ERR(st->pga_gpios))
574
+
return dev_err_probe(dev, PTR_ERR(st->pga_gpios),
575
+
"Failed to get PGA gpios.\n");
576
+
577
+
if (st->pga_gpios->ndescs != ADAQ7768_PGA_PINS)
578
+
return dev_err_probe(dev, -EINVAL,
579
+
"Expected %d GPIOs for PGA control.\n",
580
+
ADAQ7768_PGA_PINS);
581
+
return 0;
582
+
}
583
+
584
+
static int ad7768_calc_pga_gain(struct ad7768_state *st, int gain_int,
585
+
int gain_fract, int precision)
586
+
{
587
+
u64 gain_nano;
588
+
u32 tmp;
589
+
590
+
gain_nano = gain_int * NANO + gain_fract;
591
+
gain_nano = clamp(gain_nano, 0, ADAQ776X_GAIN_MAX_NANO);
592
+
tmp = DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO);
593
+
gain_nano = DIV_ROUND_CLOSEST(st->vref_uv, tmp);
594
+
if (st->chip->has_variable_aaf)
595
+
gain_nano = DIV_ROUND_CLOSEST_ULL(gain_nano * PERMYRIAD,
596
+
ad7768_aaf_gains_bp[st->aaf_gain]);
597
+
598
+
return find_closest(gain_nano, st->chip->pga_gains,
599
+
(int)st->chip->num_pga_modes);
600
+
}
601
+
602
+
static int ad7768_set_pga_gain(struct ad7768_state *st,
603
+
int gain_mode)
604
+
{
605
+
int pgia_pins_value = abs(gain_mode - st->chip->pgia_mode2pin_offset);
606
+
DECLARE_BITMAP(bitmap, ADAQ7768_PGA_PINS) = { };
607
+
int ret;
608
+
609
+
guard(mutex)(&st->pga_lock);
610
+
611
+
bitmap_write(bitmap, pgia_pins_value, 0, ADAQ7768_PGA_PINS);
612
+
ret = gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap);
613
+
if (ret)
614
+
return ret;
615
+
616
+
st->pga_gain_mode = gain_mode;
617
+
618
+
return 0;
675
619
}
676
620
677
621
static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
···
899
735
return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)];
900
736
}
901
737
738
+
static int ad7768_update_dec_rate(struct iio_dev *dev, unsigned int dec_rate)
739
+
{
740
+
struct ad7768_state *st = iio_priv(dev);
741
+
int ret;
742
+
743
+
ret = ad7768_configure_dig_fil(dev, st->filter_type, dec_rate);
744
+
if (ret)
745
+
return ret;
746
+
747
+
/* Update sampling frequency */
748
+
return ad7768_set_freq(st, st->samp_freq);
749
+
}
750
+
902
751
static const struct iio_enum ad7768_filter_type_iio_enum = {
903
752
.items = ad7768_filter_enum,
904
753
.num_items = ARRAY_SIZE(ad7768_filter_enum),
···
925
748
{ }
926
749
};
927
750
751
+
#define AD7768_CHAN(_idx, _msk_avail) \
752
+
{ \
753
+
.type = IIO_VOLTAGE, \
754
+
.info_mask_separate_available = _msk_avail, \
755
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
756
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
757
+
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
758
+
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
759
+
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
760
+
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
761
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
762
+
.ext_info = ad7768_ext_info, \
763
+
.indexed = 1, \
764
+
.channel = _idx, \
765
+
.scan_index = _idx, \
766
+
.has_ext_scan_type = 1, \
767
+
.ext_scan_type = ad7768_scan_type, \
768
+
.num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), \
769
+
}
770
+
928
771
static const struct iio_chan_spec ad7768_channels[] = {
929
-
{
930
-
.type = IIO_VOLTAGE,
931
-
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
932
-
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
933
-
BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
934
-
BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
935
-
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
936
-
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
937
-
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
938
-
.ext_info = ad7768_ext_info,
939
-
.indexed = 1,
940
-
.channel = 0,
941
-
.scan_index = 0,
942
-
.has_ext_scan_type = 1,
943
-
.ext_scan_type = ad7768_scan_type,
944
-
.num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type),
945
-
},
772
+
AD7768_CHAN(0, 0),
773
+
};
774
+
775
+
static const struct iio_chan_spec adaq776x_channels[] = {
776
+
AD7768_CHAN(0, BIT(IIO_CHAN_INFO_SCALE)),
946
777
};
947
778
948
779
static int ad7768_read_raw(struct iio_dev *indio_dev,
···
980
795
return IIO_VAL_INT;
981
796
982
797
case IIO_CHAN_INFO_SCALE:
983
-
*val = (st->vref_uv * 2) / 1000;
798
+
if (st->chip->has_pga) {
799
+
guard(mutex)(&st->pga_lock);
800
+
801
+
*val = st->scale_tbl[st->pga_gain_mode][0];
802
+
*val2 = st->scale_tbl[st->pga_gain_mode][1];
803
+
return IIO_VAL_INT_PLUS_NANO;
804
+
}
805
+
806
+
temp = (st->vref_uv * 2) / 1000;
807
+
if (st->chip->has_variable_aaf)
808
+
temp = (temp * PERMYRIAD) / ad7768_aaf_gains_bp[st->aaf_gain];
809
+
810
+
*val = temp;
984
811
*val2 = scan_type->realbits;
985
812
986
813
return IIO_VAL_FRACTIONAL_LOG2;
···
1048
851
*length = st->samp_freq_avail_len;
1049
852
*type = IIO_VAL_INT;
1050
853
return IIO_AVAIL_LIST;
854
+
case IIO_CHAN_INFO_SCALE:
855
+
*vals = (int *)st->scale_tbl;
856
+
*length = st->chip->num_pga_modes * 2;
857
+
*type = IIO_VAL_INT_PLUS_NANO;
858
+
return IIO_AVAIL_LIST;
1051
859
default:
1052
860
return -EINVAL;
1053
861
}
1054
862
}
1055
863
1056
-
static int __ad7768_write_raw(struct iio_dev *indio_dev,
1057
-
struct iio_chan_spec const *chan,
1058
-
int val, int val2, long info)
864
+
static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev,
865
+
struct iio_chan_spec const *chan, long mask)
1059
866
{
1060
-
struct ad7768_state *st = iio_priv(indio_dev);
1061
-
int ret;
1062
-
1063
-
switch (info) {
1064
-
case IIO_CHAN_INFO_SAMP_FREQ:
1065
-
return ad7768_set_freq(st, val);
1066
-
1067
-
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1068
-
ret = ad7768_configure_dig_fil(indio_dev, st->filter_type, val);
1069
-
if (ret)
1070
-
return ret;
1071
-
1072
-
/* Update sampling frequency */
1073
-
return ad7768_set_freq(st, st->samp_freq);
867
+
switch (mask) {
868
+
case IIO_CHAN_INFO_SCALE:
869
+
return IIO_VAL_INT_PLUS_NANO;
1074
870
default:
1075
-
return -EINVAL;
871
+
return IIO_VAL_INT_PLUS_MICRO;
1076
872
}
1077
873
}
1078
874
···
1073
883
struct iio_chan_spec const *chan,
1074
884
int val, int val2, long info)
1075
885
{
886
+
struct ad7768_state *st = iio_priv(indio_dev);
887
+
const struct iio_scan_type *scan_type;
1076
888
int ret;
1077
889
1078
-
if (!iio_device_claim_direct(indio_dev))
1079
-
return -EBUSY;
890
+
scan_type = iio_get_current_scan_type(indio_dev, chan);
891
+
if (IS_ERR(scan_type))
892
+
return PTR_ERR(scan_type);
1080
893
1081
-
ret = __ad7768_write_raw(indio_dev, chan, val, val2, info);
1082
-
iio_device_release_direct(indio_dev);
894
+
switch (info) {
895
+
case IIO_CHAN_INFO_SAMP_FREQ:
896
+
if (!iio_device_claim_direct(indio_dev))
897
+
return -EBUSY;
1083
898
1084
-
return ret;
899
+
ret = ad7768_set_freq(st, val);
900
+
iio_device_release_direct(indio_dev);
901
+
return ret;
902
+
case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
903
+
if (!iio_device_claim_direct(indio_dev))
904
+
return -EBUSY;
905
+
906
+
ret = ad7768_update_dec_rate(indio_dev, val);
907
+
iio_device_release_direct(indio_dev);
908
+
return ret;
909
+
case IIO_CHAN_INFO_SCALE: {
910
+
int gain_mode;
911
+
912
+
if (!st->chip->has_pga)
913
+
return -EOPNOTSUPP;
914
+
915
+
if (scan_type->sign == 's')
916
+
gain_mode = ad7768_calc_pga_gain(st, val, val2,
917
+
scan_type->realbits - 1);
918
+
else
919
+
gain_mode = ad7768_calc_pga_gain(st, val, val2,
920
+
scan_type->realbits);
921
+
922
+
return ad7768_set_pga_gain(st, gain_mode);
923
+
}
924
+
default:
925
+
return -EINVAL;
926
+
}
1085
927
}
1086
928
1087
929
static int ad7768_read_label(struct iio_dev *indio_dev,
···
1137
915
.read_raw = &ad7768_read_raw,
1138
916
.read_avail = &ad7768_read_avail,
1139
917
.write_raw = &ad7768_write_raw,
918
+
.write_raw_get_fmt = &ad7768_write_raw_get_fmt,
1140
919
.read_label = ad7768_read_label,
1141
920
.get_current_scan_type = &ad7768_get_current_scan_type,
1142
921
.debugfs_reg_access = &ad7768_reg_access,
···
1521
1298
.owner = THIS_MODULE,
1522
1299
};
1523
1300
1524
-
static int ad7768_register_regulators(struct device *dev, struct ad7768_state *st,
1525
-
struct iio_dev *indio_dev)
1301
+
static int ad7768_register_vcm_regulator(struct device *dev,
1302
+
struct ad7768_state *st,
1303
+
struct iio_dev *indio_dev)
1526
1304
{
1527
1305
struct regulator_config config = {
1528
1306
.dev = dev,
···
1544
1320
1545
1321
return 0;
1546
1322
}
1323
+
1324
+
static int ad7768_parse_aaf_gain(struct device *dev, struct ad7768_state *st)
1325
+
{
1326
+
u32 val;
1327
+
int ret;
1328
+
1329
+
ret = device_property_read_u32(dev, "adi,aaf-gain-bp", &val);
1330
+
if (ret == -EINVAL) {
1331
+
/* If controllable, use default */
1332
+
if (st->chip->has_variable_aaf)
1333
+
st->aaf_gain = AD7768_AAF_IN1;
1334
+
return 0;
1335
+
}
1336
+
if (ret)
1337
+
return dev_err_probe(dev, ret, "Failed to get AAF gain value\n");
1338
+
1339
+
if (!st->chip->has_variable_aaf)
1340
+
return dev_err_probe(dev, -EOPNOTSUPP,
1341
+
"AAF gain provided, but not supported for %s\n", st->chip->name);
1342
+
1343
+
switch (val) {
1344
+
case 10000:
1345
+
st->aaf_gain = AD7768_AAF_IN1;
1346
+
break;
1347
+
case 3640:
1348
+
st->aaf_gain = AD7768_AAF_IN2;
1349
+
break;
1350
+
case 1430:
1351
+
st->aaf_gain = AD7768_AAF_IN3;
1352
+
break;
1353
+
default:
1354
+
return dev_err_probe(dev, -EINVAL, "Invalid firmware provided AAF gain\n");
1355
+
}
1356
+
1357
+
return 0;
1358
+
}
1359
+
1360
+
static const struct ad7768_chip_info ad7768_chip_info = {
1361
+
.name = "ad7768-1",
1362
+
.channel_spec = ad7768_channels,
1363
+
.num_channels = ARRAY_SIZE(ad7768_channels),
1364
+
.has_vcm_regulator = true,
1365
+
};
1366
+
1367
+
static const struct ad7768_chip_info adaq7767_chip_info = {
1368
+
.name = "adaq7767-1",
1369
+
.channel_spec = ad7768_channels,
1370
+
.num_channels = ARRAY_SIZE(ad7768_channels),
1371
+
.has_variable_aaf = true,
1372
+
};
1373
+
1374
+
static const struct ad7768_chip_info adaq7768_chip_info = {
1375
+
.name = "adaq7768-1",
1376
+
.channel_spec = adaq776x_channels,
1377
+
.num_channels = ARRAY_SIZE(adaq776x_channels),
1378
+
.pga_gains = adaq7768_gains,
1379
+
.default_pga_mode = AD7768_PGA_GAIN_2,
1380
+
.num_pga_modes = ARRAY_SIZE(adaq7768_gains),
1381
+
.pgia_mode2pin_offset = 6,
1382
+
.has_pga = true,
1383
+
};
1384
+
1385
+
static const struct ad7768_chip_info adaq7769_chip_info = {
1386
+
.name = "adaq7769-1",
1387
+
.channel_spec = adaq776x_channels,
1388
+
.num_channels = ARRAY_SIZE(adaq776x_channels),
1389
+
.pga_gains = adaq7769_gains,
1390
+
.default_pga_mode = AD7768_PGA_GAIN_0,
1391
+
.num_pga_modes = ARRAY_SIZE(adaq7769_gains),
1392
+
.pgia_mode2pin_offset = 0,
1393
+
.has_pga = true,
1394
+
.has_variable_aaf = true,
1395
+
};
1547
1396
1548
1397
static int ad7768_probe(struct spi_device *spi)
1549
1398
{
···
1644
1347
return ret;
1645
1348
}
1646
1349
1350
+
st->chip = spi_get_device_match_data(spi);
1647
1351
st->spi = spi;
1648
1352
1649
1353
st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config);
···
1669
1371
1670
1372
st->mclk_freq = clk_get_rate(st->mclk);
1671
1373
1672
-
indio_dev->channels = ad7768_channels;
1673
-
indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
1674
-
indio_dev->name = spi_get_device_id(spi)->name;
1374
+
indio_dev->channels = st->chip->channel_spec;
1375
+
indio_dev->num_channels = st->chip->num_channels;
1376
+
indio_dev->name = st->chip->name;
1675
1377
indio_dev->info = &ad7768_info;
1676
1378
indio_dev->modes = INDIO_DIRECT_MODE;
1677
1379
1678
1380
/* Register VCM output regulator */
1679
-
ret = ad7768_register_regulators(&spi->dev, st, indio_dev);
1381
+
if (st->chip->has_vcm_regulator) {
1382
+
ret = ad7768_register_vcm_regulator(&spi->dev, st, indio_dev);
1383
+
if (ret)
1384
+
return ret;
1385
+
}
1386
+
1387
+
ret = ad7768_parse_aaf_gain(&spi->dev, st);
1680
1388
if (ret)
1681
1389
return ret;
1682
1390
···
1693
1389
}
1694
1390
1695
1391
init_completion(&st->completion);
1696
-
1697
-
ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
1392
+
ret = devm_mutex_init(&spi->dev, &st->pga_lock);
1698
1393
if (ret)
1699
1394
return ret;
1700
1395
1701
-
ret = devm_request_irq(&spi->dev, spi->irq,
1702
-
&ad7768_interrupt,
1703
-
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1396
+
if (st->chip->has_pga) {
1397
+
ret = ad7768_setup_pga(&spi->dev, st);
1398
+
if (ret)
1399
+
return ret;
1400
+
1401
+
ret = ad7768_set_pga_gain(st, st->chip->default_pga_mode);
1402
+
if (ret)
1403
+
return ret;
1404
+
}
1405
+
1406
+
ret = ad7768_set_channel_label(indio_dev, st->chip->num_channels);
1407
+
if (ret)
1408
+
return ret;
1409
+
1410
+
ret = devm_request_irq(&spi->dev, spi->irq, &ad7768_interrupt,
1411
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
1704
1412
indio_dev->name, indio_dev);
1705
1413
if (ret)
1706
1414
return ret;
···
1725
1409
}
1726
1410
1727
1411
static const struct spi_device_id ad7768_id_table[] = {
1728
-
{ "ad7768-1", 0 },
1412
+
{ "ad7768-1", (kernel_ulong_t)&ad7768_chip_info },
1413
+
{ "adaq7767-1", (kernel_ulong_t)&adaq7767_chip_info },
1414
+
{ "adaq7768-1", (kernel_ulong_t)&adaq7768_chip_info },
1415
+
{ "adaq7769-1", (kernel_ulong_t)&adaq7769_chip_info },
1729
1416
{ }
1730
1417
};
1731
1418
MODULE_DEVICE_TABLE(spi, ad7768_id_table);
1732
1419
1733
1420
static const struct of_device_id ad7768_of_match[] = {
1734
-
{ .compatible = "adi,ad7768-1" },
1421
+
{ .compatible = "adi,ad7768-1", .data = &ad7768_chip_info },
1422
+
{ .compatible = "adi,adaq7767-1", .data = &adaq7767_chip_info },
1423
+
{ .compatible = "adi,adaq7768-1", .data = &adaq7768_chip_info },
1424
+
{ .compatible = "adi,adaq7769-1", .data = &adaq7769_chip_info },
1735
1425
{ }
1736
1426
};
1737
1427
MODULE_DEVICE_TABLE(of, ad7768_of_match);
+1
-1
drivers/iio/adc/ad7779.c
+1
-1
drivers/iio/adc/ad7779.c
···
840
840
iio_trigger_set_drvdata(st->trig, st);
841
841
842
842
ret = devm_request_irq(dev, st->spi->irq, iio_trigger_generic_data_rdy_poll,
843
-
IRQF_ONESHOT | IRQF_NO_AUTOEN, indio_dev->name,
843
+
IRQF_NO_THREAD | IRQF_NO_AUTOEN, indio_dev->name,
844
844
st->trig);
845
845
if (ret)
846
846
return dev_err_probe(dev, ret, "request IRQ %d failed\n",
+134
-18
drivers/iio/adc/ad9467.c
+134
-18
drivers/iio/adc/ad9467.c
···
5
5
* Copyright 2012-2020 Analog Devices Inc.
6
6
*/
7
7
8
+
#include <linux/bitfield.h>
8
9
#include <linux/bitmap.h>
9
10
#include <linux/bitops.h>
10
11
#include <linux/cleanup.h>
12
+
#include <linux/clk.h>
11
13
#include <linux/debugfs.h>
14
+
#include <linux/delay.h>
15
+
#include <linux/device.h>
16
+
#include <linux/err.h>
17
+
#include <linux/gpio/consumer.h>
18
+
#include <linux/kernel.h>
12
19
#include <linux/module.h>
13
20
#include <linux/mutex.h>
14
-
#include <linux/device.h>
15
-
#include <linux/kernel.h>
21
+
#include <linux/of.h>
22
+
#include <linux/seq_file.h>
16
23
#include <linux/slab.h>
17
24
#include <linux/spi/spi.h>
18
-
#include <linux/seq_file.h>
19
-
#include <linux/err.h>
20
-
#include <linux/delay.h>
21
-
#include <linux/gpio/consumer.h>
22
-
#include <linux/of.h>
23
-
25
+
#include <linux/units.h>
24
26
25
27
#include <linux/iio/backend.h>
26
28
#include <linux/iio/iio.h>
27
29
#include <linux/iio/sysfs.h>
28
-
29
-
#include <linux/clk.h>
30
30
31
31
/*
32
32
* ADI High-Speed ADC common spi interface registers
···
73
73
#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
74
74
#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
75
75
#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
76
+
#define AN877_ADC_OUTPUT_MODE_MASK GENMASK(1, 0)
76
77
77
78
/* AN877_ADC_REG_OUTPUT_PHASE */
78
79
#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
···
83
82
#define AN877_ADC_DCO_DELAY_ENABLE 0x80
84
83
85
84
/*
85
+
* Analog Devices AD9211 10-Bit, 200/250/300 MSPS ADC
86
+
*/
87
+
88
+
#define CHIPID_AD9211 0x06
89
+
#define AD9211_DEF_OUTPUT_MODE 0x01
90
+
#define AD9211_REG_VREF_MASK GENMASK(4, 0)
91
+
92
+
/*
86
93
* Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
87
94
*/
88
95
89
96
#define CHIPID_AD9265 0x64
90
-
#define AD9265_DEF_OUTPUT_MODE 0x40
97
+
#define AD9265_DEF_OUTPUT_MODE 0x41
91
98
#define AD9265_REG_VREF_MASK 0xC0
92
99
93
100
/*
···
103
94
*/
104
95
105
96
#define CHIPID_AD9434 0x6A
106
-
#define AD9434_DEF_OUTPUT_MODE 0x00
97
+
#define AD9434_DEF_OUTPUT_MODE 0x01
107
98
#define AD9434_REG_VREF_MASK GENMASK(4, 0)
108
99
109
100
/*
···
111
102
*/
112
103
113
104
#define CHIPID_AD9467 0x50
114
-
#define AD9467_DEF_OUTPUT_MODE 0x08
105
+
#define AD9467_DEF_OUTPUT_MODE 0x09
115
106
#define AD9467_REG_VREF_MASK 0x0F
116
107
117
108
/*
···
119
110
*/
120
111
121
112
#define CHIPID_AD9643 0x82
113
+
#define AD9643_DEF_OUTPUT_MODE 0x01
122
114
#define AD9643_REG_VREF_MASK 0x1F
123
115
124
116
/*
···
127
117
*/
128
118
129
119
#define CHIPID_AD9652 0xC1
120
+
#define AD9652_DEF_OUTPUT_MODE 0x01
130
121
#define AD9652_REG_VREF_MASK 0xC0
131
122
132
123
/*
···
135
124
*/
136
125
137
126
#define CHIPID_AD9649 0x6F
127
+
#define AD9649_DEF_OUTPUT_MODE 0x01
138
128
#define AD9649_TEST_POINTS 8
139
129
140
130
#define AD9647_MAX_TEST_POINTS 32
···
157
145
unsigned int num_lanes;
158
146
unsigned int dco_en;
159
147
unsigned int test_points;
148
+
const int *offset_range;
160
149
/* data clock output */
161
150
bool has_dco;
162
151
bool has_dco_invert;
···
247
234
return 0;
248
235
}
249
236
237
+
static const int ad9434_offset_range[] = {
238
+
-128, 1, 127,
239
+
};
240
+
241
+
static const unsigned int ad9211_scale_table[][2] = {
242
+
{980, 0x10}, {1000, 0x11}, {1020, 0x12}, {1040, 0x13},
243
+
{1060, 0x14}, {1080, 0x15}, {1100, 0x16}, {1120, 0x17},
244
+
{1140, 0x18}, {1160, 0x19}, {1180, 0x1A}, {1190, 0x1B},
245
+
{1200, 0x1C}, {1210, 0x1D}, {1220, 0x1E}, {1230, 0x1F},
246
+
{1250, 0x0}, {1270, 0x1}, {1290, 0x2}, {1310, 0x3},
247
+
{1330, 0x4}, {1350, 0x5}, {1370, 0x6}, {1390, 0x7},
248
+
{1410, 0x8}, {1430, 0x9}, {1450, 0xA}, {1460, 0xB},
249
+
{1470, 0xC}, {1480, 0xD}, {1490, 0xE}, {1500, 0xF},
250
+
};
251
+
250
252
static const unsigned int ad9265_scale_table[][2] = {
251
253
{1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
252
254
};
···
325
297
}, \
326
298
}
327
299
300
+
static const struct iio_chan_spec ad9211_channels[] = {
301
+
AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 10, 's'),
302
+
};
303
+
328
304
static const struct iio_chan_spec ad9434_channels[] = {
329
-
AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'),
305
+
{
306
+
.type = IIO_VOLTAGE,
307
+
.indexed = 1,
308
+
.channel = 0,
309
+
.info_mask_shared_by_type =
310
+
BIT(IIO_CHAN_INFO_SCALE) |
311
+
BIT(IIO_CHAN_INFO_SAMP_FREQ) |
312
+
BIT(IIO_CHAN_INFO_CALIBBIAS),
313
+
.info_mask_shared_by_type_available =
314
+
BIT(IIO_CHAN_INFO_SCALE) |
315
+
BIT(IIO_CHAN_INFO_CALIBBIAS),
316
+
.scan_index = 0,
317
+
.scan_type = {
318
+
.sign = 's',
319
+
.realbits = 12,
320
+
.storagebits = 16,
321
+
},
322
+
},
330
323
};
331
324
332
325
static const struct iio_chan_spec ad9467_channels[] = {
···
416
367
.default_output_mode = AD9434_DEF_OUTPUT_MODE,
417
368
.vref_mask = AD9434_REG_VREF_MASK,
418
369
.num_lanes = 6,
370
+
.offset_range = ad9434_offset_range,
371
+
};
372
+
373
+
static const struct ad9467_chip_info ad9211_chip_tbl = {
374
+
.name = "ad9211",
375
+
.id = CHIPID_AD9211,
376
+
.max_rate = 300 * HZ_PER_MHZ,
377
+
.scale_table = ad9211_scale_table,
378
+
.num_scales = ARRAY_SIZE(ad9211_scale_table),
379
+
.channels = ad9211_channels,
380
+
.num_channels = ARRAY_SIZE(ad9211_channels),
381
+
.test_points = AD9647_MAX_TEST_POINTS,
382
+
.test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,
383
+
AN877_ADC_TESTMODE_OFF),
384
+
.test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1,
385
+
.default_output_mode = AD9211_DEF_OUTPUT_MODE,
386
+
.vref_mask = AD9211_REG_VREF_MASK,
387
+
.has_dco = true,
419
388
};
420
389
421
390
static const struct ad9467_chip_info ad9265_chip_tbl = {
···
466
399
.test_mask = BIT(AN877_ADC_TESTMODE_RAMP) |
467
400
GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMODE_OFF),
468
401
.test_mask_len = AN877_ADC_TESTMODE_RAMP + 1,
402
+
.default_output_mode = AD9643_DEF_OUTPUT_MODE,
469
403
.vref_mask = AD9643_REG_VREF_MASK,
470
404
.has_dco = true,
471
405
.has_dco_invert = true,
···
485
417
.test_mask = GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY,
486
418
AN877_ADC_TESTMODE_OFF),
487
419
.test_mask_len = AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY + 1,
420
+
.default_output_mode = AD9649_DEF_OUTPUT_MODE,
488
421
.has_dco = true,
489
422
.has_dco_invert = true,
490
423
.dco_en = AN877_ADC_DCO_DELAY_ENABLE,
···
503
434
.test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,
504
435
AN877_ADC_TESTMODE_OFF),
505
436
.test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1,
437
+
.default_output_mode = AD9652_DEF_OUTPUT_MODE,
506
438
.vref_mask = AD9652_REG_VREF_MASK,
507
439
.has_dco = true,
508
440
};
···
567
497
}
568
498
569
499
return -EINVAL;
500
+
}
501
+
502
+
static int ad9467_get_offset(struct ad9467_state *st, int *val)
503
+
{
504
+
int ret;
505
+
506
+
ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET);
507
+
if (ret < 0)
508
+
return ret;
509
+
*val = ret;
510
+
511
+
return IIO_VAL_INT;
512
+
}
513
+
514
+
static int ad9467_set_offset(struct ad9467_state *st, int val)
515
+
{
516
+
int ret;
517
+
518
+
if (val < st->info->offset_range[0] || val > st->info->offset_range[2])
519
+
return -EINVAL;
520
+
521
+
ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val);
522
+
if (ret < 0)
523
+
return ret;
524
+
525
+
return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
526
+
AN877_ADC_TRANSFER_SYNC);
570
527
}
571
528
572
529
static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode)
···
679
582
680
583
static int ad9647_calibrate_prepare(struct ad9467_state *st)
681
584
{
585
+
unsigned int cmode;
682
586
unsigned int c;
683
587
int ret;
684
588
685
-
ret = ad9467_outputmode_set(st, st->info->default_output_mode);
589
+
cmode = st->info->default_output_mode;
590
+
FIELD_MODIFY(AN877_ADC_OUTPUT_MODE_MASK, &cmode,
591
+
AN877_ADC_OUTPUT_MODE_OFFSET_BINARY);
592
+
ret = ad9467_outputmode_set(st, cmode);
686
593
if (ret)
687
594
return ret;
688
595
···
790
689
return ret;
791
690
}
792
691
793
-
mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
692
+
mode = st->info->default_output_mode;
794
693
return ad9467_outputmode_set(st, mode);
795
694
}
796
695
···
903
802
struct ad9467_state *st = iio_priv(indio_dev);
904
803
905
804
switch (m) {
805
+
case IIO_CHAN_INFO_CALIBBIAS:
806
+
return ad9467_get_offset(st, val);
906
807
case IIO_CHAN_INFO_SCALE:
907
808
return ad9467_get_scale(st, val, val2);
908
809
case IIO_CHAN_INFO_SAMP_FREQ:
···
939
836
int ret;
940
837
941
838
switch (mask) {
839
+
case IIO_CHAN_INFO_CALIBBIAS:
840
+
return ad9467_set_offset(st, val);
942
841
case IIO_CHAN_INFO_SCALE:
943
842
return ad9467_set_scale(st, val, val2);
944
843
case IIO_CHAN_INFO_SAMP_FREQ:
···
979
874
const struct ad9467_chip_info *info = st->info;
980
875
981
876
switch (mask) {
877
+
case IIO_CHAN_INFO_CALIBBIAS:
878
+
*type = IIO_VAL_INT;
879
+
*vals = info->offset_range;
880
+
return IIO_AVAIL_RANGE;
982
881
case IIO_CHAN_INFO_SCALE:
983
882
*vals = (const int *)st->scales;
984
883
*type = IIO_VAL_INT_PLUS_MICRO;
···
1186
1077
if (ret)
1187
1078
return ret;
1188
1079
1189
-
out_mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
1080
+
out_mode = st->info->default_output_mode;
1190
1081
ret = ad9467_outputmode_set(st, out_mode);
1191
1082
if (ret)
1192
1083
return ret;
1193
1084
} else {
1194
-
ret = ad9467_outputmode_set(st, st->info->default_output_mode);
1085
+
unsigned int cmode;
1086
+
1087
+
cmode = st->info->default_output_mode;
1088
+
FIELD_MODIFY(AN877_ADC_OUTPUT_MODE_MASK, &cmode,
1089
+
AN877_ADC_OUTPUT_MODE_OFFSET_BINARY);
1090
+
ret = ad9467_outputmode_set(st, cmode);
1195
1091
if (ret)
1196
1092
return ret;
1197
1093
···
1378
1264
}
1379
1265
1380
1266
static const struct of_device_id ad9467_of_match[] = {
1267
+
{ .compatible = "adi,ad9211", .data = &ad9211_chip_tbl, },
1381
1268
{ .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, },
1382
1269
{ .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, },
1383
1270
{ .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, },
···
1390
1275
MODULE_DEVICE_TABLE(of, ad9467_of_match);
1391
1276
1392
1277
static const struct spi_device_id ad9467_ids[] = {
1278
+
{ "ad9211", (kernel_ulong_t)&ad9211_chip_tbl },
1393
1279
{ "ad9265", (kernel_ulong_t)&ad9265_chip_tbl },
1394
1280
{ "ad9434", (kernel_ulong_t)&ad9434_chip_tbl },
1395
1281
{ "ad9467", (kernel_ulong_t)&ad9467_chip_tbl },
+1
-1
drivers/iio/adc/ade9000.c
+1
-1
drivers/iio/adc/ade9000.c
···
964
964
struct iio_dev *indio_dev = data;
965
965
966
966
/* Handle data ready interrupt from C4/EVENT/DREADY pin */
967
-
if (!iio_device_claim_buffer_mode(indio_dev)) {
967
+
if (iio_device_try_claim_buffer_mode(indio_dev)) {
968
968
ade9000_iio_push_buffer(indio_dev);
969
969
iio_device_release_buffer_mode(indio_dev);
970
970
}
+26
-36
drivers/iio/adc/adi-axi-adc.c
+26
-36
drivers/iio/adc/adi-axi-adc.c
···
591
591
.size_data = st->info->pdata_sz,
592
592
};
593
593
struct platform_device *pdev;
594
-
int ret;
595
594
596
595
pdev = platform_device_register_full(&pi);
597
596
if (IS_ERR(pdev))
598
597
return PTR_ERR(pdev);
599
598
600
-
ret = devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev);
601
-
if (ret)
602
-
return ret;
603
-
604
-
return 0;
599
+
return devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev);
605
600
}
606
601
607
602
static const struct iio_backend_ops adi_axi_adc_ops = {
···
669
674
670
675
static int adi_axi_adc_probe(struct platform_device *pdev)
671
676
{
677
+
struct device *dev = &pdev->dev;
672
678
struct adi_axi_adc_state *st;
673
679
void __iomem *base;
674
680
unsigned int ver;
675
681
struct clk *clk;
676
682
int ret;
677
683
678
-
st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
684
+
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
679
685
if (!st)
680
686
return -ENOMEM;
681
687
···
684
688
if (IS_ERR(base))
685
689
return PTR_ERR(base);
686
690
687
-
st->dev = &pdev->dev;
688
-
st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
689
-
&axi_adc_regmap_config);
691
+
st->dev = dev;
692
+
st->regmap = devm_regmap_init_mmio(dev, base, &axi_adc_regmap_config);
690
693
if (IS_ERR(st->regmap))
691
-
return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap),
694
+
return dev_err_probe(dev, PTR_ERR(st->regmap),
692
695
"failed to init register map\n");
693
696
694
-
st->info = device_get_match_data(&pdev->dev);
697
+
st->info = device_get_match_data(dev);
695
698
if (!st->info)
696
699
return -ENODEV;
697
700
698
-
clk = devm_clk_get_enabled(&pdev->dev, NULL);
701
+
clk = devm_clk_get_enabled(dev, NULL);
699
702
if (IS_ERR(clk))
700
-
return dev_err_probe(&pdev->dev, PTR_ERR(clk),
703
+
return dev_err_probe(dev, PTR_ERR(clk),
701
704
"failed to get clock\n");
702
705
703
706
/*
···
711
716
if (ret)
712
717
return ret;
713
718
714
-
if (ADI_AXI_PCORE_VER_MAJOR(ver) !=
715
-
ADI_AXI_PCORE_VER_MAJOR(st->info->version)) {
716
-
dev_err(&pdev->dev,
717
-
"Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
718
-
ADI_AXI_PCORE_VER_MAJOR(st->info->version),
719
-
ADI_AXI_PCORE_VER_MINOR(st->info->version),
720
-
ADI_AXI_PCORE_VER_PATCH(st->info->version),
721
-
ADI_AXI_PCORE_VER_MAJOR(ver),
722
-
ADI_AXI_PCORE_VER_MINOR(ver),
723
-
ADI_AXI_PCORE_VER_PATCH(ver));
724
-
return -ENODEV;
725
-
}
719
+
if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(st->info->version))
720
+
return dev_err_probe(dev, -ENODEV,
721
+
"Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
722
+
ADI_AXI_PCORE_VER_MAJOR(st->info->version),
723
+
ADI_AXI_PCORE_VER_MINOR(st->info->version),
724
+
ADI_AXI_PCORE_VER_PATCH(st->info->version),
725
+
ADI_AXI_PCORE_VER_MAJOR(ver),
726
+
ADI_AXI_PCORE_VER_MINOR(ver),
727
+
ADI_AXI_PCORE_VER_PATCH(ver));
726
728
727
-
ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st);
729
+
ret = devm_iio_backend_register(dev, st->info->backend_info, st);
728
730
if (ret)
729
-
return dev_err_probe(&pdev->dev, ret,
730
-
"failed to register iio backend\n");
731
+
return dev_err_probe(dev, ret, "failed to register iio backend\n");
731
732
732
-
device_for_each_child_node_scoped(&pdev->dev, child) {
733
+
device_for_each_child_node_scoped(dev, child) {
733
734
int val;
734
735
735
736
if (!st->info->has_child_nodes)
736
-
return dev_err_probe(&pdev->dev, -EINVAL,
737
+
return dev_err_probe(dev, -EINVAL,
737
738
"invalid fdt axi-dac compatible.");
738
739
739
740
/* Processing only reg 0 node */
740
741
ret = fwnode_property_read_u32(child, "reg", &val);
741
742
if (ret)
742
-
return dev_err_probe(&pdev->dev, ret,
743
-
"invalid reg property.");
743
+
return dev_err_probe(dev, ret, "invalid reg property.");
744
744
if (val != 0)
745
-
return dev_err_probe(&pdev->dev, -EINVAL,
745
+
return dev_err_probe(dev, -EINVAL,
746
746
"invalid node address.");
747
747
748
748
ret = axi_adc_create_platform_device(st, child);
749
749
if (ret)
750
-
return dev_err_probe(&pdev->dev, -EINVAL,
750
+
return dev_err_probe(dev, -EINVAL,
751
751
"cannot create device.");
752
752
}
753
753
754
-
dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
754
+
dev_info(dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
755
755
ADI_AXI_PCORE_VER_MAJOR(ver),
756
756
ADI_AXI_PCORE_VER_MINOR(ver),
757
757
ADI_AXI_PCORE_VER_PATCH(ver));
+22
-27
drivers/iio/adc/aspeed_adc.c
+22
-27
drivers/iio/adc/aspeed_adc.c
···
472
472
struct aspeed_adc_data *data;
473
473
int ret;
474
474
u32 adc_engine_control_reg_val;
475
+
struct device *dev = &pdev->dev;
476
+
struct device_node *np = dev_of_node(dev);
475
477
unsigned long scaler_flags = 0;
476
478
char clk_name[32], clk_parent_name[32];
477
479
478
-
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
480
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
479
481
if (!indio_dev)
480
482
return -ENOMEM;
481
483
482
484
data = iio_priv(indio_dev);
483
-
data->dev = &pdev->dev;
484
-
data->model_data = of_device_get_match_data(&pdev->dev);
485
+
data->dev = dev;
486
+
data->model_data = of_device_get_match_data(dev);
485
487
platform_set_drvdata(pdev, indio_dev);
486
488
487
489
data->base = devm_platform_ioremap_resource(pdev, 0);
···
493
491
/* Register ADC clock prescaler with source specified by device tree. */
494
492
spin_lock_init(&data->clk_lock);
495
493
snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s",
496
-
of_clk_get_parent_name(pdev->dev.of_node, 0));
494
+
of_clk_get_parent_name(np, 0));
497
495
snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div",
498
496
data->model_data->model_name);
499
-
data->fixed_div_clk = clk_hw_register_fixed_factor(
500
-
&pdev->dev, clk_name, clk_parent_name, 0, 1, 2);
497
+
data->fixed_div_clk = clk_hw_register_fixed_factor(dev, clk_name,
498
+
clk_parent_name, 0, 1, 2);
501
499
if (IS_ERR(data->fixed_div_clk))
502
500
return PTR_ERR(data->fixed_div_clk);
503
501
504
-
ret = devm_add_action_or_reset(data->dev,
505
-
aspeed_adc_unregister_fixed_divider,
502
+
ret = devm_add_action_or_reset(dev, aspeed_adc_unregister_fixed_divider,
506
503
data->fixed_div_clk);
507
504
if (ret)
508
505
return ret;
···
511
510
snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler",
512
511
data->model_data->model_name);
513
512
data->clk_prescaler = devm_clk_hw_register_divider(
514
-
&pdev->dev, clk_name, clk_parent_name, 0,
513
+
dev, clk_name, clk_parent_name, 0,
515
514
data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0,
516
515
&data->clk_lock);
517
516
if (IS_ERR(data->clk_prescaler))
···
527
526
snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler",
528
527
data->model_data->model_name);
529
528
data->clk_scaler = devm_clk_hw_register_divider(
530
-
&pdev->dev, clk_name, clk_parent_name, scaler_flags,
529
+
dev, clk_name, clk_parent_name, scaler_flags,
531
530
data->base + ASPEED_REG_CLOCK_CONTROL, 0,
532
531
data->model_data->scaler_bit_width,
533
532
data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
···
535
534
if (IS_ERR(data->clk_scaler))
536
535
return PTR_ERR(data->clk_scaler);
537
536
538
-
data->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
539
-
if (IS_ERR(data->rst)) {
540
-
dev_err(&pdev->dev,
541
-
"invalid or missing reset controller device tree entry");
542
-
return PTR_ERR(data->rst);
543
-
}
537
+
data->rst = devm_reset_control_get_shared(dev, NULL);
538
+
if (IS_ERR(data->rst))
539
+
return dev_err_probe(dev, PTR_ERR(data->rst),
540
+
"invalid or missing reset controller device tree entry");
541
+
544
542
reset_control_deassert(data->rst);
545
543
546
-
ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert,
547
-
data->rst);
544
+
ret = devm_add_action_or_reset(dev, aspeed_adc_reset_assert, data->rst);
548
545
if (ret)
549
546
return ret;
550
547
···
554
555
if (ret)
555
556
return ret;
556
557
557
-
if (of_property_present(data->dev->of_node, "aspeed,battery-sensing")) {
558
+
if (of_property_present(np, "aspeed,battery-sensing")) {
558
559
if (data->model_data->bat_sense_sup) {
559
560
data->battery_sensing = 1;
560
561
if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) &
···
566
567
data->battery_mode_gain.div = 2;
567
568
}
568
569
} else
569
-
dev_warn(&pdev->dev,
570
-
"Failed to enable battery-sensing mode\n");
570
+
dev_warn(dev, "Failed to enable battery-sensing mode\n");
571
571
}
572
572
573
573
ret = clk_prepare_enable(data->clk_scaler->clk);
574
574
if (ret)
575
575
return ret;
576
-
ret = devm_add_action_or_reset(data->dev,
577
-
aspeed_adc_clk_disable_unprepare,
576
+
ret = devm_add_action_or_reset(dev, aspeed_adc_clk_disable_unprepare,
578
577
data->clk_scaler->clk);
579
578
if (ret)
580
579
return ret;
···
590
593
writel(adc_engine_control_reg_val,
591
594
data->base + ASPEED_REG_ENGINE_CONTROL);
592
595
593
-
ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down,
594
-
data);
596
+
ret = devm_add_action_or_reset(dev, aspeed_adc_power_down, data);
595
597
if (ret)
596
598
return ret;
597
599
···
622
626
aspeed_adc_iio_channels;
623
627
indio_dev->num_channels = data->model_data->num_channels;
624
628
625
-
ret = devm_iio_device_register(data->dev, indio_dev);
626
-
return ret;
629
+
return devm_iio_device_register(dev, indio_dev);
627
630
}
628
631
629
632
static const struct aspeed_adc_trim_locate ast2500_adc_trim = {
+22
-35
drivers/iio/adc/exynos_adc.c
+22
-35
drivers/iio/adc/exynos_adc.c
···
543
543
static int exynos_adc_probe(struct platform_device *pdev)
544
544
{
545
545
struct exynos_adc *info = NULL;
546
+
struct device *dev = &pdev->dev;
546
547
struct device_node *np = pdev->dev.of_node;
547
548
struct iio_dev *indio_dev = NULL;
548
549
int ret;
549
550
int irq;
550
551
551
-
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
552
+
indio_dev = devm_iio_device_alloc(dev, sizeof(struct exynos_adc));
552
553
if (!indio_dev)
553
554
return -ENOMEM;
554
555
555
556
info = iio_priv(indio_dev);
556
557
557
558
info->data = exynos_adc_get_data(pdev);
558
-
if (!info->data) {
559
-
dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
560
-
return -EINVAL;
561
-
}
559
+
if (!info->data)
560
+
return dev_err_probe(dev, -EINVAL, "failed getting exynos_adc_data\n");
562
561
563
562
info->regs = devm_platform_ioremap_resource(pdev, 0);
564
563
if (IS_ERR(info->regs))
···
565
566
566
567
567
568
if (info->data->needs_adc_phy) {
568
-
info->pmu_map = syscon_regmap_lookup_by_phandle(
569
-
pdev->dev.of_node,
570
-
"samsung,syscon-phandle");
571
-
if (IS_ERR(info->pmu_map)) {
572
-
dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
573
-
return PTR_ERR(info->pmu_map);
574
-
}
569
+
info->pmu_map = syscon_regmap_lookup_by_phandle(np, "samsung,syscon-phandle");
570
+
if (IS_ERR(info->pmu_map))
571
+
return dev_err_probe(dev, PTR_ERR(info->pmu_map),
572
+
"syscon regmap lookup failed.\n");
575
573
}
576
574
577
575
irq = platform_get_irq(pdev, 0);
578
576
if (irq < 0)
579
577
return irq;
580
578
info->irq = irq;
581
-
info->dev = &pdev->dev;
579
+
info->dev = dev;
582
580
583
581
init_completion(&info->completion);
584
582
585
-
info->clk = devm_clk_get(&pdev->dev, "adc");
586
-
if (IS_ERR(info->clk)) {
587
-
dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
588
-
PTR_ERR(info->clk));
589
-
return PTR_ERR(info->clk);
590
-
}
583
+
info->clk = devm_clk_get(dev, "adc");
584
+
if (IS_ERR(info->clk))
585
+
return dev_err_probe(dev, PTR_ERR(info->clk), "failed getting clock\n");
591
586
592
587
if (info->data->needs_sclk) {
593
-
info->sclk = devm_clk_get(&pdev->dev, "sclk");
594
-
if (IS_ERR(info->sclk)) {
595
-
dev_err(&pdev->dev,
596
-
"failed getting sclk clock, err = %ld\n",
597
-
PTR_ERR(info->sclk));
598
-
return PTR_ERR(info->sclk);
599
-
}
588
+
info->sclk = devm_clk_get(dev, "sclk");
589
+
if (IS_ERR(info->sclk))
590
+
return dev_err_probe(dev, PTR_ERR(info->sclk),
591
+
"failed getting sclk clock\n");
600
592
}
601
593
602
-
info->vdd = devm_regulator_get(&pdev->dev, "vdd");
594
+
info->vdd = devm_regulator_get(dev, "vdd");
603
595
if (IS_ERR(info->vdd))
604
-
return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
605
-
"failed getting regulator");
596
+
return dev_err_probe(dev, PTR_ERR(info->vdd), "failed getting regulator");
606
597
607
598
ret = regulator_enable(info->vdd);
608
599
if (ret)
···
608
619
609
620
platform_set_drvdata(pdev, indio_dev);
610
621
611
-
indio_dev->name = dev_name(&pdev->dev);
622
+
indio_dev->name = dev_name(dev);
612
623
indio_dev->info = &exynos_adc_iio_info;
613
624
indio_dev->modes = INDIO_DIRECT_MODE;
614
625
indio_dev->channels = exynos_adc_iio_channels;
···
616
627
617
628
mutex_init(&info->lock);
618
629
619
-
ret = request_irq(info->irq, exynos_adc_isr,
620
-
0, dev_name(&pdev->dev), info);
630
+
ret = request_irq(info->irq, exynos_adc_isr, 0, dev_name(dev), info);
621
631
if (ret < 0) {
622
-
dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
623
-
info->irq);
632
+
dev_err(dev, "failed requesting irq, irq = %d\n", info->irq);
624
633
goto err_disable_clk;
625
634
}
626
635
···
631
644
632
645
ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
633
646
if (ret < 0) {
634
-
dev_err(&pdev->dev, "failed adding child nodes\n");
647
+
dev_err(dev, "failed adding child nodes\n");
635
648
goto err_of_populate;
636
649
}
637
650
+1
-1
drivers/iio/adc/mcp3911.c
+1
-1
drivers/iio/adc/mcp3911.c
···
815
815
* don't enable the interrupt to avoid extra load on the system.
816
816
*/
817
817
ret = devm_request_irq(dev, spi->irq, &iio_trigger_generic_data_rdy_poll,
818
-
IRQF_NO_AUTOEN | IRQF_ONESHOT,
818
+
IRQF_NO_AUTOEN | IRQF_NO_THREAD,
819
819
indio_dev->name, adc->trig);
820
820
if (ret)
821
821
return ret;
-1
drivers/iio/adc/men_z188_adc.c
-1
drivers/iio/adc/men_z188_adc.c
+1016
drivers/iio/adc/nxp-sar-adc.c
+1016
drivers/iio/adc/nxp-sar-adc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* NXP SAR-ADC driver (adapted from Freescale Vybrid vf610 ADC driver
4
+
* by Fugang Duan <B38611@freescale.com>)
5
+
*
6
+
* Copyright 2013 Freescale Semiconductor, Inc.
7
+
* Copyright 2017, 2020-2025 NXP
8
+
* Copyright 2025, Linaro Ltd
9
+
*/
10
+
#include <linux/bitfield.h>
11
+
#include <linux/bitops.h>
12
+
#include <linux/circ_buf.h>
13
+
#include <linux/cleanup.h>
14
+
#include <linux/clk.h>
15
+
#include <linux/completion.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/dma-mapping.h>
18
+
#include <linux/dmaengine.h>
19
+
#include <linux/err.h>
20
+
#include <linux/interrupt.h>
21
+
#include <linux/iopoll.h>
22
+
#include <linux/math64.h>
23
+
#include <linux/minmax.h>
24
+
#include <linux/mod_devicetable.h>
25
+
#include <linux/module.h>
26
+
#include <linux/platform_device.h>
27
+
#include <linux/pm.h>
28
+
#include <linux/property.h>
29
+
#include <linux/slab.h>
30
+
#include <linux/spinlock.h>
31
+
#include <linux/time.h>
32
+
#include <linux/types.h>
33
+
#include <linux/units.h>
34
+
35
+
#include <linux/iio/iio.h>
36
+
#include <linux/iio/triggered_buffer.h>
37
+
#include <linux/iio/trigger_consumer.h>
38
+
39
+
/* SAR ADC registers. */
40
+
#define NXP_SAR_ADC_CDR(__base, __channel) (((__base) + 0x100) + ((__channel) * 0x4))
41
+
42
+
#define NXP_SAR_ADC_CDR_CDATA_MASK GENMASK(11, 0)
43
+
#define NXP_SAR_ADC_CDR_VALID BIT(19)
44
+
45
+
/* Main Configuration Register */
46
+
#define NXP_SAR_ADC_MCR(__base) ((__base) + 0x00)
47
+
48
+
#define NXP_SAR_ADC_MCR_PWDN BIT(0)
49
+
#define NXP_SAR_ADC_MCR_ACKO BIT(5)
50
+
#define NXP_SAR_ADC_MCR_ADCLKSEL BIT(8)
51
+
#define NXP_SAR_ADC_MCR_TSAMP_MASK GENMASK(10, 9)
52
+
#define NXP_SAR_ADC_MCR_NRSMPL_MASK GENMASK(12, 11)
53
+
#define NXP_SAR_ADC_MCR_AVGEN BIT(13)
54
+
#define NXP_SAR_ADC_MCR_CALSTART BIT(14)
55
+
#define NXP_SAR_ADC_MCR_NSTART BIT(24)
56
+
#define NXP_SAR_ADC_MCR_MODE BIT(29)
57
+
#define NXP_SAR_ADC_MCR_OWREN BIT(31)
58
+
59
+
/* Main Status Register */
60
+
#define NXP_SAR_ADC_MSR(__base) ((__base) + 0x04)
61
+
62
+
#define NXP_SAR_ADC_MSR_CALBUSY BIT(29)
63
+
#define NXP_SAR_ADC_MSR_CALFAIL BIT(30)
64
+
65
+
/* Interrupt Status Register */
66
+
#define NXP_SAR_ADC_ISR(__base) ((__base) + 0x10)
67
+
68
+
#define NXP_SAR_ADC_ISR_ECH BIT(0)
69
+
70
+
/* Channel Pending Register */
71
+
#define NXP_SAR_ADC_CEOCFR0(__base) ((__base) + 0x14)
72
+
#define NXP_SAR_ADC_CEOCFR1(__base) ((__base) + 0x18)
73
+
74
+
#define NXP_SAR_ADC_EOC_CH(c) BIT(c)
75
+
76
+
/* Interrupt Mask Register */
77
+
#define NXP_SAR_ADC_IMR(__base) ((__base) + 0x20)
78
+
79
+
/* Channel Interrupt Mask Register */
80
+
#define NXP_SAR_ADC_CIMR0(__base) ((__base) + 0x24)
81
+
#define NXP_SAR_ADC_CIMR1(__base) ((__base) + 0x28)
82
+
83
+
/* DMA Setting Register */
84
+
#define NXP_SAR_ADC_DMAE(__base) ((__base) + 0x40)
85
+
86
+
#define NXP_SAR_ADC_DMAE_DMAEN BIT(0)
87
+
#define NXP_SAR_ADC_DMAE_DCLR BIT(1)
88
+
89
+
/* DMA Control register */
90
+
#define NXP_SAR_ADC_DMAR0(__base) ((__base) + 0x44)
91
+
#define NXP_SAR_ADC_DMAR1(__base) ((__base) + 0x48)
92
+
93
+
/* Conversion Timing Register */
94
+
#define NXP_SAR_ADC_CTR0(__base) ((__base) + 0x94)
95
+
#define NXP_SAR_ADC_CTR1(__base) ((__base) + 0x98)
96
+
97
+
#define NXP_SAR_ADC_CTR_INPSAMP_MIN 0x08
98
+
#define NXP_SAR_ADC_CTR_INPSAMP_MAX 0xff
99
+
100
+
/* Normal Conversion Mask Register */
101
+
#define NXP_SAR_ADC_NCMR0(__base) ((__base) + 0xa4)
102
+
#define NXP_SAR_ADC_NCMR1(__base) ((__base) + 0xa8)
103
+
104
+
/* Normal Conversion Mask Register field define */
105
+
#define NXP_SAR_ADC_CH_MASK GENMASK(7, 0)
106
+
107
+
/* Other field define */
108
+
#define NXP_SAR_ADC_CONV_TIMEOUT (msecs_to_jiffies(100))
109
+
#define NXP_SAR_ADC_CAL_TIMEOUT_US (100 * USEC_PER_MSEC)
110
+
#define NXP_SAR_ADC_WAIT_US (2 * USEC_PER_MSEC)
111
+
#define NXP_SAR_ADC_RESOLUTION 12
112
+
113
+
/* Duration of conversion phases */
114
+
#define NXP_SAR_ADC_TPT 2
115
+
#define NXP_SAR_ADC_DP 2
116
+
#define NXP_SAR_ADC_CT ((NXP_SAR_ADC_RESOLUTION + 2) * 4)
117
+
#define NXP_SAR_ADC_CONV_TIME (NXP_SAR_ADC_TPT + NXP_SAR_ADC_CT + NXP_SAR_ADC_DP)
118
+
119
+
#define NXP_SAR_ADC_NR_CHANNELS 8
120
+
121
+
#define NXP_PAGE_SIZE SZ_4K
122
+
#define NXP_SAR_ADC_DMA_SAMPLE_SZ DMA_SLAVE_BUSWIDTH_4_BYTES
123
+
#define NXP_SAR_ADC_DMA_BUFF_SZ (NXP_PAGE_SIZE * NXP_SAR_ADC_DMA_SAMPLE_SZ)
124
+
#define NXP_SAR_ADC_DMA_SAMPLE_CNT (NXP_SAR_ADC_DMA_BUFF_SZ / NXP_SAR_ADC_DMA_SAMPLE_SZ)
125
+
126
+
struct nxp_sar_adc {
127
+
void __iomem *regs;
128
+
phys_addr_t regs_phys;
129
+
u8 current_channel;
130
+
u8 channels_used;
131
+
u16 value;
132
+
u32 vref_mV;
133
+
134
+
/* Save and restore context. */
135
+
u32 inpsamp;
136
+
u32 pwdn;
137
+
138
+
struct clk *clk;
139
+
struct dma_chan *dma_chan;
140
+
struct completion completion;
141
+
struct circ_buf dma_buf;
142
+
143
+
dma_addr_t rx_dma_buf;
144
+
dma_cookie_t cookie;
145
+
146
+
/* Protect circular buffers access. */
147
+
spinlock_t lock;
148
+
149
+
/* Array of enabled channels. */
150
+
u16 buffered_chan[NXP_SAR_ADC_NR_CHANNELS];
151
+
152
+
/* Buffer to be filled by the DMA. */
153
+
IIO_DECLARE_BUFFER_WITH_TS(u16, buffer, NXP_SAR_ADC_NR_CHANNELS);
154
+
};
155
+
156
+
struct nxp_sar_adc_data {
157
+
u32 vref_mV;
158
+
const char *model;
159
+
};
160
+
161
+
#define ADC_CHAN(_idx, _chan_type) { \
162
+
.type = (_chan_type), \
163
+
.indexed = 1, \
164
+
.channel = (_idx), \
165
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
166
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
167
+
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
168
+
.scan_index = (_idx), \
169
+
.scan_type = { \
170
+
.sign = 'u', \
171
+
.realbits = 12, \
172
+
.storagebits = 16, \
173
+
}, \
174
+
}
175
+
176
+
static const struct iio_chan_spec nxp_sar_adc_iio_channels[] = {
177
+
ADC_CHAN(0, IIO_VOLTAGE),
178
+
ADC_CHAN(1, IIO_VOLTAGE),
179
+
ADC_CHAN(2, IIO_VOLTAGE),
180
+
ADC_CHAN(3, IIO_VOLTAGE),
181
+
ADC_CHAN(4, IIO_VOLTAGE),
182
+
ADC_CHAN(5, IIO_VOLTAGE),
183
+
ADC_CHAN(6, IIO_VOLTAGE),
184
+
ADC_CHAN(7, IIO_VOLTAGE),
185
+
/*
186
+
* The NXP SAR ADC documentation marks the channels 8 to 31 as
187
+
* "Reserved". Reflect the same in the driver in case new ADC
188
+
* variants comes with more channels.
189
+
*/
190
+
IIO_CHAN_SOFT_TIMESTAMP(32),
191
+
};
192
+
193
+
static void nxp_sar_adc_irq_cfg(struct nxp_sar_adc *info, bool enable)
194
+
{
195
+
if (enable)
196
+
writel(NXP_SAR_ADC_ISR_ECH, NXP_SAR_ADC_IMR(info->regs));
197
+
else
198
+
writel(0, NXP_SAR_ADC_IMR(info->regs));
199
+
}
200
+
201
+
static bool nxp_sar_adc_set_enabled(struct nxp_sar_adc *info, bool enable)
202
+
{
203
+
u32 mcr;
204
+
bool pwdn;
205
+
206
+
mcr = readl(NXP_SAR_ADC_MCR(info->regs));
207
+
208
+
/*
209
+
* Get the current state and return it later. This is used for
210
+
* suspend/resume to get the power state
211
+
*/
212
+
pwdn = FIELD_GET(NXP_SAR_ADC_MCR_PWDN, mcr);
213
+
214
+
/* When the enabled flag is not set, we set the power down bit */
215
+
FIELD_MODIFY(NXP_SAR_ADC_MCR_PWDN, &mcr, !enable);
216
+
217
+
writel(mcr, NXP_SAR_ADC_MCR(info->regs));
218
+
219
+
/*
220
+
* Ensure there are at least three cycles between the
221
+
* configuration of NCMR and the setting of NSTART.
222
+
*/
223
+
if (enable)
224
+
ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk) * 3));
225
+
226
+
return pwdn;
227
+
}
228
+
229
+
static inline bool nxp_sar_adc_enable(struct nxp_sar_adc *info)
230
+
{
231
+
return nxp_sar_adc_set_enabled(info, true);
232
+
}
233
+
234
+
static inline bool nxp_sar_adc_disable(struct nxp_sar_adc *info)
235
+
{
236
+
return nxp_sar_adc_set_enabled(info, false);
237
+
}
238
+
239
+
static inline void nxp_sar_adc_calibration_start(void __iomem *base)
240
+
{
241
+
u32 mcr = readl(NXP_SAR_ADC_MCR(base));
242
+
243
+
FIELD_MODIFY(NXP_SAR_ADC_MCR_CALSTART, &mcr, 0x1);
244
+
245
+
writel(mcr, NXP_SAR_ADC_MCR(base));
246
+
}
247
+
248
+
static inline int nxp_sar_adc_calibration_wait(void __iomem *base)
249
+
{
250
+
u32 msr, ret;
251
+
252
+
ret = readl_poll_timeout(NXP_SAR_ADC_MSR(base), msr,
253
+
!FIELD_GET(NXP_SAR_ADC_MSR_CALBUSY, msr),
254
+
NXP_SAR_ADC_WAIT_US,
255
+
NXP_SAR_ADC_CAL_TIMEOUT_US);
256
+
if (ret)
257
+
return ret;
258
+
259
+
if (FIELD_GET(NXP_SAR_ADC_MSR_CALFAIL, msr)) {
260
+
/*
261
+
* If the calibration fails, the status register bit must be
262
+
* cleared.
263
+
*/
264
+
FIELD_MODIFY(NXP_SAR_ADC_MSR_CALFAIL, &msr, 0x0);
265
+
writel(msr, NXP_SAR_ADC_MSR(base));
266
+
267
+
return -EAGAIN;
268
+
}
269
+
270
+
return 0;
271
+
}
272
+
273
+
static int nxp_sar_adc_calibration(struct nxp_sar_adc *info)
274
+
{
275
+
int ret;
276
+
277
+
/* Calibration works only if the ADC is powered up. */
278
+
nxp_sar_adc_enable(info);
279
+
280
+
/* The calibration operation starts. */
281
+
nxp_sar_adc_calibration_start(info->regs);
282
+
283
+
ret = nxp_sar_adc_calibration_wait(info->regs);
284
+
285
+
/*
286
+
* Calibration works only if the ADC is powered up. However
287
+
* the calibration is called from the probe function where the
288
+
* iio is not enabled, so we disable after the calibration.
289
+
*/
290
+
nxp_sar_adc_disable(info);
291
+
292
+
return ret;
293
+
}
294
+
295
+
static void nxp_sar_adc_conversion_timing_set(struct nxp_sar_adc *info, u32 inpsamp)
296
+
{
297
+
inpsamp = clamp(inpsamp, NXP_SAR_ADC_CTR_INPSAMP_MIN, NXP_SAR_ADC_CTR_INPSAMP_MAX);
298
+
299
+
writel(inpsamp, NXP_SAR_ADC_CTR0(info->regs));
300
+
}
301
+
302
+
static u32 nxp_sar_adc_conversion_timing_get(struct nxp_sar_adc *info)
303
+
{
304
+
return readl(NXP_SAR_ADC_CTR0(info->regs));
305
+
}
306
+
307
+
static void nxp_sar_adc_read_notify(struct nxp_sar_adc *info)
308
+
{
309
+
writel(NXP_SAR_ADC_CH_MASK, NXP_SAR_ADC_CEOCFR0(info->regs));
310
+
writel(NXP_SAR_ADC_CH_MASK, NXP_SAR_ADC_CEOCFR1(info->regs));
311
+
}
312
+
313
+
static int nxp_sar_adc_read_data(struct nxp_sar_adc *info, unsigned int chan)
314
+
{
315
+
u32 ceocfr, cdr;
316
+
317
+
ceocfr = readl(NXP_SAR_ADC_CEOCFR0(info->regs));
318
+
319
+
/*
320
+
* FIELD_GET() can not be used here because EOC_CH is not constant.
321
+
* TODO: Switch to field_get() when it will be available.
322
+
*/
323
+
if (!(NXP_SAR_ADC_EOC_CH(chan) & ceocfr))
324
+
return -EIO;
325
+
326
+
cdr = readl(NXP_SAR_ADC_CDR(info->regs, chan));
327
+
if (!(FIELD_GET(NXP_SAR_ADC_CDR_VALID, cdr)))
328
+
return -EIO;
329
+
330
+
return FIELD_GET(NXP_SAR_ADC_CDR_CDATA_MASK, cdr);
331
+
}
332
+
333
+
static void nxp_sar_adc_isr_buffer(struct iio_dev *indio_dev)
334
+
{
335
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
336
+
unsigned int i;
337
+
int ret;
338
+
339
+
for (i = 0; i < info->channels_used; i++) {
340
+
ret = nxp_sar_adc_read_data(info, info->buffered_chan[i]);
341
+
if (ret < 0) {
342
+
nxp_sar_adc_read_notify(info);
343
+
return;
344
+
}
345
+
346
+
info->buffer[i] = ret;
347
+
}
348
+
349
+
nxp_sar_adc_read_notify(info);
350
+
351
+
iio_push_to_buffers_with_ts(indio_dev, info->buffer, sizeof(info->buffer),
352
+
iio_get_time_ns(indio_dev));
353
+
354
+
iio_trigger_notify_done(indio_dev->trig);
355
+
}
356
+
357
+
static void nxp_sar_adc_isr_read_raw(struct iio_dev *indio_dev)
358
+
{
359
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
360
+
int ret;
361
+
362
+
ret = nxp_sar_adc_read_data(info, info->current_channel);
363
+
nxp_sar_adc_read_notify(info);
364
+
if (ret < 0)
365
+
return;
366
+
367
+
info->value = ret;
368
+
complete(&info->completion);
369
+
}
370
+
371
+
static irqreturn_t nxp_sar_adc_isr(int irq, void *dev_id)
372
+
{
373
+
struct iio_dev *indio_dev = dev_id;
374
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
375
+
int isr;
376
+
377
+
isr = readl(NXP_SAR_ADC_ISR(info->regs));
378
+
if (!(FIELD_GET(NXP_SAR_ADC_ISR_ECH, isr)))
379
+
return IRQ_NONE;
380
+
381
+
if (iio_buffer_enabled(indio_dev))
382
+
nxp_sar_adc_isr_buffer(indio_dev);
383
+
else
384
+
nxp_sar_adc_isr_read_raw(indio_dev);
385
+
386
+
writel(NXP_SAR_ADC_ISR_ECH, NXP_SAR_ADC_ISR(info->regs));
387
+
388
+
return IRQ_HANDLED;
389
+
}
390
+
391
+
static void nxp_sar_adc_channels_disable(struct nxp_sar_adc *info, u32 mask)
392
+
{
393
+
u32 ncmr, cimr;
394
+
395
+
ncmr = readl(NXP_SAR_ADC_NCMR0(info->regs));
396
+
cimr = readl(NXP_SAR_ADC_CIMR0(info->regs));
397
+
398
+
/* FIELD_MODIFY() can not be used because the mask is not constant */
399
+
ncmr &= ~mask;
400
+
cimr &= ~mask;
401
+
402
+
writel(ncmr, NXP_SAR_ADC_NCMR0(info->regs));
403
+
writel(cimr, NXP_SAR_ADC_CIMR0(info->regs));
404
+
}
405
+
406
+
static void nxp_sar_adc_channels_enable(struct nxp_sar_adc *info, u32 mask)
407
+
{
408
+
u32 ncmr, cimr;
409
+
410
+
ncmr = readl(NXP_SAR_ADC_NCMR0(info->regs));
411
+
cimr = readl(NXP_SAR_ADC_CIMR0(info->regs));
412
+
413
+
ncmr |= mask;
414
+
cimr |= mask;
415
+
416
+
writel(ncmr, NXP_SAR_ADC_NCMR0(info->regs));
417
+
writel(cimr, NXP_SAR_ADC_CIMR0(info->regs));
418
+
}
419
+
420
+
static void nxp_sar_adc_dma_channels_enable(struct nxp_sar_adc *info, u32 mask)
421
+
{
422
+
u32 dmar;
423
+
424
+
dmar = readl(NXP_SAR_ADC_DMAR0(info->regs));
425
+
426
+
dmar |= mask;
427
+
428
+
writel(dmar, NXP_SAR_ADC_DMAR0(info->regs));
429
+
}
430
+
431
+
static void nxp_sar_adc_dma_channels_disable(struct nxp_sar_adc *info, u32 mask)
432
+
{
433
+
u32 dmar;
434
+
435
+
dmar = readl(NXP_SAR_ADC_DMAR0(info->regs));
436
+
437
+
dmar &= ~mask;
438
+
439
+
writel(dmar, NXP_SAR_ADC_DMAR0(info->regs));
440
+
}
441
+
442
+
static void nxp_sar_adc_dma_cfg(struct nxp_sar_adc *info, bool enable)
443
+
{
444
+
u32 dmae;
445
+
446
+
dmae = readl(NXP_SAR_ADC_DMAE(info->regs));
447
+
448
+
FIELD_MODIFY(NXP_SAR_ADC_DMAE_DMAEN, &dmae, enable);
449
+
450
+
writel(dmae, NXP_SAR_ADC_DMAE(info->regs));
451
+
}
452
+
453
+
static void nxp_sar_adc_stop_conversion(struct nxp_sar_adc *info)
454
+
{
455
+
u32 mcr;
456
+
457
+
mcr = readl(NXP_SAR_ADC_MCR(info->regs));
458
+
459
+
FIELD_MODIFY(NXP_SAR_ADC_MCR_NSTART, &mcr, 0x0);
460
+
461
+
writel(mcr, NXP_SAR_ADC_MCR(info->regs));
462
+
463
+
/*
464
+
* On disable, we have to wait for the transaction to finish.
465
+
* ADC does not abort the transaction if a chain conversion is
466
+
* in progress. Wait for the worst case scenario - 80 ADC clk
467
+
* cycles. The clock rate is 80MHz, this routine is called
468
+
* only when the capture finishes. The delay will be very
469
+
* short, usec-ish, which is acceptable in the atomic context.
470
+
*/
471
+
ndelay(div64_u64(NSEC_PER_SEC, clk_get_rate(info->clk)) * 80);
472
+
}
473
+
474
+
static int nxp_sar_adc_start_conversion(struct nxp_sar_adc *info, bool raw)
475
+
{
476
+
u32 mcr;
477
+
478
+
mcr = readl(NXP_SAR_ADC_MCR(info->regs));
479
+
480
+
FIELD_MODIFY(NXP_SAR_ADC_MCR_NSTART, &mcr, 0x1);
481
+
FIELD_MODIFY(NXP_SAR_ADC_MCR_MODE, &mcr, raw ? 0 : 1);
482
+
483
+
writel(mcr, NXP_SAR_ADC_MCR(info->regs));
484
+
485
+
return 0;
486
+
}
487
+
488
+
static int nxp_sar_adc_read_channel(struct nxp_sar_adc *info, int channel)
489
+
{
490
+
int ret;
491
+
492
+
info->current_channel = channel;
493
+
nxp_sar_adc_channels_enable(info, BIT(channel));
494
+
nxp_sar_adc_irq_cfg(info, true);
495
+
nxp_sar_adc_enable(info);
496
+
497
+
reinit_completion(&info->completion);
498
+
ret = nxp_sar_adc_start_conversion(info, true);
499
+
if (ret < 0)
500
+
goto out_disable;
501
+
502
+
if (!wait_for_completion_interruptible_timeout(&info->completion,
503
+
NXP_SAR_ADC_CONV_TIMEOUT))
504
+
ret = -ETIMEDOUT;
505
+
506
+
nxp_sar_adc_stop_conversion(info);
507
+
508
+
out_disable:
509
+
nxp_sar_adc_channels_disable(info, BIT(channel));
510
+
nxp_sar_adc_irq_cfg(info, false);
511
+
nxp_sar_adc_disable(info);
512
+
513
+
return ret;
514
+
}
515
+
516
+
static int nxp_sar_adc_read_raw(struct iio_dev *indio_dev,
517
+
struct iio_chan_spec const *chan, int *val,
518
+
int *val2, long mask)
519
+
{
520
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
521
+
u32 inpsamp;
522
+
int ret;
523
+
524
+
switch (mask) {
525
+
case IIO_CHAN_INFO_RAW:
526
+
if (!iio_device_claim_direct(indio_dev))
527
+
return -EBUSY;
528
+
529
+
ret = nxp_sar_adc_read_channel(info, chan->channel);
530
+
531
+
iio_device_release_direct(indio_dev);
532
+
533
+
if (ret)
534
+
return ret;
535
+
536
+
*val = info->value;
537
+
return IIO_VAL_INT;
538
+
539
+
case IIO_CHAN_INFO_SCALE:
540
+
*val = info->vref_mV;
541
+
*val2 = NXP_SAR_ADC_RESOLUTION;
542
+
return IIO_VAL_FRACTIONAL_LOG2;
543
+
544
+
case IIO_CHAN_INFO_SAMP_FREQ:
545
+
inpsamp = nxp_sar_adc_conversion_timing_get(info);
546
+
*val = clk_get_rate(info->clk) / (inpsamp + NXP_SAR_ADC_CONV_TIME);
547
+
return IIO_VAL_INT;
548
+
549
+
default:
550
+
return -EINVAL;
551
+
}
552
+
}
553
+
554
+
static int nxp_sar_adc_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
555
+
int val, int val2, long mask)
556
+
{
557
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
558
+
u32 inpsamp;
559
+
560
+
switch (mask) {
561
+
case IIO_CHAN_INFO_SAMP_FREQ:
562
+
/*
563
+
* Configures the sample period duration in terms of the SAR
564
+
* controller clock. The minimum acceptable value is 8.
565
+
* Configuring it to a value lower than 8 sets the sample period
566
+
* to 8 cycles. We read the clock value and divide by the
567
+
* sampling timing which gives us the number of cycles expected.
568
+
* The value is 8-bit wide, consequently the max value is 0xFF.
569
+
*/
570
+
inpsamp = clk_get_rate(info->clk) / val - NXP_SAR_ADC_CONV_TIME;
571
+
nxp_sar_adc_conversion_timing_set(info, inpsamp);
572
+
return 0;
573
+
574
+
default:
575
+
return -EINVAL;
576
+
}
577
+
}
578
+
579
+
static void nxp_sar_adc_dma_cb(void *data)
580
+
{
581
+
struct iio_dev *indio_dev = data;
582
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
583
+
struct dma_tx_state state;
584
+
struct circ_buf *dma_buf;
585
+
struct device *dev_dma;
586
+
u32 *dma_samples;
587
+
s64 timestamp;
588
+
int idx, ret;
589
+
590
+
guard(spinlock_irqsave)(&info->lock);
591
+
592
+
dma_buf = &info->dma_buf;
593
+
dma_samples = (u32 *)dma_buf->buf;
594
+
dev_dma = info->dma_chan->device->dev;
595
+
596
+
/*
597
+
* DMA in some corner cases might have already be charged for
598
+
* the next transfer. Potentially there can be a race where
599
+
* the residue changes while the dma engine updates the
600
+
* buffer. That could be handled by using the
601
+
* callback_result() instead of callback() because the residue
602
+
* will be passed as a parameter to the function. However this
603
+
* new callback is pretty new and the backend does not update
604
+
* the residue. So let's stick to the version other drivers do
605
+
* which has proven running well in production since several
606
+
* years.
607
+
*/
608
+
dmaengine_tx_status(info->dma_chan, info->cookie, &state);
609
+
610
+
dma_sync_single_for_cpu(dev_dma, info->rx_dma_buf,
611
+
NXP_SAR_ADC_DMA_BUFF_SZ, DMA_FROM_DEVICE);
612
+
613
+
/* Current head position. */
614
+
dma_buf->head = (NXP_SAR_ADC_DMA_BUFF_SZ - state.residue) /
615
+
NXP_SAR_ADC_DMA_SAMPLE_SZ;
616
+
617
+
/* If everything was transferred, avoid an off by one error. */
618
+
if (!state.residue)
619
+
dma_buf->head--;
620
+
621
+
/* Something went wrong and nothing transferred. */
622
+
if (state.residue != NXP_SAR_ADC_DMA_BUFF_SZ) {
623
+
/* Make sure that head is multiple of info->channels_used. */
624
+
dma_buf->head -= dma_buf->head % info->channels_used;
625
+
626
+
/*
627
+
* dma_buf->tail != dma_buf->head condition will become false
628
+
* because dma_buf->tail will be incremented with 1.
629
+
*/
630
+
while (dma_buf->tail != dma_buf->head) {
631
+
idx = dma_buf->tail % info->channels_used;
632
+
info->buffer[idx] = dma_samples[dma_buf->tail];
633
+
dma_buf->tail = (dma_buf->tail + 1) % NXP_SAR_ADC_DMA_SAMPLE_CNT;
634
+
if (idx != info->channels_used - 1)
635
+
continue;
636
+
637
+
/*
638
+
* iio_push_to_buffers_with_ts() should not be
639
+
* called with dma_samples as parameter. The samples
640
+
* will be smashed if timestamp is enabled.
641
+
*/
642
+
timestamp = iio_get_time_ns(indio_dev);
643
+
ret = iio_push_to_buffers_with_ts(indio_dev, info->buffer,
644
+
sizeof(info->buffer),
645
+
timestamp);
646
+
if (ret < 0 && ret != -EBUSY)
647
+
dev_err_ratelimited(&indio_dev->dev,
648
+
"failed to push iio buffer: %d",
649
+
ret);
650
+
}
651
+
652
+
dma_buf->tail = dma_buf->head;
653
+
}
654
+
655
+
dma_sync_single_for_device(dev_dma, info->rx_dma_buf,
656
+
NXP_SAR_ADC_DMA_BUFF_SZ, DMA_FROM_DEVICE);
657
+
}
658
+
659
+
static int nxp_sar_adc_start_cyclic_dma(struct iio_dev *indio_dev)
660
+
{
661
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
662
+
struct dma_slave_config config;
663
+
struct dma_async_tx_descriptor *desc;
664
+
int ret;
665
+
666
+
info->dma_buf.head = 0;
667
+
info->dma_buf.tail = 0;
668
+
669
+
config.direction = DMA_DEV_TO_MEM;
670
+
config.src_addr_width = NXP_SAR_ADC_DMA_SAMPLE_SZ;
671
+
config.src_addr = NXP_SAR_ADC_CDR(info->regs_phys, info->buffered_chan[0]);
672
+
config.src_port_window_size = info->channels_used;
673
+
config.src_maxburst = info->channels_used;
674
+
ret = dmaengine_slave_config(info->dma_chan, &config);
675
+
if (ret < 0)
676
+
return ret;
677
+
678
+
desc = dmaengine_prep_dma_cyclic(info->dma_chan,
679
+
info->rx_dma_buf,
680
+
NXP_SAR_ADC_DMA_BUFF_SZ,
681
+
NXP_SAR_ADC_DMA_BUFF_SZ / 2,
682
+
DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
683
+
if (!desc)
684
+
return -EINVAL;
685
+
686
+
desc->callback = nxp_sar_adc_dma_cb;
687
+
desc->callback_param = indio_dev;
688
+
info->cookie = dmaengine_submit(desc);
689
+
ret = dma_submit_error(info->cookie);
690
+
if (ret) {
691
+
dmaengine_terminate_async(info->dma_chan);
692
+
return ret;
693
+
}
694
+
695
+
dma_async_issue_pending(info->dma_chan);
696
+
697
+
return 0;
698
+
}
699
+
700
+
static void nxp_sar_adc_buffer_software_do_predisable(struct iio_dev *indio_dev)
701
+
{
702
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
703
+
704
+
/*
705
+
* The ADC DMAEN bit should be cleared before DMA transaction
706
+
* is canceled.
707
+
*/
708
+
nxp_sar_adc_stop_conversion(info);
709
+
dmaengine_terminate_sync(info->dma_chan);
710
+
nxp_sar_adc_dma_cfg(info, false);
711
+
nxp_sar_adc_dma_channels_disable(info, *indio_dev->active_scan_mask);
712
+
713
+
dma_release_channel(info->dma_chan);
714
+
}
715
+
716
+
static int nxp_sar_adc_buffer_software_do_postenable(struct iio_dev *indio_dev)
717
+
{
718
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
719
+
int ret;
720
+
721
+
nxp_sar_adc_dma_channels_enable(info, *indio_dev->active_scan_mask);
722
+
723
+
nxp_sar_adc_dma_cfg(info, true);
724
+
725
+
ret = nxp_sar_adc_start_cyclic_dma(indio_dev);
726
+
if (ret)
727
+
goto out_dma_channels_disable;
728
+
729
+
ret = nxp_sar_adc_start_conversion(info, false);
730
+
if (ret)
731
+
goto out_stop_cyclic_dma;
732
+
733
+
return 0;
734
+
735
+
out_stop_cyclic_dma:
736
+
dmaengine_terminate_sync(info->dma_chan);
737
+
738
+
out_dma_channels_disable:
739
+
nxp_sar_adc_dma_cfg(info, false);
740
+
nxp_sar_adc_dma_channels_disable(info, *indio_dev->active_scan_mask);
741
+
742
+
return ret;
743
+
}
744
+
745
+
static void nxp_sar_adc_buffer_trigger_do_predisable(struct iio_dev *indio_dev)
746
+
{
747
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
748
+
749
+
nxp_sar_adc_irq_cfg(info, false);
750
+
}
751
+
752
+
static int nxp_sar_adc_buffer_trigger_do_postenable(struct iio_dev *indio_dev)
753
+
{
754
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
755
+
756
+
nxp_sar_adc_irq_cfg(info, true);
757
+
758
+
return 0;
759
+
}
760
+
761
+
static int nxp_sar_adc_buffer_postenable(struct iio_dev *indio_dev)
762
+
{
763
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
764
+
int current_mode = iio_device_get_current_mode(indio_dev);
765
+
unsigned long channel;
766
+
int ret;
767
+
768
+
info->dma_chan = dma_request_chan(indio_dev->dev.parent, "rx");
769
+
if (IS_ERR(info->dma_chan))
770
+
return PTR_ERR(info->dma_chan);
771
+
772
+
info->channels_used = 0;
773
+
774
+
/*
775
+
* The SAR-ADC has two groups of channels.
776
+
*
777
+
* - Group #0:
778
+
* * bit 0-7 : channel 0 -> channel 7
779
+
* * bit 8-31 : reserved
780
+
*
781
+
* - Group #32:
782
+
* * bit 0-7 : Internal
783
+
* * bit 8-31 : reserved
784
+
*
785
+
* The 8 channels from group #0 are used in this driver for
786
+
* ADC as described when declaring the IIO device and the
787
+
* mapping is the same. That means the active_scan_mask can be
788
+
* used directly to write the channel interrupt mask.
789
+
*/
790
+
nxp_sar_adc_channels_enable(info, *indio_dev->active_scan_mask);
791
+
792
+
for_each_set_bit(channel, indio_dev->active_scan_mask, NXP_SAR_ADC_NR_CHANNELS)
793
+
info->buffered_chan[info->channels_used++] = channel;
794
+
795
+
nxp_sar_adc_enable(info);
796
+
797
+
if (current_mode == INDIO_BUFFER_SOFTWARE)
798
+
ret = nxp_sar_adc_buffer_software_do_postenable(indio_dev);
799
+
else
800
+
ret = nxp_sar_adc_buffer_trigger_do_postenable(indio_dev);
801
+
if (ret)
802
+
goto out_postenable;
803
+
804
+
return 0;
805
+
806
+
out_postenable:
807
+
nxp_sar_adc_disable(info);
808
+
nxp_sar_adc_channels_disable(info, *indio_dev->active_scan_mask);
809
+
810
+
return ret;
811
+
}
812
+
813
+
static int nxp_sar_adc_buffer_predisable(struct iio_dev *indio_dev)
814
+
{
815
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
816
+
int currentmode = iio_device_get_current_mode(indio_dev);
817
+
818
+
if (currentmode == INDIO_BUFFER_SOFTWARE)
819
+
nxp_sar_adc_buffer_software_do_predisable(indio_dev);
820
+
else
821
+
nxp_sar_adc_buffer_trigger_do_predisable(indio_dev);
822
+
823
+
nxp_sar_adc_disable(info);
824
+
825
+
nxp_sar_adc_channels_disable(info, *indio_dev->active_scan_mask);
826
+
827
+
return 0;
828
+
}
829
+
830
+
static irqreturn_t nxp_sar_adc_trigger_handler(int irq, void *p)
831
+
{
832
+
struct iio_poll_func *pf = p;
833
+
struct iio_dev *indio_dev = pf->indio_dev;
834
+
struct nxp_sar_adc *info = iio_priv(indio_dev);
835
+
int ret;
836
+
837
+
ret = nxp_sar_adc_start_conversion(info, true);
838
+
if (ret < 0)
839
+
dev_dbg(&indio_dev->dev, "Failed to start conversion\n");
840
+
841
+
return IRQ_HANDLED;
842
+
}
843
+
844
+
static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
845
+
.postenable = nxp_sar_adc_buffer_postenable,
846
+
.predisable = nxp_sar_adc_buffer_predisable,
847
+
};
848
+
849
+
static const struct iio_info nxp_sar_adc_iio_info = {
850
+
.read_raw = nxp_sar_adc_read_raw,
851
+
.write_raw = nxp_sar_adc_write_raw,
852
+
};
853
+
854
+
static int nxp_sar_adc_dma_probe(struct device *dev, struct nxp_sar_adc *info)
855
+
{
856
+
u8 *rx_buf;
857
+
858
+
rx_buf = dmam_alloc_coherent(dev, NXP_SAR_ADC_DMA_BUFF_SZ,
859
+
&info->rx_dma_buf, GFP_KERNEL);
860
+
if (!rx_buf)
861
+
return -ENOMEM;
862
+
863
+
info->dma_buf.buf = rx_buf;
864
+
865
+
return 0;
866
+
}
867
+
868
+
/*
869
+
* The documentation describes the reset values for the registers.
870
+
* However some registers do not have these values after a reset. It
871
+
* is not a desirable situation. In some other SoC family
872
+
* documentation NXP recommends not assuming the default values are
873
+
* set and to initialize the registers conforming to the documentation
874
+
* reset information to prevent this situation. Assume the same rule
875
+
* applies here as there is a discrepancy between what is read from
876
+
* the registers at reset time and the documentation.
877
+
*/
878
+
static void nxp_sar_adc_set_default_values(struct nxp_sar_adc *info)
879
+
{
880
+
writel(0x00003901, NXP_SAR_ADC_MCR(info->regs));
881
+
writel(0x00000001, NXP_SAR_ADC_MSR(info->regs));
882
+
writel(0x00000014, NXP_SAR_ADC_CTR0(info->regs));
883
+
writel(0x00000014, NXP_SAR_ADC_CTR1(info->regs));
884
+
writel(0x00000000, NXP_SAR_ADC_CIMR0(info->regs));
885
+
writel(0x00000000, NXP_SAR_ADC_CIMR1(info->regs));
886
+
writel(0x00000000, NXP_SAR_ADC_NCMR0(info->regs));
887
+
writel(0x00000000, NXP_SAR_ADC_NCMR1(info->regs));
888
+
}
889
+
890
+
static int nxp_sar_adc_probe(struct platform_device *pdev)
891
+
{
892
+
struct device *dev = &pdev->dev;
893
+
const struct nxp_sar_adc_data *data = device_get_match_data(dev);
894
+
struct nxp_sar_adc *info;
895
+
struct iio_dev *indio_dev;
896
+
struct resource *mem;
897
+
int irq, ret;
898
+
899
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
900
+
if (!indio_dev)
901
+
return -ENOMEM;
902
+
903
+
info = iio_priv(indio_dev);
904
+
info->vref_mV = data->vref_mV;
905
+
spin_lock_init(&info->lock);
906
+
info->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
907
+
if (IS_ERR(info->regs))
908
+
return dev_err_probe(dev, PTR_ERR(info->regs),
909
+
"Failed to get and remap resource");
910
+
911
+
info->regs_phys = mem->start;
912
+
913
+
irq = platform_get_irq(pdev, 0);
914
+
if (irq < 0)
915
+
return irq;
916
+
917
+
ret = devm_request_irq(dev, irq, nxp_sar_adc_isr, 0, dev_name(dev),
918
+
indio_dev);
919
+
if (ret < 0)
920
+
return ret;
921
+
922
+
info->clk = devm_clk_get_enabled(dev, NULL);
923
+
if (IS_ERR(info->clk))
924
+
return dev_err_probe(dev, PTR_ERR(info->clk),
925
+
"Failed to get the clock\n");
926
+
927
+
platform_set_drvdata(pdev, indio_dev);
928
+
929
+
init_completion(&info->completion);
930
+
931
+
indio_dev->name = data->model;
932
+
indio_dev->info = &nxp_sar_adc_iio_info;
933
+
indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
934
+
indio_dev->channels = nxp_sar_adc_iio_channels;
935
+
indio_dev->num_channels = ARRAY_SIZE(nxp_sar_adc_iio_channels);
936
+
937
+
nxp_sar_adc_set_default_values(info);
938
+
939
+
ret = nxp_sar_adc_calibration(info);
940
+
if (ret)
941
+
dev_err_probe(dev, ret, "Calibration failed\n");
942
+
943
+
ret = nxp_sar_adc_dma_probe(dev, info);
944
+
if (ret)
945
+
return dev_err_probe(dev, ret, "Failed to initialize the DMA\n");
946
+
947
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
948
+
&iio_pollfunc_store_time,
949
+
&nxp_sar_adc_trigger_handler,
950
+
&iio_triggered_buffer_setup_ops);
951
+
if (ret < 0)
952
+
return dev_err_probe(dev, ret, "Couldn't initialise the buffer\n");
953
+
954
+
ret = devm_iio_device_register(dev, indio_dev);
955
+
if (ret)
956
+
return dev_err_probe(dev, ret, "Couldn't register the device\n");
957
+
958
+
return 0;
959
+
}
960
+
961
+
static int nxp_sar_adc_suspend(struct device *dev)
962
+
{
963
+
struct nxp_sar_adc *info = iio_priv(dev_get_drvdata(dev));
964
+
965
+
info->pwdn = nxp_sar_adc_disable(info);
966
+
info->inpsamp = nxp_sar_adc_conversion_timing_get(info);
967
+
968
+
clk_disable_unprepare(info->clk);
969
+
970
+
return 0;
971
+
}
972
+
973
+
static int nxp_sar_adc_resume(struct device *dev)
974
+
{
975
+
struct nxp_sar_adc *info = iio_priv(dev_get_drvdata(dev));
976
+
int ret;
977
+
978
+
ret = clk_prepare_enable(info->clk);
979
+
if (ret)
980
+
return ret;
981
+
982
+
nxp_sar_adc_conversion_timing_set(info, info->inpsamp);
983
+
984
+
if (!info->pwdn)
985
+
nxp_sar_adc_enable(info);
986
+
987
+
return 0;
988
+
}
989
+
990
+
static DEFINE_SIMPLE_DEV_PM_OPS(nxp_sar_adc_pm_ops, nxp_sar_adc_suspend,
991
+
nxp_sar_adc_resume);
992
+
993
+
static const struct nxp_sar_adc_data s32g2_sar_adc_data = {
994
+
.vref_mV = 1800,
995
+
.model = "s32g2-sar-adc",
996
+
};
997
+
998
+
static const struct of_device_id nxp_sar_adc_match[] = {
999
+
{ .compatible = "nxp,s32g2-sar-adc", .data = &s32g2_sar_adc_data },
1000
+
{ }
1001
+
};
1002
+
MODULE_DEVICE_TABLE(of, nxp_sar_adc_match);
1003
+
1004
+
static struct platform_driver nxp_sar_adc_driver = {
1005
+
.probe = nxp_sar_adc_probe,
1006
+
.driver = {
1007
+
.name = "nxp-sar-adc",
1008
+
.of_match_table = nxp_sar_adc_match,
1009
+
.pm = pm_sleep_ptr(&nxp_sar_adc_pm_ops),
1010
+
},
1011
+
};
1012
+
module_platform_driver(nxp_sar_adc_driver);
1013
+
1014
+
MODULE_AUTHOR("NXP");
1015
+
MODULE_DESCRIPTION("NXP SAR-ADC driver");
1016
+
MODULE_LICENSE("GPL");
+7
-13
drivers/iio/adc/qcom-spmi-rradc.c
+7
-13
drivers/iio/adc/qcom-spmi-rradc.c
···
934
934
935
935
chip = iio_priv(indio_dev);
936
936
chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
937
-
if (!chip->regmap) {
938
-
dev_err(dev, "Couldn't get parent's regmap\n");
939
-
return -EINVAL;
940
-
}
937
+
if (!chip->regmap)
938
+
return dev_err_probe(dev, -EINVAL, "Couldn't get parent's regmap\n");
941
939
942
940
chip->dev = dev;
943
941
mutex_init(&chip->conversion_lock);
944
942
945
943
ret = device_property_read_u32(dev, "reg", &chip->base);
946
-
if (ret < 0) {
947
-
dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",
948
-
ret);
949
-
return ret;
950
-
}
944
+
if (ret < 0)
945
+
return dev_err_probe(dev, ret, "Couldn't find reg address\n");
951
946
952
947
batt_id_delay = -1;
953
948
ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",
···
970
975
971
976
/* Get the PMIC revision, we need it to handle some varying coefficients */
972
977
chip->pmic = qcom_pmic_get(chip->dev);
973
-
if (IS_ERR(chip->pmic)) {
974
-
dev_err(chip->dev, "Unable to get reference to PMIC device\n");
975
-
return PTR_ERR(chip->pmic);
976
-
}
978
+
if (IS_ERR(chip->pmic))
979
+
return dev_err_probe(dev, PTR_ERR(chip->pmic),
980
+
"Unable to get reference to PMIC device\n");
977
981
978
982
switch (chip->pmic->subtype) {
979
983
case PMI8998_SUBTYPE:
+25
-34
drivers/iio/adc/rockchip_saradc.c
+25
-34
drivers/iio/adc/rockchip_saradc.c
···
456
456
{
457
457
const struct rockchip_saradc_data *match_data;
458
458
struct rockchip_saradc *info = NULL;
459
+
struct device *dev = &pdev->dev;
459
460
struct device_node *np = pdev->dev.of_node;
460
461
struct iio_dev *indio_dev = NULL;
461
462
int ret;
···
465
464
if (!np)
466
465
return -ENODEV;
467
466
468
-
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
467
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
469
468
if (!indio_dev)
470
469
return -ENOMEM;
471
470
472
471
info = iio_priv(indio_dev);
473
472
474
-
match_data = of_device_get_match_data(&pdev->dev);
473
+
match_data = of_device_get_match_data(dev);
475
474
if (!match_data)
476
-
return dev_err_probe(&pdev->dev, -ENODEV,
477
-
"failed to match device\n");
475
+
return dev_err_probe(dev, -ENODEV, "failed to match device\n");
478
476
479
477
info->data = match_data;
480
478
481
479
/* Sanity check for possible later IP variants with more channels */
482
480
if (info->data->num_channels > SARADC_MAX_CHANNELS)
483
-
return dev_err_probe(&pdev->dev, -EINVAL,
484
-
"max channels exceeded");
481
+
return dev_err_probe(dev, -EINVAL, "max channels exceeded");
485
482
486
483
info->regs = devm_platform_ioremap_resource(pdev, 0);
487
484
if (IS_ERR(info->regs))
···
489
490
* The reset should be an optional property, as it should work
490
491
* with old devicetrees as well
491
492
*/
492
-
info->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
493
-
"saradc-apb");
494
-
if (IS_ERR(info->reset)) {
495
-
ret = PTR_ERR(info->reset);
496
-
return dev_err_probe(&pdev->dev, ret, "failed to get saradc-apb\n");
497
-
}
493
+
info->reset = devm_reset_control_get_optional_exclusive(dev, "saradc-apb");
494
+
if (IS_ERR(info->reset))
495
+
return dev_err_probe(dev, PTR_ERR(info->reset),
496
+
"failed to get saradc-apb\n");
498
497
499
498
init_completion(&info->completion);
500
499
···
500
503
if (irq < 0)
501
504
return irq;
502
505
503
-
ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
506
+
ret = devm_request_irq(dev, irq, rockchip_saradc_isr,
504
507
0, dev_name(&pdev->dev), info);
505
-
if (ret < 0) {
506
-
dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
507
-
return ret;
508
-
}
508
+
if (ret < 0)
509
+
return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq);
509
510
510
-
info->vref = devm_regulator_get(&pdev->dev, "vref");
511
+
info->vref = devm_regulator_get(dev, "vref");
511
512
if (IS_ERR(info->vref))
512
-
return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
513
+
return dev_err_probe(dev, PTR_ERR(info->vref),
513
514
"failed to get regulator\n");
514
515
515
516
if (info->reset)
···
515
520
516
521
ret = regulator_enable(info->vref);
517
522
if (ret < 0)
518
-
return dev_err_probe(&pdev->dev, ret,
519
-
"failed to enable vref regulator\n");
523
+
return dev_err_probe(dev, ret, "failed to enable vref regulator\n");
520
524
521
-
ret = devm_add_action_or_reset(&pdev->dev,
522
-
rockchip_saradc_regulator_disable, info);
525
+
ret = devm_add_action_or_reset(dev, rockchip_saradc_regulator_disable, info);
523
526
if (ret)
524
527
return ret;
525
528
···
527
534
528
535
info->uv_vref = ret;
529
536
530
-
info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
537
+
info->pclk = devm_clk_get_enabled(dev, "apb_pclk");
531
538
if (IS_ERR(info->pclk))
532
-
return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
533
-
"failed to get pclk\n");
539
+
return dev_err_probe(dev, PTR_ERR(info->pclk), "failed to get pclk\n");
534
540
535
-
info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
541
+
info->clk = devm_clk_get_enabled(dev, "saradc");
536
542
if (IS_ERR(info->clk))
537
-
return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
543
+
return dev_err_probe(dev, PTR_ERR(info->clk),
538
544
"failed to get adc clock\n");
539
545
/*
540
546
* Use a default value for the converter clock.
···
541
549
*/
542
550
ret = clk_set_rate(info->clk, info->data->clk_rate);
543
551
if (ret < 0)
544
-
return dev_err_probe(&pdev->dev, ret,
545
-
"failed to set adc clk rate\n");
552
+
return dev_err_probe(dev, ret, "failed to set adc clk rate\n");
546
553
547
554
platform_set_drvdata(pdev, indio_dev);
548
555
549
-
indio_dev->name = dev_name(&pdev->dev);
556
+
indio_dev->name = dev_name(dev);
550
557
indio_dev->info = &rockchip_saradc_iio_info;
551
558
indio_dev->modes = INDIO_DIRECT_MODE;
552
559
553
560
indio_dev->channels = info->data->channels;
554
561
indio_dev->num_channels = info->data->num_channels;
555
-
ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
562
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
556
563
rockchip_saradc_trigger_handler,
557
564
NULL);
558
565
if (ret)
···
562
571
if (ret)
563
572
return ret;
564
573
565
-
ret = devm_add_action_or_reset(&pdev->dev,
574
+
ret = devm_add_action_or_reset(dev,
566
575
rockchip_saradc_regulator_unreg_notifier,
567
576
info);
568
577
if (ret)
···
570
579
571
580
mutex_init(&info->lock);
572
581
573
-
return devm_iio_device_register(&pdev->dev, indio_dev);
582
+
return devm_iio_device_register(dev, indio_dev);
574
583
}
575
584
576
585
static int rockchip_saradc_suspend(struct device *dev)
+17
-32
drivers/iio/adc/sc27xx_adc.c
+17
-32
drivers/iio/adc/sc27xx_adc.c
···
867
867
int ret;
868
868
869
869
pdata = of_device_get_match_data(dev);
870
-
if (!pdata) {
871
-
dev_err(dev, "No matching driver data found\n");
872
-
return -EINVAL;
873
-
}
870
+
if (!pdata)
871
+
return dev_err_probe(dev, -EINVAL, "No matching driver data found\n");
874
872
875
873
indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
876
874
if (!indio_dev)
···
877
879
sc27xx_data = iio_priv(indio_dev);
878
880
879
881
sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
880
-
if (!sc27xx_data->regmap) {
881
-
dev_err(dev, "failed to get ADC regmap\n");
882
-
return -ENODEV;
883
-
}
882
+
if (!sc27xx_data->regmap)
883
+
return dev_err_probe(dev, -ENODEV, "failed to get ADC regmap\n");
884
884
885
885
ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
886
-
if (ret) {
887
-
dev_err(dev, "failed to get ADC base address\n");
888
-
return ret;
889
-
}
886
+
if (ret)
887
+
return dev_err_probe(dev, ret, "failed to get ADC base address\n");
890
888
891
889
sc27xx_data->irq = platform_get_irq(pdev, 0);
892
890
if (sc27xx_data->irq < 0)
893
891
return sc27xx_data->irq;
894
892
895
893
ret = of_hwspin_lock_get_id(np, 0);
896
-
if (ret < 0) {
897
-
dev_err(dev, "failed to get hwspinlock id\n");
898
-
return ret;
899
-
}
894
+
if (ret < 0)
895
+
return dev_err_probe(dev, ret, "failed to get hwspinlock id\n");
900
896
901
897
sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
902
-
if (!sc27xx_data->hwlock) {
903
-
dev_err(dev, "failed to request hwspinlock\n");
904
-
return -ENXIO;
905
-
}
898
+
if (!sc27xx_data->hwlock)
899
+
return dev_err_probe(dev, -ENXIO, "failed to request hwspinlock\n");
906
900
907
901
sc27xx_data->dev = dev;
908
902
if (pdata->set_volref) {
909
903
sc27xx_data->volref = devm_regulator_get(dev, "vref");
910
-
if (IS_ERR(sc27xx_data->volref)) {
911
-
ret = PTR_ERR(sc27xx_data->volref);
912
-
return dev_err_probe(dev, ret, "failed to get ADC volref\n");
913
-
}
904
+
if (IS_ERR(sc27xx_data->volref))
905
+
return dev_err_probe(dev, PTR_ERR(sc27xx_data->volref),
906
+
"failed to get ADC volref\n");
914
907
}
915
908
916
909
sc27xx_data->var_data = pdata;
917
910
sc27xx_data->var_data->init_scale(sc27xx_data);
918
911
919
912
ret = sc27xx_adc_enable(sc27xx_data);
920
-
if (ret) {
921
-
dev_err(dev, "failed to enable ADC module\n");
922
-
return ret;
923
-
}
913
+
if (ret)
914
+
return dev_err_probe(dev, ret, "failed to enable ADC module\n");
924
915
925
916
ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
926
-
if (ret) {
927
-
dev_err(dev, "failed to add ADC disable action\n");
928
-
return ret;
929
-
}
917
+
if (ret)
918
+
return dev_err_probe(dev, ret, "failed to add ADC disable action\n");
930
919
931
920
indio_dev->name = dev_name(dev);
932
921
indio_dev->modes = INDIO_DIRECT_MODE;
+739
drivers/iio/adc/ti-ads1018.c
+739
drivers/iio/adc/ti-ads1018.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Texas Instruments ADS1018 ADC driver
4
+
*
5
+
* Copyright (C) 2025 Kurt Borja <kuurtb@gmail.com>
6
+
*/
7
+
8
+
#include <linux/array_size.h>
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bitmap.h>
11
+
#include <linux/dev_printk.h>
12
+
#include <linux/gpio/consumer.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/math.h>
15
+
#include <linux/mod_devicetable.h>
16
+
#include <linux/module.h>
17
+
#include <linux/spi/spi.h>
18
+
#include <linux/types.h>
19
+
#include <linux/units.h>
20
+
21
+
#include <asm/byteorder.h>
22
+
23
+
#include <linux/iio/buffer.h>
24
+
#include <linux/iio/iio.h>
25
+
#include <linux/iio/trigger.h>
26
+
#include <linux/iio/trigger_consumer.h>
27
+
#include <linux/iio/triggered_buffer.h>
28
+
29
+
#define ADS1018_CFG_OS_TRIG BIT(15)
30
+
#define ADS1018_CFG_TS_MODE_EN BIT(4)
31
+
#define ADS1018_CFG_PULL_UP BIT(3)
32
+
#define ADS1018_CFG_NOP BIT(1)
33
+
#define ADS1018_CFG_VALID (ADS1018_CFG_PULL_UP | ADS1018_CFG_NOP)
34
+
35
+
#define ADS1018_CFG_MUX_MASK GENMASK(14, 12)
36
+
37
+
#define ADS1018_CFG_PGA_MASK GENMASK(11, 9)
38
+
#define ADS1018_PGA_DEFAULT 2
39
+
40
+
#define ADS1018_CFG_MODE_MASK BIT(8)
41
+
#define ADS1018_MODE_CONTINUOUS 0
42
+
#define ADS1018_MODE_ONESHOT 1
43
+
44
+
#define ADS1018_CFG_DRATE_MASK GENMASK(7, 5)
45
+
#define ADS1018_DRATE_DEFAULT 4
46
+
47
+
#define ADS1018_NUM_PGA_MODES 6
48
+
#define ADS1018_CHANNELS_MAX 10
49
+
50
+
struct ads1018_chan_data {
51
+
u8 pga_mode;
52
+
u8 data_rate_mode;
53
+
};
54
+
55
+
struct ads1018_chip_info {
56
+
const char *name;
57
+
const struct iio_chan_spec *channels;
58
+
unsigned long num_channels;
59
+
60
+
/* IIO_VAL_INT */
61
+
const u32 *data_rate_mode_to_hz;
62
+
unsigned long num_data_rate_mode_to_hz;
63
+
64
+
/*
65
+
* Let `res` be the chip's resolution and `fsr` (millivolts) be the
66
+
* full-scale range corresponding to the PGA mode given by the array
67
+
* index. Then, the gain is calculated using the following formula:
68
+
*
69
+
* gain = |fsr| / 2^(res - 1)
70
+
*
71
+
* This value then has to be represented in IIO_VAL_INT_PLUS_NANO
72
+
* format. For example if:
73
+
*
74
+
* gain = 6144 / 2^(16 - 1) = 0.1875
75
+
*
76
+
* ...then the formatted value is:
77
+
*
78
+
* { 0, 187500000 }
79
+
*/
80
+
const u32 pga_mode_to_gain[ADS1018_NUM_PGA_MODES][2];
81
+
82
+
/* IIO_VAL_INT_PLUS_MICRO */
83
+
const u32 temp_scale[2];
84
+
};
85
+
86
+
struct ads1018 {
87
+
struct spi_device *spi;
88
+
struct iio_trigger *indio_trig;
89
+
90
+
struct gpio_desc *drdy_gpiod;
91
+
int drdy_irq;
92
+
93
+
struct ads1018_chan_data chan_data[ADS1018_CHANNELS_MAX];
94
+
const struct ads1018_chip_info *chip_info;
95
+
96
+
struct spi_message msg_read;
97
+
struct spi_transfer xfer;
98
+
__be16 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
99
+
__be16 rx_buf[2];
100
+
};
101
+
102
+
#define ADS1018_VOLT_DIFF_CHAN(_index, _chan, _chan2, _realbits) { \
103
+
.type = IIO_VOLTAGE, \
104
+
.channel = _chan, \
105
+
.channel2 = _chan2, \
106
+
.scan_index = _index, \
107
+
.scan_type = { \
108
+
.sign = 's', \
109
+
.realbits = _realbits, \
110
+
.storagebits = 16, \
111
+
.shift = 16 - _realbits, \
112
+
.endianness = IIO_BE, \
113
+
}, \
114
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
115
+
BIT(IIO_CHAN_INFO_SCALE) | \
116
+
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
117
+
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
118
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
119
+
.indexed = true, \
120
+
.differential = true, \
121
+
}
122
+
123
+
#define ADS1018_VOLT_CHAN(_index, _chan, _realbits) { \
124
+
.type = IIO_VOLTAGE, \
125
+
.channel = _chan, \
126
+
.scan_index = _index, \
127
+
.scan_type = { \
128
+
.sign = 's', \
129
+
.realbits = _realbits, \
130
+
.storagebits = 16, \
131
+
.shift = 16 - _realbits, \
132
+
.endianness = IIO_BE, \
133
+
}, \
134
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
135
+
BIT(IIO_CHAN_INFO_SCALE) | \
136
+
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
137
+
.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
138
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
139
+
.indexed = true, \
140
+
}
141
+
142
+
#define ADS1018_TEMP_CHAN(_index, _realbits) { \
143
+
.type = IIO_TEMP, \
144
+
.scan_index = _index, \
145
+
.scan_type = { \
146
+
.sign = 's', \
147
+
.realbits = _realbits, \
148
+
.storagebits = 16, \
149
+
.shift = 16 - _realbits, \
150
+
.endianness = IIO_BE, \
151
+
}, \
152
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
153
+
BIT(IIO_CHAN_INFO_SCALE) | \
154
+
BIT(IIO_CHAN_INFO_SAMP_FREQ), \
155
+
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
156
+
}
157
+
158
+
static const struct iio_chan_spec ads1118_iio_channels[] = {
159
+
ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 16),
160
+
ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 16),
161
+
ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 16),
162
+
ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 16),
163
+
ADS1018_VOLT_CHAN(4, 0, 16),
164
+
ADS1018_VOLT_CHAN(5, 1, 16),
165
+
ADS1018_VOLT_CHAN(6, 2, 16),
166
+
ADS1018_VOLT_CHAN(7, 3, 16),
167
+
ADS1018_TEMP_CHAN(8, 14),
168
+
IIO_CHAN_SOFT_TIMESTAMP(9),
169
+
};
170
+
171
+
static const struct iio_chan_spec ads1018_iio_channels[] = {
172
+
ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 12),
173
+
ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 12),
174
+
ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 12),
175
+
ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 12),
176
+
ADS1018_VOLT_CHAN(4, 0, 12),
177
+
ADS1018_VOLT_CHAN(5, 1, 12),
178
+
ADS1018_VOLT_CHAN(6, 2, 12),
179
+
ADS1018_VOLT_CHAN(7, 3, 12),
180
+
ADS1018_TEMP_CHAN(8, 12),
181
+
IIO_CHAN_SOFT_TIMESTAMP(9),
182
+
};
183
+
184
+
/**
185
+
* ads1018_calc_delay - Calculates a suitable delay for a single-shot reading
186
+
* @hz: Sampling frequency
187
+
*
188
+
* Calculates an appropriate delay for a single shot reading given a sampling
189
+
* frequency.
190
+
*
191
+
* Return: Delay in microseconds (Always greater than 0).
192
+
*/
193
+
static u32 ads1018_calc_delay(unsigned int hz)
194
+
{
195
+
/*
196
+
* Calculate the worst-case sampling rate by subtracting 10% error
197
+
* specified in the datasheet...
198
+
*/
199
+
hz -= DIV_ROUND_UP(hz, 10);
200
+
201
+
/* ...Then calculate time per sample in microseconds. */
202
+
return DIV_ROUND_UP(HZ_PER_MHZ, hz);
203
+
}
204
+
205
+
/**
206
+
* ads1018_spi_read_exclusive - Reads a conversion value from the device
207
+
* @ads1018: Device data
208
+
* @cnv: ADC Conversion value (optional)
209
+
* @hold_cs: Keep CS line asserted after the SPI transfer
210
+
*
211
+
* Reads the most recent ADC conversion value, without updating the
212
+
* device's configuration.
213
+
*
214
+
* Context: Expects SPI bus *exclusive* use.
215
+
*
216
+
* Return: 0 on success, negative errno on error.
217
+
*/
218
+
static int ads1018_spi_read_exclusive(struct ads1018 *ads1018, __be16 *cnv,
219
+
bool hold_cs)
220
+
{
221
+
int ret;
222
+
223
+
ads1018->xfer.cs_change = hold_cs;
224
+
225
+
ret = spi_sync_locked(ads1018->spi, &ads1018->msg_read);
226
+
if (ret)
227
+
return ret;
228
+
229
+
if (cnv)
230
+
*cnv = ads1018->rx_buf[0];
231
+
232
+
return 0;
233
+
}
234
+
235
+
/**
236
+
* ads1018_single_shot - Performs a one-shot reading sequence
237
+
* @ads1018: Device data
238
+
* @chan: Channel specification
239
+
* @cnv: Conversion value
240
+
*
241
+
* Writes a new configuration, waits an appropriate delay, then reads the most
242
+
* recent conversion.
243
+
*
244
+
* Context: Expects iio_device_claim_direct() is held.
245
+
*
246
+
* Return: 0 on success, negative errno on error.
247
+
*/
248
+
static int ads1018_single_shot(struct ads1018 *ads1018,
249
+
struct iio_chan_spec const *chan, u16 *cnv)
250
+
{
251
+
u8 max_drate_mode = ads1018->chip_info->num_data_rate_mode_to_hz - 1;
252
+
u8 drate = ads1018->chip_info->data_rate_mode_to_hz[max_drate_mode];
253
+
u8 pga_mode = ads1018->chan_data[chan->scan_index].pga_mode;
254
+
struct spi_transfer xfer[2] = {
255
+
{
256
+
.tx_buf = ads1018->tx_buf,
257
+
.len = sizeof(ads1018->tx_buf[0]),
258
+
.delay = {
259
+
.value = ads1018_calc_delay(drate),
260
+
.unit = SPI_DELAY_UNIT_USECS,
261
+
},
262
+
.cs_change = 1, /* 16-bit mode requires CS de-assert */
263
+
},
264
+
{
265
+
.rx_buf = ads1018->rx_buf,
266
+
.len = sizeof(ads1018->rx_buf[0]),
267
+
},
268
+
};
269
+
u16 cfg;
270
+
int ret;
271
+
272
+
cfg = ADS1018_CFG_VALID | ADS1018_CFG_OS_TRIG;
273
+
cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, chan->scan_index);
274
+
cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga_mode);
275
+
cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT);
276
+
cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, max_drate_mode);
277
+
278
+
if (chan->type == IIO_TEMP)
279
+
cfg |= ADS1018_CFG_TS_MODE_EN;
280
+
281
+
ads1018->tx_buf[0] = cpu_to_be16(cfg);
282
+
ret = spi_sync_transfer(ads1018->spi, xfer, ARRAY_SIZE(xfer));
283
+
if (ret)
284
+
return ret;
285
+
286
+
*cnv = be16_to_cpu(ads1018->rx_buf[0]);
287
+
288
+
return 0;
289
+
}
290
+
291
+
static int
292
+
ads1018_read_raw_direct_mode(struct iio_dev *indio_dev,
293
+
struct iio_chan_spec const *chan, int *val, int *val2,
294
+
long mask)
295
+
{
296
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
297
+
const struct ads1018_chip_info *chip_info = ads1018->chip_info;
298
+
u8 addr = chan->scan_index;
299
+
u8 pga_mode, drate_mode;
300
+
u16 cnv;
301
+
int ret;
302
+
303
+
switch (mask) {
304
+
case IIO_CHAN_INFO_RAW:
305
+
ret = ads1018_single_shot(ads1018, chan, &cnv);
306
+
if (ret)
307
+
return ret;
308
+
309
+
cnv >>= chan->scan_type.shift;
310
+
*val = sign_extend32(cnv, chan->scan_type.realbits - 1);
311
+
312
+
return IIO_VAL_INT;
313
+
314
+
case IIO_CHAN_INFO_SCALE:
315
+
switch (chan->type) {
316
+
case IIO_VOLTAGE:
317
+
pga_mode = ads1018->chan_data[addr].pga_mode;
318
+
*val = chip_info->pga_mode_to_gain[pga_mode][0];
319
+
*val2 = chip_info->pga_mode_to_gain[pga_mode][1];
320
+
return IIO_VAL_INT_PLUS_NANO;
321
+
322
+
case IIO_TEMP:
323
+
*val = chip_info->temp_scale[0];
324
+
*val2 = chip_info->temp_scale[1];
325
+
return IIO_VAL_INT_PLUS_MICRO;
326
+
327
+
default:
328
+
return -EOPNOTSUPP;
329
+
}
330
+
331
+
case IIO_CHAN_INFO_SAMP_FREQ:
332
+
drate_mode = ads1018->chan_data[addr].data_rate_mode;
333
+
*val = chip_info->data_rate_mode_to_hz[drate_mode];
334
+
return IIO_VAL_INT;
335
+
336
+
default:
337
+
return -EOPNOTSUPP;
338
+
}
339
+
}
340
+
341
+
static int
342
+
ads1018_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
343
+
int *val, int *val2, long mask)
344
+
{
345
+
int ret;
346
+
347
+
if (!iio_device_claim_direct(indio_dev))
348
+
return -EBUSY;
349
+
ret = ads1018_read_raw_direct_mode(indio_dev, chan, val, val2, mask);
350
+
iio_device_release_direct(indio_dev);
351
+
352
+
return ret;
353
+
}
354
+
355
+
static int
356
+
ads1018_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
357
+
const int **vals, int *type, int *length, long mask)
358
+
{
359
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
360
+
361
+
switch (mask) {
362
+
case IIO_CHAN_INFO_SCALE:
363
+
*type = IIO_VAL_INT_PLUS_NANO;
364
+
*vals = (const int *)ads1018->chip_info->pga_mode_to_gain;
365
+
*length = ADS1018_NUM_PGA_MODES * 2;
366
+
return IIO_AVAIL_LIST;
367
+
368
+
case IIO_CHAN_INFO_SAMP_FREQ:
369
+
*type = IIO_VAL_INT;
370
+
*vals = ads1018->chip_info->data_rate_mode_to_hz;
371
+
*length = ads1018->chip_info->num_data_rate_mode_to_hz;
372
+
return IIO_AVAIL_LIST;
373
+
374
+
default:
375
+
return -EOPNOTSUPP;
376
+
}
377
+
}
378
+
379
+
static int
380
+
ads1018_write_raw_direct_mode(struct iio_dev *indio_dev,
381
+
struct iio_chan_spec const *chan, int val, int val2,
382
+
long mask)
383
+
{
384
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
385
+
const struct ads1018_chip_info *info = ads1018->chip_info;
386
+
unsigned int i;
387
+
388
+
switch (mask) {
389
+
case IIO_CHAN_INFO_SCALE:
390
+
for (i = 0; i < ADS1018_NUM_PGA_MODES; i++) {
391
+
if (val == info->pga_mode_to_gain[i][0] &&
392
+
val2 == info->pga_mode_to_gain[i][1])
393
+
break;
394
+
}
395
+
if (i == ADS1018_NUM_PGA_MODES)
396
+
return -EINVAL;
397
+
398
+
ads1018->chan_data[chan->scan_index].pga_mode = i;
399
+
return 0;
400
+
401
+
case IIO_CHAN_INFO_SAMP_FREQ:
402
+
for (i = 0; i < info->num_data_rate_mode_to_hz; i++) {
403
+
if (val == info->data_rate_mode_to_hz[i])
404
+
break;
405
+
}
406
+
if (i == info->num_data_rate_mode_to_hz)
407
+
return -EINVAL;
408
+
409
+
ads1018->chan_data[chan->scan_index].data_rate_mode = i;
410
+
return 0;
411
+
412
+
default:
413
+
return -EOPNOTSUPP;
414
+
}
415
+
}
416
+
417
+
static int
418
+
ads1018_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
419
+
int val, int val2, long mask)
420
+
{
421
+
int ret;
422
+
423
+
if (!iio_device_claim_direct(indio_dev))
424
+
return -EBUSY;
425
+
ret = ads1018_write_raw_direct_mode(indio_dev, chan, val, val2, mask);
426
+
iio_device_release_direct(indio_dev);
427
+
428
+
return ret;
429
+
}
430
+
431
+
static int
432
+
ads1018_write_raw_get_fmt(struct iio_dev *indio_dev,
433
+
struct iio_chan_spec const *chan, long mask)
434
+
{
435
+
switch (mask) {
436
+
case IIO_CHAN_INFO_SCALE:
437
+
return IIO_VAL_INT_PLUS_NANO;
438
+
default:
439
+
return IIO_VAL_INT_PLUS_MICRO;
440
+
}
441
+
}
442
+
443
+
static const struct iio_info ads1018_iio_info = {
444
+
.read_raw = ads1018_read_raw,
445
+
.read_avail = ads1018_read_avail,
446
+
.write_raw = ads1018_write_raw,
447
+
.write_raw_get_fmt = ads1018_write_raw_get_fmt,
448
+
};
449
+
450
+
static void ads1018_set_trigger_enable(struct ads1018 *ads1018)
451
+
{
452
+
spi_bus_lock(ads1018->spi->controller);
453
+
ads1018_spi_read_exclusive(ads1018, NULL, true);
454
+
enable_irq(ads1018->drdy_irq);
455
+
}
456
+
457
+
static void ads1018_set_trigger_disable(struct ads1018 *ads1018)
458
+
{
459
+
disable_irq(ads1018->drdy_irq);
460
+
ads1018_spi_read_exclusive(ads1018, NULL, false);
461
+
spi_bus_unlock(ads1018->spi->controller);
462
+
}
463
+
464
+
static int ads1018_set_trigger_state(struct iio_trigger *trig, bool state)
465
+
{
466
+
struct ads1018 *ads1018 = iio_trigger_get_drvdata(trig);
467
+
468
+
/*
469
+
* We need to lock the SPI bus and tie CS low (hold_cs) to catch
470
+
* data-ready interrupts, otherwise the MISO line enters a Hi-Z state.
471
+
*/
472
+
473
+
if (state)
474
+
ads1018_set_trigger_enable(ads1018);
475
+
else
476
+
ads1018_set_trigger_disable(ads1018);
477
+
478
+
return 0;
479
+
}
480
+
481
+
static const struct iio_trigger_ops ads1018_trigger_ops = {
482
+
.set_trigger_state = ads1018_set_trigger_state,
483
+
.validate_device = iio_trigger_validate_own_device,
484
+
};
485
+
486
+
static int ads1018_buffer_preenable(struct iio_dev *indio_dev)
487
+
{
488
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
489
+
const struct ads1018_chip_info *chip_info = ads1018->chip_info;
490
+
unsigned int pga, drate, addr;
491
+
u16 cfg;
492
+
493
+
addr = find_first_bit(indio_dev->active_scan_mask,
494
+
iio_get_masklength(indio_dev));
495
+
pga = ads1018->chan_data[addr].pga_mode;
496
+
drate = ads1018->chan_data[addr].data_rate_mode;
497
+
498
+
cfg = ADS1018_CFG_VALID;
499
+
cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, addr);
500
+
cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga);
501
+
cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_CONTINUOUS);
502
+
cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, drate);
503
+
504
+
if (chip_info->channels[addr].type == IIO_TEMP)
505
+
cfg |= ADS1018_CFG_TS_MODE_EN;
506
+
507
+
ads1018->tx_buf[0] = cpu_to_be16(cfg);
508
+
ads1018->tx_buf[1] = 0;
509
+
510
+
return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf));
511
+
}
512
+
513
+
static int ads1018_buffer_postdisable(struct iio_dev *indio_dev)
514
+
{
515
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
516
+
u16 cfg;
517
+
518
+
cfg = ADS1018_CFG_VALID;
519
+
cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT);
520
+
521
+
ads1018->tx_buf[0] = cpu_to_be16(cfg);
522
+
ads1018->tx_buf[1] = 0;
523
+
524
+
return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf));
525
+
}
526
+
527
+
static const struct iio_buffer_setup_ops ads1018_buffer_ops = {
528
+
.preenable = ads1018_buffer_preenable,
529
+
.postdisable = ads1018_buffer_postdisable,
530
+
.validate_scan_mask = iio_validate_scan_mask_onehot,
531
+
};
532
+
533
+
static irqreturn_t ads1018_irq_handler(int irq, void *dev_id)
534
+
{
535
+
struct ads1018 *ads1018 = dev_id;
536
+
537
+
/*
538
+
* We need to check if the "drdy" pin is actually active or if it's a
539
+
* pending interrupt triggered by the SPI transfer.
540
+
*/
541
+
if (!gpiod_get_value(ads1018->drdy_gpiod))
542
+
return IRQ_HANDLED;
543
+
544
+
iio_trigger_poll(ads1018->indio_trig);
545
+
546
+
return IRQ_HANDLED;
547
+
}
548
+
549
+
static irqreturn_t ads1018_trigger_handler(int irq, void *p)
550
+
{
551
+
struct iio_poll_func *pf = p;
552
+
struct iio_dev *indio_dev = pf->indio_dev;
553
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
554
+
struct {
555
+
__be16 conv;
556
+
aligned_s64 ts;
557
+
} scan = {};
558
+
int ret;
559
+
560
+
if (iio_trigger_using_own(indio_dev)) {
561
+
disable_irq(ads1018->drdy_irq);
562
+
ret = ads1018_spi_read_exclusive(ads1018, &scan.conv, true);
563
+
enable_irq(ads1018->drdy_irq);
564
+
} else {
565
+
ret = spi_read(ads1018->spi, ads1018->rx_buf, sizeof(ads1018->rx_buf));
566
+
scan.conv = ads1018->rx_buf[0];
567
+
}
568
+
569
+
if (!ret)
570
+
iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan),
571
+
pf->timestamp);
572
+
573
+
iio_trigger_notify_done(indio_dev->trig);
574
+
575
+
return IRQ_HANDLED;
576
+
}
577
+
578
+
static int ads1018_trigger_setup(struct iio_dev *indio_dev)
579
+
{
580
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
581
+
struct spi_device *spi = ads1018->spi;
582
+
struct device *dev = &spi->dev;
583
+
const char *con_id = "drdy";
584
+
int ret;
585
+
586
+
ads1018->drdy_gpiod = devm_gpiod_get_optional(dev, con_id, GPIOD_IN);
587
+
if (IS_ERR(ads1018->drdy_gpiod))
588
+
return dev_err_probe(dev, PTR_ERR(ads1018->drdy_gpiod),
589
+
"Failed to get %s GPIO.\n", con_id);
590
+
591
+
/* First try to get IRQ from SPI core, then from GPIO */
592
+
if (spi->irq > 0)
593
+
ads1018->drdy_irq = spi->irq;
594
+
else if (ads1018->drdy_gpiod)
595
+
ads1018->drdy_irq = gpiod_to_irq(ads1018->drdy_gpiod);
596
+
if (ads1018->drdy_irq < 0)
597
+
return dev_err_probe(dev, ads1018->drdy_irq,
598
+
"Failed to get IRQ from %s GPIO.\n", con_id);
599
+
600
+
/* An IRQ line is only an optional requirement for the IIO trigger */
601
+
if (ads1018->drdy_irq == 0)
602
+
return 0;
603
+
604
+
ads1018->indio_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-%s",
605
+
indio_dev->name,
606
+
iio_device_id(indio_dev),
607
+
con_id);
608
+
if (!ads1018->indio_trig)
609
+
return -ENOMEM;
610
+
611
+
iio_trigger_set_drvdata(ads1018->indio_trig, ads1018);
612
+
ads1018->indio_trig->ops = &ads1018_trigger_ops;
613
+
614
+
ret = devm_iio_trigger_register(dev, ads1018->indio_trig);
615
+
if (ret)
616
+
return ret;
617
+
618
+
/*
619
+
* The "data-ready" IRQ line is shared with the MOSI pin, thus we need
620
+
* to keep it disabled until we actually request data.
621
+
*/
622
+
return devm_request_irq(dev, ads1018->drdy_irq, ads1018_irq_handler,
623
+
IRQF_NO_AUTOEN, ads1018->chip_info->name, ads1018);
624
+
}
625
+
626
+
static int ads1018_spi_probe(struct spi_device *spi)
627
+
{
628
+
const struct ads1018_chip_info *info = spi_get_device_match_data(spi);
629
+
struct device *dev = &spi->dev;
630
+
struct iio_dev *indio_dev;
631
+
struct ads1018 *ads1018;
632
+
int ret;
633
+
634
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*ads1018));
635
+
if (!indio_dev)
636
+
return -ENOMEM;
637
+
638
+
ads1018 = iio_priv(indio_dev);
639
+
ads1018->spi = spi;
640
+
ads1018->chip_info = info;
641
+
642
+
indio_dev->modes = INDIO_DIRECT_MODE;
643
+
indio_dev->name = info->name;
644
+
indio_dev->info = &ads1018_iio_info;
645
+
indio_dev->channels = info->channels;
646
+
indio_dev->num_channels = info->num_channels;
647
+
648
+
for (unsigned int i = 0; i < ADS1018_CHANNELS_MAX; i++) {
649
+
ads1018->chan_data[i].data_rate_mode = ADS1018_DRATE_DEFAULT;
650
+
ads1018->chan_data[i].pga_mode = ADS1018_PGA_DEFAULT;
651
+
}
652
+
653
+
ads1018->xfer.rx_buf = ads1018->rx_buf;
654
+
ads1018->xfer.len = sizeof(ads1018->rx_buf);
655
+
spi_message_init_with_transfers(&ads1018->msg_read, &ads1018->xfer, 1);
656
+
657
+
ret = ads1018_trigger_setup(indio_dev);
658
+
if (ret)
659
+
return ret;
660
+
661
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
662
+
iio_pollfunc_store_time,
663
+
ads1018_trigger_handler,
664
+
&ads1018_buffer_ops);
665
+
if (ret)
666
+
return ret;
667
+
668
+
return devm_iio_device_register(&spi->dev, indio_dev);
669
+
}
670
+
671
+
static const unsigned int ads1018_data_rate_table[] = {
672
+
128, 250, 490, 920, 1600, 2400, 3300,
673
+
};
674
+
675
+
static const unsigned int ads1118_data_rate_table[] = {
676
+
8, 16, 32, 64, 128, 250, 475, 860,
677
+
};
678
+
679
+
static const struct ads1018_chip_info ads1018_chip_info = {
680
+
.name = "ads1018",
681
+
.channels = ads1018_iio_channels,
682
+
.num_channels = ARRAY_SIZE(ads1018_iio_channels),
683
+
.data_rate_mode_to_hz = ads1018_data_rate_table,
684
+
.num_data_rate_mode_to_hz = ARRAY_SIZE(ads1018_data_rate_table),
685
+
.pga_mode_to_gain = {
686
+
{ 3, 0 }, /* fsr = 6144 mV */
687
+
{ 2, 0 }, /* fsr = 4096 mV */
688
+
{ 1, 0 }, /* fsr = 2048 mV */
689
+
{ 0, 500000000 }, /* fsr = 1024 mV */
690
+
{ 0, 250000000 }, /* fsr = 512 mV */
691
+
{ 0, 125000000 }, /* fsr = 256 mV */
692
+
},
693
+
.temp_scale = { 125, 0 },
694
+
};
695
+
696
+
static const struct ads1018_chip_info ads1118_chip_info = {
697
+
.name = "ads1118",
698
+
.channels = ads1118_iio_channels,
699
+
.num_channels = ARRAY_SIZE(ads1118_iio_channels),
700
+
.data_rate_mode_to_hz = ads1118_data_rate_table,
701
+
.num_data_rate_mode_to_hz = ARRAY_SIZE(ads1118_data_rate_table),
702
+
.pga_mode_to_gain = {
703
+
{ 0, 187500000 }, /* fsr = 6144 mV */
704
+
{ 0, 125000000 }, /* fsr = 4096 mV */
705
+
{ 0, 62500000 }, /* fsr = 2048 mV */
706
+
{ 0, 31250000 }, /* fsr = 1024 mV */
707
+
{ 0, 15625000 }, /* fsr = 512 mV */
708
+
{ 0, 7812500 }, /* fsr = 256 mV */
709
+
},
710
+
.temp_scale = { 31, 250000 },
711
+
};
712
+
713
+
static const struct of_device_id ads1018_of_match[] = {
714
+
{ .compatible = "ti,ads1018", .data = &ads1018_chip_info },
715
+
{ .compatible = "ti,ads1118", .data = &ads1118_chip_info },
716
+
{ }
717
+
};
718
+
MODULE_DEVICE_TABLE(of, ads1018_of_match);
719
+
720
+
static const struct spi_device_id ads1018_spi_match[] = {
721
+
{ "ads1018", (kernel_ulong_t)&ads1018_chip_info },
722
+
{ "ads1118", (kernel_ulong_t)&ads1118_chip_info },
723
+
{ }
724
+
};
725
+
MODULE_DEVICE_TABLE(spi, ads1018_spi_match);
726
+
727
+
static struct spi_driver ads1018_spi_driver = {
728
+
.driver = {
729
+
.name = "ads1018",
730
+
.of_match_table = ads1018_of_match,
731
+
},
732
+
.probe = ads1018_spi_probe,
733
+
.id_table = ads1018_spi_match,
734
+
};
735
+
module_spi_driver(ads1018_spi_driver);
736
+
737
+
MODULE_DESCRIPTION("Texas Instruments ADS1018 ADC Driver");
738
+
MODULE_LICENSE("GPL");
739
+
MODULE_AUTHOR("Kurt Borja <kuurtb@gmail.com>");
+1
-1
drivers/iio/adc/ti-ads131e08.c
+1
-1
drivers/iio/adc/ti-ads131e08.c
···
827
827
if (spi->irq) {
828
828
ret = devm_request_irq(&spi->dev, spi->irq,
829
829
ads131e08_interrupt,
830
-
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
830
+
IRQF_TRIGGER_FALLING | IRQF_NO_THREAD,
831
831
spi->dev.driver->name, indio_dev);
832
832
if (ret)
833
833
return dev_err_probe(&spi->dev, ret,
+968
drivers/iio/adc/ti-ads131m02.c
+968
drivers/iio/adc/ti-ads131m02.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Driver for Texas Instruments ADS131M02 family ADC chips.
4
+
*
5
+
* Copyright (C) 2024 Protonic Holland
6
+
* Copyright (C) 2025 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
7
+
*
8
+
* Primary Datasheet Reference (used for citations):
9
+
* ADS131M08 8-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC
10
+
* Document SBAS950B, Revised February 2021
11
+
* https://www.ti.com/lit/ds/symlink/ads131m08.pdf
12
+
*/
13
+
14
+
#include <linux/array_size.h>
15
+
#include <linux/bitfield.h>
16
+
#include <linux/bitops.h>
17
+
#include <linux/cleanup.h>
18
+
#include <linux/clk.h>
19
+
#include <linux/crc-itu-t.h>
20
+
#include <linux/delay.h>
21
+
#include <linux/dev_printk.h>
22
+
#include <linux/device/devres.h>
23
+
#include <linux/err.h>
24
+
#include <linux/iio/iio.h>
25
+
#include <linux/lockdep.h>
26
+
#include <linux/mod_devicetable.h>
27
+
#include <linux/module.h>
28
+
#include <linux/mutex.h>
29
+
#include <linux/regulator/consumer.h>
30
+
#include <linux/reset.h>
31
+
#include <linux/spi/spi.h>
32
+
#include <linux/string.h>
33
+
#include <linux/types.h>
34
+
#include <linux/unaligned.h>
35
+
36
+
/* Max channels supported by the largest variant in the family (ADS131M08) */
37
+
#define ADS131M_MAX_CHANNELS 8
38
+
39
+
/* Section 6.7, t_REGACQ (min time after reset) is 5us */
40
+
#define ADS131M_RESET_DELAY_US 5
41
+
42
+
#define ADS131M_WORD_SIZE_BYTES 3
43
+
#define ADS131M_RESPONSE_WORDS 1
44
+
#define ADS131M_CRC_WORDS 1
45
+
46
+
/*
47
+
* SPI Frame word count calculation.
48
+
* Frame = N channel words + 1 response word + 1 CRC word.
49
+
* Word size depends on WLENGTH bits in MODE register (Default 24-bit).
50
+
*/
51
+
#define ADS131M_FRAME_WORDS(nch) \
52
+
((nch) + ADS131M_RESPONSE_WORDS + ADS131M_CRC_WORDS)
53
+
54
+
/*
55
+
* SPI Frame byte size calculation.
56
+
* Assumes default word size of 24 bits (3 bytes).
57
+
*/
58
+
#define ADS131M_FRAME_BYTES(nch) \
59
+
(ADS131M_FRAME_WORDS(nch) * ADS131M_WORD_SIZE_BYTES)
60
+
61
+
/*
62
+
* Index calculation for the start byte of channel 'x' data within the RX buffer.
63
+
* Assumes 24-bit words (3 bytes per word).
64
+
* The received frame starts with the response word (e.g., STATUS register
65
+
* content when NULL command was sent), followed by data for channels 0 to N-1,
66
+
* and finally the output CRC word.
67
+
* Response = index 0..2, Chan0 = index 3..5, Chan1 = index 6..8, ...
68
+
* Index for ChanX = 3 (response) + x * 3 (channel data size).
69
+
*/
70
+
#define ADS131M_CHANNEL_INDEX(x) \
71
+
((x) * ADS131M_WORD_SIZE_BYTES + ADS131M_WORD_SIZE_BYTES)
72
+
73
+
#define ADS131M_CMD_NULL 0x0000
74
+
#define ADS131M_CMD_RESET 0x0011
75
+
76
+
#define ADS131M_CMD_ADDR_MASK GENMASK(11, 7)
77
+
#define ADS131M_CMD_NUM_MASK GENMASK(6, 0)
78
+
79
+
#define ADS131M_CMD_RREG_OP 0xa000
80
+
#define ADS131M_CMD_WREG_OP 0x6000
81
+
82
+
#define ADS131M_CMD_RREG(a, n) \
83
+
(ADS131M_CMD_RREG_OP | \
84
+
FIELD_PREP(ADS131M_CMD_ADDR_MASK, a) | \
85
+
FIELD_PREP(ADS131M_CMD_NUM_MASK, n))
86
+
#define ADS131M_CMD_WREG(a, n) \
87
+
(ADS131M_CMD_WREG_OP | \
88
+
FIELD_PREP(ADS131M_CMD_ADDR_MASK, a) | \
89
+
FIELD_PREP(ADS131M_CMD_NUM_MASK, n))
90
+
91
+
/* STATUS Register (0x01h) bit definitions */
92
+
#define ADS131M_STATUS_CRC_ERR BIT(12) /* Input CRC error */
93
+
94
+
#define ADS131M_REG_MODE 0x02
95
+
#define ADS131M_MODE_RX_CRC_EN BIT(12) /* Enable Input CRC */
96
+
#define ADS131M_MODE_CRC_TYPE_ANSI BIT(11) /* 0 = CCITT, 1 = ANSI */
97
+
#define ADS131M_MODE_RESET_FLAG BIT(10)
98
+
99
+
#define ADS131M_REG_CLOCK 0x03
100
+
#define ADS131M_CLOCK_XTAL_DIS BIT(7)
101
+
#define ADS131M_CLOCK_EXTREF_EN BIT(6)
102
+
103
+
/* 1.2V internal reference, in millivolts, for IIO_VAL_FRACTIONAL_LOG2 */
104
+
#define ADS131M_VREF_INTERNAL_mV 1200
105
+
/* 24-bit resolution */
106
+
#define ADS131M_RESOLUTION_BITS 24
107
+
/* Signed data uses (RESOLUTION_BITS - 1) magnitude bits */
108
+
#define ADS131M_CODE_BITS (ADS131M_RESOLUTION_BITS - 1)
109
+
110
+
/* External ref FSR = Vref * 0.96 */
111
+
#define ADS131M_EXTREF_SCALE_NUM 96
112
+
#define ADS131M_EXTREF_SCALE_DEN 100
113
+
114
+
struct ads131m_configuration {
115
+
const struct iio_chan_spec *channels;
116
+
const char *name;
117
+
u16 reset_ack;
118
+
u8 num_channels;
119
+
u8 supports_extref:1;
120
+
u8 supports_xtal:1;
121
+
};
122
+
123
+
struct ads131m_priv {
124
+
struct iio_dev *indio_dev;
125
+
struct spi_device *spi;
126
+
const struct ads131m_configuration *config;
127
+
128
+
bool use_external_ref;
129
+
int scale_val;
130
+
int scale_val2;
131
+
132
+
struct spi_transfer xfer;
133
+
struct spi_message msg;
134
+
135
+
/*
136
+
* Protects the shared tx_buffer and rx_buffer. More importantly,
137
+
* this serializes all SPI communication to ensure the atomicity
138
+
* of multi-cycle command sequences (like WREG, RREG, or RESET).
139
+
*/
140
+
struct mutex lock;
141
+
142
+
/* DMA-safe buffers should be placed at the end of the struct. */
143
+
u8 tx_buffer[ADS131M_FRAME_BYTES(ADS131M_MAX_CHANNELS)]
144
+
__aligned(IIO_DMA_MINALIGN);
145
+
u8 rx_buffer[ADS131M_FRAME_BYTES(ADS131M_MAX_CHANNELS)];
146
+
};
147
+
148
+
/**
149
+
* ads131m_tx_frame_unlocked - Sends a command frame with Input CRC
150
+
* @priv: Device private data structure.
151
+
* @command: The 16-bit command to send (e.g., NULL, RREG, RESET).
152
+
*
153
+
* This function sends a command in Word 0, and its calculated 16-bit
154
+
* CRC in Word 1, as required when Input CRC is enabled.
155
+
*
156
+
* Return: 0 on success, or a negative error code.
157
+
*/
158
+
static int ads131m_tx_frame_unlocked(struct ads131m_priv *priv, u32 command)
159
+
{
160
+
struct iio_dev *indio_dev = priv->indio_dev;
161
+
u16 crc;
162
+
163
+
lockdep_assert_held(&priv->lock);
164
+
165
+
memset(priv->tx_buffer, 0, ADS131M_FRAME_BYTES(indio_dev->num_channels));
166
+
167
+
/* Word 0: 16-bit command, MSB-aligned in 24-bit word */
168
+
put_unaligned_be16(command, &priv->tx_buffer[0]);
169
+
170
+
/* Word 1: Input CRC. Calculated over the 3 bytes of Word 0. */
171
+
crc = crc_itu_t(0xffff, priv->tx_buffer, 3);
172
+
put_unaligned_be16(crc, &priv->tx_buffer[3]);
173
+
174
+
return spi_sync(priv->spi, &priv->msg);
175
+
}
176
+
177
+
/**
178
+
* ads131m_rx_frame_unlocked - Receives a full SPI data frame.
179
+
* @priv: Device private data structure.
180
+
*
181
+
* This function sends a NULL command (with its CRC) to clock out a
182
+
* full SPI frame from the device (e.g., response + channel data + CRC).
183
+
*
184
+
* Return: 0 on success, or a negative error code.
185
+
*/
186
+
static int ads131m_rx_frame_unlocked(struct ads131m_priv *priv)
187
+
{
188
+
return ads131m_tx_frame_unlocked(priv, ADS131M_CMD_NULL);
189
+
}
190
+
191
+
/**
192
+
* ads131m_check_status_crc_err - Checks for an Input CRC error.
193
+
* @priv: Device private data structure.
194
+
*
195
+
* Sends a NULL command to fetch the STATUS register and checks the
196
+
* CRC_ERR bit. This is used to verify the integrity of the previous
197
+
* command (like RREG or WREG).
198
+
*
199
+
* Return: 0 on success, -EIO if CRC_ERR bit is set.
200
+
*/
201
+
static int ads131m_check_status_crc_err(struct ads131m_priv *priv)
202
+
{
203
+
struct device *dev = &priv->spi->dev;
204
+
u16 status;
205
+
int ret;
206
+
207
+
lockdep_assert_held(&priv->lock);
208
+
209
+
ret = ads131m_rx_frame_unlocked(priv);
210
+
if (ret < 0) {
211
+
dev_err_ratelimited(dev,
212
+
"SPI error on STATUS read for CRC check\n");
213
+
return ret;
214
+
}
215
+
216
+
status = get_unaligned_be16(&priv->rx_buffer[0]);
217
+
if (status & ADS131M_STATUS_CRC_ERR) {
218
+
dev_err_ratelimited(dev,
219
+
"Input CRC error reported in STATUS = 0x%04x\n",
220
+
status);
221
+
return -EIO;
222
+
}
223
+
224
+
return 0;
225
+
}
226
+
227
+
/**
228
+
* ads131m_write_reg_unlocked - Writes a single register and verifies the ACK.
229
+
* @priv: Device private data structure.
230
+
* @reg: The 8-bit register address.
231
+
* @val: The 16-bit value to write.
232
+
*
233
+
* This function performs the full 3-cycle WREG operation with Input CRC:
234
+
* 1. (Cycle 1) Sends WREG command, data, and its calculated CRC.
235
+
* 2. (Cycle 2) Sends NULL+CRC to retrieve the response from Cycle 1.
236
+
* 3. Verifies the response is the correct ACK for the WREG.
237
+
* 4. (Cycle 3) Sends NULL+CRC to retrieve STATUS and check for CRC_ERR.
238
+
*
239
+
* Return: 0 on success, or a negative error code.
240
+
*/
241
+
static int ads131m_write_reg_unlocked(struct ads131m_priv *priv, u8 reg, u16 val)
242
+
{
243
+
struct iio_dev *indio_dev = priv->indio_dev;
244
+
u16 command, expected_ack, response, crc;
245
+
struct device *dev = &priv->spi->dev;
246
+
int ret_crc_err = 0;
247
+
int ret;
248
+
249
+
lockdep_assert_held(&priv->lock);
250
+
251
+
command = ADS131M_CMD_WREG(reg, 0); /* n = 0 for 1 register */
252
+
/*
253
+
* Per Table 8-11, WREG response is: 010a aaaa ammm mmmm
254
+
* For 1 reg (n = 0 -> m = 0): 010a aaaa a000 0000 = 0x4000 | (reg << 7)
255
+
*/
256
+
expected_ack = 0x4000 | (reg << 7);
257
+
258
+
/* Cycle 1: Send WREG Command + Data + Input CRC */
259
+
260
+
memset(priv->tx_buffer, 0, ADS131M_FRAME_BYTES(indio_dev->num_channels));
261
+
262
+
/* Word 0: WREG command, 1 reg (n = 0), MSB-aligned */
263
+
put_unaligned_be16(command, &priv->tx_buffer[0]);
264
+
265
+
/* Word 1: Data, MSB-aligned */
266
+
put_unaligned_be16(val, &priv->tx_buffer[3]);
267
+
268
+
/* Word 2: Input CRC. Calculated over Word 0 (Cmd) and Word 1 (Data). */
269
+
crc = crc_itu_t(0xffff, priv->tx_buffer, 6);
270
+
put_unaligned_be16(crc, &priv->tx_buffer[6]);
271
+
272
+
/* Ignore the RX buffer (it's from the previous command) */
273
+
ret = spi_sync(priv->spi, &priv->msg);
274
+
if (ret < 0) {
275
+
dev_err_ratelimited(dev, "SPI error on WREG (cycle 1)\n");
276
+
return ret;
277
+
}
278
+
279
+
/* Cycle 2: Send NULL Command to get the WREG response */
280
+
ret = ads131m_rx_frame_unlocked(priv);
281
+
if (ret < 0) {
282
+
dev_err_ratelimited(dev, "SPI error on WREG ACK (cycle 2)\n");
283
+
return ret;
284
+
}
285
+
286
+
/*
287
+
* Response is in the first 2 bytes of the RX buffer
288
+
* (MSB-aligned 16-bit response)
289
+
*/
290
+
response = get_unaligned_be16(&priv->rx_buffer[0]);
291
+
if (response != expected_ack) {
292
+
dev_err_ratelimited(dev, "WREG(0x%02x) failed, expected ACK 0x%04x, got 0x%04x\n",
293
+
reg, expected_ack, response);
294
+
ret_crc_err = -EIO;
295
+
/*
296
+
* Don't return yet, still need to do Cycle 3 to clear
297
+
* any potential CRC_ERR flag from this failed command.
298
+
*/
299
+
}
300
+
301
+
/*
302
+
* Cycle 3: Check STATUS for Input CRC error.
303
+
* This is necessary even if ACK was wrong, to clear the CRC_ERR flag.
304
+
*/
305
+
ret = ads131m_check_status_crc_err(priv);
306
+
if (ret < 0)
307
+
return ret;
308
+
309
+
return ret_crc_err;
310
+
}
311
+
312
+
/**
313
+
* ads131m_read_reg_unlocked - Reads a single register from the device.
314
+
* @priv: Device private data structure.
315
+
* @reg: The 8-bit register address.
316
+
* @val: Pointer to store the 16-bit register value.
317
+
*
318
+
* This function performs the full 3-cycle RREG operation with Input CRC:
319
+
* 1. (Cycle 1) Sends the RREG command + Input CRC.
320
+
* 2. (Cycle 2) Sends NULL+CRC to retrieve the register data.
321
+
* 3. (Cycle 3) Sends NULL+CRC to retrieve STATUS and check for CRC_ERR.
322
+
*
323
+
* Return: 0 on success, or a negative error code.
324
+
*/
325
+
static int ads131m_read_reg_unlocked(struct ads131m_priv *priv, u8 reg, u16 *val)
326
+
{
327
+
struct device *dev = &priv->spi->dev;
328
+
u16 command;
329
+
int ret;
330
+
331
+
lockdep_assert_held(&priv->lock);
332
+
333
+
command = ADS131M_CMD_RREG(reg, 0); /* n=0 for 1 register */
334
+
335
+
/*
336
+
* Cycle 1: Send RREG Command + Input CRC
337
+
* Ignore the RX buffer (it's from the previous command)
338
+
*/
339
+
ret = ads131m_tx_frame_unlocked(priv, command);
340
+
if (ret < 0) {
341
+
dev_err_ratelimited(dev, "SPI error on RREG (cycle 1)\n");
342
+
return ret;
343
+
}
344
+
345
+
/* Cycle 2: Send NULL Command to get the register data */
346
+
ret = ads131m_rx_frame_unlocked(priv);
347
+
if (ret < 0) {
348
+
dev_err_ratelimited(dev, "SPI error on RREG data (cycle 2)\n");
349
+
return ret;
350
+
}
351
+
352
+
/*
353
+
* Per datasheet, for a single reg read, the response is the data.
354
+
* It's in the first 2 bytes of the RX buffer (MSB-aligned 16-bit).
355
+
*/
356
+
*val = get_unaligned_be16(&priv->rx_buffer[0]);
357
+
358
+
/*
359
+
* Cycle 3: Check STATUS for Input CRC error.
360
+
* The RREG command does not execute if CRC is bad, but we read
361
+
* STATUS anyway to clear the flag in case it was set.
362
+
*/
363
+
return ads131m_check_status_crc_err(priv);
364
+
}
365
+
366
+
/**
367
+
* ads131m_rmw_reg - Reads, modifies, and writes a single register.
368
+
* @priv: Device private data structure.
369
+
* @reg: The 8-bit register address.
370
+
* @clear: Bitmask of bits to clear.
371
+
* @set: Bitmask of bits to set.
372
+
*
373
+
* This function performs an atomic read-modify-write operation on a register.
374
+
* It reads the register, applies the clear and set masks, and writes
375
+
* the new value back if it has changed.
376
+
*
377
+
* Return: 0 on success, or a negative error code.
378
+
*/
379
+
static int ads131m_rmw_reg(struct ads131m_priv *priv, u8 reg, u16 clear, u16 set)
380
+
{
381
+
u16 old_val, new_val;
382
+
int ret;
383
+
384
+
guard(mutex)(&priv->lock);
385
+
386
+
ret = ads131m_read_reg_unlocked(priv, reg, &old_val);
387
+
if (ret < 0)
388
+
return ret;
389
+
390
+
new_val = (old_val & ~clear) | set;
391
+
if (new_val == old_val)
392
+
return 0;
393
+
394
+
return ads131m_write_reg_unlocked(priv, reg, new_val);
395
+
}
396
+
397
+
/**
398
+
* ads131m_verify_output_crc - Verifies the CRC of the received SPI frame.
399
+
* @priv: Device private data structure.
400
+
*
401
+
* This function calculates the CRC-16-CCITT (Poly 0x1021, Seed 0xFFFF) over
402
+
* the received response and channel data, and compares it to the CRC word
403
+
* received at the end of the SPI frame.
404
+
*
405
+
* Return: 0 on success, -EIO on CRC mismatch.
406
+
*/
407
+
static int ads131m_verify_output_crc(struct ads131m_priv *priv)
408
+
{
409
+
struct iio_dev *indio_dev = priv->indio_dev;
410
+
struct device *dev = &priv->spi->dev;
411
+
u16 calculated_crc, received_crc;
412
+
size_t data_len;
413
+
414
+
lockdep_assert_held(&priv->lock);
415
+
416
+
/*
417
+
* Frame: [Response][Chan 0]...[Chan N-1][CRC Word]
418
+
* Data for CRC: [Response][Chan 0]...[Chan N-1]
419
+
* Data length = (N_channels + 1) * 3 bytes (at 24-bit word size)
420
+
*/
421
+
data_len = ADS131M_FRAME_BYTES(indio_dev->num_channels) - 3;
422
+
calculated_crc = crc_itu_t(0xffff, priv->rx_buffer, data_len);
423
+
424
+
/*
425
+
* The received 16-bit CRC is MSB-aligned in the last 24-bit word.
426
+
* We extract it from the first 2 bytes (BE) of that word.
427
+
*/
428
+
received_crc = get_unaligned_be16(&priv->rx_buffer[data_len]);
429
+
if (calculated_crc != received_crc) {
430
+
dev_err_ratelimited(dev, "Output CRC error. Got %04x, expected %04x\n",
431
+
received_crc, calculated_crc);
432
+
return -EIO;
433
+
}
434
+
435
+
return 0;
436
+
}
437
+
438
+
/**
439
+
* ads131m_adc_read - Reads channel data, checks input and output CRCs.
440
+
* @priv: Device private data structure.
441
+
* @channel: The channel number to read.
442
+
* @val: Pointer to store the raw 24-bit value.
443
+
*
444
+
* This function sends a NULL command (with Input CRC) to retrieve data.
445
+
* It checks the received STATUS word for any Input CRC errors from the
446
+
* previous command, and then verifies the Output CRC of the current
447
+
* data frame.
448
+
*
449
+
* Return: 0 on success, or a negative error code.
450
+
*/
451
+
static int ads131m_adc_read(struct ads131m_priv *priv, u8 channel, s32 *val)
452
+
{
453
+
struct device *dev = &priv->spi->dev;
454
+
u16 status;
455
+
int ret;
456
+
u8 *buf;
457
+
458
+
guard(mutex)(&priv->lock);
459
+
460
+
/* Send NULL command + Input CRC, and receive data frame */
461
+
ret = ads131m_rx_frame_unlocked(priv);
462
+
if (ret < 0)
463
+
return ret;
464
+
465
+
/*
466
+
* Check STATUS for Input CRC error from the previous command frame.
467
+
* Note: the STATUS word belongs to the frame before this NULL command.
468
+
*/
469
+
status = get_unaligned_be16(&priv->rx_buffer[0]);
470
+
if (status & ADS131M_STATUS_CRC_ERR) {
471
+
dev_err_ratelimited(dev,
472
+
"Previous input CRC error reported in STATUS (0x%04x)\n",
473
+
status);
474
+
}
475
+
476
+
ret = ads131m_verify_output_crc(priv);
477
+
if (ret < 0)
478
+
return ret;
479
+
480
+
buf = &priv->rx_buffer[ADS131M_CHANNEL_INDEX(channel)];
481
+
*val = sign_extend32(get_unaligned_be24(buf), ADS131M_CODE_BITS);
482
+
483
+
return 0;
484
+
}
485
+
486
+
static int ads131m_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *channel,
487
+
int *val, int *val2, long mask)
488
+
{
489
+
struct ads131m_priv *priv = iio_priv(indio_dev);
490
+
int ret;
491
+
492
+
switch (mask) {
493
+
case IIO_CHAN_INFO_RAW:
494
+
ret = ads131m_adc_read(priv, channel->channel, val);
495
+
if (ret)
496
+
return ret;
497
+
return IIO_VAL_INT;
498
+
case IIO_CHAN_INFO_SCALE:
499
+
*val = priv->scale_val;
500
+
*val2 = priv->scale_val2;
501
+
502
+
return IIO_VAL_FRACTIONAL;
503
+
default:
504
+
return -EINVAL;
505
+
}
506
+
}
507
+
508
+
#define ADS131M_VOLTAGE_CHANNEL(num) \
509
+
{ \
510
+
.type = IIO_VOLTAGE, \
511
+
.differential = 1, \
512
+
.indexed = 1, \
513
+
.channel = (num), \
514
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
515
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
516
+
}
517
+
518
+
static const struct iio_chan_spec ads131m02_channels[] = {
519
+
ADS131M_VOLTAGE_CHANNEL(0),
520
+
ADS131M_VOLTAGE_CHANNEL(1),
521
+
};
522
+
523
+
static const struct iio_chan_spec ads131m03_channels[] = {
524
+
ADS131M_VOLTAGE_CHANNEL(0),
525
+
ADS131M_VOLTAGE_CHANNEL(1),
526
+
ADS131M_VOLTAGE_CHANNEL(2),
527
+
};
528
+
529
+
static const struct iio_chan_spec ads131m04_channels[] = {
530
+
ADS131M_VOLTAGE_CHANNEL(0),
531
+
ADS131M_VOLTAGE_CHANNEL(1),
532
+
ADS131M_VOLTAGE_CHANNEL(2),
533
+
ADS131M_VOLTAGE_CHANNEL(3),
534
+
};
535
+
536
+
static const struct iio_chan_spec ads131m06_channels[] = {
537
+
ADS131M_VOLTAGE_CHANNEL(0),
538
+
ADS131M_VOLTAGE_CHANNEL(1),
539
+
ADS131M_VOLTAGE_CHANNEL(2),
540
+
ADS131M_VOLTAGE_CHANNEL(3),
541
+
ADS131M_VOLTAGE_CHANNEL(4),
542
+
ADS131M_VOLTAGE_CHANNEL(5),
543
+
};
544
+
545
+
static const struct iio_chan_spec ads131m08_channels[] = {
546
+
ADS131M_VOLTAGE_CHANNEL(0),
547
+
ADS131M_VOLTAGE_CHANNEL(1),
548
+
ADS131M_VOLTAGE_CHANNEL(2),
549
+
ADS131M_VOLTAGE_CHANNEL(3),
550
+
ADS131M_VOLTAGE_CHANNEL(4),
551
+
ADS131M_VOLTAGE_CHANNEL(5),
552
+
ADS131M_VOLTAGE_CHANNEL(6),
553
+
ADS131M_VOLTAGE_CHANNEL(7),
554
+
};
555
+
556
+
static const struct ads131m_configuration ads131m02_config = {
557
+
.channels = ads131m02_channels,
558
+
.num_channels = ARRAY_SIZE(ads131m02_channels),
559
+
.reset_ack = 0xff22,
560
+
.name = "ads131m02",
561
+
};
562
+
563
+
static const struct ads131m_configuration ads131m03_config = {
564
+
.channels = ads131m03_channels,
565
+
.num_channels = ARRAY_SIZE(ads131m03_channels),
566
+
.reset_ack = 0xff23,
567
+
.name = "ads131m03",
568
+
};
569
+
570
+
static const struct ads131m_configuration ads131m04_config = {
571
+
.channels = ads131m04_channels,
572
+
.num_channels = ARRAY_SIZE(ads131m04_channels),
573
+
.reset_ack = 0xff24,
574
+
.name = "ads131m04",
575
+
};
576
+
577
+
static const struct ads131m_configuration ads131m06_config = {
578
+
.channels = ads131m06_channels,
579
+
.num_channels = ARRAY_SIZE(ads131m06_channels),
580
+
.reset_ack = 0xff26,
581
+
.supports_extref = true,
582
+
.supports_xtal = true,
583
+
.name = "ads131m06",
584
+
};
585
+
586
+
static const struct ads131m_configuration ads131m08_config = {
587
+
.channels = ads131m08_channels,
588
+
.num_channels = ARRAY_SIZE(ads131m08_channels),
589
+
.reset_ack = 0xff28,
590
+
.supports_extref = true,
591
+
.supports_xtal = true,
592
+
.name = "ads131m08",
593
+
};
594
+
595
+
static const struct iio_info ads131m_info = {
596
+
.read_raw = ads131m_read_raw,
597
+
};
598
+
599
+
/*
600
+
* Prepares the reusable SPI message structure for a full-duplex transfer.
601
+
* The ADS131M requires sending a command frame while simultaneously
602
+
* receiving the response/data frame from the previous command cycle.
603
+
*
604
+
* This message is optimized for the primary data acquisition workflow:
605
+
* sending a single-word command (like NULL) and receiving a full data
606
+
* frame (Response + N*Channels + CRC).
607
+
*
608
+
* This message is sized for a full data frame and is reused for all
609
+
* command/data cycles. The driver does not implement variable-length SPI
610
+
* messages.
611
+
*
612
+
* Return: 0 on success, or a negative error code.
613
+
*/
614
+
static int ads131m_prepare_message(struct ads131m_priv *priv)
615
+
{
616
+
struct iio_dev *indio_dev = priv->indio_dev;
617
+
struct device *dev = &priv->spi->dev;
618
+
int ret;
619
+
620
+
priv->xfer.tx_buf = priv->tx_buffer;
621
+
priv->xfer.rx_buf = priv->rx_buffer;
622
+
priv->xfer.len = ADS131M_FRAME_BYTES(indio_dev->num_channels);
623
+
spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
624
+
625
+
ret = devm_spi_optimize_message(dev, priv->spi, &priv->msg);
626
+
if (ret)
627
+
return dev_err_probe(dev, ret, "failed to optimize SPI message\n");
628
+
629
+
return 0;
630
+
}
631
+
632
+
/**
633
+
* ads131m_hw_reset - Pulses the optional hardware reset.
634
+
* @priv: Device private data structure.
635
+
* @rstc: Reset control for the /RESET line.
636
+
*
637
+
* Pulses the /RESET line to perform a hardware reset and waits the
638
+
* required t_REGACQ time for the device to be ready.
639
+
*
640
+
* Return: 0 on success, or a negative error code.
641
+
*/
642
+
static int ads131m_hw_reset(struct ads131m_priv *priv,
643
+
struct reset_control *rstc)
644
+
{
645
+
struct device *dev = &priv->spi->dev;
646
+
int ret;
647
+
648
+
/*
649
+
* Manually pulse the reset line using the framework.
650
+
* The reset-gpio provider does not implement the .reset op,
651
+
* so we must use .assert and .deassert.
652
+
*/
653
+
ret = reset_control_assert(rstc);
654
+
if (ret)
655
+
return dev_err_probe(dev, ret, "Failed to assert reset\n");
656
+
657
+
/* Datasheet: Hold /RESET low for > 2 f_CLKIN cycles. 1us is ample. */
658
+
fsleep(1);
659
+
660
+
ret = reset_control_deassert(rstc);
661
+
if (ret < 0)
662
+
return dev_err_probe(dev, ret, "Failed to deassert reset\n");
663
+
664
+
/* Wait t_REGACQ (5us) for registers to be accessible */
665
+
fsleep(ADS131M_RESET_DELAY_US);
666
+
667
+
return 0;
668
+
}
669
+
670
+
/**
671
+
* ads131m_sw_reset - Issues a software RESET and verifies ACK.
672
+
* @priv: Device private data structure.
673
+
*
674
+
* This function sends a RESET command (with Input CRC), waits t_REGACQ,
675
+
* reads back the RESET ACK, and then sends a final NULL to check for
676
+
* any input CRC errors.
677
+
*
678
+
* Return: 0 on success, or a negative error code.
679
+
*/
680
+
static int ads131m_sw_reset(struct ads131m_priv *priv)
681
+
{
682
+
u16 expected_ack = priv->config->reset_ack;
683
+
struct device *dev = &priv->spi->dev;
684
+
u16 response;
685
+
int ret;
686
+
687
+
guard(mutex)(&priv->lock);
688
+
689
+
ret = ads131m_tx_frame_unlocked(priv, ADS131M_CMD_RESET);
690
+
if (ret < 0)
691
+
return dev_err_probe(dev, ret, "Failed to send RESET command\n");
692
+
693
+
/* Wait t_REGACQ (5us) for device to be ready after reset */
694
+
fsleep(ADS131M_RESET_DELAY_US);
695
+
696
+
/* Cycle 2: Send NULL + CRC to retrieve the response to the RESET */
697
+
ret = ads131m_rx_frame_unlocked(priv);
698
+
if (ret < 0)
699
+
return dev_err_probe(dev, ret, "Failed to read RESET ACK\n");
700
+
701
+
response = get_unaligned_be16(&priv->rx_buffer[0]);
702
+
703
+
/* Check against the device-specific ACK value */
704
+
if (response != expected_ack)
705
+
return dev_err_probe(dev, -EIO,
706
+
"RESET ACK mismatch, got 0x%04x, expected 0x%04x\n",
707
+
response, expected_ack);
708
+
709
+
/* Cycle 3: Check STATUS for Input CRC error on the RESET command. */
710
+
return ads131m_check_status_crc_err(priv);
711
+
}
712
+
713
+
/**
714
+
* ads131m_reset - Resets the device using hardware or software.
715
+
* @priv: Device private data structure.
716
+
* @rstc: Optional reset control, or NULL for software reset.
717
+
*
718
+
* This function performs a hardware reset if supported (rstc provided),
719
+
* otherwise it issues a software RESET command via SPI.
720
+
*
721
+
* Note: The software reset path also validates the device's reset
722
+
* acknowledgment against the expected ID for the compatible string.
723
+
* The hardware reset path bypasses this ID check.
724
+
*
725
+
* Return: 0 on success, or a negative error code.
726
+
*/
727
+
static int ads131m_reset(struct ads131m_priv *priv, struct reset_control *rstc)
728
+
{
729
+
if (rstc)
730
+
return ads131m_hw_reset(priv, rstc);
731
+
732
+
return ads131m_sw_reset(priv);
733
+
}
734
+
735
+
static int ads131m_power_init(struct ads131m_priv *priv)
736
+
{
737
+
static const char * const supply_ids[] = { "avdd", "dvdd" };
738
+
struct device *dev = &priv->spi->dev;
739
+
int vref_uV;
740
+
int ret;
741
+
742
+
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(supply_ids), supply_ids);
743
+
if (ret < 0)
744
+
return dev_err_probe(dev, ret, "failed to enable regulators\n");
745
+
746
+
/* Default to Internal 1.2V reference: 1200mV / 2^23 */
747
+
priv->scale_val = ADS131M_VREF_INTERNAL_mV;
748
+
priv->scale_val2 = BIT(ADS131M_CODE_BITS);
749
+
750
+
if (!priv->config->supports_extref)
751
+
return 0;
752
+
753
+
ret = devm_regulator_get_enable_read_voltage(dev, "refin");
754
+
if (ret < 0 && ret != -ENODEV)
755
+
return dev_err_probe(dev, ret, "failed to get refin supply\n");
756
+
757
+
if (ret == 0)
758
+
return dev_err_probe(dev, -EINVAL, "refin supply reports 0V\n");
759
+
760
+
if (ret == -ENODEV)
761
+
return 0;
762
+
763
+
vref_uV = ret;
764
+
765
+
/*
766
+
* External reference found: Scale(mV) = (vref_uV * 0.96) / 1000
767
+
* The denominator is 100 * 2^23 because of the 0.96 factor (96/100).
768
+
*/
769
+
priv->scale_val = div_s64((s64)vref_uV * ADS131M_EXTREF_SCALE_NUM, 1000);
770
+
priv->scale_val2 = ADS131M_EXTREF_SCALE_DEN * BIT(ADS131M_CODE_BITS);
771
+
priv->use_external_ref = true;
772
+
773
+
return 0;
774
+
}
775
+
776
+
/**
777
+
* ads131m_hw_init - Initialize the ADC hardware.
778
+
* @priv: Device private data structure.
779
+
* @rstc: Optional reset control, or NULL for software reset.
780
+
* @is_xtal: True if 'clock-names' is "xtal", false if "clkin".
781
+
*
782
+
* Return: 0 on success, or a negative error code.
783
+
*/
784
+
static int ads131m_hw_init(struct ads131m_priv *priv,
785
+
struct reset_control *rstc, bool is_xtal)
786
+
{
787
+
struct device *dev = &priv->spi->dev;
788
+
u16 mode_clear, mode_set;
789
+
int ret;
790
+
791
+
ret = ads131m_reset(priv, rstc);
792
+
if (ret < 0)
793
+
return ret;
794
+
795
+
/*
796
+
* Configure CLOCK register (0x03) based on DT properties.
797
+
* This register only needs configuration for 32-pin (M06/M08)
798
+
* variants, as the configurable bits (XTAL_DIS, EXTREF_EN)
799
+
* are reserved on 20-pin (M02/M03/M04) variants.
800
+
*/
801
+
if (priv->config->supports_xtal || priv->config->supports_extref) {
802
+
u16 clk_set = 0;
803
+
804
+
if (priv->config->supports_xtal && !is_xtal)
805
+
clk_set |= ADS131M_CLOCK_XTAL_DIS;
806
+
807
+
if (priv->config->supports_extref && priv->use_external_ref)
808
+
clk_set |= ADS131M_CLOCK_EXTREF_EN;
809
+
810
+
ret = ads131m_rmw_reg(priv, ADS131M_REG_CLOCK,
811
+
ADS131M_CLOCK_EXTREF_EN | ADS131M_CLOCK_XTAL_DIS,
812
+
clk_set);
813
+
if (ret < 0)
814
+
return dev_err_probe(dev, ret, "Failed to configure CLOCK register\n");
815
+
}
816
+
817
+
/*
818
+
* The RESET command sets all registers to default, which means:
819
+
* 1. The RESET bit (Bit 10) in MODE is set to '1'.
820
+
* 2. The CRC_TYPE bit (Bit 11) in MODE is '0' (CCITT).
821
+
* 3. The RX_CRC_EN bit (Bit 12) in MODE is '0' (Disabled).
822
+
*
823
+
* We must:
824
+
* 1. Clear the RESET bit.
825
+
* 2. Enable Input CRC (RX_CRC_EN).
826
+
* 3. Explicitly clear the ANSI CRC bit (for certainty).
827
+
*/
828
+
mode_clear = ADS131M_MODE_CRC_TYPE_ANSI | ADS131M_MODE_RESET_FLAG;
829
+
mode_set = ADS131M_MODE_RX_CRC_EN;
830
+
831
+
ret = ads131m_rmw_reg(priv, ADS131M_REG_MODE, mode_clear, mode_set);
832
+
if (ret < 0)
833
+
return dev_err_probe(dev, ret, "Failed to configure MODE register\n");
834
+
835
+
return 0;
836
+
}
837
+
838
+
/**
839
+
* ads131m_parse_clock - enable clock and detect "xtal" selection
840
+
* @priv: Device private data structure.
841
+
* @is_xtal: result flag (true if "xtal", false if default "clkin")
842
+
*
843
+
* Return: 0 on success, or a negative error code.
844
+
*/
845
+
static int ads131m_parse_clock(struct ads131m_priv *priv, bool *is_xtal)
846
+
{
847
+
struct device *dev = &priv->spi->dev;
848
+
struct clk *clk;
849
+
int ret;
850
+
851
+
clk = devm_clk_get_enabled(dev, NULL);
852
+
if (IS_ERR_OR_NULL(clk)) {
853
+
if (IS_ERR(clk))
854
+
ret = PTR_ERR(clk);
855
+
else
856
+
ret = -ENODEV;
857
+
858
+
return dev_err_probe(dev, ret, "clk get enabled failed\n");
859
+
}
860
+
861
+
ret = device_property_match_string(dev, "clock-names", "xtal");
862
+
if (ret > 0)
863
+
return dev_err_probe(dev, -EINVAL,
864
+
"'xtal' must be the only or first clock name");
865
+
866
+
if (ret < 0 && ret != -ENODATA)
867
+
return dev_err_probe(dev, ret,
868
+
"failed to read 'clock-names' property");
869
+
870
+
if (ret == 0 && !priv->config->supports_xtal)
871
+
return dev_err_probe(dev, -EINVAL,
872
+
"'xtal' clock not supported on this device");
873
+
874
+
*is_xtal = !ret;
875
+
876
+
return 0;
877
+
}
878
+
879
+
static int ads131m_probe(struct spi_device *spi)
880
+
{
881
+
const struct ads131m_configuration *config;
882
+
struct device *dev = &spi->dev;
883
+
struct reset_control *rstc;
884
+
struct iio_dev *indio_dev;
885
+
struct ads131m_priv *priv;
886
+
bool is_xtal;
887
+
int ret;
888
+
889
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
890
+
if (!indio_dev)
891
+
return -ENOMEM;
892
+
893
+
priv = iio_priv(indio_dev);
894
+
priv->indio_dev = indio_dev;
895
+
priv->spi = spi;
896
+
897
+
indio_dev->modes = INDIO_DIRECT_MODE;
898
+
indio_dev->info = &ads131m_info;
899
+
900
+
config = spi_get_device_match_data(spi);
901
+
902
+
priv->config = config;
903
+
indio_dev->name = config->name;
904
+
indio_dev->channels = config->channels;
905
+
indio_dev->num_channels = config->num_channels;
906
+
907
+
rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
908
+
if (IS_ERR(rstc))
909
+
return dev_err_probe(dev, PTR_ERR(rstc),
910
+
"Failed to get reset controller\n");
911
+
912
+
ret = devm_mutex_init(dev, &priv->lock);
913
+
if (ret < 0)
914
+
return ret;
915
+
916
+
ret = ads131m_prepare_message(priv);
917
+
if (ret < 0)
918
+
return ret;
919
+
920
+
ret = ads131m_power_init(priv);
921
+
if (ret < 0)
922
+
return ret;
923
+
924
+
/* Power must be applied and stable before the clock is enabled. */
925
+
ret = ads131m_parse_clock(priv, &is_xtal);
926
+
if (ret < 0)
927
+
return ret;
928
+
929
+
ret = ads131m_hw_init(priv, rstc, is_xtal);
930
+
if (ret < 0)
931
+
return ret;
932
+
933
+
return devm_iio_device_register(dev, indio_dev);
934
+
}
935
+
936
+
static const struct of_device_id ads131m_of_match[] = {
937
+
{ .compatible = "ti,ads131m02", .data = &ads131m02_config },
938
+
{ .compatible = "ti,ads131m03", .data = &ads131m03_config },
939
+
{ .compatible = "ti,ads131m04", .data = &ads131m04_config },
940
+
{ .compatible = "ti,ads131m06", .data = &ads131m06_config },
941
+
{ .compatible = "ti,ads131m08", .data = &ads131m08_config },
942
+
{ }
943
+
};
944
+
MODULE_DEVICE_TABLE(of, ads131m_of_match);
945
+
946
+
static const struct spi_device_id ads131m_id[] = {
947
+
{ "ads131m02", (kernel_ulong_t)&ads131m02_config },
948
+
{ "ads131m03", (kernel_ulong_t)&ads131m03_config },
949
+
{ "ads131m04", (kernel_ulong_t)&ads131m04_config },
950
+
{ "ads131m06", (kernel_ulong_t)&ads131m06_config },
951
+
{ "ads131m08", (kernel_ulong_t)&ads131m08_config },
952
+
{ }
953
+
};
954
+
MODULE_DEVICE_TABLE(spi, ads131m_id);
955
+
956
+
static struct spi_driver ads131m_driver = {
957
+
.driver = {
958
+
.name = "ads131m02",
959
+
.of_match_table = ads131m_of_match,
960
+
},
961
+
.probe = ads131m_probe,
962
+
.id_table = ads131m_id,
963
+
};
964
+
module_spi_driver(ads131m_driver);
965
+
966
+
MODULE_AUTHOR("David Jander <david@protonic.nl>");
967
+
MODULE_DESCRIPTION("Texas Instruments ADS131M02 ADC driver");
968
+
MODULE_LICENSE("GPL");
+12
drivers/iio/amplifiers/Kconfig
+12
drivers/iio/amplifiers/Kconfig
···
36
36
To compile this driver as a module, choose M here: the
37
37
module will be called ada4250.
38
38
39
+
config ADL8113
40
+
tristate "Analog Devices ADL8113 Low Noise Amplifier"
41
+
depends on GPIOLIB
42
+
help
43
+
Say yes here to build support for Analog Devices ADL8113 Low Noise
44
+
Amplifier with integrated bypass switches. The device supports four
45
+
operation modes controlled by GPIO pins: internal amplifier,
46
+
internal bypass, and two external bypass modes.
47
+
48
+
To compile this driver as a module, choose M here: the
49
+
module will be called adl8113.
50
+
39
51
config HMC425
40
52
tristate "Analog Devices HMC425A and similar GPIO Gain Amplifiers"
41
53
depends on GPIOLIB
+1
drivers/iio/amplifiers/Makefile
+1
drivers/iio/amplifiers/Makefile
+269
drivers/iio/amplifiers/adl8113.c
+269
drivers/iio/amplifiers/adl8113.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* ADL8113 Low Noise Amplifier with integrated bypass switches
4
+
*
5
+
* Copyright 2025 Analog Devices Inc.
6
+
*/
7
+
8
+
#include <linux/array_size.h>
9
+
#include <linux/bitmap.h>
10
+
#include <linux/device/driver.h>
11
+
#include <linux/dev_printk.h>
12
+
#include <linux/err.h>
13
+
#include <linux/gpio/consumer.h>
14
+
#include <linux/iio/iio.h>
15
+
#include <linux/mod_devicetable.h>
16
+
#include <linux/module.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/property.h>
19
+
#include <linux/regulator/consumer.h>
20
+
#include <linux/types.h>
21
+
22
+
enum adl8113_signal_path {
23
+
ADL8113_INTERNAL_AMP,
24
+
ADL8113_INTERNAL_BYPASS,
25
+
ADL8113_EXTERNAL_A,
26
+
ADL8113_EXTERNAL_B,
27
+
};
28
+
29
+
struct adl8113_gain_config {
30
+
enum adl8113_signal_path path;
31
+
int gain_db;
32
+
};
33
+
34
+
struct adl8113_state {
35
+
struct gpio_descs *gpios;
36
+
struct adl8113_gain_config *gain_configs;
37
+
unsigned int num_gain_configs;
38
+
enum adl8113_signal_path current_path;
39
+
};
40
+
41
+
static const char * const adl8113_supply_names[] = {
42
+
"vdd1",
43
+
"vss2",
44
+
"vdd2",
45
+
};
46
+
47
+
static int adl8113_set_path(struct adl8113_state *st,
48
+
enum adl8113_signal_path path)
49
+
{
50
+
DECLARE_BITMAP(values, 2);
51
+
int ret;
52
+
53
+
/*
54
+
* Determine GPIO values based on signal path.
55
+
* Va: bit 0, Vb: bit 1.
56
+
*/
57
+
switch (path) {
58
+
case ADL8113_INTERNAL_AMP:
59
+
bitmap_write(values, 0x00, 0, 2);
60
+
break;
61
+
case ADL8113_INTERNAL_BYPASS:
62
+
bitmap_write(values, 0x03, 0, 2);
63
+
break;
64
+
case ADL8113_EXTERNAL_A:
65
+
bitmap_write(values, 0x02, 0, 2);
66
+
break;
67
+
case ADL8113_EXTERNAL_B:
68
+
bitmap_write(values, 0x01, 0, 2);
69
+
break;
70
+
default:
71
+
return -EINVAL;
72
+
}
73
+
74
+
ret = gpiod_set_array_value_cansleep(st->gpios->ndescs, st->gpios->desc,
75
+
st->gpios->info, values);
76
+
if (ret)
77
+
return ret;
78
+
79
+
st->current_path = path;
80
+
return 0;
81
+
}
82
+
83
+
static int adl8113_find_gain_config(struct adl8113_state *st, int gain_db)
84
+
{
85
+
unsigned int i;
86
+
87
+
for (i = 0; i < st->num_gain_configs; i++) {
88
+
if (st->gain_configs[i].gain_db == gain_db)
89
+
return i;
90
+
}
91
+
return -EINVAL;
92
+
}
93
+
94
+
static const struct iio_chan_spec adl8113_channels[] = {
95
+
{
96
+
.type = IIO_VOLTAGE,
97
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_HARDWAREGAIN),
98
+
},
99
+
};
100
+
101
+
static int adl8113_read_raw(struct iio_dev *indio_dev,
102
+
struct iio_chan_spec const *chan,
103
+
int *val, int *val2, long mask)
104
+
{
105
+
struct adl8113_state *st = iio_priv(indio_dev);
106
+
unsigned int i;
107
+
108
+
switch (mask) {
109
+
case IIO_CHAN_INFO_HARDWAREGAIN:
110
+
/* Find current gain configuration */
111
+
for (i = 0; i < st->num_gain_configs; i++) {
112
+
if (st->gain_configs[i].path == st->current_path) {
113
+
*val = st->gain_configs[i].gain_db;
114
+
*val2 = 0;
115
+
return IIO_VAL_INT_PLUS_MICRO_DB;
116
+
}
117
+
}
118
+
return -EINVAL;
119
+
default:
120
+
return -EINVAL;
121
+
}
122
+
}
123
+
124
+
static int adl8113_write_raw(struct iio_dev *indio_dev,
125
+
struct iio_chan_spec const *chan,
126
+
int val, int val2, long mask)
127
+
{
128
+
struct adl8113_state *st = iio_priv(indio_dev);
129
+
int config_idx;
130
+
131
+
switch (mask) {
132
+
case IIO_CHAN_INFO_HARDWAREGAIN:
133
+
if (val2 != 0)
134
+
return -EINVAL;
135
+
136
+
config_idx = adl8113_find_gain_config(st, val);
137
+
if (config_idx < 0)
138
+
return config_idx;
139
+
140
+
return adl8113_set_path(st, st->gain_configs[config_idx].path);
141
+
default:
142
+
return -EINVAL;
143
+
}
144
+
}
145
+
146
+
static const struct iio_info adl8113_info = {
147
+
.read_raw = adl8113_read_raw,
148
+
.write_raw = adl8113_write_raw,
149
+
};
150
+
151
+
static int adl8113_init_gain_configs(struct device *dev, struct adl8113_state *st)
152
+
{
153
+
int external_a_gain, external_b_gain;
154
+
unsigned int i;
155
+
156
+
/*
157
+
* Allocate for all 4 possible paths:
158
+
* - Internal amp and bypass (always present)
159
+
* - External bypass A and B (optional if configured)
160
+
*/
161
+
st->gain_configs = devm_kcalloc(dev, 4, sizeof(*st->gain_configs),
162
+
GFP_KERNEL);
163
+
if (!st->gain_configs)
164
+
return -ENOMEM;
165
+
166
+
/* Start filling the gain configurations with data */
167
+
i = 0;
168
+
169
+
/* Always include internal amplifier (14dB) */
170
+
st->gain_configs[i++] = (struct adl8113_gain_config) {
171
+
.path = ADL8113_INTERNAL_AMP,
172
+
.gain_db = 14,
173
+
};
174
+
175
+
/* Always include internal bypass (-2dB insertion loss) */
176
+
st->gain_configs[i++] = (struct adl8113_gain_config) {
177
+
.path = ADL8113_INTERNAL_BYPASS,
178
+
.gain_db = -2,
179
+
};
180
+
181
+
/* Add external bypass A if configured */
182
+
if (!device_property_read_u32(dev, "adi,external-bypass-a-gain-db",
183
+
&external_a_gain)) {
184
+
st->gain_configs[i++] = (struct adl8113_gain_config) {
185
+
.path = ADL8113_EXTERNAL_A,
186
+
.gain_db = external_a_gain,
187
+
};
188
+
}
189
+
190
+
/* Add external bypass B if configured */
191
+
if (!device_property_read_u32(dev, "adi,external-bypass-b-gain-db",
192
+
&external_b_gain)) {
193
+
st->gain_configs[i++] = (struct adl8113_gain_config) {
194
+
.path = ADL8113_EXTERNAL_B,
195
+
.gain_db = external_b_gain,
196
+
};
197
+
}
198
+
199
+
st->num_gain_configs = i;
200
+
201
+
return 0;
202
+
}
203
+
204
+
static int adl8113_probe(struct platform_device *pdev)
205
+
{
206
+
struct device *dev = &pdev->dev;
207
+
struct adl8113_state *st;
208
+
struct iio_dev *indio_dev;
209
+
int ret;
210
+
211
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
212
+
if (!indio_dev)
213
+
return -ENOMEM;
214
+
215
+
st = iio_priv(indio_dev);
216
+
217
+
st->gpios = devm_gpiod_get_array(dev, "ctrl", GPIOD_OUT_LOW);
218
+
if (IS_ERR(st->gpios))
219
+
return dev_err_probe(dev, PTR_ERR(st->gpios),
220
+
"failed to get control GPIOs\n");
221
+
222
+
if (st->gpios->ndescs != 2)
223
+
return dev_err_probe(dev, -EINVAL,
224
+
"expected 2 control GPIOs, got %u\n",
225
+
st->gpios->ndescs);
226
+
227
+
ret = devm_regulator_bulk_get_enable(dev,
228
+
ARRAY_SIZE(adl8113_supply_names),
229
+
adl8113_supply_names);
230
+
if (ret)
231
+
return dev_err_probe(dev, ret,
232
+
"failed to get and enable supplies\n");
233
+
234
+
/* Initialize gain configurations from devicetree */
235
+
ret = adl8113_init_gain_configs(dev, st);
236
+
if (ret)
237
+
return ret;
238
+
239
+
/* Initialize to internal amplifier path (14dB) */
240
+
ret = adl8113_set_path(st, ADL8113_INTERNAL_AMP);
241
+
if (ret)
242
+
return ret;
243
+
244
+
indio_dev->info = &adl8113_info;
245
+
indio_dev->name = "adl8113";
246
+
indio_dev->channels = adl8113_channels;
247
+
indio_dev->num_channels = ARRAY_SIZE(adl8113_channels);
248
+
249
+
return devm_iio_device_register(dev, indio_dev);
250
+
}
251
+
252
+
static const struct of_device_id adl8113_of_match[] = {
253
+
{ .compatible = "adi,adl8113" },
254
+
{ }
255
+
};
256
+
MODULE_DEVICE_TABLE(of, adl8113_of_match);
257
+
258
+
static struct platform_driver adl8113_driver = {
259
+
.driver = {
260
+
.name = "adl8113",
261
+
.of_match_table = adl8113_of_match,
262
+
},
263
+
.probe = adl8113_probe,
264
+
};
265
+
module_platform_driver(adl8113_driver);
266
+
267
+
MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
268
+
MODULE_DESCRIPTION("Analog Devices ADL8113 Low Noise Amplifier");
269
+
MODULE_LICENSE("GPL");
+77
-111
drivers/iio/buffer/industrialio-buffer-dma.c
+77
-111
drivers/iio/buffer/industrialio-buffer-dma.c
···
6
6
7
7
#include <linux/atomic.h>
8
8
#include <linux/cleanup.h>
9
+
#include <linux/lockdep.h>
9
10
#include <linux/slab.h>
10
11
#include <linux/kernel.h>
11
12
#include <linux/module.h>
···
136
135
struct iio_dma_buffer_block *block, *_block;
137
136
LIST_HEAD(block_list);
138
137
139
-
spin_lock_irq(&iio_dma_buffer_dead_blocks_lock);
140
-
list_splice_tail_init(&iio_dma_buffer_dead_blocks, &block_list);
141
-
spin_unlock_irq(&iio_dma_buffer_dead_blocks_lock);
138
+
scoped_guard(spinlock_irq, &iio_dma_buffer_dead_blocks_lock)
139
+
list_splice_tail_init(&iio_dma_buffer_dead_blocks, &block_list);
142
140
143
141
list_for_each_entry_safe(block, _block, &block_list, head)
144
142
iio_buffer_block_release(&block->kref);
···
147
147
static void iio_buffer_block_release_atomic(struct kref *kref)
148
148
{
149
149
struct iio_dma_buffer_block *block;
150
-
unsigned long flags;
151
150
152
151
block = container_of(kref, struct iio_dma_buffer_block, kref);
153
152
154
-
spin_lock_irqsave(&iio_dma_buffer_dead_blocks_lock, flags);
155
-
list_add_tail(&block->head, &iio_dma_buffer_dead_blocks);
156
-
spin_unlock_irqrestore(&iio_dma_buffer_dead_blocks_lock, flags);
153
+
scoped_guard(spinlock_irqsave, &iio_dma_buffer_dead_blocks_lock)
154
+
list_add_tail(&block->head, &iio_dma_buffer_dead_blocks);
157
155
158
156
schedule_work(&iio_dma_buffer_cleanup_work);
159
157
}
···
169
171
return container_of(buf, struct iio_dma_buffer_queue, buffer);
170
172
}
171
173
172
-
static struct iio_dma_buffer_block *iio_dma_buffer_alloc_block(
173
-
struct iio_dma_buffer_queue *queue, size_t size, bool fileio)
174
+
static struct iio_dma_buffer_block *
175
+
iio_dma_buffer_alloc_block(struct iio_dma_buffer_queue *queue, size_t size,
176
+
bool fileio)
174
177
{
175
-
struct iio_dma_buffer_block *block;
176
-
177
-
block = kzalloc(sizeof(*block), GFP_KERNEL);
178
+
struct iio_dma_buffer_block *block __free(kfree) =
179
+
kzalloc(sizeof(*block), GFP_KERNEL);
178
180
if (!block)
179
181
return NULL;
180
182
181
183
if (fileio) {
182
184
block->vaddr = dma_alloc_coherent(queue->dev, PAGE_ALIGN(size),
183
185
&block->phys_addr, GFP_KERNEL);
184
-
if (!block->vaddr) {
185
-
kfree(block);
186
+
if (!block->vaddr)
186
187
return NULL;
187
-
}
188
188
}
189
189
190
190
block->fileio = fileio;
···
197
201
if (!fileio)
198
202
atomic_inc(&queue->num_dmabufs);
199
203
200
-
return block;
204
+
return_ptr(block);
201
205
}
202
206
203
207
static void _iio_dma_buffer_block_done(struct iio_dma_buffer_block *block)
···
228
232
void iio_dma_buffer_block_done(struct iio_dma_buffer_block *block)
229
233
{
230
234
struct iio_dma_buffer_queue *queue = block->queue;
231
-
unsigned long flags;
232
235
bool cookie;
233
236
234
237
cookie = dma_fence_begin_signalling();
235
238
236
-
spin_lock_irqsave(&queue->list_lock, flags);
237
-
_iio_dma_buffer_block_done(block);
238
-
spin_unlock_irqrestore(&queue->list_lock, flags);
239
+
scoped_guard(spinlock_irqsave, &queue->list_lock)
240
+
_iio_dma_buffer_block_done(block);
239
241
240
242
if (!block->fileio)
241
243
iio_buffer_signal_dmabuf_done(block->fence, 0);
···
255
261
* hand the blocks back to the queue.
256
262
*/
257
263
void iio_dma_buffer_block_list_abort(struct iio_dma_buffer_queue *queue,
258
-
struct list_head *list)
264
+
struct list_head *list)
259
265
{
260
266
struct iio_dma_buffer_block *block, *_block;
261
-
unsigned long flags;
262
267
bool cookie;
263
268
264
269
cookie = dma_fence_begin_signalling();
265
270
266
-
spin_lock_irqsave(&queue->list_lock, flags);
267
-
list_for_each_entry_safe(block, _block, list, head) {
268
-
list_del(&block->head);
269
-
block->bytes_used = 0;
270
-
_iio_dma_buffer_block_done(block);
271
+
scoped_guard(spinlock_irqsave, &queue->list_lock) {
272
+
list_for_each_entry_safe(block, _block, list, head) {
273
+
list_del(&block->head);
274
+
block->bytes_used = 0;
275
+
_iio_dma_buffer_block_done(block);
271
276
272
-
if (!block->fileio)
273
-
iio_buffer_signal_dmabuf_done(block->fence, -EINTR);
274
-
iio_buffer_block_put_atomic(block);
277
+
if (!block->fileio)
278
+
iio_buffer_signal_dmabuf_done(block->fence,
279
+
-EINTR);
280
+
iio_buffer_block_put_atomic(block);
281
+
}
275
282
}
276
-
spin_unlock_irqrestore(&queue->list_lock, flags);
277
283
278
284
if (queue->fileio.enabled)
279
285
queue->fileio.enabled = false;
···
322
328
struct iio_dma_buffer_block *block;
323
329
bool try_reuse = false;
324
330
size_t size;
325
-
int ret = 0;
326
331
int i;
327
332
328
333
/*
···
332
339
size = DIV_ROUND_UP(queue->buffer.bytes_per_datum *
333
340
queue->buffer.length, 2);
334
341
335
-
mutex_lock(&queue->lock);
342
+
guard(mutex)(&queue->lock);
336
343
337
344
queue->fileio.enabled = iio_dma_buffer_can_use_fileio(queue);
338
345
339
346
/* If DMABUFs were created, disable fileio interface */
340
347
if (!queue->fileio.enabled)
341
-
goto out_unlock;
348
+
return 0;
342
349
343
350
/* Allocations are page aligned */
344
351
if (PAGE_ALIGN(queue->fileio.block_size) == PAGE_ALIGN(size))
···
347
354
queue->fileio.block_size = size;
348
355
queue->fileio.active_block = NULL;
349
356
350
-
spin_lock_irq(&queue->list_lock);
351
-
for (i = 0; i < ARRAY_SIZE(queue->fileio.blocks); i++) {
352
-
block = queue->fileio.blocks[i];
357
+
scoped_guard(spinlock_irq, &queue->list_lock) {
358
+
for (i = 0; i < ARRAY_SIZE(queue->fileio.blocks); i++) {
359
+
block = queue->fileio.blocks[i];
353
360
354
-
/* If we can't re-use it free it */
355
-
if (block && (!iio_dma_block_reusable(block) || !try_reuse))
356
-
block->state = IIO_BLOCK_STATE_DEAD;
361
+
/* If we can't re-use it free it */
362
+
if (block && (!iio_dma_block_reusable(block) || !try_reuse))
363
+
block->state = IIO_BLOCK_STATE_DEAD;
364
+
}
365
+
366
+
/*
367
+
* At this point all blocks are either owned by the core or
368
+
* marked as dead. This means we can reset the lists without
369
+
* having to fear corruption.
370
+
*/
357
371
}
358
-
359
-
/*
360
-
* At this point all blocks are either owned by the core or marked as
361
-
* dead. This means we can reset the lists without having to fear
362
-
* corrution.
363
-
*/
364
-
spin_unlock_irq(&queue->list_lock);
365
372
366
373
INIT_LIST_HEAD(&queue->incoming);
367
374
···
381
388
382
389
if (!block) {
383
390
block = iio_dma_buffer_alloc_block(queue, size, true);
384
-
if (!block) {
385
-
ret = -ENOMEM;
386
-
goto out_unlock;
387
-
}
391
+
if (!block)
392
+
return -ENOMEM;
393
+
388
394
queue->fileio.blocks[i] = block;
389
395
}
390
396
···
407
415
}
408
416
}
409
417
410
-
out_unlock:
411
-
mutex_unlock(&queue->lock);
412
-
413
-
return ret;
418
+
return 0;
414
419
}
415
420
EXPORT_SYMBOL_NS_GPL(iio_dma_buffer_request_update, "IIO_DMA_BUFFER");
416
421
···
415
426
{
416
427
unsigned int i;
417
428
418
-
spin_lock_irq(&queue->list_lock);
419
-
for (i = 0; i < ARRAY_SIZE(queue->fileio.blocks); i++) {
420
-
if (!queue->fileio.blocks[i])
421
-
continue;
422
-
queue->fileio.blocks[i]->state = IIO_BLOCK_STATE_DEAD;
429
+
scoped_guard(spinlock_irq, &queue->list_lock) {
430
+
for (i = 0; i < ARRAY_SIZE(queue->fileio.blocks); i++) {
431
+
if (!queue->fileio.blocks[i])
432
+
continue;
433
+
queue->fileio.blocks[i]->state = IIO_BLOCK_STATE_DEAD;
434
+
}
423
435
}
424
-
spin_unlock_irq(&queue->list_lock);
425
436
426
437
INIT_LIST_HEAD(&queue->incoming);
427
438
···
435
446
}
436
447
437
448
static void iio_dma_buffer_submit_block(struct iio_dma_buffer_queue *queue,
438
-
struct iio_dma_buffer_block *block)
449
+
struct iio_dma_buffer_block *block)
439
450
{
440
451
int ret;
441
452
···
479
490
*
480
491
* This will allocate the DMA buffers and start the DMA transfers.
481
492
*/
482
-
int iio_dma_buffer_enable(struct iio_buffer *buffer,
483
-
struct iio_dev *indio_dev)
493
+
int iio_dma_buffer_enable(struct iio_buffer *buffer, struct iio_dev *indio_dev)
484
494
{
485
495
struct iio_dma_buffer_queue *queue = iio_buffer_to_queue(buffer);
486
496
struct iio_dma_buffer_block *block, *_block;
487
497
488
-
mutex_lock(&queue->lock);
498
+
guard(mutex)(&queue->lock);
489
499
queue->active = true;
490
500
list_for_each_entry_safe(block, _block, &queue->incoming, head) {
491
501
list_del(&block->head);
492
502
iio_dma_buffer_submit_block(queue, block);
493
503
}
494
-
mutex_unlock(&queue->lock);
495
504
496
505
return 0;
497
506
}
···
503
516
* Needs to be called when the device that the buffer is attached to stops
504
517
* sampling. Typically should be the iio_buffer_access_ops disable callback.
505
518
*/
506
-
int iio_dma_buffer_disable(struct iio_buffer *buffer,
507
-
struct iio_dev *indio_dev)
519
+
int iio_dma_buffer_disable(struct iio_buffer *buffer, struct iio_dev *indio_dev)
508
520
{
509
521
struct iio_dma_buffer_queue *queue = iio_buffer_to_queue(buffer);
510
522
511
-
mutex_lock(&queue->lock);
523
+
guard(mutex)(&queue->lock);
512
524
queue->active = false;
513
525
514
526
if (queue->ops && queue->ops->abort)
515
527
queue->ops->abort(queue);
516
-
mutex_unlock(&queue->lock);
517
528
518
529
return 0;
519
530
}
520
531
EXPORT_SYMBOL_NS_GPL(iio_dma_buffer_disable, "IIO_DMA_BUFFER");
521
532
522
533
static void iio_dma_buffer_enqueue(struct iio_dma_buffer_queue *queue,
523
-
struct iio_dma_buffer_block *block)
534
+
struct iio_dma_buffer_block *block)
524
535
{
525
536
if (block->state == IIO_BLOCK_STATE_DEAD) {
526
537
iio_buffer_block_put(block);
···
530
545
}
531
546
}
532
547
533
-
static struct iio_dma_buffer_block *iio_dma_buffer_dequeue(
534
-
struct iio_dma_buffer_queue *queue)
548
+
static struct iio_dma_buffer_block *
549
+
iio_dma_buffer_dequeue(struct iio_dma_buffer_queue *queue)
535
550
{
536
551
struct iio_dma_buffer_block *block;
537
552
unsigned int idx;
538
553
539
-
spin_lock_irq(&queue->list_lock);
554
+
guard(spinlock_irq)(&queue->list_lock);
540
555
541
556
idx = queue->fileio.next_dequeue;
542
557
block = queue->fileio.blocks[idx];
543
558
544
-
if (block->state == IIO_BLOCK_STATE_DONE) {
545
-
idx = (idx + 1) % ARRAY_SIZE(queue->fileio.blocks);
546
-
queue->fileio.next_dequeue = idx;
547
-
} else {
548
-
block = NULL;
549
-
}
559
+
if (block->state != IIO_BLOCK_STATE_DONE)
560
+
return NULL;
550
561
551
-
spin_unlock_irq(&queue->list_lock);
562
+
idx = (idx + 1) % ARRAY_SIZE(queue->fileio.blocks);
563
+
queue->fileio.next_dequeue = idx;
552
564
553
565
return block;
554
566
}
···
561
579
if (n < buffer->bytes_per_datum)
562
580
return -EINVAL;
563
581
564
-
mutex_lock(&queue->lock);
582
+
guard(mutex)(&queue->lock);
565
583
566
584
if (!queue->fileio.active_block) {
567
585
block = iio_dma_buffer_dequeue(queue);
568
-
if (block == NULL) {
569
-
ret = 0;
570
-
goto out_unlock;
571
-
}
586
+
if (!block)
587
+
return 0;
588
+
572
589
queue->fileio.pos = 0;
573
590
queue->fileio.active_block = block;
574
591
} else {
···
583
602
ret = copy_from_user(addr, user_buffer, n);
584
603
else
585
604
ret = copy_to_user(user_buffer, addr, n);
586
-
if (ret) {
587
-
ret = -EFAULT;
588
-
goto out_unlock;
589
-
}
605
+
if (ret)
606
+
return -EFAULT;
590
607
591
608
queue->fileio.pos += n;
592
609
···
593
614
iio_dma_buffer_enqueue(queue, block);
594
615
}
595
616
596
-
ret = n;
597
-
598
-
out_unlock:
599
-
mutex_unlock(&queue->lock);
600
-
601
-
return ret;
617
+
return n;
602
618
}
603
619
604
620
/**
···
651
677
* but won't increase since all blocks are in use.
652
678
*/
653
679
654
-
mutex_lock(&queue->lock);
680
+
guard(mutex)(&queue->lock);
655
681
if (queue->fileio.active_block)
656
682
data_available += queue->fileio.active_block->size;
657
683
658
-
spin_lock_irq(&queue->list_lock);
684
+
guard(spinlock_irq)(&queue->list_lock);
659
685
660
686
for (i = 0; i < ARRAY_SIZE(queue->fileio.blocks); i++) {
661
687
block = queue->fileio.blocks[i];
662
688
663
-
if (block != queue->fileio.active_block
664
-
&& block->state == IIO_BLOCK_STATE_DONE)
689
+
if (block != queue->fileio.active_block && block->state == IIO_BLOCK_STATE_DONE)
665
690
data_available += block->size;
666
691
}
667
-
668
-
spin_unlock_irq(&queue->list_lock);
669
-
mutex_unlock(&queue->lock);
670
692
671
693
return data_available;
672
694
}
···
734
764
bool cookie;
735
765
int ret;
736
766
737
-
WARN_ON(!mutex_is_locked(&queue->lock));
767
+
lockdep_assert_held(&queue->lock);
738
768
739
769
cookie = dma_fence_begin_signalling();
740
770
···
824
854
* should refer to the device that will perform the DMA to ensure that
825
855
* allocations are done from a memory region that can be accessed by the device.
826
856
*/
827
-
int iio_dma_buffer_init(struct iio_dma_buffer_queue *queue,
828
-
struct device *dev, const struct iio_dma_buffer_ops *ops)
857
+
void iio_dma_buffer_init(struct iio_dma_buffer_queue *queue, struct device *dev,
858
+
const struct iio_dma_buffer_ops *ops)
829
859
{
830
860
iio_buffer_init(&queue->buffer);
831
861
queue->buffer.length = PAGE_SIZE;
···
837
867
838
868
mutex_init(&queue->lock);
839
869
spin_lock_init(&queue->list_lock);
840
-
841
-
return 0;
842
870
}
843
871
EXPORT_SYMBOL_NS_GPL(iio_dma_buffer_init, "IIO_DMA_BUFFER");
844
872
···
849
881
*/
850
882
void iio_dma_buffer_exit(struct iio_dma_buffer_queue *queue)
851
883
{
852
-
mutex_lock(&queue->lock);
884
+
guard(mutex)(&queue->lock);
853
885
854
886
iio_dma_buffer_fileio_free(queue);
855
887
queue->ops = NULL;
856
-
857
-
mutex_unlock(&queue->lock);
858
888
}
859
889
EXPORT_SYMBOL_NS_GPL(iio_dma_buffer_exit, "IIO_DMA_BUFFER");
860
890
+10
-13
drivers/iio/buffer/industrialio-buffer-dmaengine.c
+10
-13
drivers/iio/buffer/industrialio-buffer-dmaengine.c
···
6
6
7
7
#include <linux/slab.h>
8
8
#include <linux/kernel.h>
9
+
#include <linux/cleanup.h>
9
10
#include <linux/dmaengine.h>
10
11
#include <linux/dma-mapping.h>
11
12
#include <linux/spinlock.h>
···
40
39
size_t max_size;
41
40
};
42
41
43
-
static struct dmaengine_buffer *iio_buffer_to_dmaengine_buffer(
44
-
struct iio_buffer *buffer)
42
+
static struct dmaengine_buffer *iio_buffer_to_dmaengine_buffer(struct iio_buffer *buffer)
45
43
{
46
44
return container_of(buffer, struct dmaengine_buffer, queue.buffer);
47
45
}
48
46
49
47
static void iio_dmaengine_buffer_block_done(void *data,
50
-
const struct dmaengine_result *result)
48
+
const struct dmaengine_result *result)
51
49
{
52
50
struct iio_dma_buffer_block *block = data;
53
-
unsigned long flags;
54
51
55
-
spin_lock_irqsave(&block->queue->list_lock, flags);
56
-
list_del(&block->head);
57
-
spin_unlock_irqrestore(&block->queue->list_lock, flags);
52
+
scoped_guard(spinlock_irqsave, &block->queue->list_lock)
53
+
list_del(&block->head);
58
54
block->bytes_used -= result->residue;
59
55
iio_dma_buffer_block_done(block);
60
56
}
61
57
62
58
static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue,
63
-
struct iio_dma_buffer_block *block)
59
+
struct iio_dma_buffer_block *block)
64
60
{
65
61
struct dmaengine_buffer *dmaengine_buffer =
66
62
iio_buffer_to_dmaengine_buffer(&queue->buffer);
···
129
131
if (dma_submit_error(cookie))
130
132
return dma_submit_error(cookie);
131
133
132
-
spin_lock_irq(&dmaengine_buffer->queue.list_lock);
133
-
list_add_tail(&block->head, &dmaengine_buffer->active);
134
-
spin_unlock_irq(&dmaengine_buffer->queue.list_lock);
134
+
scoped_guard(spinlock_irq, &dmaengine_buffer->queue.list_lock)
135
+
list_add_tail(&block->head, &dmaengine_buffer->active);
135
136
136
137
dma_async_issue_pending(dmaengine_buffer->chan);
137
138
···
186
189
};
187
190
188
191
static ssize_t iio_dmaengine_buffer_get_length_align(struct device *dev,
189
-
struct device_attribute *attr, char *buf)
192
+
struct device_attribute *attr, char *buf)
190
193
{
191
194
struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer;
192
195
struct dmaengine_buffer *dmaengine_buffer =
···
245
248
dmaengine_buffer->max_size = dma_get_max_seg_size(chan->device->dev);
246
249
247
250
iio_dma_buffer_init(&dmaengine_buffer->queue, chan->device->dev,
248
-
&iio_dmaengine_default_ops);
251
+
&iio_dmaengine_default_ops);
249
252
250
253
dmaengine_buffer->queue.buffer.attrs = iio_dmaengine_buffer_attrs;
251
254
dmaengine_buffer->queue.buffer.access = &iio_dmaengine_buffer_ops;
+3
-6
drivers/iio/chemical/ens160_core.c
+3
-6
drivers/iio/chemical/ens160_core.c
···
316
316
317
317
indio_dev->trig = iio_trigger_get(trig);
318
318
319
-
ret = devm_request_threaded_irq(dev, irq,
320
-
iio_trigger_generic_data_rdy_poll,
321
-
NULL,
322
-
IRQF_ONESHOT,
323
-
indio_dev->name,
324
-
indio_dev->trig);
319
+
ret = devm_request_irq(dev, irq, iio_trigger_generic_data_rdy_poll,
320
+
IRQF_NO_THREAD, indio_dev->name,
321
+
indio_dev->trig);
325
322
if (ret)
326
323
return dev_err_probe(dev, ret, "failed to request irq\n");
327
324
+3
drivers/iio/chemical/scd4x.c
+3
drivers/iio/chemical/scd4x.c
···
59
59
SCD4X_CO2,
60
60
SCD4X_TEMP,
61
61
SCD4X_HR,
62
+
/* kernel timestamp, at the end of buffer */
63
+
SCD4X_TS,
62
64
};
63
65
64
66
struct scd4x_state {
···
617
615
.endianness = IIO_CPU,
618
616
},
619
617
},
618
+
IIO_CHAN_SOFT_TIMESTAMP(SCD4X_TS),
620
619
};
621
620
622
621
static int scd4x_suspend(struct device *dev)
+4
-7
drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c
+4
-7
drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c
···
188
188
/*
189
189
* Ignore samples if the buffer is not set: it is needed if the ODR is
190
190
* set but the buffer is not enabled yet.
191
-
*
192
-
* Note: iio_device_claim_buffer_mode() returns -EBUSY if the buffer
193
-
* is not enabled.
194
191
*/
195
-
if (iio_device_claim_buffer_mode(indio_dev) < 0)
192
+
if (!iio_device_try_claim_buffer_mode(indio_dev))
196
193
return 0;
197
194
198
195
out = (s16 *)st->samples;
···
441
444
ret = kstrtobool(buf, &calibrate);
442
445
if (ret < 0)
443
446
return ret;
444
-
if (!calibrate)
445
-
return -EINVAL;
446
447
447
448
mutex_lock(&st->cmd_lock);
448
449
st->param.cmd = MOTIONSENSE_CMD_PERFORM_CALIB;
450
+
st->param.perform_calib.enable = calibrate;
449
451
ret = cros_ec_motion_send_host_cmd(st, 0);
450
452
if (ret != 0) {
451
-
dev_warn(&indio_dev->dev, "Unable to calibrate sensor\n");
453
+
dev_warn(&indio_dev->dev, "Unable to calibrate sensor: %d\n",
454
+
ret);
452
455
} else {
453
456
/* Save values */
454
457
for (i = CROS_EC_SENSOR_X; i < CROS_EC_SENSOR_MAX_AXIS; i++)
+33
drivers/iio/dac/Kconfig
+33
drivers/iio/dac/Kconfig
···
482
482
This driver can also be built as a module. If so, the module
483
483
will be called max517.
484
484
485
+
config MAX22007
486
+
tristate "Analog Devices MAX22007 DAC Driver"
487
+
depends on SPI
488
+
select REGMAP_SPI
489
+
select CRC8
490
+
help
491
+
Say Y here if you want to build a driver for Analog Devices MAX22007.
492
+
493
+
MAX22007 is a quad-channel, 12-bit, voltage-output digital to
494
+
analog converter (DAC) with SPI interface.
495
+
496
+
If compiled as a module, it will be called max22007.
497
+
485
498
config MAX5522
486
499
tristate "Maxim MAX5522 DAC driver"
487
500
depends on SPI_MASTER
···
536
523
537
524
To compile this driver as a module, choose M here: the module
538
525
will be called mcp4728.
526
+
527
+
config MCP47FEB02
528
+
tristate "MCP47F(E/V)B01/02/04/08/11/12/14/18/21/22/24/28 DAC driver"
529
+
depends on I2C
530
+
help
531
+
Say yes here if you want to build the driver for the Microchip:
532
+
- 8-bit DAC:
533
+
MCP47FEB01, MCP47FEB02, MCP47FEB04, MCP47FEB08,
534
+
MCP47FVB01, MCP47FVB02, MCP47FVB04, MCP47FVB08
535
+
- 10-bit DAC:
536
+
MCP47FEB11, MCP47FEB12, MCP47FEB14, MCP47FEB18,
537
+
MCP47FVB11, MCP47FVB12, MCP47FVB14, MCP47FVB18
538
+
- 12-bit DAC:
539
+
MCP47FEB21, MCP47FEB22, MCP47FEB24, MCP47FEB28,
540
+
MCP47FVB21, MCP47FVB22, MCP47FVB24, MCP47FVB28
541
+
having 1 to 8 channels, 8/10/12-bit digital-to-analog converter
542
+
(DAC) with I2C interface.
543
+
544
+
To compile this driver as a module, choose M here: the module
545
+
will be called mcp47feb02.
539
546
540
547
config MCP4821
541
548
tristate "MCP4801/02/11/12/21/22 DAC driver"
+2
drivers/iio/dac/Makefile
+2
drivers/iio/dac/Makefile
···
48
48
obj-$(CONFIG_LTC2688) += ltc2688.o
49
49
obj-$(CONFIG_M62332) += m62332.o
50
50
obj-$(CONFIG_MAX517) += max517.o
51
+
obj-$(CONFIG_MAX22007) += max22007.o
51
52
obj-$(CONFIG_MAX5522) += max5522.o
52
53
obj-$(CONFIG_MAX5821) += max5821.o
53
54
obj-$(CONFIG_MCP4725) += mcp4725.o
54
55
obj-$(CONFIG_MCP4728) += mcp4728.o
56
+
obj-$(CONFIG_MCP47FEB02) += mcp47feb02.o
55
57
obj-$(CONFIG_MCP4821) += mcp4821.o
56
58
obj-$(CONFIG_MCP4922) += mcp4922.o
57
59
obj-$(CONFIG_STM32_DAC_CORE) += stm32-dac-core.o
+31
-35
drivers/iio/dac/adi-axi-dac.c
+31
-35
drivers/iio/dac/adi-axi-dac.c
···
885
885
886
886
static int axi_dac_probe(struct platform_device *pdev)
887
887
{
888
+
struct device *dev = &pdev->dev;
888
889
struct axi_dac_state *st;
889
890
void __iomem *base;
890
891
unsigned int ver;
891
892
struct clk *clk;
892
893
int ret;
893
894
894
-
st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
895
+
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
895
896
if (!st)
896
897
return -ENOMEM;
897
898
898
-
st->info = device_get_match_data(&pdev->dev);
899
+
st->info = device_get_match_data(dev);
899
900
if (!st->info)
900
901
return -ENODEV;
901
-
clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
902
+
clk = devm_clk_get_enabled(dev, "s_axi_aclk");
902
903
if (IS_ERR(clk)) {
903
904
/* Backward compat., old fdt versions without clock-names. */
904
-
clk = devm_clk_get_enabled(&pdev->dev, NULL);
905
+
clk = devm_clk_get_enabled(dev, NULL);
905
906
if (IS_ERR(clk))
906
-
return dev_err_probe(&pdev->dev, PTR_ERR(clk),
907
-
"failed to get clock\n");
907
+
return dev_err_probe(dev, PTR_ERR(clk),
908
+
"failed to get clock\n");
908
909
}
909
910
910
911
if (st->info->has_dac_clk) {
911
912
struct clk *dac_clk;
912
913
913
-
dac_clk = devm_clk_get_enabled(&pdev->dev, "dac_clk");
914
+
dac_clk = devm_clk_get_enabled(dev, "dac_clk");
914
915
if (IS_ERR(dac_clk))
915
-
return dev_err_probe(&pdev->dev, PTR_ERR(dac_clk),
916
+
return dev_err_probe(dev, PTR_ERR(dac_clk),
916
917
"failed to get dac_clk clock\n");
917
918
918
919
/* We only care about the streaming mode rate */
···
924
923
if (IS_ERR(base))
925
924
return PTR_ERR(base);
926
925
927
-
st->dev = &pdev->dev;
928
-
st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
929
-
&axi_dac_regmap_config);
926
+
st->dev = dev;
927
+
st->regmap = devm_regmap_init_mmio(dev, base, &axi_dac_regmap_config);
930
928
if (IS_ERR(st->regmap))
931
-
return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap),
929
+
return dev_err_probe(dev, PTR_ERR(st->regmap),
932
930
"failed to init register map\n");
933
931
934
932
/*
···
942
942
if (ret)
943
943
return ret;
944
944
945
-
if (ADI_AXI_PCORE_VER_MAJOR(ver) !=
946
-
ADI_AXI_PCORE_VER_MAJOR(st->info->version)) {
947
-
dev_err(&pdev->dev,
948
-
"Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
949
-
ADI_AXI_PCORE_VER_MAJOR(st->info->version),
950
-
ADI_AXI_PCORE_VER_MINOR(st->info->version),
951
-
ADI_AXI_PCORE_VER_PATCH(st->info->version),
952
-
ADI_AXI_PCORE_VER_MAJOR(ver),
953
-
ADI_AXI_PCORE_VER_MINOR(ver),
954
-
ADI_AXI_PCORE_VER_PATCH(ver));
955
-
return -ENODEV;
956
-
}
945
+
if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(st->info->version))
946
+
return dev_err_probe(dev, -ENODEV,
947
+
"Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
948
+
ADI_AXI_PCORE_VER_MAJOR(st->info->version),
949
+
ADI_AXI_PCORE_VER_MINOR(st->info->version),
950
+
ADI_AXI_PCORE_VER_PATCH(st->info->version),
951
+
ADI_AXI_PCORE_VER_MAJOR(ver),
952
+
ADI_AXI_PCORE_VER_MINOR(ver),
953
+
ADI_AXI_PCORE_VER_PATCH(ver));
957
954
958
955
/* Let's get the core read only configuration */
959
956
ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config);
···
972
975
973
976
mutex_init(&st->lock);
974
977
975
-
ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st);
978
+
ret = devm_iio_backend_register(dev, st->info->backend_info, st);
976
979
if (ret)
977
-
return dev_err_probe(&pdev->dev, ret,
980
+
return dev_err_probe(dev, ret,
978
981
"failed to register iio backend\n");
979
982
980
-
device_for_each_child_node_scoped(&pdev->dev, child) {
983
+
device_for_each_child_node_scoped(dev, child) {
981
984
int val;
982
985
983
986
if (!st->info->has_child_nodes)
984
-
return dev_err_probe(&pdev->dev, -EINVAL,
987
+
return dev_err_probe(dev, -EINVAL,
985
988
"invalid fdt axi-dac compatible.");
986
989
987
990
/* Processing only reg 0 node */
988
991
ret = fwnode_property_read_u32(child, "reg", &val);
989
992
if (ret)
990
-
return dev_err_probe(&pdev->dev, ret,
991
-
"invalid reg property.");
993
+
return dev_err_probe(dev, ret, "invalid reg property.");
992
994
if (val != 0)
993
-
return dev_err_probe(&pdev->dev, -EINVAL,
994
-
"invalid node address.");
995
+
return dev_err_probe(dev, -EINVAL,
996
+
"invalid node address.");
995
997
996
998
ret = axi_dac_create_platform_device(st, child);
997
999
if (ret)
998
-
return dev_err_probe(&pdev->dev, -EINVAL,
999
-
"cannot create device.");
1000
+
return dev_err_probe(dev, -EINVAL,
1001
+
"cannot create device.");
1000
1002
}
1001
1003
1002
-
dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n",
1004
+
dev_info(dev, "AXI DAC IP core (%d.%.2d.%c) probed\n",
1003
1005
ADI_AXI_PCORE_VER_MAJOR(ver),
1004
1006
ADI_AXI_PCORE_VER_MINOR(ver),
1005
1007
ADI_AXI_PCORE_VER_PATCH(ver));
-1
drivers/iio/dac/ds4424.c
-1
drivers/iio/dac/ds4424.c
+491
drivers/iio/dac/max22007.c
+491
drivers/iio/dac/max22007.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* max22007.c - MAX22007 DAC driver
4
+
*
5
+
* Driver for Analog Devices MAX22007 Digital to Analog Converter.
6
+
*
7
+
* Copyright (c) 2026 Analog Devices Inc.
8
+
*/
9
+
10
+
#include <linux/bitfield.h>
11
+
#include <linux/bits.h>
12
+
#include <linux/crc8.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/dev_printk.h>
15
+
#include <linux/device/devres.h>
16
+
#include <linux/err.h>
17
+
#include <linux/errno.h>
18
+
#include <linux/gpio/consumer.h>
19
+
#include <linux/iio/iio.h>
20
+
#include <linux/kstrtox.h>
21
+
#include <linux/minmax.h>
22
+
#include <linux/mod_devicetable.h>
23
+
#include <linux/module.h>
24
+
#include <linux/property.h>
25
+
#include <linux/regmap.h>
26
+
#include <linux/regulator/consumer.h>
27
+
#include <linux/slab.h>
28
+
#include <linux/spi/spi.h>
29
+
#include <linux/string.h>
30
+
#include <linux/sysfs.h>
31
+
#include <linux/types.h>
32
+
33
+
#include <dt-bindings/iio/addac/adi,ad74413r.h>
34
+
struct device;
35
+
36
+
#define MAX22007_NUM_CHANNELS 4
37
+
#define MAX22007_REV_ID_REG 0x00
38
+
#define MAX22007_STAT_INTR_REG 0x01
39
+
#define MAX22007_INTERRUPT_EN_REG 0x02
40
+
#define MAX22007_CONFIG_REG 0x03
41
+
#define MAX22007_CONTROL_REG 0x04
42
+
#define MAX22007_CHANNEL_MODE_REG 0x05
43
+
#define MAX22007_SOFT_RESET_REG 0x06
44
+
#define MAX22007_DAC_CHANNEL_REG(ch) (0x07 + (ch))
45
+
#define MAX22007_GPIO_CTRL_REG 0x0B
46
+
#define MAX22007_GPIO_DATA_REG 0x0C
47
+
#define MAX22007_GPI_EDGE_INT_CTRL_REG 0x0D
48
+
#define MAX22007_GPI_INT_STATUS_REG 0x0E
49
+
50
+
/* Channel mask definitions */
51
+
#define MAX22007_CH_MODE_CH_MASK(ch) BIT(12 + (ch))
52
+
#define MAX22007_CH_PWRON_CH_MASK(ch) BIT(8 + (ch))
53
+
#define MAX22007_DAC_LATCH_MODE_MASK(ch) BIT(12 + (ch))
54
+
#define MAX22007_LDAC_UPDATE_MASK(ch) BIT(12 + (ch))
55
+
#define MAX22007_SW_RST_MASK BIT(8)
56
+
#define MAX22007_SW_CLR_MASK BIT(12)
57
+
#define MAX22007_SOFT_RESET_BITS_MASK (MAX22007_SW_RST_MASK | \
58
+
MAX22007_SW_CLR_MASK)
59
+
#define MAX22007_DAC_DATA_MASK GENMASK(15, 4)
60
+
#define MAX22007_DAC_MAX_RAW GENMASK(11, 0)
61
+
#define MAX22007_CRC8_POLYNOMIAL 0x8C
62
+
#define MAX22007_CRC_EN_MASK BIT(0)
63
+
#define MAX22007_RW_MASK BIT(0)
64
+
#define MAX22007_CRC_OVERHEAD 1
65
+
#define MAX22007_NUM_SUPPLIES 3
66
+
#define MAX22007_REF_MV 2500
67
+
68
+
/* Field value preparation macros with masking */
69
+
#define MAX22007_CH_PWR_VAL(ch, val) (((val) & 0x1) << (8 + (ch)))
70
+
#define MAX22007_CH_MODE_VAL(ch, val) (((val) & 0x1) << (12 + (ch)))
71
+
#define MAX22007_DAC_LATCH_MODE_VAL(ch, val) (((val) & 0x1) << (12 + (ch)))
72
+
73
+
static u8 max22007_crc8_table[CRC8_TABLE_SIZE];
74
+
75
+
static const char * const max22007_supply_names[MAX22007_NUM_SUPPLIES] = {
76
+
"vdd",
77
+
"hvdd",
78
+
"hvss",
79
+
};
80
+
81
+
struct max22007_state {
82
+
struct spi_device *spi;
83
+
struct regmap *regmap;
84
+
struct iio_chan_spec *iio_chans;
85
+
u8 tx_buf[4] __aligned(IIO_DMA_MINALIGN);
86
+
u8 rx_buf[4];
87
+
};
88
+
89
+
static int max22007_spi_read(void *context, const void *reg, size_t reg_size,
90
+
void *val, size_t val_size)
91
+
{
92
+
struct max22007_state *st = context;
93
+
u8 calculated_crc, received_crc;
94
+
u8 rx_buf[4];
95
+
u8 reg_byte;
96
+
int ret;
97
+
98
+
if (reg_size != 1)
99
+
return -EINVAL;
100
+
101
+
if (val_size == 0 || val_size > 3)
102
+
return -EINVAL;
103
+
104
+
memcpy(®_byte, reg, 1);
105
+
106
+
ret = spi_write_then_read(st->spi, ®_byte, 1, rx_buf,
107
+
val_size + MAX22007_CRC_OVERHEAD);
108
+
if (ret) {
109
+
dev_err(&st->spi->dev, "SPI transfer failed: %d\n", ret);
110
+
return ret;
111
+
}
112
+
113
+
calculated_crc = crc8(max22007_crc8_table, ®_byte, 1, 0x00);
114
+
calculated_crc = crc8(max22007_crc8_table, rx_buf, 2, calculated_crc);
115
+
received_crc = rx_buf[val_size];
116
+
117
+
if (calculated_crc != received_crc) {
118
+
dev_err(&st->spi->dev, "CRC mismatch on read register %02x\n", reg_byte);
119
+
return -EIO;
120
+
}
121
+
122
+
memcpy(val, rx_buf, val_size);
123
+
124
+
return 0;
125
+
}
126
+
127
+
static int max22007_spi_write(void *context, const void *data, size_t count)
128
+
{
129
+
struct max22007_state *st = context;
130
+
struct spi_transfer xfer = {
131
+
.tx_buf = st->tx_buf,
132
+
.rx_buf = st->rx_buf,
133
+
};
134
+
135
+
if (count + MAX22007_CRC_OVERHEAD > sizeof(st->tx_buf))
136
+
return -EINVAL;
137
+
138
+
memset(st->tx_buf, 0, sizeof(st->tx_buf));
139
+
140
+
xfer.len = count + MAX22007_CRC_OVERHEAD;
141
+
142
+
memcpy(st->tx_buf, data, count);
143
+
st->tx_buf[count] = crc8(max22007_crc8_table, st->tx_buf,
144
+
sizeof(st->tx_buf) - 1, 0x00);
145
+
146
+
return spi_sync_transfer(st->spi, &xfer, 1);
147
+
}
148
+
149
+
static bool max22007_reg_readable(struct device *dev, unsigned int reg)
150
+
{
151
+
switch (reg) {
152
+
case MAX22007_REV_ID_REG:
153
+
case MAX22007_STAT_INTR_REG:
154
+
case MAX22007_CONFIG_REG:
155
+
case MAX22007_CONTROL_REG:
156
+
case MAX22007_CHANNEL_MODE_REG:
157
+
case MAX22007_SOFT_RESET_REG:
158
+
case MAX22007_GPIO_CTRL_REG:
159
+
case MAX22007_GPIO_DATA_REG:
160
+
case MAX22007_GPI_EDGE_INT_CTRL_REG:
161
+
case MAX22007_GPI_INT_STATUS_REG:
162
+
return true;
163
+
case MAX22007_DAC_CHANNEL_REG(0) ... MAX22007_DAC_CHANNEL_REG(MAX22007_NUM_CHANNELS - 1):
164
+
return true;
165
+
default:
166
+
return false;
167
+
}
168
+
}
169
+
170
+
static bool max22007_reg_writable(struct device *dev, unsigned int reg)
171
+
{
172
+
switch (reg) {
173
+
case MAX22007_CONFIG_REG:
174
+
case MAX22007_CONTROL_REG:
175
+
case MAX22007_CHANNEL_MODE_REG:
176
+
case MAX22007_SOFT_RESET_REG:
177
+
case MAX22007_GPIO_CTRL_REG:
178
+
case MAX22007_GPIO_DATA_REG:
179
+
case MAX22007_GPI_EDGE_INT_CTRL_REG:
180
+
return true;
181
+
case MAX22007_DAC_CHANNEL_REG(0) ... MAX22007_DAC_CHANNEL_REG(MAX22007_NUM_CHANNELS - 1):
182
+
return true;
183
+
default:
184
+
return false;
185
+
}
186
+
}
187
+
188
+
static const struct regmap_bus max22007_regmap_bus = {
189
+
.read = max22007_spi_read,
190
+
.write = max22007_spi_write,
191
+
.read_flag_mask = MAX22007_RW_MASK,
192
+
.reg_format_endian_default = REGMAP_ENDIAN_BIG,
193
+
.val_format_endian_default = REGMAP_ENDIAN_BIG,
194
+
};
195
+
196
+
static const struct regmap_config max22007_regmap_config = {
197
+
.reg_bits = 8,
198
+
.val_bits = 16,
199
+
.reg_shift = -1,
200
+
.readable_reg = max22007_reg_readable,
201
+
.writeable_reg = max22007_reg_writable,
202
+
.max_register = 0x0E,
203
+
};
204
+
205
+
static int max22007_write_channel_data(struct max22007_state *st,
206
+
unsigned int channel, int data)
207
+
{
208
+
unsigned int reg_val;
209
+
210
+
if (data < 0 || data > MAX22007_DAC_MAX_RAW)
211
+
return -EINVAL;
212
+
213
+
reg_val = FIELD_PREP(MAX22007_DAC_DATA_MASK, data);
214
+
215
+
return regmap_write(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), reg_val);
216
+
}
217
+
218
+
static int max22007_read_channel_data(struct max22007_state *st,
219
+
unsigned int channel, int *data)
220
+
{
221
+
unsigned int reg_val;
222
+
int ret;
223
+
224
+
ret = regmap_read(st->regmap, MAX22007_DAC_CHANNEL_REG(channel), ®_val);
225
+
if (ret)
226
+
return ret;
227
+
228
+
*data = FIELD_GET(MAX22007_DAC_DATA_MASK, reg_val);
229
+
230
+
return 0;
231
+
}
232
+
233
+
static int max22007_read_raw(struct iio_dev *indio_dev,
234
+
struct iio_chan_spec const *chan,
235
+
int *val, int *val2, long mask)
236
+
{
237
+
struct max22007_state *st = iio_priv(indio_dev);
238
+
int ret;
239
+
240
+
switch (mask) {
241
+
case IIO_CHAN_INFO_RAW:
242
+
ret = max22007_read_channel_data(st, chan->channel, val);
243
+
if (ret)
244
+
return ret;
245
+
return IIO_VAL_INT;
246
+
case IIO_CHAN_INFO_SCALE:
247
+
if (chan->type == IIO_VOLTAGE)
248
+
*val = 5 * MAX22007_REF_MV; /* 5 * Vref in mV */
249
+
else
250
+
*val = 25; /* Vref / (2 * Rsense) = MAX22007_REF_MV / 100 */
251
+
*val2 = 12; /* 12-bit DAC resolution */
252
+
return IIO_VAL_FRACTIONAL_LOG2;
253
+
default:
254
+
return -EINVAL;
255
+
}
256
+
}
257
+
258
+
static int max22007_write_raw(struct iio_dev *indio_dev,
259
+
struct iio_chan_spec const *chan,
260
+
int val, int val2, long mask)
261
+
{
262
+
struct max22007_state *st = iio_priv(indio_dev);
263
+
264
+
switch (mask) {
265
+
case IIO_CHAN_INFO_RAW:
266
+
return max22007_write_channel_data(st, chan->channel, val);
267
+
default:
268
+
return -EINVAL;
269
+
}
270
+
}
271
+
272
+
static const struct iio_info max22007_info = {
273
+
.read_raw = max22007_read_raw,
274
+
.write_raw = max22007_write_raw,
275
+
};
276
+
277
+
static ssize_t max22007_read_dac_powerdown(struct iio_dev *indio_dev,
278
+
uintptr_t private,
279
+
const struct iio_chan_spec *chan,
280
+
char *buf)
281
+
{
282
+
struct max22007_state *st = iio_priv(indio_dev);
283
+
unsigned int reg_val;
284
+
bool powerdown;
285
+
int ret;
286
+
287
+
ret = regmap_read(st->regmap, MAX22007_CHANNEL_MODE_REG, ®_val);
288
+
if (ret)
289
+
return ret;
290
+
291
+
powerdown = !(reg_val & MAX22007_CH_PWRON_CH_MASK(chan->channel));
292
+
293
+
return sysfs_emit(buf, "%d\n", powerdown);
294
+
}
295
+
296
+
static ssize_t max22007_write_dac_powerdown(struct iio_dev *indio_dev,
297
+
uintptr_t private,
298
+
const struct iio_chan_spec *chan,
299
+
const char *buf, size_t len)
300
+
{
301
+
struct max22007_state *st = iio_priv(indio_dev);
302
+
bool powerdown;
303
+
int ret;
304
+
305
+
ret = kstrtobool(buf, &powerdown);
306
+
if (ret)
307
+
return ret;
308
+
309
+
ret = regmap_update_bits(st->regmap, MAX22007_CHANNEL_MODE_REG,
310
+
MAX22007_CH_PWRON_CH_MASK(chan->channel),
311
+
MAX22007_CH_PWR_VAL(chan->channel, powerdown ? 0 : 1));
312
+
if (ret)
313
+
return ret;
314
+
315
+
return len;
316
+
}
317
+
318
+
static const struct iio_chan_spec_ext_info max22007_ext_info[] = {
319
+
{
320
+
.name = "powerdown",
321
+
.read = max22007_read_dac_powerdown,
322
+
.write = max22007_write_dac_powerdown,
323
+
.shared = IIO_SEPARATE,
324
+
},
325
+
{ }
326
+
};
327
+
328
+
static int max22007_parse_channel_cfg(struct max22007_state *st, u8 *num_channels)
329
+
{
330
+
struct device *dev = &st->spi->dev;
331
+
int ret, num_chan;
332
+
int i = 0;
333
+
u32 reg;
334
+
335
+
num_chan = device_get_child_node_count(dev);
336
+
if (!num_chan)
337
+
return dev_err_probe(dev, -ENODEV, "no channels configured\n");
338
+
339
+
st->iio_chans = devm_kcalloc(dev, num_chan, sizeof(*st->iio_chans), GFP_KERNEL);
340
+
if (!st->iio_chans)
341
+
return -ENOMEM;
342
+
343
+
device_for_each_child_node_scoped(dev, child) {
344
+
u32 ch_func;
345
+
enum iio_chan_type chan_type;
346
+
347
+
ret = fwnode_property_read_u32(child, "reg", ®);
348
+
if (ret)
349
+
return dev_err_probe(dev, ret,
350
+
"failed to read reg property of %pfwP\n", child);
351
+
352
+
if (reg >= MAX22007_NUM_CHANNELS)
353
+
return dev_err_probe(dev, -EINVAL,
354
+
"reg out of range in %pfwP\n", child);
355
+
356
+
ret = fwnode_property_read_u32(child, "adi,ch-func", &ch_func);
357
+
if (ret)
358
+
return dev_err_probe(dev, ret,
359
+
"missing adi,ch-func property for %pfwP\n", child);
360
+
361
+
switch (ch_func) {
362
+
case CH_FUNC_VOLTAGE_OUTPUT:
363
+
chan_type = IIO_VOLTAGE;
364
+
break;
365
+
case CH_FUNC_CURRENT_OUTPUT:
366
+
chan_type = IIO_CURRENT;
367
+
break;
368
+
default:
369
+
return dev_err_probe(dev, -EINVAL,
370
+
"invalid adi,ch-func %u for %pfwP\n",
371
+
ch_func, child);
372
+
}
373
+
374
+
st->iio_chans[i++] = (struct iio_chan_spec) {
375
+
.output = 1,
376
+
.indexed = 1,
377
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
378
+
BIT(IIO_CHAN_INFO_SCALE),
379
+
.ext_info = max22007_ext_info,
380
+
.channel = reg,
381
+
.type = chan_type,
382
+
};
383
+
384
+
ret = regmap_update_bits(st->regmap, MAX22007_CHANNEL_MODE_REG,
385
+
MAX22007_CH_MODE_CH_MASK(reg),
386
+
MAX22007_CH_MODE_VAL(reg, ch_func - 1));
387
+
if (ret)
388
+
return ret;
389
+
390
+
/* Set DAC to transparent mode (immediate update) */
391
+
ret = regmap_update_bits(st->regmap, MAX22007_CONFIG_REG,
392
+
MAX22007_DAC_LATCH_MODE_MASK(reg),
393
+
MAX22007_DAC_LATCH_MODE_VAL(reg, 1));
394
+
if (ret)
395
+
return ret;
396
+
}
397
+
398
+
*num_channels = num_chan;
399
+
400
+
return 0;
401
+
}
402
+
403
+
static int max22007_probe(struct spi_device *spi)
404
+
{
405
+
struct device *dev = &spi->dev;
406
+
struct gpio_desc *reset_gpio;
407
+
struct max22007_state *st;
408
+
struct iio_dev *indio_dev;
409
+
u8 num_channels;
410
+
int ret;
411
+
412
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
413
+
if (!indio_dev)
414
+
return -ENOMEM;
415
+
416
+
st = iio_priv(indio_dev);
417
+
st->spi = spi;
418
+
419
+
crc8_populate_lsb(max22007_crc8_table, MAX22007_CRC8_POLYNOMIAL);
420
+
421
+
st->regmap = devm_regmap_init(dev, &max22007_regmap_bus, st,
422
+
&max22007_regmap_config);
423
+
if (IS_ERR(st->regmap))
424
+
return dev_err_probe(dev, PTR_ERR(st->regmap),
425
+
"Failed to initialize regmap\n");
426
+
427
+
ret = devm_regulator_bulk_get_enable(dev, MAX22007_NUM_SUPPLIES,
428
+
max22007_supply_names);
429
+
if (ret)
430
+
return dev_err_probe(dev, ret, "Failed to get and enable regulators\n");
431
+
432
+
reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
433
+
if (IS_ERR(reset_gpio))
434
+
return dev_err_probe(dev, PTR_ERR(reset_gpio),
435
+
"Failed to get reset GPIO\n");
436
+
437
+
if (reset_gpio) {
438
+
gpiod_set_value_cansleep(reset_gpio, 1);
439
+
usleep_range(1000, 5000);
440
+
gpiod_set_value_cansleep(reset_gpio, 0);
441
+
usleep_range(1000, 5000);
442
+
} else {
443
+
ret = regmap_write(st->regmap, MAX22007_SOFT_RESET_REG,
444
+
MAX22007_SOFT_RESET_BITS_MASK);
445
+
if (ret)
446
+
return ret;
447
+
}
448
+
449
+
ret = regmap_set_bits(st->regmap, MAX22007_CONFIG_REG,
450
+
MAX22007_CRC_EN_MASK);
451
+
if (ret)
452
+
return ret;
453
+
454
+
ret = max22007_parse_channel_cfg(st, &num_channels);
455
+
if (ret)
456
+
return ret;
457
+
458
+
indio_dev->info = &max22007_info;
459
+
indio_dev->modes = INDIO_DIRECT_MODE;
460
+
indio_dev->channels = st->iio_chans;
461
+
indio_dev->num_channels = num_channels;
462
+
indio_dev->name = "max22007";
463
+
464
+
return devm_iio_device_register(dev, indio_dev);
465
+
}
466
+
467
+
static const struct spi_device_id max22007_id[] = {
468
+
{ "max22007" },
469
+
{ }
470
+
};
471
+
MODULE_DEVICE_TABLE(spi, max22007_id);
472
+
473
+
static const struct of_device_id max22007_of_match[] = {
474
+
{ .compatible = "adi,max22007" },
475
+
{ }
476
+
};
477
+
MODULE_DEVICE_TABLE(of, max22007_of_match);
478
+
479
+
static struct spi_driver max22007_driver = {
480
+
.driver = {
481
+
.name = "max22007",
482
+
.of_match_table = max22007_of_match,
483
+
},
484
+
.probe = max22007_probe,
485
+
.id_table = max22007_id,
486
+
};
487
+
module_spi_driver(max22007_driver);
488
+
489
+
MODULE_AUTHOR("Janani Sunil <janani.sunil@analog.com>");
490
+
MODULE_DESCRIPTION("Analog Devices MAX22007 DAC");
491
+
MODULE_LICENSE("GPL");
+1250
drivers/iio/dac/mcp47feb02.c
+1250
drivers/iio/dac/mcp47feb02.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* IIO driver for MCP47FEB02 Multi-Channel DAC with I2C interface
4
+
*
5
+
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
6
+
*
7
+
* Author: Ariana Lazar <ariana.lazar@microchip.com>
8
+
*
9
+
* Datasheet links:
10
+
* [MCP47FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005375A.pdf
11
+
* [MCP47FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/20005405A.pdf
12
+
* [MCP47FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP47FXBX48-Data-Sheet-DS200006368A.pdf
13
+
*/
14
+
#include <linux/array_size.h>
15
+
#include <linux/bits.h>
16
+
#include <linux/bitfield.h>
17
+
#include <linux/delay.h>
18
+
#include <linux/err.h>
19
+
#include <linux/i2c.h>
20
+
#include <linux/iio/iio.h>
21
+
#include <linux/iio/sysfs.h>
22
+
#include <linux/kstrtox.h>
23
+
#include <linux/module.h>
24
+
#include <linux/mod_devicetable.h>
25
+
#include <linux/mutex.h>
26
+
#include <linux/property.h>
27
+
#include <linux/regmap.h>
28
+
#include <linux/regulator/consumer.h>
29
+
#include <linux/time64.h>
30
+
#include <linux/types.h>
31
+
#include <linux/units.h>
32
+
33
+
/* Register addresses must be left shifted with 3 positions in order to append command mask */
34
+
#define MCP47FEB02_DAC0_REG_ADDR 0x00
35
+
#define MCP47FEB02_VREF_REG_ADDR 0x40
36
+
#define MCP47FEB02_POWER_DOWN_REG_ADDR 0x48
37
+
#define MCP47FEB02_DAC_CTRL_MASK GENMASK(1, 0)
38
+
39
+
#define MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR 0x50
40
+
#define MCP47FEB02_GAIN_BIT_MASK BIT(0)
41
+
#define MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK BIT(6)
42
+
#define MCP47FEB02_GAIN_BITS_MASK GENMASK(15, 8)
43
+
44
+
#define MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR 0x58
45
+
46
+
#define MCP47FEB02_NV_DAC0_REG_ADDR 0x80
47
+
#define MCP47FEB02_NV_VREF_REG_ADDR 0xC0
48
+
#define MCP47FEB02_NV_POWER_DOWN_REG_ADDR 0xC8
49
+
#define MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR 0xD0
50
+
#define MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK GENMASK(7, 0)
51
+
52
+
/* Voltage reference, Power-Down control register and DAC Wiperlock status register fields */
53
+
#define DAC_CTRL_MASK(ch) (GENMASK(1, 0) << (2 * (ch)))
54
+
#define DAC_CTRL_VAL(ch, val) ((val) << (2 * (ch)))
55
+
56
+
/* Gain Control and I2C Slave Address Reguster fields */
57
+
#define DAC_GAIN_MASK(ch) (BIT(0) << (8 + (ch)))
58
+
#define DAC_GAIN_VAL(ch, val) ((val) << (8 + (ch)))
59
+
60
+
#define REG_ADDR(reg) ((reg) << 3)
61
+
#define NV_REG_ADDR(reg) ((NV_DAC_ADDR_OFFSET + (reg)) << 3)
62
+
#define READFLAG_MASK GENMASK(2, 1)
63
+
64
+
#define MCP47FEB02_MAX_CH 8
65
+
#define MCP47FEB02_MAX_SCALES_CH 3
66
+
#define MCP47FEB02_DAC_WIPER_UNLOCKED 0
67
+
#define MCP47FEB02_NORMAL_OPERATION 0
68
+
#define MCP47FEB02_INTERNAL_BAND_GAP_mV 2440
69
+
#define NV_DAC_ADDR_OFFSET 0x10
70
+
71
+
enum mcp47feb02_vref_mode {
72
+
MCP47FEB02_VREF_VDD = 0,
73
+
MCP47FEB02_INTERNAL_BAND_GAP = 1,
74
+
MCP47FEB02_EXTERNAL_VREF_UNBUFFERED = 2,
75
+
MCP47FEB02_EXTERNAL_VREF_BUFFERED = 3,
76
+
};
77
+
78
+
enum mcp47feb02_scale {
79
+
MCP47FEB02_SCALE_VDD = 0,
80
+
MCP47FEB02_SCALE_GAIN_X1 = 1,
81
+
MCP47FEB02_SCALE_GAIN_X2 = 2,
82
+
};
83
+
84
+
enum mcp47feb02_gain_bit_mode {
85
+
MCP47FEB02_GAIN_BIT_X1 = 0,
86
+
MCP47FEB02_GAIN_BIT_X2 = 1,
87
+
};
88
+
89
+
static const char * const mcp47feb02_powerdown_modes[] = {
90
+
"1kohm_to_gnd",
91
+
"100kohm_to_gnd",
92
+
"open_circuit",
93
+
};
94
+
95
+
/**
96
+
* struct mcp47feb02_features - chip specific data
97
+
* @name: device name
98
+
* @phys_channels: number of hardware channels
99
+
* @resolution: DAC resolution
100
+
* @have_ext_vref1: does the hardware have an the second external voltage reference?
101
+
* @have_eeprom: does the hardware have an internal eeprom?
102
+
*/
103
+
struct mcp47feb02_features {
104
+
const char *name;
105
+
unsigned int phys_channels;
106
+
unsigned int resolution;
107
+
bool have_ext_vref1;
108
+
bool have_eeprom;
109
+
};
110
+
111
+
static const struct mcp47feb02_features mcp47feb01_chip_features = {
112
+
.name = "mcp47feb01",
113
+
.phys_channels = 1,
114
+
.resolution = 8,
115
+
.have_ext_vref1 = false,
116
+
.have_eeprom = true,
117
+
};
118
+
119
+
static const struct mcp47feb02_features mcp47feb02_chip_features = {
120
+
.name = "mcp47feb02",
121
+
.phys_channels = 2,
122
+
.resolution = 8,
123
+
.have_ext_vref1 = false,
124
+
.have_eeprom = true,
125
+
};
126
+
127
+
static const struct mcp47feb02_features mcp47feb04_chip_features = {
128
+
.name = "mcp47feb04",
129
+
.phys_channels = 4,
130
+
.resolution = 8,
131
+
.have_ext_vref1 = true,
132
+
.have_eeprom = true,
133
+
};
134
+
135
+
static const struct mcp47feb02_features mcp47feb08_chip_features = {
136
+
.name = "mcp47feb08",
137
+
.phys_channels = 8,
138
+
.resolution = 8,
139
+
.have_ext_vref1 = true,
140
+
.have_eeprom = true,
141
+
};
142
+
143
+
static const struct mcp47feb02_features mcp47feb11_chip_features = {
144
+
.name = "mcp47feb11",
145
+
.phys_channels = 1,
146
+
.resolution = 10,
147
+
.have_ext_vref1 = false,
148
+
.have_eeprom = true,
149
+
};
150
+
151
+
static const struct mcp47feb02_features mcp47feb12_chip_features = {
152
+
.name = "mcp47feb12",
153
+
.phys_channels = 2,
154
+
.resolution = 10,
155
+
.have_ext_vref1 = false,
156
+
.have_eeprom = true,
157
+
};
158
+
159
+
static const struct mcp47feb02_features mcp47feb14_chip_features = {
160
+
.name = "mcp47feb14",
161
+
.phys_channels = 4,
162
+
.resolution = 10,
163
+
.have_ext_vref1 = true,
164
+
.have_eeprom = true,
165
+
};
166
+
167
+
static const struct mcp47feb02_features mcp47feb18_chip_features = {
168
+
.name = "mcp47feb18",
169
+
.phys_channels = 8,
170
+
.resolution = 10,
171
+
.have_ext_vref1 = true,
172
+
.have_eeprom = true,
173
+
};
174
+
175
+
static const struct mcp47feb02_features mcp47feb21_chip_features = {
176
+
.name = "mcp47feb21",
177
+
.phys_channels = 1,
178
+
.resolution = 12,
179
+
.have_ext_vref1 = false,
180
+
.have_eeprom = true,
181
+
};
182
+
183
+
static const struct mcp47feb02_features mcp47feb22_chip_features = {
184
+
.name = "mcp47feb22",
185
+
.phys_channels = 2,
186
+
.resolution = 12,
187
+
.have_ext_vref1 = false,
188
+
.have_eeprom = true,
189
+
};
190
+
191
+
static const struct mcp47feb02_features mcp47feb24_chip_features = {
192
+
.name = "mcp47feb24",
193
+
.phys_channels = 4,
194
+
.resolution = 12,
195
+
.have_ext_vref1 = true,
196
+
.have_eeprom = true,
197
+
};
198
+
199
+
static const struct mcp47feb02_features mcp47feb28_chip_features = {
200
+
.name = "mcp47feb28",
201
+
.phys_channels = 8,
202
+
.resolution = 12,
203
+
.have_ext_vref1 = true,
204
+
.have_eeprom = true,
205
+
};
206
+
207
+
static const struct mcp47feb02_features mcp47fvb01_chip_features = {
208
+
.name = "mcp47fvb01",
209
+
.phys_channels = 1,
210
+
.resolution = 8,
211
+
.have_ext_vref1 = false,
212
+
.have_eeprom = false,
213
+
};
214
+
215
+
static const struct mcp47feb02_features mcp47fvb02_chip_features = {
216
+
.name = "mcp47fvb02",
217
+
.phys_channels = 2,
218
+
.resolution = 8,
219
+
.have_ext_vref1 = false,
220
+
.have_eeprom = false,
221
+
};
222
+
223
+
static const struct mcp47feb02_features mcp47fvb04_chip_features = {
224
+
.name = "mcp47fvb04",
225
+
.phys_channels = 4,
226
+
.resolution = 8,
227
+
.have_ext_vref1 = true,
228
+
.have_eeprom = false,
229
+
};
230
+
231
+
static const struct mcp47feb02_features mcp47fvb08_chip_features = {
232
+
.name = "mcp47fvb08",
233
+
.phys_channels = 8,
234
+
.resolution = 8,
235
+
.have_ext_vref1 = true,
236
+
.have_eeprom = false,
237
+
};
238
+
239
+
static const struct mcp47feb02_features mcp47fvb11_chip_features = {
240
+
.name = "mcp47fvb11",
241
+
.phys_channels = 1,
242
+
.resolution = 10,
243
+
.have_ext_vref1 = false,
244
+
.have_eeprom = false,
245
+
};
246
+
247
+
static const struct mcp47feb02_features mcp47fvb12_chip_features = {
248
+
.name = "mcp47fvb12",
249
+
.phys_channels = 2,
250
+
.resolution = 10,
251
+
.have_ext_vref1 = false,
252
+
.have_eeprom = false,
253
+
};
254
+
255
+
static const struct mcp47feb02_features mcp47fvb14_chip_features = {
256
+
.name = "mcp47fvb14",
257
+
.phys_channels = 4,
258
+
.resolution = 10,
259
+
.have_ext_vref1 = true,
260
+
.have_eeprom = false,
261
+
};
262
+
263
+
static const struct mcp47feb02_features mcp47fvb18_chip_features = {
264
+
.name = "mcp47fvb18",
265
+
.phys_channels = 8,
266
+
.resolution = 10,
267
+
.have_ext_vref1 = true,
268
+
.have_eeprom = false,
269
+
};
270
+
271
+
static const struct mcp47feb02_features mcp47fvb21_chip_features = {
272
+
.name = "mcp47fvb21",
273
+
.phys_channels = 1,
274
+
.resolution = 12,
275
+
.have_ext_vref1 = false,
276
+
.have_eeprom = false,
277
+
};
278
+
279
+
static const struct mcp47feb02_features mcp47fvb22_chip_features = {
280
+
.name = "mcp47fvb22",
281
+
.phys_channels = 2,
282
+
.resolution = 12,
283
+
.have_ext_vref1 = false,
284
+
.have_eeprom = false,
285
+
};
286
+
287
+
static const struct mcp47feb02_features mcp47fvb24_chip_features = {
288
+
.name = "mcp47fvb24",
289
+
.phys_channels = 4,
290
+
.resolution = 12,
291
+
.have_ext_vref1 = true,
292
+
.have_eeprom = false,
293
+
};
294
+
295
+
static const struct mcp47feb02_features mcp47fvb28_chip_features = {
296
+
.name = "mcp47fvb28",
297
+
.phys_channels = 8,
298
+
.resolution = 12,
299
+
.have_ext_vref1 = true,
300
+
.have_eeprom = false,
301
+
};
302
+
303
+
/**
304
+
* struct mcp47feb02_channel_data - channel configuration
305
+
* @ref_mode: chosen voltage for reference
306
+
* @use_2x_gain: output driver gain control
307
+
* @powerdown: is false if the channel is in normal operation mode
308
+
* @powerdown_mode: selected power-down mode
309
+
* @dac_data: dac value
310
+
*/
311
+
struct mcp47feb02_channel_data {
312
+
u8 ref_mode;
313
+
bool use_2x_gain;
314
+
bool powerdown;
315
+
u8 powerdown_mode;
316
+
u16 dac_data;
317
+
};
318
+
319
+
/**
320
+
* struct mcp47feb02_data - chip configuration
321
+
* @chdata: options configured for each channel on the device
322
+
* @lock: prevents concurrent reads/writes to driver's state members
323
+
* @chip_features: pointer to features struct
324
+
* @scale_1: scales set on channels that are based on Vref1
325
+
* @scale: scales set on channels that are based on Vref/Vref0
326
+
* @active_channels_mask: enabled channels
327
+
* @regmap: regmap for directly accessing device register
328
+
* @labels: table with channels labels
329
+
* @phys_channels: physical channels on the device
330
+
* @vref1_buffered: Vref1 buffer is enabled
331
+
* @vref_buffered: Vref/Vref0 buffer is enabled
332
+
* @use_vref1: vref1-supply is defined
333
+
* @use_vref: vref-supply is defined
334
+
*/
335
+
struct mcp47feb02_data {
336
+
struct mcp47feb02_channel_data chdata[MCP47FEB02_MAX_CH];
337
+
struct mutex lock; /* prevents concurrent reads/writes to driver's state members */
338
+
const struct mcp47feb02_features *chip_features;
339
+
int scale_1[2 * MCP47FEB02_MAX_SCALES_CH];
340
+
int scale[2 * MCP47FEB02_MAX_SCALES_CH];
341
+
unsigned long active_channels_mask;
342
+
struct regmap *regmap;
343
+
const char *labels[MCP47FEB02_MAX_CH];
344
+
u16 phys_channels;
345
+
bool vref1_buffered;
346
+
bool vref_buffered;
347
+
bool use_vref1;
348
+
bool use_vref;
349
+
};
350
+
351
+
static const struct regmap_range mcp47feb02_readable_ranges[] = {
352
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
353
+
regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
354
+
};
355
+
356
+
static const struct regmap_range mcp47feb02_writable_ranges[] = {
357
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
358
+
regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
359
+
};
360
+
361
+
static const struct regmap_range mcp47feb02_volatile_ranges[] = {
362
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
363
+
regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
364
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
365
+
regmap_reg_range(MCP47FEB02_NV_DAC0_REG_ADDR, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR),
366
+
};
367
+
368
+
static const struct regmap_access_table mcp47feb02_readable_table = {
369
+
.yes_ranges = mcp47feb02_readable_ranges,
370
+
.n_yes_ranges = ARRAY_SIZE(mcp47feb02_readable_ranges),
371
+
};
372
+
373
+
static const struct regmap_access_table mcp47feb02_writable_table = {
374
+
.yes_ranges = mcp47feb02_writable_ranges,
375
+
.n_yes_ranges = ARRAY_SIZE(mcp47feb02_writable_ranges),
376
+
};
377
+
378
+
static const struct regmap_access_table mcp47feb02_volatile_table = {
379
+
.yes_ranges = mcp47feb02_volatile_ranges,
380
+
.n_yes_ranges = ARRAY_SIZE(mcp47feb02_volatile_ranges),
381
+
};
382
+
383
+
static const struct regmap_config mcp47feb02_regmap_config = {
384
+
.name = "mcp47feb02_regmap",
385
+
.reg_bits = 8,
386
+
.val_bits = 16,
387
+
.rd_table = &mcp47feb02_readable_table,
388
+
.wr_table = &mcp47feb02_writable_table,
389
+
.volatile_table = &mcp47feb02_volatile_table,
390
+
.max_register = MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR,
391
+
.read_flag_mask = READFLAG_MASK,
392
+
.cache_type = REGCACHE_MAPLE,
393
+
.val_format_endian = REGMAP_ENDIAN_BIG,
394
+
};
395
+
396
+
/* For devices that doesn't have nonvolatile memory */
397
+
static const struct regmap_range mcp47fvb02_readable_ranges[] = {
398
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
399
+
};
400
+
401
+
static const struct regmap_range mcp47fvb02_writable_ranges[] = {
402
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
403
+
};
404
+
405
+
static const struct regmap_range mcp47fvb02_volatile_ranges[] = {
406
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
407
+
regmap_reg_range(MCP47FEB02_DAC0_REG_ADDR, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR),
408
+
};
409
+
410
+
static const struct regmap_access_table mcp47fvb02_readable_table = {
411
+
.yes_ranges = mcp47fvb02_readable_ranges,
412
+
.n_yes_ranges = ARRAY_SIZE(mcp47fvb02_readable_ranges),
413
+
};
414
+
415
+
static const struct regmap_access_table mcp47fvb02_writable_table = {
416
+
.yes_ranges = mcp47fvb02_writable_ranges,
417
+
.n_yes_ranges = ARRAY_SIZE(mcp47fvb02_writable_ranges),
418
+
};
419
+
420
+
static const struct regmap_access_table mcp47fvb02_volatile_table = {
421
+
.yes_ranges = mcp47fvb02_volatile_ranges,
422
+
.n_yes_ranges = ARRAY_SIZE(mcp47fvb02_volatile_ranges),
423
+
};
424
+
425
+
static const struct regmap_config mcp47fvb02_regmap_config = {
426
+
.name = "mcp47fvb02_regmap",
427
+
.reg_bits = 8,
428
+
.val_bits = 16,
429
+
.rd_table = &mcp47fvb02_readable_table,
430
+
.wr_table = &mcp47fvb02_writable_table,
431
+
.volatile_table = &mcp47fvb02_volatile_table,
432
+
.max_register = MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR,
433
+
.read_flag_mask = READFLAG_MASK,
434
+
.cache_type = REGCACHE_MAPLE,
435
+
.val_format_endian = REGMAP_ENDIAN_BIG,
436
+
};
437
+
438
+
static int mcp47feb02_write_to_eeprom(struct mcp47feb02_data *data, unsigned int reg,
439
+
unsigned int val)
440
+
{
441
+
int eewa_val, ret;
442
+
443
+
/*
444
+
* Wait until the currently occurring EEPROM Write Cycle is completed.
445
+
* Only serial commands to the volatile memory are allowed.
446
+
*/
447
+
guard(mutex)(&data->lock);
448
+
449
+
ret = regmap_read_poll_timeout(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR,
450
+
eewa_val,
451
+
!(eewa_val & MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK),
452
+
USEC_PER_MSEC, USEC_PER_MSEC * 5);
453
+
if (ret)
454
+
return ret;
455
+
456
+
return regmap_write(data->regmap, reg, val);
457
+
}
458
+
459
+
static ssize_t store_eeprom_store(struct device *dev, struct device_attribute *attr,
460
+
const char *buf, size_t len)
461
+
{
462
+
struct mcp47feb02_data *data = iio_priv(dev_to_iio_dev(dev));
463
+
unsigned int i, val, val1, eewa_val;
464
+
bool state;
465
+
int ret;
466
+
467
+
ret = kstrtobool(buf, &state);
468
+
if (ret)
469
+
return ret;
470
+
471
+
if (!state)
472
+
return 0;
473
+
474
+
/*
475
+
* Verify DAC Wiper and DAC Configuration are unlocked. If both are disabled,
476
+
* writing to EEPROM is available.
477
+
*/
478
+
ret = regmap_read(data->regmap, MCP47FEB02_WIPERLOCK_STATUS_REG_ADDR, &val);
479
+
if (ret)
480
+
return ret;
481
+
482
+
if (val) {
483
+
dev_err(dev, "DAC Wiper and DAC Configuration not are unlocked.\n");
484
+
return -EINVAL;
485
+
}
486
+
487
+
for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) {
488
+
ret = mcp47feb02_write_to_eeprom(data, NV_REG_ADDR(i),
489
+
data->chdata[i].dac_data);
490
+
if (ret)
491
+
return ret;
492
+
}
493
+
494
+
ret = regmap_read(data->regmap, MCP47FEB02_VREF_REG_ADDR, &val);
495
+
if (ret)
496
+
return ret;
497
+
498
+
ret = mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_VREF_REG_ADDR, val);
499
+
if (ret)
500
+
return ret;
501
+
502
+
ret = regmap_read(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, &val);
503
+
if (ret)
504
+
return ret;
505
+
506
+
ret = mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_POWER_DOWN_REG_ADDR, val);
507
+
if (ret)
508
+
return ret;
509
+
510
+
ret = regmap_read_poll_timeout(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, eewa_val,
511
+
!(eewa_val & MCP47FEB02_GAIN_BIT_STATUS_EEWA_MASK),
512
+
USEC_PER_MSEC, USEC_PER_MSEC * 5);
513
+
if (ret)
514
+
return ret;
515
+
516
+
ret = regmap_read(data->regmap, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR, &val);
517
+
if (ret)
518
+
return ret;
519
+
520
+
ret = regmap_read(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, &val1);
521
+
if (ret)
522
+
return ret;
523
+
524
+
ret = mcp47feb02_write_to_eeprom(data, MCP47FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR,
525
+
(val1 & MCP47FEB02_GAIN_BITS_MASK) |
526
+
(val & MCP47FEB02_NV_I2C_SLAVE_ADDR_MASK));
527
+
if (ret)
528
+
return ret;
529
+
530
+
return len;
531
+
}
532
+
533
+
static IIO_DEVICE_ATTR_WO(store_eeprom, 0);
534
+
535
+
static struct attribute *mcp47feb02_attributes[] = {
536
+
&iio_dev_attr_store_eeprom.dev_attr.attr,
537
+
NULL
538
+
};
539
+
540
+
static const struct attribute_group mcp47feb02_attribute_group = {
541
+
.attrs = mcp47feb02_attributes,
542
+
};
543
+
544
+
static int mcp47feb02_suspend(struct device *dev)
545
+
{
546
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
547
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
548
+
int ret;
549
+
u8 ch;
550
+
551
+
guard(mutex)(&data->lock);
552
+
553
+
for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) {
554
+
u8 pd_mode;
555
+
556
+
data->chdata[ch].powerdown = true;
557
+
pd_mode = data->chdata[ch].powerdown_mode + 1;
558
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR,
559
+
DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, pd_mode));
560
+
if (ret)
561
+
return ret;
562
+
563
+
ret = regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_data);
564
+
if (ret)
565
+
return ret;
566
+
}
567
+
568
+
return 0;
569
+
}
570
+
571
+
static int mcp47feb02_resume(struct device *dev)
572
+
{
573
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
574
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
575
+
u8 ch;
576
+
577
+
guard(mutex)(&data->lock);
578
+
579
+
for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) {
580
+
u8 pd_mode;
581
+
int ret;
582
+
583
+
data->chdata[ch].powerdown = false;
584
+
pd_mode = data->chdata[ch].powerdown_mode + 1;
585
+
586
+
ret = regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_data);
587
+
if (ret)
588
+
return ret;
589
+
590
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_VREF_REG_ADDR,
591
+
DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, pd_mode));
592
+
if (ret)
593
+
return ret;
594
+
595
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR,
596
+
DAC_GAIN_MASK(ch),
597
+
DAC_GAIN_VAL(ch, data->chdata[ch].use_2x_gain));
598
+
if (ret)
599
+
return ret;
600
+
601
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR,
602
+
DAC_CTRL_MASK(ch),
603
+
DAC_CTRL_VAL(ch, MCP47FEB02_NORMAL_OPERATION));
604
+
if (ret)
605
+
return ret;
606
+
}
607
+
608
+
return 0;
609
+
}
610
+
611
+
static int mcp47feb02_get_powerdown_mode(struct iio_dev *indio_dev,
612
+
const struct iio_chan_spec *chan)
613
+
{
614
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
615
+
616
+
return data->chdata[chan->address].powerdown_mode;
617
+
}
618
+
619
+
static int mcp47feb02_set_powerdown_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *ch,
620
+
unsigned int mode)
621
+
{
622
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
623
+
624
+
data->chdata[ch->address].powerdown_mode = mode;
625
+
626
+
return 0;
627
+
}
628
+
629
+
static ssize_t mcp47feb02_read_powerdown(struct iio_dev *indio_dev, uintptr_t private,
630
+
const struct iio_chan_spec *ch, char *buf)
631
+
{
632
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
633
+
634
+
/* Print if channel is in a power-down mode or not */
635
+
return sysfs_emit(buf, "%d\n", data->chdata[ch->address].powerdown);
636
+
}
637
+
638
+
static ssize_t mcp47feb02_write_powerdown(struct iio_dev *indio_dev, uintptr_t private,
639
+
const struct iio_chan_spec *ch, const char *buf,
640
+
size_t len)
641
+
{
642
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
643
+
u32 reg = ch->address;
644
+
u8 tmp_pd_mode;
645
+
bool state;
646
+
int ret;
647
+
648
+
guard(mutex)(&data->lock);
649
+
650
+
ret = kstrtobool(buf, &state);
651
+
if (ret)
652
+
return ret;
653
+
654
+
/*
655
+
* Set the channel to the specified power-down mode. Exiting power-down mode
656
+
* requires writing normal operation mode (0) to the channel-specific register bits.
657
+
*/
658
+
tmp_pd_mode = state ? (data->chdata[reg].powerdown_mode + 1) : MCP47FEB02_NORMAL_OPERATION;
659
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR,
660
+
DAC_CTRL_MASK(reg), DAC_CTRL_VAL(reg, tmp_pd_mode));
661
+
if (ret)
662
+
return ret;
663
+
664
+
data->chdata[reg].powerdown = state;
665
+
666
+
return len;
667
+
}
668
+
669
+
static DEFINE_SIMPLE_DEV_PM_OPS(mcp47feb02_pm_ops, mcp47feb02_suspend, mcp47feb02_resume);
670
+
671
+
static const struct iio_enum mcp47febxx_powerdown_mode_enum = {
672
+
.items = mcp47feb02_powerdown_modes,
673
+
.num_items = ARRAY_SIZE(mcp47feb02_powerdown_modes),
674
+
.get = mcp47feb02_get_powerdown_mode,
675
+
.set = mcp47feb02_set_powerdown_mode,
676
+
};
677
+
678
+
static const struct iio_chan_spec_ext_info mcp47feb02_ext_info[] = {
679
+
{
680
+
.name = "powerdown",
681
+
.read = mcp47feb02_read_powerdown,
682
+
.write = mcp47feb02_write_powerdown,
683
+
.shared = IIO_SEPARATE,
684
+
},
685
+
IIO_ENUM("powerdown_mode", IIO_SEPARATE, &mcp47febxx_powerdown_mode_enum),
686
+
IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &mcp47febxx_powerdown_mode_enum),
687
+
{ }
688
+
};
689
+
690
+
static const struct iio_chan_spec mcp47febxx_ch_template = {
691
+
.type = IIO_VOLTAGE,
692
+
.output = 1,
693
+
.indexed = 1,
694
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
695
+
.info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
696
+
.ext_info = mcp47feb02_ext_info,
697
+
};
698
+
699
+
static void mcp47feb02_init_scale(struct mcp47feb02_data *data, enum mcp47feb02_scale scale,
700
+
int vref_mV, int scale_avail[])
701
+
{
702
+
u32 value_micro, value_int;
703
+
u64 tmp;
704
+
705
+
/* vref_mV should not be negative */
706
+
tmp = (u64)vref_mV * MICRO >> data->chip_features->resolution;
707
+
value_int = div_u64_rem(tmp, MICRO, &value_micro);
708
+
scale_avail[scale * 2] = value_int;
709
+
scale_avail[scale * 2 + 1] = value_micro;
710
+
}
711
+
712
+
static int mcp47feb02_init_scales_avail(struct mcp47feb02_data *data, int vdd_mV,
713
+
int vref_mV, int vref1_mV)
714
+
{
715
+
struct device *dev = regmap_get_device(data->regmap);
716
+
int tmp_vref;
717
+
718
+
mcp47feb02_init_scale(data, MCP47FEB02_SCALE_VDD, vdd_mV, data->scale);
719
+
720
+
if (data->use_vref)
721
+
tmp_vref = vref_mV;
722
+
else
723
+
tmp_vref = MCP47FEB02_INTERNAL_BAND_GAP_mV;
724
+
725
+
mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X1, tmp_vref, data->scale);
726
+
mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X2, tmp_vref * 2, data->scale);
727
+
728
+
if (data->phys_channels >= 4) {
729
+
mcp47feb02_init_scale(data, MCP47FEB02_SCALE_VDD, vdd_mV, data->scale_1);
730
+
731
+
if (data->use_vref1 && vref1_mV <= 0)
732
+
return dev_err_probe(dev, vref1_mV, "Invalid voltage for Vref1\n");
733
+
734
+
if (data->use_vref1)
735
+
tmp_vref = vref1_mV;
736
+
else
737
+
tmp_vref = MCP47FEB02_INTERNAL_BAND_GAP_mV;
738
+
739
+
mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X1,
740
+
tmp_vref, data->scale_1);
741
+
mcp47feb02_init_scale(data, MCP47FEB02_SCALE_GAIN_X2,
742
+
tmp_vref * 2, data->scale_1);
743
+
}
744
+
745
+
return 0;
746
+
}
747
+
748
+
static int mcp47feb02_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
749
+
const int **vals, int *type, int *length, long info)
750
+
{
751
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
752
+
753
+
switch (info) {
754
+
case IIO_CHAN_INFO_SCALE:
755
+
switch (ch->type) {
756
+
case IIO_VOLTAGE:
757
+
if (data->phys_channels >= 4 && (ch->address % 2))
758
+
*vals = data->scale_1;
759
+
else
760
+
*vals = data->scale;
761
+
762
+
*length = 2 * MCP47FEB02_MAX_SCALES_CH;
763
+
*type = IIO_VAL_INT_PLUS_MICRO;
764
+
return IIO_AVAIL_LIST;
765
+
default:
766
+
return -EINVAL;
767
+
}
768
+
default:
769
+
return -EINVAL;
770
+
}
771
+
}
772
+
773
+
static void mcp47feb02_get_scale(int ch, struct mcp47feb02_data *data, int *val, int *val2)
774
+
{
775
+
enum mcp47feb02_scale current_scale;
776
+
777
+
if (data->chdata[ch].ref_mode == MCP47FEB02_VREF_VDD)
778
+
current_scale = MCP47FEB02_SCALE_VDD;
779
+
else if (data->chdata[ch].use_2x_gain)
780
+
current_scale = MCP47FEB02_SCALE_GAIN_X2;
781
+
else
782
+
current_scale = MCP47FEB02_SCALE_GAIN_X1;
783
+
784
+
if (data->phys_channels >= 4 && (ch % 2)) {
785
+
*val = data->scale_1[current_scale * 2];
786
+
*val2 = data->scale_1[current_scale * 2 + 1];
787
+
} else {
788
+
*val = data->scale[current_scale * 2];
789
+
*val2 = data->scale[current_scale * 2 + 1];
790
+
}
791
+
}
792
+
793
+
static int mcp47feb02_check_scale(struct mcp47feb02_data *data, int val, int val2, int scale[])
794
+
{
795
+
unsigned int i;
796
+
797
+
for (i = 0; i < MCP47FEB02_MAX_SCALES_CH; i++) {
798
+
if (scale[i * 2] == val && scale[i * 2 + 1] == val2)
799
+
return i;
800
+
}
801
+
802
+
return -EINVAL;
803
+
}
804
+
805
+
static int mcp47feb02_ch_scale(struct mcp47feb02_data *data, int ch, int scale)
806
+
{
807
+
int tmp_val, ret;
808
+
809
+
if (scale == MCP47FEB02_SCALE_VDD) {
810
+
tmp_val = MCP47FEB02_VREF_VDD;
811
+
} else if (data->phys_channels >= 4 && (ch % 2)) {
812
+
if (data->use_vref1) {
813
+
if (data->vref1_buffered)
814
+
tmp_val = MCP47FEB02_EXTERNAL_VREF_BUFFERED;
815
+
else
816
+
tmp_val = MCP47FEB02_EXTERNAL_VREF_UNBUFFERED;
817
+
} else {
818
+
tmp_val = MCP47FEB02_INTERNAL_BAND_GAP;
819
+
}
820
+
} else if (data->use_vref) {
821
+
if (data->vref_buffered)
822
+
tmp_val = MCP47FEB02_EXTERNAL_VREF_BUFFERED;
823
+
else
824
+
tmp_val = MCP47FEB02_EXTERNAL_VREF_UNBUFFERED;
825
+
} else {
826
+
tmp_val = MCP47FEB02_INTERNAL_BAND_GAP;
827
+
}
828
+
829
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_VREF_REG_ADDR,
830
+
DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, tmp_val));
831
+
if (ret)
832
+
return ret;
833
+
834
+
data->chdata[ch].ref_mode = tmp_val;
835
+
836
+
return 0;
837
+
}
838
+
839
+
/*
840
+
* Setting the scale in order to choose between VDD and (Vref or Band Gap) from the user
841
+
* space. The VREF pin is either an input or an output, therefore the user cannot
842
+
* simultaneously connect an external voltage reference to the pin and select the
843
+
* internal Band Gap.
844
+
* When the DAC’s voltage reference is configured as the VREF pin, the pin is an input.
845
+
* When the DAC’s voltage reference is configured as the internal Band Gap,
846
+
* the VREF pin is an output.
847
+
* If Vref/Vref1 voltage is not available, then the internal Band Gap will be used
848
+
* to calculate the values for the scale.
849
+
*/
850
+
static int mcp47feb02_set_scale(struct mcp47feb02_data *data, int ch, int scale)
851
+
{
852
+
int tmp_val, ret;
853
+
854
+
ret = mcp47feb02_ch_scale(data, ch, scale);
855
+
if (ret)
856
+
return ret;
857
+
858
+
if (scale == MCP47FEB02_SCALE_GAIN_X2)
859
+
tmp_val = MCP47FEB02_GAIN_BIT_X2;
860
+
else
861
+
tmp_val = MCP47FEB02_GAIN_BIT_X1;
862
+
863
+
ret = regmap_update_bits(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR,
864
+
DAC_GAIN_MASK(ch), DAC_GAIN_VAL(ch, tmp_val));
865
+
if (ret)
866
+
return ret;
867
+
868
+
data->chdata[ch].use_2x_gain = tmp_val;
869
+
870
+
return 0;
871
+
}
872
+
873
+
static int mcp47feb02_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
874
+
int *val, int *val2, long mask)
875
+
{
876
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
877
+
int ret;
878
+
879
+
switch (mask) {
880
+
case IIO_CHAN_INFO_RAW:
881
+
ret = regmap_read(data->regmap, REG_ADDR(ch->address), val);
882
+
if (ret)
883
+
return ret;
884
+
return IIO_VAL_INT;
885
+
case IIO_CHAN_INFO_SCALE:
886
+
mcp47feb02_get_scale(ch->address, data, val, val2);
887
+
return IIO_VAL_INT_PLUS_MICRO;
888
+
default:
889
+
return -EINVAL;
890
+
}
891
+
}
892
+
893
+
static int mcp47feb02_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
894
+
int val, int val2, long mask)
895
+
{
896
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
897
+
int *tmp_scale, ret;
898
+
899
+
guard(mutex)(&data->lock);
900
+
901
+
switch (mask) {
902
+
case IIO_CHAN_INFO_RAW:
903
+
ret = regmap_write(data->regmap, REG_ADDR(ch->address), val);
904
+
if (ret)
905
+
return ret;
906
+
907
+
data->chdata[ch->address].dac_data = val;
908
+
return 0;
909
+
case IIO_CHAN_INFO_SCALE:
910
+
if (data->phys_channels >= 4 && (ch->address % 2))
911
+
tmp_scale = data->scale_1;
912
+
else
913
+
tmp_scale = data->scale;
914
+
915
+
ret = mcp47feb02_check_scale(data, val, val2, tmp_scale);
916
+
if (ret < 0)
917
+
return ret;
918
+
919
+
return mcp47feb02_set_scale(data, ch->address, ret);
920
+
default:
921
+
return -EINVAL;
922
+
}
923
+
}
924
+
925
+
static int mcp47feb02_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *ch,
926
+
char *label)
927
+
{
928
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
929
+
930
+
return sysfs_emit(label, "%s\n", data->labels[ch->address]);
931
+
}
932
+
933
+
static const struct iio_info mcp47feb02_info = {
934
+
.read_raw = mcp47feb02_read_raw,
935
+
.write_raw = mcp47feb02_write_raw,
936
+
.read_label = mcp47feb02_read_label,
937
+
.read_avail = &mcp47feb02_read_avail,
938
+
.attrs = &mcp47feb02_attribute_group,
939
+
};
940
+
941
+
static const struct iio_info mcp47fvb02_info = {
942
+
.read_raw = mcp47feb02_read_raw,
943
+
.write_raw = mcp47feb02_write_raw,
944
+
.read_label = mcp47feb02_read_label,
945
+
.read_avail = &mcp47feb02_read_avail,
946
+
};
947
+
948
+
static int mcp47feb02_parse_fw(struct iio_dev *indio_dev,
949
+
const struct mcp47feb02_features *chip_features)
950
+
{
951
+
struct iio_chan_spec chanspec = mcp47febxx_ch_template;
952
+
struct mcp47feb02_data *data = iio_priv(indio_dev);
953
+
struct device *dev = regmap_get_device(data->regmap);
954
+
struct iio_chan_spec *channels;
955
+
u32 num_channels;
956
+
u8 chan_idx = 0;
957
+
958
+
guard(mutex)(&data->lock);
959
+
960
+
num_channels = device_get_child_node_count(dev);
961
+
if (num_channels > chip_features->phys_channels)
962
+
return dev_err_probe(dev, -EINVAL, "More channels than the chip supports\n");
963
+
964
+
if (!num_channels)
965
+
return dev_err_probe(dev, -EINVAL, "No channel specified in the devicetree.\n");
966
+
967
+
channels = devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNEL);
968
+
if (!channels)
969
+
return -ENOMEM;
970
+
971
+
device_for_each_child_node_scoped(dev, child) {
972
+
u32 reg = 0;
973
+
int ret;
974
+
975
+
ret = fwnode_property_read_u32(child, "reg", ®);
976
+
if (ret)
977
+
return dev_err_probe(dev, ret, "Invalid channel number\n");
978
+
979
+
if (reg >= chip_features->phys_channels)
980
+
return dev_err_probe(dev, -EINVAL,
981
+
"The index of the channels does not match the chip\n");
982
+
983
+
set_bit(reg, &data->active_channels_mask);
984
+
985
+
ret = fwnode_property_read_string(child, "label", &data->labels[reg]);
986
+
if (ret)
987
+
return dev_err_probe(dev, ret, "%pfw: invalid label\n",
988
+
fwnode_get_name(child));
989
+
990
+
chanspec.address = reg;
991
+
chanspec.channel = reg;
992
+
channels[chan_idx] = chanspec;
993
+
chan_idx++;
994
+
}
995
+
996
+
indio_dev->num_channels = num_channels;
997
+
indio_dev->channels = channels;
998
+
indio_dev->modes = INDIO_DIRECT_MODE;
999
+
data->phys_channels = chip_features->phys_channels;
1000
+
1001
+
data->vref_buffered = device_property_read_bool(dev, "microchip,vref-buffered");
1002
+
1003
+
if (chip_features->have_ext_vref1)
1004
+
data->vref1_buffered = device_property_read_bool(dev, "microchip,vref1-buffered");
1005
+
1006
+
return 0;
1007
+
}
1008
+
1009
+
static int mcp47feb02_init_ctrl_regs(struct mcp47feb02_data *data)
1010
+
{
1011
+
unsigned int i, vref_ch, gain_ch, pd_ch;
1012
+
int ret;
1013
+
1014
+
ret = regmap_read(data->regmap, MCP47FEB02_VREF_REG_ADDR, &vref_ch);
1015
+
if (ret)
1016
+
return ret;
1017
+
1018
+
ret = regmap_read(data->regmap, MCP47FEB02_GAIN_CTRL_STATUS_REG_ADDR, &gain_ch);
1019
+
if (ret)
1020
+
return ret;
1021
+
1022
+
ret = regmap_read(data->regmap, MCP47FEB02_POWER_DOWN_REG_ADDR, &pd_ch);
1023
+
if (ret)
1024
+
return ret;
1025
+
1026
+
gain_ch = gain_ch & MCP47FEB02_GAIN_BITS_MASK;
1027
+
for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) {
1028
+
struct device *dev = regmap_get_device(data->regmap);
1029
+
unsigned int pd_tmp;
1030
+
1031
+
data->chdata[i].ref_mode = (vref_ch >> (2 * i)) & MCP47FEB02_DAC_CTRL_MASK;
1032
+
data->chdata[i].use_2x_gain = (gain_ch >> i) & MCP47FEB02_GAIN_BIT_MASK;
1033
+
1034
+
/*
1035
+
* Inform the user that the current voltage reference read from the volatile
1036
+
* register of the chip is different from the one specified in the device tree.
1037
+
* Considering that the user cannot have an external voltage reference connected
1038
+
* to the pin and select the internal Band Gap at the same time, in order to avoid
1039
+
* miscofiguring the reference voltage, the volatile register will not be written.
1040
+
* In order to overwrite the setting from volatile register with the one from the
1041
+
* device tree, the user needs to write the chosen scale.
1042
+
*/
1043
+
switch (data->chdata[i].ref_mode) {
1044
+
case MCP47FEB02_INTERNAL_BAND_GAP:
1045
+
if (data->phys_channels >= 4 && (i % 2) && data->use_vref1) {
1046
+
dev_dbg(dev, "ch[%u]: was configured to use internal band gap", i);
1047
+
dev_dbg(dev, "ch[%u]: reference voltage set to VREF1", i);
1048
+
break;
1049
+
}
1050
+
if ((data->phys_channels < 4 || (data->phys_channels >= 4 && !(i % 2))) &&
1051
+
data->use_vref) {
1052
+
dev_dbg(dev, "ch[%u]: was configured to use internal band gap", i);
1053
+
dev_dbg(dev, "ch[%u]: reference voltage set to VREF", i);
1054
+
break;
1055
+
}
1056
+
break;
1057
+
case MCP47FEB02_EXTERNAL_VREF_UNBUFFERED:
1058
+
case MCP47FEB02_EXTERNAL_VREF_BUFFERED:
1059
+
if (data->phys_channels >= 4 && (i % 2) && !data->use_vref1) {
1060
+
dev_dbg(dev, "ch[%u]: was configured to use VREF1", i);
1061
+
dev_dbg(dev,
1062
+
"ch[%u]: reference voltage set to internal band gap", i);
1063
+
break;
1064
+
}
1065
+
if ((data->phys_channels < 4 || (data->phys_channels >= 4 && !(i % 2))) &&
1066
+
!data->use_vref) {
1067
+
dev_dbg(dev, "ch[%u]: was configured to use VREF", i);
1068
+
dev_dbg(dev,
1069
+
"ch[%u]: reference voltage set to internal band gap", i);
1070
+
break;
1071
+
}
1072
+
break;
1073
+
}
1074
+
1075
+
pd_tmp = (pd_ch >> (2 * i)) & MCP47FEB02_DAC_CTRL_MASK;
1076
+
data->chdata[i].powerdown_mode = pd_tmp ? (pd_tmp - 1) : pd_tmp;
1077
+
data->chdata[i].powerdown = !!(data->chdata[i].powerdown_mode);
1078
+
}
1079
+
1080
+
return 0;
1081
+
}
1082
+
1083
+
static int mcp47feb02_init_ch_scales(struct mcp47feb02_data *data, int vdd_mV,
1084
+
int vref_mV, int vref1_mV)
1085
+
{
1086
+
unsigned int i;
1087
+
1088
+
for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) {
1089
+
struct device *dev = regmap_get_device(data->regmap);
1090
+
int ret;
1091
+
1092
+
ret = mcp47feb02_init_scales_avail(data, vdd_mV, vref_mV, vref1_mV);
1093
+
if (ret)
1094
+
return dev_err_probe(dev, ret, "failed to init scales for ch %u\n", i);
1095
+
}
1096
+
1097
+
return 0;
1098
+
}
1099
+
1100
+
static int mcp47feb02_probe(struct i2c_client *client)
1101
+
{
1102
+
const struct mcp47feb02_features *chip_features;
1103
+
struct device *dev = &client->dev;
1104
+
struct mcp47feb02_data *data;
1105
+
struct iio_dev *indio_dev;
1106
+
int vref1_mV = 0;
1107
+
int vref_mV = 0;
1108
+
int vdd_mV;
1109
+
int ret;
1110
+
1111
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1112
+
if (!indio_dev)
1113
+
return -ENOMEM;
1114
+
1115
+
data = iio_priv(indio_dev);
1116
+
chip_features = i2c_get_match_data(client);
1117
+
if (!chip_features)
1118
+
return -EINVAL;
1119
+
1120
+
data->chip_features = chip_features;
1121
+
1122
+
if (chip_features->have_eeprom) {
1123
+
data->regmap = devm_regmap_init_i2c(client, &mcp47feb02_regmap_config);
1124
+
indio_dev->info = &mcp47feb02_info;
1125
+
} else {
1126
+
data->regmap = devm_regmap_init_i2c(client, &mcp47fvb02_regmap_config);
1127
+
indio_dev->info = &mcp47fvb02_info;
1128
+
}
1129
+
if (IS_ERR(data->regmap))
1130
+
return dev_err_probe(dev, PTR_ERR(data->regmap), "Error initializing i2c regmap\n");
1131
+
1132
+
indio_dev->name = chip_features->name;
1133
+
1134
+
ret = mcp47feb02_parse_fw(indio_dev, chip_features);
1135
+
if (ret)
1136
+
return dev_err_probe(dev, ret, "Error parsing firmware data\n");
1137
+
1138
+
ret = devm_mutex_init(dev, &data->lock);
1139
+
if (ret)
1140
+
return ret;
1141
+
1142
+
ret = devm_regulator_get_enable_read_voltage(dev, "vdd");
1143
+
if (ret < 0)
1144
+
return ret;
1145
+
1146
+
vdd_mV = ret / MILLI;
1147
+
1148
+
ret = devm_regulator_get_enable_read_voltage(dev, "vref");
1149
+
if (ret > 0) {
1150
+
vref_mV = ret / MILLI;
1151
+
data->use_vref = true;
1152
+
} else {
1153
+
dev_dbg(dev, "using internal band gap as voltage reference.\n");
1154
+
dev_dbg(dev, "Vref is unavailable.\n");
1155
+
}
1156
+
1157
+
if (chip_features->have_ext_vref1) {
1158
+
ret = devm_regulator_get_enable_read_voltage(dev, "vref1");
1159
+
if (ret > 0) {
1160
+
vref1_mV = ret / MILLI;
1161
+
data->use_vref1 = true;
1162
+
} else {
1163
+
dev_dbg(dev, "using internal band gap as voltage reference 1.\n");
1164
+
dev_dbg(dev, "Vref1 is unavailable.\n");
1165
+
}
1166
+
}
1167
+
1168
+
ret = mcp47feb02_init_ctrl_regs(data);
1169
+
if (ret)
1170
+
return dev_err_probe(dev, ret, "Error initialising vref register\n");
1171
+
1172
+
ret = mcp47feb02_init_ch_scales(data, vdd_mV, vref_mV, vref1_mV);
1173
+
if (ret)
1174
+
return ret;
1175
+
1176
+
return devm_iio_device_register(dev, indio_dev);
1177
+
}
1178
+
1179
+
static const struct i2c_device_id mcp47feb02_id[] = {
1180
+
{ "mcp47feb01", (kernel_ulong_t)&mcp47feb01_chip_features },
1181
+
{ "mcp47feb02", (kernel_ulong_t)&mcp47feb02_chip_features },
1182
+
{ "mcp47feb04", (kernel_ulong_t)&mcp47feb04_chip_features },
1183
+
{ "mcp47feb08", (kernel_ulong_t)&mcp47feb08_chip_features },
1184
+
{ "mcp47feb11", (kernel_ulong_t)&mcp47feb11_chip_features },
1185
+
{ "mcp47feb12", (kernel_ulong_t)&mcp47feb12_chip_features },
1186
+
{ "mcp47feb14", (kernel_ulong_t)&mcp47feb14_chip_features },
1187
+
{ "mcp47feb18", (kernel_ulong_t)&mcp47feb18_chip_features },
1188
+
{ "mcp47feb21", (kernel_ulong_t)&mcp47feb21_chip_features },
1189
+
{ "mcp47feb22", (kernel_ulong_t)&mcp47feb22_chip_features },
1190
+
{ "mcp47feb24", (kernel_ulong_t)&mcp47feb24_chip_features },
1191
+
{ "mcp47feb28", (kernel_ulong_t)&mcp47feb28_chip_features },
1192
+
{ "mcp47fvb01", (kernel_ulong_t)&mcp47fvb01_chip_features },
1193
+
{ "mcp47fvb02", (kernel_ulong_t)&mcp47fvb02_chip_features },
1194
+
{ "mcp47fvb04", (kernel_ulong_t)&mcp47fvb04_chip_features },
1195
+
{ "mcp47fvb08", (kernel_ulong_t)&mcp47fvb08_chip_features },
1196
+
{ "mcp47fvb11", (kernel_ulong_t)&mcp47fvb11_chip_features },
1197
+
{ "mcp47fvb12", (kernel_ulong_t)&mcp47fvb12_chip_features },
1198
+
{ "mcp47fvb14", (kernel_ulong_t)&mcp47fvb14_chip_features },
1199
+
{ "mcp47fvb18", (kernel_ulong_t)&mcp47fvb18_chip_features },
1200
+
{ "mcp47fvb21", (kernel_ulong_t)&mcp47fvb21_chip_features },
1201
+
{ "mcp47fvb22", (kernel_ulong_t)&mcp47fvb22_chip_features },
1202
+
{ "mcp47fvb24", (kernel_ulong_t)&mcp47fvb24_chip_features },
1203
+
{ "mcp47fvb28", (kernel_ulong_t)&mcp47fvb28_chip_features },
1204
+
{ }
1205
+
};
1206
+
MODULE_DEVICE_TABLE(i2c, mcp47feb02_id);
1207
+
1208
+
static const struct of_device_id mcp47feb02_of_match[] = {
1209
+
{ .compatible = "microchip,mcp47feb01", .data = &mcp47feb01_chip_features },
1210
+
{ .compatible = "microchip,mcp47feb02", .data = &mcp47feb02_chip_features },
1211
+
{ .compatible = "microchip,mcp47feb04", .data = &mcp47feb04_chip_features },
1212
+
{ .compatible = "microchip,mcp47feb08", .data = &mcp47feb08_chip_features },
1213
+
{ .compatible = "microchip,mcp47feb11", .data = &mcp47feb11_chip_features },
1214
+
{ .compatible = "microchip,mcp47feb12", .data = &mcp47feb12_chip_features },
1215
+
{ .compatible = "microchip,mcp47feb14", .data = &mcp47feb14_chip_features },
1216
+
{ .compatible = "microchip,mcp47feb18", .data = &mcp47feb18_chip_features },
1217
+
{ .compatible = "microchip,mcp47feb21", .data = &mcp47feb21_chip_features },
1218
+
{ .compatible = "microchip,mcp47feb22", .data = &mcp47feb22_chip_features },
1219
+
{ .compatible = "microchip,mcp47feb24", .data = &mcp47feb24_chip_features },
1220
+
{ .compatible = "microchip,mcp47feb28", .data = &mcp47feb28_chip_features },
1221
+
{ .compatible = "microchip,mcp47fvb01", .data = &mcp47fvb01_chip_features },
1222
+
{ .compatible = "microchip,mcp47fvb02", .data = &mcp47fvb02_chip_features },
1223
+
{ .compatible = "microchip,mcp47fvb04", .data = &mcp47fvb04_chip_features },
1224
+
{ .compatible = "microchip,mcp47fvb08", .data = &mcp47fvb08_chip_features },
1225
+
{ .compatible = "microchip,mcp47fvb11", .data = &mcp47fvb11_chip_features },
1226
+
{ .compatible = "microchip,mcp47fvb12", .data = &mcp47fvb12_chip_features },
1227
+
{ .compatible = "microchip,mcp47fvb14", .data = &mcp47fvb14_chip_features },
1228
+
{ .compatible = "microchip,mcp47fvb18", .data = &mcp47fvb18_chip_features },
1229
+
{ .compatible = "microchip,mcp47fvb21", .data = &mcp47fvb21_chip_features },
1230
+
{ .compatible = "microchip,mcp47fvb22", .data = &mcp47fvb22_chip_features },
1231
+
{ .compatible = "microchip,mcp47fvb24", .data = &mcp47fvb24_chip_features },
1232
+
{ .compatible = "microchip,mcp47fvb28", .data = &mcp47fvb28_chip_features },
1233
+
{ }
1234
+
};
1235
+
MODULE_DEVICE_TABLE(of, mcp47feb02_of_match);
1236
+
1237
+
static struct i2c_driver mcp47feb02_driver = {
1238
+
.driver = {
1239
+
.name = "mcp47feb02",
1240
+
.of_match_table = mcp47feb02_of_match,
1241
+
.pm = pm_sleep_ptr(&mcp47feb02_pm_ops),
1242
+
},
1243
+
.probe = mcp47feb02_probe,
1244
+
.id_table = mcp47feb02_id,
1245
+
};
1246
+
module_i2c_driver(mcp47feb02_driver);
1247
+
1248
+
MODULE_AUTHOR("Ariana Lazar <ariana.lazar@microchip.com>");
1249
+
MODULE_DESCRIPTION("IIO driver for MCP47FEB02 Multi-Channel DAC with I2C interface");
1250
+
MODULE_LICENSE("GPL");
+120
-2
drivers/iio/frequency/adf4377.c
+120
-2
drivers/iio/frequency/adf4377.c
···
8
8
#include <linux/bitfield.h>
9
9
#include <linux/bits.h>
10
10
#include <linux/clk.h>
11
+
#include <linux/clk-provider.h>
11
12
#include <linux/clkdev.h>
13
+
#include <linux/container_of.h>
12
14
#include <linux/delay.h>
13
15
#include <linux/device.h>
14
16
#include <linux/gpio/consumer.h>
···
437
435
struct gpio_desc *gpio_ce;
438
436
struct gpio_desc *gpio_enclk1;
439
437
struct gpio_desc *gpio_enclk2;
438
+
struct clk *clk;
439
+
struct clk *clkout;
440
+
struct clk_hw hw;
440
441
u8 buf[2] __aligned(IIO_DMA_MINALIGN);
441
442
};
443
+
444
+
#define to_adf4377_state(h) container_of(h, struct adf4377_state, hw)
442
445
443
446
static const char * const adf4377_muxout_modes[] = {
444
447
[ADF4377_MUXOUT_HIGH_Z] = "high_z",
···
936
929
return NOTIFY_OK;
937
930
}
938
931
932
+
static unsigned long adf4377_clk_recalc_rate(struct clk_hw *hw,
933
+
unsigned long parent_rate)
934
+
{
935
+
struct adf4377_state *st = to_adf4377_state(hw);
936
+
u64 freq;
937
+
int ret;
938
+
939
+
ret = adf4377_get_freq(st, &freq);
940
+
if (ret)
941
+
return 0;
942
+
943
+
return freq;
944
+
}
945
+
946
+
static int adf4377_clk_set_rate(struct clk_hw *hw,
947
+
unsigned long rate,
948
+
unsigned long parent_rate)
949
+
{
950
+
struct adf4377_state *st = to_adf4377_state(hw);
951
+
952
+
return adf4377_set_freq(st, rate);
953
+
}
954
+
955
+
static int adf4377_clk_prepare(struct clk_hw *hw)
956
+
{
957
+
struct adf4377_state *st = to_adf4377_state(hw);
958
+
959
+
return regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK |
960
+
ADF4377_001A_PD_CLKOUT2_MSK,
961
+
FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) |
962
+
FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0));
963
+
}
964
+
965
+
static void adf4377_clk_unprepare(struct clk_hw *hw)
966
+
{
967
+
struct adf4377_state *st = to_adf4377_state(hw);
968
+
969
+
regmap_update_bits(st->regmap, 0x1a, ADF4377_001A_PD_CLKOUT1_MSK |
970
+
ADF4377_001A_PD_CLKOUT2_MSK,
971
+
FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 1) |
972
+
FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 1));
973
+
}
974
+
975
+
static int adf4377_clk_is_prepared(struct clk_hw *hw)
976
+
{
977
+
struct adf4377_state *st = to_adf4377_state(hw);
978
+
unsigned int readval;
979
+
int ret;
980
+
981
+
ret = regmap_read(st->regmap, 0x1a, &readval);
982
+
if (ret)
983
+
return ret;
984
+
985
+
return !(readval & (ADF4377_001A_PD_CLKOUT1_MSK | ADF4377_001A_PD_CLKOUT2_MSK));
986
+
}
987
+
988
+
static const struct clk_ops adf4377_clk_ops = {
989
+
.recalc_rate = adf4377_clk_recalc_rate,
990
+
.set_rate = adf4377_clk_set_rate,
991
+
.prepare = adf4377_clk_prepare,
992
+
.unprepare = adf4377_clk_unprepare,
993
+
.is_prepared = adf4377_clk_is_prepared,
994
+
};
995
+
996
+
static int adf4377_clk_register(struct adf4377_state *st)
997
+
{
998
+
struct spi_device *spi = st->spi;
999
+
struct device *dev = &spi->dev;
1000
+
struct clk_init_data init;
1001
+
struct clk_parent_data parent_data;
1002
+
int ret;
1003
+
1004
+
if (!device_property_present(dev, "#clock-cells"))
1005
+
return 0;
1006
+
1007
+
ret = device_property_read_string(dev, "clock-output-names", &init.name);
1008
+
if (ret) {
1009
+
init.name = devm_kasprintf(dev, GFP_KERNEL, "%pfw-clk",
1010
+
dev_fwnode(dev));
1011
+
if (!init.name)
1012
+
return -ENOMEM;
1013
+
}
1014
+
1015
+
parent_data.fw_name = "ref_in";
1016
+
1017
+
init.ops = &adf4377_clk_ops;
1018
+
init.parent_data = &parent_data;
1019
+
init.num_parents = 1;
1020
+
init.flags = CLK_SET_RATE_PARENT;
1021
+
1022
+
st->hw.init = &init;
1023
+
ret = devm_clk_hw_register(dev, &st->hw);
1024
+
if (ret)
1025
+
return ret;
1026
+
1027
+
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &st->hw);
1028
+
if (ret)
1029
+
return ret;
1030
+
1031
+
st->clkout = st->hw.clk;
1032
+
1033
+
return 0;
1034
+
}
1035
+
939
1036
static const struct adf4377_chip_info adf4377_chip_info = {
940
1037
.name = "adf4377",
941
1038
.has_gpio_enclk2 = true,
···
1069
958
1070
959
indio_dev->info = &adf4377_info;
1071
960
indio_dev->name = "adf4377";
1072
-
indio_dev->channels = adf4377_channels;
1073
-
indio_dev->num_channels = ARRAY_SIZE(adf4377_channels);
1074
961
1075
962
st->regmap = regmap;
1076
963
st->spi = spi;
···
1087
978
ret = adf4377_init(st);
1088
979
if (ret)
1089
980
return ret;
981
+
982
+
ret = adf4377_clk_register(st);
983
+
if (ret)
984
+
return ret;
985
+
986
+
if (!st->clkout) {
987
+
indio_dev->channels = adf4377_channels;
988
+
indio_dev->num_channels = ARRAY_SIZE(adf4377_channels);
989
+
}
1090
990
1091
991
return devm_iio_device_register(&spi->dev, indio_dev);
1092
992
}
+1
-1
drivers/iio/gyro/adxrs290.c
+1
-1
drivers/iio/gyro/adxrs290.c
···
597
597
598
598
ret = devm_request_irq(&st->spi->dev, st->spi->irq,
599
599
&iio_trigger_generic_data_rdy_poll,
600
-
IRQF_ONESHOT, "adxrs290_irq", st->dready_trig);
600
+
IRQF_NO_THREAD, "adxrs290_irq", st->dready_trig);
601
601
if (ret < 0)
602
602
return dev_err_probe(&st->spi->dev, ret,
603
603
"request irq %d failed\n", st->spi->irq);
+3
-5
drivers/iio/gyro/itg3200_buffer.c
+3
-5
drivers/iio/gyro/itg3200_buffer.c
···
118
118
if (!st->trig)
119
119
return -ENOMEM;
120
120
121
-
ret = request_irq(st->i2c->irq,
122
-
&iio_trigger_generic_data_rdy_poll,
123
-
IRQF_TRIGGER_RISING,
124
-
"itg3200_data_rdy",
125
-
st->trig);
121
+
ret = request_irq(st->i2c->irq, &iio_trigger_generic_data_rdy_poll,
122
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
123
+
"itg3200_data_rdy", st->trig);
126
124
if (ret)
127
125
goto error_free_trig;
128
126
+2
drivers/iio/gyro/itg3200_core.c
+2
drivers/iio/gyro/itg3200_core.c
+2
-4
drivers/iio/gyro/mpu3050-core.c
+2
-4
drivers/iio/gyro/mpu3050-core.c
···
1162
1162
mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1163
1163
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1164
1164
mpu3050->regs);
1165
-
if (ret) {
1166
-
dev_err(dev, "Cannot get regulators\n");
1167
-
return ret;
1168
-
}
1165
+
if (ret)
1166
+
return dev_err_probe(dev, ret, "Cannot get regulators\n");
1169
1167
1170
1168
ret = mpu3050_power_up(mpu3050);
1171
1169
if (ret)
+4
-5
drivers/iio/health/afe4403.c
+4
-5
drivers/iio/health/afe4403.c
···
540
540
return ret;
541
541
}
542
542
543
-
ret = devm_request_threaded_irq(dev, afe->irq,
544
-
iio_trigger_generic_data_rdy_poll,
545
-
NULL, IRQF_ONESHOT,
546
-
AFE4403_DRIVER_NAME,
547
-
afe->trig);
543
+
ret = devm_request_irq(dev, afe->irq,
544
+
iio_trigger_generic_data_rdy_poll,
545
+
IRQF_NO_THREAD, AFE4403_DRIVER_NAME,
546
+
afe->trig);
548
547
if (ret) {
549
548
dev_err(dev, "Unable to request IRQ\n");
550
549
return ret;
+4
-5
drivers/iio/health/afe4404.c
+4
-5
drivers/iio/health/afe4404.c
···
547
547
return ret;
548
548
}
549
549
550
-
ret = devm_request_threaded_irq(dev, afe->irq,
551
-
iio_trigger_generic_data_rdy_poll,
552
-
NULL, IRQF_ONESHOT,
553
-
AFE4404_DRIVER_NAME,
554
-
afe->trig);
550
+
ret = devm_request_irq(dev, afe->irq,
551
+
iio_trigger_generic_data_rdy_poll,
552
+
IRQF_NO_THREAD, AFE4404_DRIVER_NAME,
553
+
afe->trig);
555
554
if (ret) {
556
555
dev_err(dev, "Unable to request IRQ\n");
557
556
return ret;
+1
-7
drivers/iio/health/max30100.c
+1
-7
drivers/iio/health/max30100.c
···
417
417
* Temperature reading can only be acquired while engine
418
418
* is running
419
419
*/
420
-
if (iio_device_claim_buffer_mode(indio_dev)) {
421
-
/*
422
-
* Replacing -EBUSY or other error code
423
-
* returned by iio_device_claim_buffer_mode()
424
-
* because user space may rely on the current
425
-
* one.
426
-
*/
420
+
if (!iio_device_try_claim_buffer_mode(indio_dev)) {
427
421
ret = -EAGAIN;
428
422
} else {
429
423
ret = max30100_get_temp(data, val);
+9
-24
drivers/iio/health/max30102.c
+9
-24
drivers/iio/health/max30102.c
···
467
467
int *val, int *val2, long mask)
468
468
{
469
469
struct max30102_data *data = iio_priv(indio_dev);
470
-
int ret = -EINVAL;
470
+
int ret;
471
471
472
472
switch (mask) {
473
-
case IIO_CHAN_INFO_RAW:
473
+
case IIO_CHAN_INFO_RAW: {
474
474
/*
475
475
* Temperature reading can only be acquired when not in
476
476
* shutdown; leave shutdown briefly when buffer not running
477
477
*/
478
-
any_mode_retry:
479
-
if (iio_device_claim_buffer_mode(indio_dev)) {
480
-
/*
481
-
* This one is a *bit* hacky. If we cannot claim buffer
482
-
* mode, then try direct mode so that we make sure
483
-
* things cannot concurrently change. And we just keep
484
-
* trying until we get one of the modes...
485
-
*/
486
-
if (!iio_device_claim_direct(indio_dev))
487
-
goto any_mode_retry;
478
+
IIO_DEV_GUARD_CURRENT_MODE(indio_dev);
488
479
489
-
ret = max30102_get_temp(data, val, true);
490
-
iio_device_release_direct(indio_dev);
491
-
} else {
492
-
ret = max30102_get_temp(data, val, false);
493
-
iio_device_release_buffer_mode(indio_dev);
494
-
}
480
+
ret = max30102_get_temp(data, val, !iio_buffer_enabled(indio_dev));
495
481
if (ret)
496
482
return ret;
497
483
498
-
ret = IIO_VAL_INT;
499
-
break;
484
+
return IIO_VAL_INT;
485
+
}
500
486
case IIO_CHAN_INFO_SCALE:
501
487
*val = 1000; /* 62.5 */
502
488
*val2 = 16;
503
-
ret = IIO_VAL_FRACTIONAL;
504
-
break;
489
+
return IIO_VAL_FRACTIONAL;
490
+
default:
491
+
return -EINVAL;
505
492
}
506
-
507
-
return ret;
508
493
}
509
494
510
495
static const struct iio_info max30102_info = {
+3
drivers/iio/imu/bmi270/bmi270_i2c.c
+3
drivers/iio/imu/bmi270/bmi270_i2c.c
···
37
37
{ "bmi270", (kernel_ulong_t)&bmi270_chip_info },
38
38
{ }
39
39
};
40
+
MODULE_DEVICE_TABLE(i2c, bmi270_i2c_id);
40
41
41
42
static const struct acpi_device_id bmi270_acpi_match[] = {
42
43
/* GPD Win Mini, Aya Neo AIR Pro, OXP Mini Pro, etc. */
···
46
45
{ "BMI0260", (kernel_ulong_t)&bmi260_chip_info },
47
46
{ }
48
47
};
48
+
MODULE_DEVICE_TABLE(acpi, bmi270_acpi_match);
49
49
50
50
static const struct of_device_id bmi270_of_match[] = {
51
51
{ .compatible = "bosch,bmi260", .data = &bmi260_chip_info },
52
52
{ .compatible = "bosch,bmi270", .data = &bmi270_chip_info },
53
53
{ }
54
54
};
55
+
MODULE_DEVICE_TABLE(of, bmi270_of_match);
55
56
56
57
static struct i2c_driver bmi270_i2c_driver = {
57
58
.driver = {
-3
drivers/iio/imu/inv_icm42600/inv_icm42600_temp.c
-3
drivers/iio/imu/inv_icm42600/inv_icm42600_temp.c
+2
-7
drivers/iio/imu/smi330/smi330_core.c
+2
-7
drivers/iio/imu/smi330/smi330_core.c
···
67
67
#define SMI330_CHIP_ID 0x42
68
68
#define SMI330_SOFT_RESET_DELAY 2000
69
69
70
-
/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
71
-
#define smi330_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
72
-
#define smi330_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
73
-
74
70
#define SMI330_ACCEL_CHANNEL(_axis) { \
75
71
.type = IIO_ACCEL, \
76
72
.modified = 1, \
···
357
361
if (ret)
358
362
return ret;
359
363
360
-
reg_val = smi330_field_get(attr->mask, reg_val);
364
+
reg_val = field_get(attr->mask, reg_val);
361
365
362
366
if (attr->type == IIO_VAL_INT) {
363
367
for (i = 0; i < attr->len; i++) {
···
406
410
if (ret)
407
411
return ret;
408
412
409
-
reg_val = smi330_field_prep(attr->mask, reg_val);
413
+
reg_val = field_prep(attr->mask, reg_val);
410
414
ret = regmap_update_bits(data->regmap, reg, attr->mask, reg_val);
411
415
if (ret)
412
416
return ret;
···
471
475
*vals = smi330_average_attr.vals;
472
476
*length = smi330_average_attr.len;
473
477
*type = smi330_average_attr.type;
474
-
*type = IIO_VAL_INT;
475
478
return IIO_AVAIL_LIST;
476
479
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
477
480
*vals = smi330_bandwidth_attr.vals;
+32
-23
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
+32
-23
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
···
79
79
#define ST_LSM6DSX_MAX_TAGGED_WORD_LEN ((32 / ST_LSM6DSX_TAGGED_SAMPLE_SIZE) \
80
80
* ST_LSM6DSX_TAGGED_SAMPLE_SIZE)
81
81
#define ST_LSM6DSX_SHIFT_VAL(val, mask) (((val) << __ffs(mask)) & (mask))
82
+
#define st_lsm6dsx_field_get(mask, reg) ((reg & mask) >> __ffs(mask))
82
83
83
-
#define ST_LSM6DSX_CHANNEL_ACC(chan_type, addr, mod, scan_idx) \
84
+
#define ST_LSM6DSX_CHANNEL_ACC(addr, mod, scan_idx, events) \
84
85
{ \
85
-
.type = chan_type, \
86
+
.type = IIO_ACCEL, \
86
87
.address = addr, \
87
88
.modified = 1, \
88
89
.channel2 = mod, \
···
97
96
.storagebits = 16, \
98
97
.endianness = IIO_LE, \
99
98
}, \
100
-
.event_spec = &st_lsm6dsx_event, \
99
+
.event_spec = events, \
100
+
.num_event_specs = ARRAY_SIZE(events), \
101
101
.ext_info = st_lsm6dsx_ext_info, \
102
-
.num_event_specs = 1, \
103
102
}
104
103
105
104
#define ST_LSM6DSX_CHANNEL(chan_type, addr, mod, scan_idx) \
···
261
260
u8 pause;
262
261
};
263
262
263
+
enum st_lsm6dsx_event_id {
264
+
ST_LSM6DSX_EVENT_WAKEUP,
265
+
ST_LSM6DSX_EVENT_TAP,
266
+
ST_LSM6DSX_EVENT_MAX
267
+
};
268
+
269
+
struct st_lsm6dsx_event_src {
270
+
struct st_lsm6dsx_reg value;
271
+
struct st_lsm6dsx_reg x_value;
272
+
struct st_lsm6dsx_reg y_value;
273
+
struct st_lsm6dsx_reg z_value;
274
+
u8 enable_mask;
275
+
u8 enable_axis_reg;
276
+
u8 enable_x_mask;
277
+
u8 enable_y_mask;
278
+
u8 enable_z_mask;
279
+
struct st_lsm6dsx_reg status;
280
+
u8 status_x_mask;
281
+
u8 status_y_mask;
282
+
u8 status_z_mask;
283
+
};
284
+
264
285
struct st_lsm6dsx_event_settings {
265
286
struct st_lsm6dsx_reg enable_reg;
266
-
struct st_lsm6dsx_reg wakeup_reg;
267
-
u8 wakeup_src_reg;
268
-
u8 wakeup_src_status_mask;
269
-
u8 wakeup_src_z_mask;
270
-
u8 wakeup_src_y_mask;
271
-
u8 wakeup_src_x_mask;
287
+
struct st_lsm6dsx_event_src sources[ST_LSM6DSX_EVENT_MAX];
272
288
};
273
289
274
290
enum st_lsm6dsx_sensor_id {
···
371
353
struct {
372
354
struct st_lsm6dsx_reg irq1;
373
355
struct st_lsm6dsx_reg irq2;
374
-
struct st_lsm6dsx_reg irq1_func;
375
-
struct st_lsm6dsx_reg irq2_func;
356
+
u8 irq1_func;
357
+
u8 irq2_func;
376
358
struct st_lsm6dsx_reg lir;
377
359
struct st_lsm6dsx_reg clear_on_read;
378
360
struct st_lsm6dsx_reg hla;
···
448
430
* @sip: Total number of samples (acc/gyro/ts) in a given pattern.
449
431
* @buff: Device read buffer.
450
432
* @irq_routing: pointer to interrupt routing configuration.
451
-
* @event_threshold: wakeup event threshold.
452
433
* @enable_event: enabled event bitmask.
453
434
* @iio_devs: Pointers to acc/gyro iio_dev instances.
454
435
* @settings: Pointer to the specific sensor settings in use.
···
470
453
u8 ts_sip;
471
454
u8 sip;
472
455
473
-
const struct st_lsm6dsx_reg *irq_routing;
474
-
u8 event_threshold;
475
-
u8 enable_event;
456
+
u8 irq_routing;
457
+
u8 enable_event[ST_LSM6DSX_EVENT_MAX];
476
458
477
459
u8 *buff;
478
460
···
485
469
__le16 channels[3];
486
470
aligned_s64 ts;
487
471
} scan[ST_LSM6DSX_ID_MAX];
488
-
};
489
-
490
-
static __maybe_unused const struct iio_event_spec st_lsm6dsx_event = {
491
-
.type = IIO_EV_TYPE_THRESH,
492
-
.dir = IIO_EV_DIR_EITHER,
493
-
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
494
-
BIT(IIO_EV_INFO_ENABLE)
495
472
};
496
473
497
474
static __maybe_unused const unsigned long st_lsm6dsx_available_scan_masks[] = {
+383
-172
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
+383
-172
drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
···
94
94
95
95
#define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
96
96
97
+
static const struct iio_event_spec st_lsm6dsx_ev_motion[] = {
98
+
{
99
+
.type = IIO_EV_TYPE_THRESH,
100
+
.dir = IIO_EV_DIR_EITHER,
101
+
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
102
+
BIT(IIO_EV_INFO_ENABLE),
103
+
},
104
+
};
105
+
106
+
static const struct iio_event_spec st_lsm6dsx_ev_motion_tap[] = {
107
+
{
108
+
.type = IIO_EV_TYPE_THRESH,
109
+
.dir = IIO_EV_DIR_EITHER,
110
+
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
111
+
BIT(IIO_EV_INFO_ENABLE),
112
+
},
113
+
{
114
+
.type = IIO_EV_TYPE_GESTURE,
115
+
.dir = IIO_EV_DIR_SINGLETAP,
116
+
.mask_separate = BIT(IIO_EV_INFO_VALUE) |
117
+
BIT(IIO_EV_INFO_ENABLE),
118
+
},
119
+
};
120
+
97
121
static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = {
98
-
ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0),
99
-
ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1),
100
-
ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2),
122
+
ST_LSM6DSX_CHANNEL_ACC(0x28, IIO_MOD_X, 0, st_lsm6dsx_ev_motion),
123
+
ST_LSM6DSX_CHANNEL_ACC(0x2a, IIO_MOD_Y, 1, st_lsm6dsx_ev_motion),
124
+
ST_LSM6DSX_CHANNEL_ACC(0x2c, IIO_MOD_Z, 2, st_lsm6dsx_ev_motion),
125
+
IIO_CHAN_SOFT_TIMESTAMP(3),
126
+
};
127
+
128
+
static const struct iio_chan_spec st_lsm6dsx_acc_tap_channels[] = {
129
+
ST_LSM6DSX_CHANNEL_ACC(0x28, IIO_MOD_X, 0, st_lsm6dsx_ev_motion_tap),
130
+
ST_LSM6DSX_CHANNEL_ACC(0x2a, IIO_MOD_Y, 1, st_lsm6dsx_ev_motion_tap),
131
+
ST_LSM6DSX_CHANNEL_ACC(0x2c, IIO_MOD_Z, 2, st_lsm6dsx_ev_motion_tap),
101
132
IIO_CHAN_SOFT_TIMESTAMP(3),
102
133
};
103
134
···
357
326
.addr = 0x58,
358
327
.mask = BIT(0),
359
328
},
360
-
.irq1_func = {
361
-
.addr = 0x5e,
362
-
.mask = BIT(5),
363
-
},
364
-
.irq2_func = {
365
-
.addr = 0x5f,
366
-
.mask = BIT(5),
367
-
},
329
+
.irq1_func = 0x5e,
330
+
.irq2_func = 0x5f,
368
331
.hla = {
369
332
.addr = 0x12,
370
333
.mask = BIT(5),
···
411
386
},
412
387
},
413
388
.event_settings = {
414
-
.wakeup_reg = {
415
-
.addr = 0x5B,
416
-
.mask = GENMASK(5, 0),
389
+
.sources = {
390
+
[ST_LSM6DSX_EVENT_WAKEUP] = {
391
+
.value = {
392
+
.addr = 0x5b,
393
+
.mask = GENMASK(5, 0),
394
+
},
395
+
.enable_mask = BIT(5),
396
+
.status = {
397
+
.addr = 0x1b,
398
+
.mask = BIT(3),
399
+
},
400
+
.status_z_mask = BIT(0),
401
+
.status_y_mask = BIT(1),
402
+
.status_x_mask = BIT(2),
403
+
},
417
404
},
418
-
.wakeup_src_reg = 0x1b,
419
-
.wakeup_src_status_mask = BIT(3),
420
-
.wakeup_src_z_mask = BIT(0),
421
-
.wakeup_src_y_mask = BIT(1),
422
-
.wakeup_src_x_mask = BIT(2),
423
405
},
424
406
},
425
407
{
···
524
492
.addr = 0x58,
525
493
.mask = BIT(0),
526
494
},
527
-
.irq1_func = {
528
-
.addr = 0x5e,
529
-
.mask = BIT(5),
530
-
},
531
-
.irq2_func = {
532
-
.addr = 0x5f,
533
-
.mask = BIT(5),
534
-
},
495
+
.irq1_func = 0x5e,
496
+
.irq2_func = 0x5f,
535
497
.hla = {
536
498
.addr = 0x12,
537
499
.mask = BIT(5),
···
578
552
},
579
553
},
580
554
.event_settings = {
581
-
.wakeup_reg = {
582
-
.addr = 0x5B,
583
-
.mask = GENMASK(5, 0),
555
+
.sources = {
556
+
[ST_LSM6DSX_EVENT_WAKEUP] = {
557
+
.value = {
558
+
.addr = 0x5b,
559
+
.mask = GENMASK(5, 0),
560
+
},
561
+
.enable_mask = BIT(5),
562
+
.status = {
563
+
.addr = 0x1b,
564
+
.mask = BIT(3),
565
+
},
566
+
.status_z_mask = BIT(0),
567
+
.status_y_mask = BIT(1),
568
+
.status_x_mask = BIT(2),
569
+
},
584
570
},
585
-
.wakeup_src_reg = 0x1b,
586
-
.wakeup_src_status_mask = BIT(3),
587
-
.wakeup_src_z_mask = BIT(0),
588
-
.wakeup_src_y_mask = BIT(1),
589
-
.wakeup_src_x_mask = BIT(2),
590
571
},
591
572
},
592
573
{
···
721
688
.addr = 0x58,
722
689
.mask = BIT(0),
723
690
},
724
-
.irq1_func = {
725
-
.addr = 0x5e,
726
-
.mask = BIT(5),
727
-
},
728
-
.irq2_func = {
729
-
.addr = 0x5f,
730
-
.mask = BIT(5),
731
-
},
691
+
.irq1_func = 0x5e,
692
+
.irq2_func = 0x5f,
732
693
.hla = {
733
694
.addr = 0x12,
734
695
.mask = BIT(5),
···
816
789
.addr = 0x58,
817
790
.mask = BIT(7),
818
791
},
819
-
.wakeup_reg = {
820
-
.addr = 0x5B,
821
-
.mask = GENMASK(5, 0),
792
+
.sources = {
793
+
[ST_LSM6DSX_EVENT_WAKEUP] = {
794
+
.value = {
795
+
.addr = 0x5b,
796
+
.mask = GENMASK(5, 0),
797
+
},
798
+
.enable_mask = BIT(5),
799
+
.status = {
800
+
.addr = 0x1b,
801
+
.mask = BIT(3),
802
+
},
803
+
.status_z_mask = BIT(0),
804
+
.status_y_mask = BIT(1),
805
+
.status_x_mask = BIT(2),
806
+
},
822
807
},
823
-
.wakeup_src_reg = 0x1b,
824
-
.wakeup_src_status_mask = BIT(3),
825
-
.wakeup_src_z_mask = BIT(0),
826
-
.wakeup_src_y_mask = BIT(1),
827
-
.wakeup_src_x_mask = BIT(2),
828
808
},
829
809
},
830
810
{
···
971
937
.addr = 0x56,
972
938
.mask = BIT(6),
973
939
},
974
-
.irq1_func = {
975
-
.addr = 0x5e,
976
-
.mask = BIT(5),
977
-
},
978
-
.irq2_func = {
979
-
.addr = 0x5f,
980
-
.mask = BIT(5),
981
-
},
940
+
.irq1_func = 0x5e,
941
+
.irq2_func = 0x5f,
982
942
.hla = {
983
943
.addr = 0x12,
984
944
.mask = BIT(5),
···
1056
1028
.addr = 0x58,
1057
1029
.mask = BIT(7),
1058
1030
},
1059
-
.wakeup_reg = {
1060
-
.addr = 0x5b,
1061
-
.mask = GENMASK(5, 0),
1031
+
.sources = {
1032
+
[ST_LSM6DSX_EVENT_WAKEUP] = {
1033
+
.value = {
1034
+
.addr = 0x5b,
1035
+
.mask = GENMASK(5, 0),
1036
+
},
1037
+
.enable_mask = BIT(5),
1038
+
.status = {
1039
+
.addr = 0x1b,
1040
+
.mask = BIT(3),
1041
+
},
1042
+
.status_z_mask = BIT(0),
1043
+
.status_y_mask = BIT(1),
1044
+
.status_x_mask = BIT(2),
1045
+
},
1062
1046
},
1063
-
.wakeup_src_reg = 0x1b,
1064
-
.wakeup_src_status_mask = BIT(3),
1065
-
.wakeup_src_z_mask = BIT(0),
1066
-
.wakeup_src_y_mask = BIT(1),
1067
-
.wakeup_src_x_mask = BIT(2),
1068
1047
},
1069
1048
},
1070
1049
{
···
1187
1152
.addr = 0x56,
1188
1153
.mask = BIT(6),
1189
1154
},
1190
-
.irq1_func = {
1191
-
.addr = 0x5e,
1192
-
.mask = BIT(5),
1193
-
},
1194
-
.irq2_func = {
1195
-
.addr = 0x5f,
1196
-
.mask = BIT(5),
1197
-
},
1155
+
.irq1_func = 0x5e,
1156
+
.irq2_func = 0x5f,
1198
1157
.hla = {
1199
1158
.addr = 0x12,
1200
1159
.mask = BIT(5),
···
1240
1211
.addr = 0x58,
1241
1212
.mask = BIT(7),
1242
1213
},
1243
-
.wakeup_reg = {
1244
-
.addr = 0x5B,
1245
-
.mask = GENMASK(5, 0),
1214
+
.sources = {
1215
+
[ST_LSM6DSX_EVENT_WAKEUP] = {
1216
+
.value = {
1217
+
.addr = 0x5b,
1218
+
.mask = GENMASK(5, 0),
1219
+
},
1220
+
.enable_mask = BIT(5),
1221
+
.status = {
1222
+
.addr = 0x1b,
1223
+
.mask = BIT(3),
1224
+
},
1225
+
.status_z_mask = BIT(0),
1226
+
.status_y_mask = BIT(1),
1227
+
.status_x_mask = BIT(2),
1228
+
},
1246
1229
},
1247
-
.wakeup_src_reg = 0x1b,
1248
-
.wakeup_src_status_mask = BIT(3),
1249
-
.wakeup_src_z_mask = BIT(0),
1250
-
.wakeup_src_y_mask = BIT(1),
1251
-
.wakeup_src_x_mask = BIT(2),
1252
1230
},
1253
1231
},
1254
1232
{
···
1284
1248
},
1285
1249
.channels = {
1286
1250
[ST_LSM6DSX_ID_ACC] = {
1287
-
.chan = st_lsm6dsx_acc_channels,
1288
-
.len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
1251
+
.chan = st_lsm6dsx_acc_tap_channels,
1252
+
.len = ARRAY_SIZE(st_lsm6dsx_acc_tap_channels),
1289
1253
},
1290
1254
[ST_LSM6DSX_ID_GYRO] = {
1291
1255
.chan = st_lsm6dsx_gyro_channels,
···
1365
1329
.addr = 0x56,
1366
1330
.mask = BIT(0),
1367
1331
},
1368
-
.irq1_func = {
1369
-
.addr = 0x5e,
1370
-
.mask = BIT(5),
1371
-
},
1372
-
.irq2_func = {
1373
-
.addr = 0x5f,
1374
-
.mask = BIT(5),
1375
-
},
1332
+
.irq1_func = 0x5e,
1333
+
.irq2_func = 0x5f,
1376
1334
.hla = {
1377
1335
.addr = 0x03,
1378
1336
.mask = BIT(4),
···
1449
1419
.addr = 0x50,
1450
1420
.mask = BIT(7),
1451
1421
},
1452
-
.wakeup_reg = {
1453
-
.addr = 0x5b,
1454
-
.mask = GENMASK(5, 0),
1422
+
.sources = {
1423
+
[ST_LSM6DSX_EVENT_WAKEUP] = {
1424
+
.value = {
1425
+
.addr = 0x5b,
1426
+
.mask = GENMASK(5, 0),
1427
+
},
1428
+
.enable_mask = BIT(5),
1429
+
.status = {
1430
+
.addr = 0x45,
1431
+
.mask = BIT(3),
1432
+
},
1433
+
.status_z_mask = BIT(0),
1434
+
.status_y_mask = BIT(1),
1435
+
.status_x_mask = BIT(2),
1436
+
},
1437
+
[ST_LSM6DSX_EVENT_TAP] = {
1438
+
.x_value = {
1439
+
.addr = 0x57,
1440
+
.mask = GENMASK(4, 0),
1441
+
},
1442
+
.y_value = {
1443
+
.addr = 0x58,
1444
+
.mask = GENMASK(4, 0),
1445
+
},
1446
+
.z_value = {
1447
+
.addr = 0x59,
1448
+
.mask = GENMASK(4, 0),
1449
+
},
1450
+
.enable_mask = BIT(6),
1451
+
.enable_axis_reg = 0x56,
1452
+
.enable_x_mask = BIT(3),
1453
+
.enable_y_mask = BIT(2),
1454
+
.enable_z_mask = BIT(1),
1455
+
.status = {
1456
+
.addr = 0x46,
1457
+
.mask = BIT(5),
1458
+
},
1459
+
.status_x_mask = BIT(2),
1460
+
.status_y_mask = BIT(1),
1461
+
.status_z_mask = BIT(0),
1462
+
},
1455
1463
},
1456
-
.wakeup_src_reg = 0x45,
1457
-
.wakeup_src_status_mask = BIT(3),
1458
-
.wakeup_src_z_mask = BIT(0),
1459
-
.wakeup_src_y_mask = BIT(1),
1460
-
.wakeup_src_x_mask = BIT(2),
1461
1464
},
1462
1465
},
1463
1466
{
···
1817
1754
}
1818
1755
1819
1756
static int
1820
-
st_lsm6dsx_check_events(struct st_lsm6dsx_sensor *sensor, bool enable)
1757
+
st_lsm6dsx_check_events(struct st_lsm6dsx_sensor *sensor)
1821
1758
{
1822
1759
struct st_lsm6dsx_hw *hw = sensor->hw;
1760
+
int event;
1823
1761
1824
-
if (sensor->id == ST_LSM6DSX_ID_GYRO || enable)
1762
+
if (sensor->id != ST_LSM6DSX_ID_ACC)
1825
1763
return 0;
1826
1764
1827
-
return hw->enable_event;
1765
+
for (event = 0; event < ST_LSM6DSX_EVENT_MAX; event++) {
1766
+
if (hw->enable_event[event])
1767
+
return true;
1768
+
}
1769
+
return false;
1828
1770
}
1829
1771
1830
1772
int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1831
1773
bool enable)
1832
1774
{
1833
-
if (st_lsm6dsx_check_events(sensor, enable))
1775
+
if (st_lsm6dsx_check_events(sensor))
1834
1776
return 0;
1835
1777
1836
1778
return __st_lsm6dsx_sensor_set_enable(sensor, enable);
···
1863
1795
if (err < 0)
1864
1796
return err;
1865
1797
1866
-
if (!hw->enable_event) {
1867
-
err = st_lsm6dsx_sensor_set_enable(sensor, false);
1868
-
if (err < 0)
1869
-
return err;
1870
-
}
1798
+
err = st_lsm6dsx_sensor_set_enable(sensor, false);
1799
+
if (err < 0)
1800
+
return err;
1871
1801
1872
1802
*val = (s16)le16_to_cpu(data);
1873
1803
···
1942
1876
return err;
1943
1877
}
1944
1878
1945
-
static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, bool state)
1879
+
static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw,
1880
+
enum st_lsm6dsx_event_id event, int axis,
1881
+
bool state)
1946
1882
{
1947
-
const struct st_lsm6dsx_reg *reg;
1883
+
const struct st_lsm6dsx_event_src *src;
1948
1884
unsigned int data;
1949
1885
int err;
1886
+
u8 old_enable, new_enable;
1950
1887
1951
-
if (!hw->settings->irq_config.irq1_func.addr)
1888
+
if (!hw->irq_routing)
1952
1889
return -ENOTSUPP;
1953
1890
1954
-
reg = &hw->settings->event_settings.enable_reg;
1955
-
if (reg->addr) {
1956
-
data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask);
1957
-
err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1958
-
reg->mask, data);
1959
-
if (err < 0)
1960
-
return err;
1891
+
/* Enable/disable event interrupt */
1892
+
src = &hw->settings->event_settings.sources[event];
1893
+
if (src->enable_axis_reg) {
1894
+
u8 enable_mask;
1895
+
1896
+
switch (axis) {
1897
+
case IIO_MOD_X:
1898
+
enable_mask = src->enable_x_mask;
1899
+
break;
1900
+
case IIO_MOD_Y:
1901
+
enable_mask = src->enable_y_mask;
1902
+
break;
1903
+
case IIO_MOD_Z:
1904
+
enable_mask = src->enable_z_mask;
1905
+
break;
1906
+
default:
1907
+
enable_mask = 0;
1908
+
}
1909
+
if (enable_mask) {
1910
+
data = ST_LSM6DSX_SHIFT_VAL(state, enable_mask);
1911
+
err = st_lsm6dsx_update_bits_locked(hw,
1912
+
src->enable_axis_reg,
1913
+
enable_mask, data);
1914
+
if (err < 0)
1915
+
return err;
1916
+
}
1961
1917
}
1962
1918
1963
-
/* Enable wakeup interrupt */
1964
-
data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask);
1965
-
return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr,
1966
-
hw->irq_routing->mask, data);
1919
+
/*
1920
+
* If the set of axes for which the event source is enabled does not
1921
+
* change from empty to non-empty or vice versa, there is nothing else
1922
+
* to do.
1923
+
*/
1924
+
old_enable = hw->enable_event[event];
1925
+
new_enable = state ? (old_enable | BIT(axis)) :
1926
+
(old_enable & ~BIT(axis));
1927
+
if (!old_enable == !new_enable)
1928
+
return 0;
1929
+
1930
+
data = ST_LSM6DSX_SHIFT_VAL(state, src->enable_mask);
1931
+
return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing,
1932
+
src->enable_mask, data);
1933
+
}
1934
+
1935
+
static enum st_lsm6dsx_event_id
1936
+
st_lsm6dsx_get_event_id(enum iio_event_type type)
1937
+
{
1938
+
switch (type) {
1939
+
case IIO_EV_TYPE_THRESH:
1940
+
return ST_LSM6DSX_EVENT_WAKEUP;
1941
+
case IIO_EV_TYPE_GESTURE:
1942
+
return ST_LSM6DSX_EVENT_TAP;
1943
+
default:
1944
+
return ST_LSM6DSX_EVENT_MAX;
1945
+
}
1946
+
}
1947
+
1948
+
static const struct st_lsm6dsx_reg *
1949
+
st_lsm6dsx_get_event_reg(struct st_lsm6dsx_hw *hw,
1950
+
enum st_lsm6dsx_event_id event,
1951
+
const struct iio_chan_spec *chan)
1952
+
{
1953
+
const struct st_lsm6dsx_event_src *src;
1954
+
const struct st_lsm6dsx_reg *reg;
1955
+
1956
+
src = &hw->settings->event_settings.sources[event];
1957
+
switch (chan->channel2) {
1958
+
case IIO_MOD_X:
1959
+
reg = &src->x_value;
1960
+
break;
1961
+
case IIO_MOD_Y:
1962
+
reg = &src->y_value;
1963
+
break;
1964
+
case IIO_MOD_Z:
1965
+
reg = &src->z_value;
1966
+
break;
1967
+
default:
1968
+
return NULL;
1969
+
}
1970
+
if (reg->addr)
1971
+
return reg;
1972
+
1973
+
/*
1974
+
* The sensor does not support configuring this event source on a per
1975
+
* axis basis: return the register to configure the event source for all
1976
+
* axes.
1977
+
*/
1978
+
return &src->value;
1967
1979
}
1968
1980
1969
1981
static int st_lsm6dsx_read_event(struct iio_dev *iio_dev,
···
2051
1907
enum iio_event_info info,
2052
1908
int *val, int *val2)
2053
1909
{
1910
+
enum st_lsm6dsx_event_id event = st_lsm6dsx_get_event_id(type);
2054
1911
struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2055
1912
struct st_lsm6dsx_hw *hw = sensor->hw;
1913
+
const struct st_lsm6dsx_reg *reg;
1914
+
u8 data;
1915
+
int err;
2056
1916
2057
-
if (type != IIO_EV_TYPE_THRESH)
1917
+
if (event == ST_LSM6DSX_EVENT_MAX)
2058
1918
return -EINVAL;
2059
1919
1920
+
reg = st_lsm6dsx_get_event_reg(hw, event, chan);
1921
+
if (!reg)
1922
+
return -EINVAL;
1923
+
1924
+
err = st_lsm6dsx_read_locked(hw, reg->addr, &data, sizeof(data));
1925
+
if (err < 0)
1926
+
return err;
1927
+
2060
1928
*val2 = 0;
2061
-
*val = hw->event_threshold;
1929
+
*val = st_lsm6dsx_field_get(reg->mask, data);
2062
1930
2063
1931
return IIO_VAL_INT;
2064
1932
}
···
2083
1927
enum iio_event_info info,
2084
1928
int val, int val2)
2085
1929
{
1930
+
enum st_lsm6dsx_event_id event = st_lsm6dsx_get_event_id(type);
2086
1931
struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2087
1932
struct st_lsm6dsx_hw *hw = sensor->hw;
2088
1933
const struct st_lsm6dsx_reg *reg;
2089
1934
unsigned int data;
2090
1935
int err;
2091
1936
2092
-
if (type != IIO_EV_TYPE_THRESH)
1937
+
if (event == ST_LSM6DSX_EVENT_MAX)
2093
1938
return -EINVAL;
2094
1939
2095
1940
if (val < 0 || val > 31)
2096
1941
return -EINVAL;
2097
1942
2098
-
reg = &hw->settings->event_settings.wakeup_reg;
1943
+
reg = st_lsm6dsx_get_event_reg(hw, event, chan);
1944
+
if (!reg)
1945
+
return -EINVAL;
1946
+
2099
1947
data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
2100
1948
err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
2101
1949
reg->mask, data);
2102
1950
if (err < 0)
2103
1951
return -EINVAL;
2104
-
2105
-
hw->event_threshold = val;
2106
1952
2107
1953
return 0;
2108
1954
}
···
2115
1957
enum iio_event_type type,
2116
1958
enum iio_event_direction dir)
2117
1959
{
1960
+
enum st_lsm6dsx_event_id event = st_lsm6dsx_get_event_id(type);
2118
1961
struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2119
1962
struct st_lsm6dsx_hw *hw = sensor->hw;
2120
1963
2121
-
if (type != IIO_EV_TYPE_THRESH)
1964
+
if (event == ST_LSM6DSX_EVENT_MAX)
2122
1965
return -EINVAL;
2123
1966
2124
-
return !!(hw->enable_event & BIT(chan->channel2));
1967
+
return !!(hw->enable_event[event] & BIT(chan->channel2));
1968
+
}
1969
+
1970
+
/**
1971
+
* st_lsm6dsx_check_other_events - Check for enabled sensor events.
1972
+
* @hw: Sensor hardware instance.
1973
+
* @curr: Current event type.
1974
+
*
1975
+
* Return: whether any events other than @curr are enabled.
1976
+
*/
1977
+
static bool st_lsm6dsx_check_other_events(struct st_lsm6dsx_hw *hw,
1978
+
enum st_lsm6dsx_event_id curr)
1979
+
{
1980
+
enum st_lsm6dsx_event_id other;
1981
+
1982
+
for (other = 0; other < ST_LSM6DSX_EVENT_MAX; other++) {
1983
+
if (other != curr && hw->enable_event[other])
1984
+
return true;
1985
+
}
1986
+
1987
+
return false;
1988
+
}
1989
+
1990
+
static int st_lsm6dsx_events_enable(struct st_lsm6dsx_sensor *sensor,
1991
+
bool state)
1992
+
{
1993
+
struct st_lsm6dsx_hw *hw = sensor->hw;
1994
+
const struct st_lsm6dsx_reg *reg;
1995
+
1996
+
reg = &hw->settings->event_settings.enable_reg;
1997
+
if (reg->addr) {
1998
+
int err;
1999
+
2000
+
err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2001
+
ST_LSM6DSX_SHIFT_VAL(state, reg->mask));
2002
+
if (err)
2003
+
return err;
2004
+
}
2005
+
2006
+
if (state || !(hw->fifo_mask & BIT(sensor->id)))
2007
+
return __st_lsm6dsx_sensor_set_enable(sensor, state);
2008
+
2009
+
return 0;
2125
2010
}
2126
2011
2127
2012
static int
···
2173
1972
enum iio_event_type type,
2174
1973
enum iio_event_direction dir, bool state)
2175
1974
{
1975
+
enum st_lsm6dsx_event_id event = st_lsm6dsx_get_event_id(type);
2176
1976
struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
2177
1977
struct st_lsm6dsx_hw *hw = sensor->hw;
2178
1978
u8 enable_event;
2179
1979
int err;
2180
1980
2181
-
if (type != IIO_EV_TYPE_THRESH)
1981
+
if (event == ST_LSM6DSX_EVENT_MAX)
2182
1982
return -EINVAL;
2183
1983
2184
-
if (state) {
2185
-
enable_event = hw->enable_event | BIT(chan->channel2);
2186
-
2187
-
/* do not enable events if they are already enabled */
2188
-
if (hw->enable_event)
2189
-
goto out;
2190
-
} else {
2191
-
enable_event = hw->enable_event & ~BIT(chan->channel2);
2192
-
2193
-
/* only turn off sensor if no events is enabled */
2194
-
if (enable_event)
2195
-
goto out;
2196
-
}
1984
+
if (state)
1985
+
enable_event = hw->enable_event[event] | BIT(chan->channel2);
1986
+
else
1987
+
enable_event = hw->enable_event[event] & ~BIT(chan->channel2);
2197
1988
2198
1989
/* stop here if no changes have been made */
2199
-
if (hw->enable_event == enable_event)
1990
+
if (hw->enable_event[event] == enable_event)
2200
1991
return 0;
2201
1992
2202
-
err = st_lsm6dsx_event_setup(hw, state);
1993
+
err = st_lsm6dsx_event_setup(hw, event, chan->channel2, state);
2203
1994
if (err < 0)
2204
1995
return err;
2205
1996
2206
1997
mutex_lock(&hw->conf_lock);
2207
-
if (enable_event || !(hw->fifo_mask & BIT(sensor->id)))
2208
-
err = __st_lsm6dsx_sensor_set_enable(sensor, state);
1998
+
if (enable_event)
1999
+
err = st_lsm6dsx_events_enable(sensor, true);
2000
+
else if (!st_lsm6dsx_check_other_events(hw, event))
2001
+
err = st_lsm6dsx_events_enable(sensor, false);
2209
2002
mutex_unlock(&hw->conf_lock);
2210
2003
if (err < 0)
2211
2004
return err;
2212
2005
2213
-
out:
2214
-
hw->enable_event = enable_event;
2006
+
hw->enable_event[event] = enable_event;
2215
2007
2216
2008
return 0;
2217
2009
}
···
2345
2151
2346
2152
switch (drdy_pin) {
2347
2153
case 1:
2348
-
hw->irq_routing = &hw->settings->irq_config.irq1_func;
2154
+
hw->irq_routing = hw->settings->irq_config.irq1_func;
2349
2155
*drdy_reg = &hw->settings->irq_config.irq1;
2350
2156
break;
2351
2157
case 2:
2352
-
hw->irq_routing = &hw->settings->irq_config.irq2_func;
2158
+
hw->irq_routing = hw->settings->irq_config.irq2_func;
2353
2159
*drdy_reg = &hw->settings->irq_config.irq2;
2354
2160
break;
2355
2161
default:
···
2608
2414
}
2609
2415
2610
2416
static bool
2611
-
st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw)
2417
+
st_lsm6dsx_report_events(struct st_lsm6dsx_hw *hw, enum st_lsm6dsx_event_id id,
2418
+
enum iio_event_type type, enum iio_event_direction dir)
2612
2419
{
2613
2420
const struct st_lsm6dsx_event_settings *event_settings;
2421
+
const struct st_lsm6dsx_event_src *src;
2614
2422
int err, data;
2615
2423
s64 timestamp;
2616
2424
2617
-
if (!hw->enable_event)
2425
+
if (!hw->enable_event[id])
2618
2426
return false;
2619
2427
2620
2428
event_settings = &hw->settings->event_settings;
2621
-
err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg,
2429
+
src = &event_settings->sources[id];
2430
+
err = st_lsm6dsx_read_locked(hw, src->status.addr,
2622
2431
&data, sizeof(data));
2623
2432
if (err < 0)
2624
2433
return false;
2625
2434
2626
2435
timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
2627
-
if ((data & hw->settings->event_settings.wakeup_src_z_mask) &&
2628
-
(hw->enable_event & BIT(IIO_MOD_Z)))
2436
+
if ((data & src->status_z_mask) &&
2437
+
(hw->enable_event[id] & BIT(IIO_MOD_Z)))
2629
2438
iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2630
2439
IIO_MOD_EVENT_CODE(IIO_ACCEL,
2631
2440
0,
2632
2441
IIO_MOD_Z,
2633
-
IIO_EV_TYPE_THRESH,
2634
-
IIO_EV_DIR_EITHER),
2442
+
type,
2443
+
dir),
2635
2444
timestamp);
2636
2445
2637
-
if ((data & hw->settings->event_settings.wakeup_src_y_mask) &&
2638
-
(hw->enable_event & BIT(IIO_MOD_Y)))
2446
+
if ((data & src->status_y_mask) &&
2447
+
(hw->enable_event[id] & BIT(IIO_MOD_Y)))
2639
2448
iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2640
2449
IIO_MOD_EVENT_CODE(IIO_ACCEL,
2641
2450
0,
2642
2451
IIO_MOD_Y,
2643
-
IIO_EV_TYPE_THRESH,
2644
-
IIO_EV_DIR_EITHER),
2452
+
type,
2453
+
dir),
2645
2454
timestamp);
2646
2455
2647
-
if ((data & hw->settings->event_settings.wakeup_src_x_mask) &&
2648
-
(hw->enable_event & BIT(IIO_MOD_X)))
2456
+
if ((data & src->status_x_mask) &&
2457
+
(hw->enable_event[id] & BIT(IIO_MOD_X)))
2649
2458
iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2650
2459
IIO_MOD_EVENT_CODE(IIO_ACCEL,
2651
2460
0,
2652
2461
IIO_MOD_X,
2653
-
IIO_EV_TYPE_THRESH,
2654
-
IIO_EV_DIR_EITHER),
2462
+
type,
2463
+
dir),
2655
2464
timestamp);
2656
2465
2657
-
return data & event_settings->wakeup_src_status_mask;
2466
+
return data & src->status.mask;
2467
+
}
2468
+
2469
+
static bool st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw)
2470
+
{
2471
+
bool events_found;
2472
+
2473
+
events_found = st_lsm6dsx_report_events(hw, ST_LSM6DSX_EVENT_WAKEUP,
2474
+
IIO_EV_TYPE_THRESH,
2475
+
IIO_EV_DIR_EITHER);
2476
+
events_found |= st_lsm6dsx_report_events(hw, ST_LSM6DSX_EVENT_TAP,
2477
+
IIO_EV_TYPE_GESTURE,
2478
+
IIO_EV_DIR_SINGLETAP);
2479
+
2480
+
return events_found;
2658
2481
}
2659
2482
2660
2483
static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private)
···
2960
2749
continue;
2961
2750
2962
2751
if (device_may_wakeup(dev) &&
2963
-
sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) {
2752
+
st_lsm6dsx_check_events(sensor)) {
2964
2753
/* Enable wake from IRQ */
2965
2754
enable_irq_wake(hw->irq);
2966
2755
continue;
···
2991
2780
2992
2781
sensor = iio_priv(hw->iio_devs[i]);
2993
2782
if (device_may_wakeup(dev) &&
2994
-
sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event)
2783
+
st_lsm6dsx_check_events(sensor))
2995
2784
disable_irq_wake(hw->irq);
2996
2785
2997
2786
if (!(hw->suspend_mask & BIT(sensor->id)))
+16
-70
drivers/iio/industrialio-core.c
+16
-70
drivers/iio/industrialio-core.c
···
2174
2174
EXPORT_SYMBOL_GPL(__devm_iio_device_register);
2175
2175
2176
2176
/**
2177
-
* __iio_device_claim_direct - Keep device in direct mode
2178
-
* @indio_dev: the iio_dev associated with the device
2177
+
* __iio_dev_mode_lock() - Locks the current IIO device mode
2178
+
* @indio_dev: the iio_dev associated with the device
2179
2179
*
2180
-
* If the device is in direct mode it is guaranteed to stay
2181
-
* that way until __iio_device_release_direct() is called.
2180
+
* If the device is either in direct or buffer mode, it's guaranteed to stay
2181
+
* that way until __iio_dev_mode_unlock() is called.
2182
2182
*
2183
-
* Use with __iio_device_release_direct().
2183
+
* This function is not meant to be used directly by drivers to protect internal
2184
+
* state; a driver should have it's own mechanisms for that matter.
2184
2185
*
2185
-
* Drivers should only call iio_device_claim_direct().
2186
-
*
2187
-
* Returns: true on success, false on failure.
2186
+
* There are very few cases where a driver actually needs to lock the current
2187
+
* mode unconditionally. It's recommended to use iio_device_claim_direct() or
2188
+
* iio_device_try_claim_buffer_mode() pairs or related helpers instead.
2188
2189
*/
2189
-
bool __iio_device_claim_direct(struct iio_dev *indio_dev)
2190
+
void __iio_dev_mode_lock(struct iio_dev *indio_dev)
2190
2191
{
2191
-
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
2192
-
2193
-
mutex_lock(&iio_dev_opaque->mlock);
2194
-
2195
-
if (iio_buffer_enabled(indio_dev)) {
2196
-
mutex_unlock(&iio_dev_opaque->mlock);
2197
-
return false;
2198
-
}
2199
-
return true;
2192
+
mutex_lock(&to_iio_dev_opaque(indio_dev)->mlock);
2200
2193
}
2201
-
EXPORT_SYMBOL_GPL(__iio_device_claim_direct);
2194
+
EXPORT_SYMBOL_GPL(__iio_dev_mode_lock);
2202
2195
2203
2196
/**
2204
-
* __iio_device_release_direct - releases claim on direct mode
2205
-
* @indio_dev: the iio_dev associated with the device
2206
-
*
2207
-
* Release the claim. Device is no longer guaranteed to stay
2208
-
* in direct mode.
2209
-
*
2210
-
* Drivers should only call iio_device_release_direct().
2211
-
*
2212
-
* Use with __iio_device_claim_direct()
2197
+
* __iio_dev_mode_unlock() - Unlocks the current IIO device mode
2198
+
* @indio_dev: the iio_dev associated with the device
2213
2199
*/
2214
-
void __iio_device_release_direct(struct iio_dev *indio_dev)
2200
+
void __iio_dev_mode_unlock(struct iio_dev *indio_dev)
2215
2201
{
2216
2202
mutex_unlock(&to_iio_dev_opaque(indio_dev)->mlock);
2217
2203
}
2218
-
EXPORT_SYMBOL_GPL(__iio_device_release_direct);
2219
-
2220
-
/**
2221
-
* iio_device_claim_buffer_mode - Keep device in buffer mode
2222
-
* @indio_dev: the iio_dev associated with the device
2223
-
*
2224
-
* If the device is in buffer mode it is guaranteed to stay
2225
-
* that way until iio_device_release_buffer_mode() is called.
2226
-
*
2227
-
* Use with iio_device_release_buffer_mode().
2228
-
*
2229
-
* Returns: 0 on success, -EBUSY on failure.
2230
-
*/
2231
-
int iio_device_claim_buffer_mode(struct iio_dev *indio_dev)
2232
-
{
2233
-
struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev);
2234
-
2235
-
mutex_lock(&iio_dev_opaque->mlock);
2236
-
2237
-
if (iio_buffer_enabled(indio_dev))
2238
-
return 0;
2239
-
2240
-
mutex_unlock(&iio_dev_opaque->mlock);
2241
-
return -EBUSY;
2242
-
}
2243
-
EXPORT_SYMBOL_GPL(iio_device_claim_buffer_mode);
2244
-
2245
-
/**
2246
-
* iio_device_release_buffer_mode - releases claim on buffer mode
2247
-
* @indio_dev: the iio_dev associated with the device
2248
-
*
2249
-
* Release the claim. Device is no longer guaranteed to stay
2250
-
* in buffer mode.
2251
-
*
2252
-
* Use with iio_device_claim_buffer_mode().
2253
-
*/
2254
-
void iio_device_release_buffer_mode(struct iio_dev *indio_dev)
2255
-
{
2256
-
mutex_unlock(&to_iio_dev_opaque(indio_dev)->mlock);
2257
-
}
2258
-
EXPORT_SYMBOL_GPL(iio_device_release_buffer_mode);
2204
+
EXPORT_SYMBOL_GPL(__iio_dev_mode_unlock);
2259
2205
2260
2206
/**
2261
2207
* iio_device_get_current_mode() - helper function providing read-only access to
+1
-1
drivers/iio/industrialio-sw-device.c
+1
-1
drivers/iio/industrialio-sw-device.c
+1
-1
drivers/iio/industrialio-sw-trigger.c
+1
-1
drivers/iio/industrialio-sw-trigger.c
+6
-6
drivers/iio/light/isl29018.c
+6
-6
drivers/iio/light/isl29018.c
···
273
273
274
274
mutex_lock(&chip->lock);
275
275
for (i = 0; i < ARRAY_SIZE(isl29018_scales[chip->int_time]); ++i)
276
-
len += sprintf(buf + len, "%d.%06d ",
277
-
isl29018_scales[chip->int_time][i].scale,
278
-
isl29018_scales[chip->int_time][i].uscale);
276
+
len += sysfs_emit_at(buf, len, "%d.%06d ",
277
+
isl29018_scales[chip->int_time][i].scale,
278
+
isl29018_scales[chip->int_time][i].uscale);
279
279
mutex_unlock(&chip->lock);
280
280
281
281
buf[len - 1] = '\n';
···
293
293
int len = 0;
294
294
295
295
for (i = 0; i < ARRAY_SIZE(isl29018_int_utimes[chip->type]); ++i)
296
-
len += sprintf(buf + len, "0.%06d ",
297
-
isl29018_int_utimes[chip->type][i]);
296
+
len += sysfs_emit_at(buf, len, "0.%06d ",
297
+
isl29018_int_utimes[chip->type][i]);
298
298
299
299
buf[len - 1] = '\n';
300
300
···
330
330
* Return the "proximity scheme" i.e. if the chip does on chip
331
331
* infrared suppression (1 means perform on chip suppression)
332
332
*/
333
-
return sprintf(buf, "%d\n", chip->prox_scheme);
333
+
return sysfs_emit(buf, "%d\n", chip->prox_scheme);
334
334
}
335
335
336
336
static ssize_t proximity_on_chip_ambient_infrared_suppression_store
+17
-35
drivers/iio/light/opt4060.c
+17
-35
drivers/iio/light/opt4060.c
···
302
302
bool continuous_irq)
303
303
{
304
304
struct opt4060_chip *chip = iio_priv(indio_dev);
305
-
int ret = 0;
306
-
any_mode_retry:
307
-
if (iio_device_claim_buffer_mode(indio_dev)) {
308
-
/*
309
-
* This one is a *bit* hacky. If we cannot claim buffer mode,
310
-
* then try direct mode so that we make sure things cannot
311
-
* concurrently change. And we just keep trying until we get one
312
-
* of the modes...
313
-
*/
314
-
if (!iio_device_claim_direct(indio_dev))
315
-
goto any_mode_retry;
316
-
/*
317
-
* This path means that we managed to claim direct mode. In
318
-
* this case the buffer isn't enabled and it's okay to leave
319
-
* continuous mode for sampling and/or irq.
320
-
*/
321
-
ret = opt4060_set_state_common(chip, continuous_sampling,
322
-
continuous_irq);
323
-
iio_device_release_direct(indio_dev);
324
-
return ret;
325
-
} else {
326
-
/*
327
-
* This path means that we managed to claim buffer mode. In
328
-
* this case the buffer is enabled and irq and sampling must go
329
-
* to or remain continuous, but only if the trigger is from this
330
-
* device.
331
-
*/
332
-
if (!iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
333
-
ret = opt4060_set_state_common(chip, true, true);
334
-
else
335
-
ret = opt4060_set_state_common(chip, continuous_sampling,
336
-
continuous_irq);
337
-
iio_device_release_buffer_mode(indio_dev);
338
-
}
339
-
return ret;
305
+
306
+
IIO_DEV_GUARD_CURRENT_MODE(indio_dev);
307
+
308
+
/*
309
+
* If we manage to claim buffer mode and we are using our own trigger,
310
+
* IRQ and sampling must go to or remain continuous.
311
+
*/
312
+
if (iio_buffer_enabled(indio_dev) &&
313
+
iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
314
+
return opt4060_set_state_common(chip, true, true);
315
+
316
+
/*
317
+
* This path means that we managed to claim direct mode. In this case
318
+
* the buffer isn't enabled and it's okay to leave continuous mode for
319
+
* sampling and/or irq.
320
+
*/
321
+
return opt4060_set_state_common(chip, continuous_sampling, continuous_irq);
340
322
}
341
323
342
324
/*
+1
-1
drivers/iio/light/si1145.c
+1
-1
drivers/iio/light/si1145.c
+18
-31
drivers/iio/light/vcnl4000.c
+18
-31
drivers/iio/light/vcnl4000.c
···
1078
1078
1079
1079
switch (mask) {
1080
1080
case IIO_CHAN_INFO_RAW:
1081
-
case IIO_CHAN_INFO_SCALE:
1082
-
if (!iio_device_claim_direct(indio_dev))
1081
+
case IIO_CHAN_INFO_SCALE: {
1082
+
IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
1083
+
if (IIO_DEV_ACQUIRE_FAILED(claim))
1083
1084
return -EBUSY;
1084
1085
1085
1086
/* Protect against event capture. */
1086
-
if (vcnl4010_is_in_periodic_mode(data)) {
1087
-
ret = -EBUSY;
1088
-
} else {
1089
-
ret = vcnl4000_read_raw(indio_dev, chan, val, val2,
1090
-
mask);
1091
-
}
1087
+
if (vcnl4010_is_in_periodic_mode(data))
1088
+
return -EBUSY;
1092
1089
1093
-
iio_device_release_direct(indio_dev);
1094
-
return ret;
1090
+
return vcnl4000_read_raw(indio_dev, chan, val, val2, mask);
1091
+
}
1095
1092
case IIO_CHAN_INFO_SAMP_FREQ:
1096
1093
switch (chan->type) {
1097
1094
case IIO_PROXIMITY:
···
1145
1148
struct iio_chan_spec const *chan,
1146
1149
int val, int val2, long mask)
1147
1150
{
1148
-
int ret;
1149
1151
struct vcnl4000_data *data = iio_priv(indio_dev);
1150
1152
1151
-
if (!iio_device_claim_direct(indio_dev))
1153
+
IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
1154
+
if (IIO_DEV_ACQUIRE_FAILED(claim))
1152
1155
return -EBUSY;
1153
1156
1154
1157
/* Protect against event capture. */
1155
-
if (vcnl4010_is_in_periodic_mode(data)) {
1156
-
ret = -EBUSY;
1157
-
goto end;
1158
-
}
1158
+
if (vcnl4010_is_in_periodic_mode(data))
1159
+
return -EBUSY;
1159
1160
1160
1161
switch (mask) {
1161
1162
case IIO_CHAN_INFO_SAMP_FREQ:
1162
1163
switch (chan->type) {
1163
1164
case IIO_PROXIMITY:
1164
-
ret = vcnl4010_write_proxy_samp_freq(data, val, val2);
1165
-
goto end;
1165
+
return vcnl4010_write_proxy_samp_freq(data, val, val2);
1166
1166
default:
1167
-
ret = -EINVAL;
1168
-
goto end;
1167
+
return -EINVAL;
1169
1168
}
1170
1169
default:
1171
-
ret = -EINVAL;
1172
-
goto end;
1170
+
return -EINVAL;
1173
1171
}
1174
-
1175
-
end:
1176
-
iio_device_release_direct(indio_dev);
1177
-
return ret;
1178
1172
}
1179
1173
1180
1174
static int vcnl4010_read_event(struct iio_dev *indio_dev,
···
1426
1438
static int vcnl4010_config_threshold(struct iio_dev *indio_dev, bool state)
1427
1439
{
1428
1440
struct vcnl4000_data *data = iio_priv(indio_dev);
1429
-
int ret;
1430
1441
1431
1442
if (state) {
1432
-
if (!iio_device_claim_direct(indio_dev))
1443
+
IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
1444
+
if (IIO_DEV_ACQUIRE_FAILED(claim))
1433
1445
return -EBUSY;
1434
-
ret = vcnl4010_config_threshold_enable(data);
1435
-
iio_device_release_direct(indio_dev);
1436
-
return ret;
1446
+
1447
+
return vcnl4010_config_threshold_enable(data);
1437
1448
} else {
1438
1449
return vcnl4010_config_threshold_disable(data);
1439
1450
}
+13
drivers/iio/magnetometer/Kconfig
+13
drivers/iio/magnetometer/Kconfig
···
139
139
To compile this driver as a module, choose M here: the module
140
140
will be called mmc35240.
141
141
142
+
config MMC5633
143
+
tristate "MEMSIC MMC5633 3-axis magnetic sensor"
144
+
select REGMAP_I2C
145
+
select REGMAP_I3C if I3C
146
+
depends on I2C
147
+
depends on I3C || !I3C
148
+
help
149
+
Say yes here to build support for the MEMSIC MMC5633 3-axis
150
+
magnetic sensor.
151
+
152
+
To compile this driver as a module, choose M here: the module
153
+
will be called mmc5633
154
+
142
155
config IIO_ST_MAGN_3AXIS
143
156
tristate "STMicroelectronics magnetometers 3-Axis Driver"
144
157
depends on (I2C || SPI_MASTER) && SYSFS
+1
drivers/iio/magnetometer/Makefile
+1
drivers/iio/magnetometer/Makefile
+1
-1
drivers/iio/magnetometer/ak8975.c
+1
-1
drivers/iio/magnetometer/ak8975.c
···
581
581
irq = gpiod_to_irq(data->eoc_gpiod);
582
582
583
583
rc = devm_request_irq(&client->dev, irq, ak8975_irq_handler,
584
-
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
584
+
IRQF_TRIGGER_RISING,
585
585
dev_name(&client->dev), data);
586
586
if (rc < 0) {
587
587
dev_err(&client->dev, "irq %d request failed: %d\n", irq, rc);
+3
-6
drivers/iio/magnetometer/bmc150_magn.c
+3
-6
drivers/iio/magnetometer/bmc150_magn.c
···
906
906
goto err_poweroff;
907
907
}
908
908
909
-
ret = request_threaded_irq(irq,
910
-
iio_trigger_generic_data_rdy_poll,
911
-
NULL,
912
-
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
913
-
"bmc150_magn_event",
914
-
data->dready_trig);
909
+
ret = request_irq(irq, iio_trigger_generic_data_rdy_poll,
910
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
911
+
"bmc150_magn_event", data->dready_trig);
915
912
if (ret < 0) {
916
913
dev_err(dev, "request irq %d failed\n", irq);
917
914
goto err_trigger_unregister;
+586
drivers/iio/magnetometer/mmc5633.c
+586
drivers/iio/magnetometer/mmc5633.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* MMC5633 - MEMSIC 3-axis Magnetic Sensor
4
+
*
5
+
* Copyright (c) 2015, Intel Corporation.
6
+
* Copyright (c) 2025, NXP
7
+
*
8
+
* IIO driver for MMC5633, base on mmc35240.c
9
+
*/
10
+
11
+
#include <linux/array_size.h>
12
+
#include <linux/bitfield.h>
13
+
#include <linux/bits.h>
14
+
#include <linux/cleanup.h>
15
+
#include <linux/delay.h>
16
+
#include <linux/device.h>
17
+
#include <linux/dev_printk.h>
18
+
#include <linux/err.h>
19
+
#include <linux/errno.h>
20
+
#include <linux/i2c.h>
21
+
#include <linux/i3c/device.h>
22
+
#include <linux/iio/iio.h>
23
+
#include <linux/iio/sysfs.h>
24
+
#include <linux/init.h>
25
+
#include <linux/iopoll.h>
26
+
#include <linux/module.h>
27
+
#include <linux/mod_devicetable.h>
28
+
#include <linux/mutex.h>
29
+
#include <linux/pm.h>
30
+
#include <linux/regmap.h>
31
+
#include <linux/time.h>
32
+
#include <linux/types.h>
33
+
#include <linux/unaligned.h>
34
+
35
+
#define MMC5633_REG_XOUT0 0x00
36
+
#define MMC5633_REG_XOUT1 0x01
37
+
#define MMC5633_REG_YOUT0 0x02
38
+
#define MMC5633_REG_YOUT1 0x03
39
+
#define MMC5633_REG_ZOUT0 0x04
40
+
#define MMC5633_REG_ZOUT1 0x05
41
+
#define MMC5633_REG_XOUT2 0x06
42
+
#define MMC5633_REG_YOUT2 0x07
43
+
#define MMC5633_REG_ZOUT2 0x08
44
+
#define MMC5633_REG_TOUT 0x09
45
+
46
+
#define MMC5633_REG_STATUS1 0x18
47
+
#define MMC5633_REG_STATUS0 0x19
48
+
#define MMC5633_REG_CTRL0 0x1b
49
+
#define MMC5633_REG_CTRL1 0x1c
50
+
#define MMC5633_REG_CTRL2 0x1d
51
+
52
+
#define MMC5633_REG_ID 0x39
53
+
54
+
#define MMC5633_STATUS1_MEAS_T_DONE_BIT BIT(7)
55
+
#define MMC5633_STATUS1_MEAS_M_DONE_BIT BIT(6)
56
+
57
+
#define MMC5633_CTRL0_CMM_FREQ_EN BIT(7)
58
+
#define MMC5633_CTRL0_AUTO_ST_EN BIT(6)
59
+
#define MMC5633_CTRL0_AUTO_SR_EN BIT(5)
60
+
#define MMC5633_CTRL0_RESET BIT(4)
61
+
#define MMC5633_CTRL0_SET BIT(3)
62
+
#define MMC5633_CTRL0_MEAS_T BIT(1)
63
+
#define MMC5633_CTRL0_MEAS_M BIT(0)
64
+
65
+
#define MMC5633_CTRL1_BW_MASK GENMASK(1, 0)
66
+
67
+
#define MMC5633_WAIT_SET_RESET_US (1 * USEC_PER_MSEC)
68
+
69
+
#define MMC5633_HDR_CTRL0_MEAS_M 0x01
70
+
#define MMC5633_HDR_CTRL0_MEAS_T 0x03
71
+
#define MMC5633_HDR_CTRL0_SET 0x05
72
+
#define MMC5633_HDR_CTRL0_RESET 0x07
73
+
74
+
enum mmc5633_axis {
75
+
MMC5633_AXIS_X,
76
+
MMC5633_AXIS_Y,
77
+
MMC5633_AXIS_Z,
78
+
MMC5633_TEMPERATURE,
79
+
};
80
+
81
+
struct mmc5633_data {
82
+
struct regmap *regmap;
83
+
struct i3c_device *i3cdev;
84
+
struct mutex mutex; /* protect to finish one whole measurement */
85
+
};
86
+
87
+
static int mmc5633_samp_freq[][2] = {
88
+
{ 1, 200000 },
89
+
{ 2, 0 },
90
+
{ 3, 500000 },
91
+
{ 6, 600000 },
92
+
};
93
+
94
+
#define MMC5633_CHANNEL(_axis) { \
95
+
.type = IIO_MAGN, \
96
+
.modified = 1, \
97
+
.channel2 = IIO_MOD_ ## _axis, \
98
+
.address = MMC5633_AXIS_ ## _axis, \
99
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
100
+
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
101
+
BIT(IIO_CHAN_INFO_SCALE), \
102
+
}
103
+
104
+
static const struct iio_chan_spec mmc5633_channels[] = {
105
+
MMC5633_CHANNEL(X),
106
+
MMC5633_CHANNEL(Y),
107
+
MMC5633_CHANNEL(Z),
108
+
{
109
+
.type = IIO_TEMP,
110
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
111
+
BIT(IIO_CHAN_INFO_SCALE) |
112
+
BIT(IIO_CHAN_INFO_OFFSET),
113
+
.address = MMC5633_TEMPERATURE,
114
+
},
115
+
};
116
+
117
+
static int mmc5633_get_samp_freq_index(struct mmc5633_data *data,
118
+
int val, int val2)
119
+
{
120
+
unsigned int i;
121
+
122
+
for (i = 0; i < ARRAY_SIZE(mmc5633_samp_freq); i++)
123
+
if (mmc5633_samp_freq[i][0] == val &&
124
+
mmc5633_samp_freq[i][1] == val2)
125
+
return i;
126
+
return -EINVAL;
127
+
}
128
+
129
+
static int mmc5633_init(struct mmc5633_data *data)
130
+
{
131
+
unsigned int reg_id;
132
+
int ret;
133
+
134
+
ret = regmap_read(data->regmap, MMC5633_REG_ID, ®_id);
135
+
if (ret)
136
+
return dev_err_probe(regmap_get_device(data->regmap), ret,
137
+
"Error reading product id\n");
138
+
139
+
/*
140
+
* Make sure we restore sensor characteristics, by doing
141
+
* a SET/RESET sequence, the axis polarity being naturally
142
+
* aligned after RESET.
143
+
*/
144
+
ret = regmap_write(data->regmap, MMC5633_REG_CTRL0, MMC5633_CTRL0_SET);
145
+
if (ret)
146
+
return ret;
147
+
148
+
/*
149
+
* Minimum time interval between SET or RESET to other operations is
150
+
* 1ms according to Operating Timing Diagram in datasheet.
151
+
*/
152
+
fsleep(MMC5633_WAIT_SET_RESET_US);
153
+
154
+
ret = regmap_write(data->regmap, MMC5633_REG_CTRL0, MMC5633_CTRL0_RESET);
155
+
if (ret)
156
+
return ret;
157
+
158
+
/* set default sampling frequency */
159
+
return regmap_update_bits(data->regmap, MMC5633_REG_CTRL1,
160
+
MMC5633_CTRL1_BW_MASK,
161
+
FIELD_PREP(MMC5633_CTRL1_BW_MASK, 0));
162
+
}
163
+
164
+
static int mmc5633_take_measurement(struct mmc5633_data *data, int address)
165
+
{
166
+
unsigned int reg_status, val;
167
+
int ret;
168
+
169
+
val = (address == MMC5633_TEMPERATURE) ? MMC5633_CTRL0_MEAS_T : MMC5633_CTRL0_MEAS_M;
170
+
ret = regmap_write(data->regmap, MMC5633_REG_CTRL0, val);
171
+
if (ret < 0)
172
+
return ret;
173
+
174
+
val = (address == MMC5633_TEMPERATURE) ?
175
+
MMC5633_STATUS1_MEAS_T_DONE_BIT : MMC5633_STATUS1_MEAS_M_DONE_BIT;
176
+
ret = regmap_read_poll_timeout(data->regmap, MMC5633_REG_STATUS1, reg_status,
177
+
reg_status & val,
178
+
10 * USEC_PER_MSEC,
179
+
100 * 10 * USEC_PER_MSEC);
180
+
if (ret) {
181
+
dev_err(regmap_get_device(data->regmap), "data not ready\n");
182
+
return ret;
183
+
}
184
+
185
+
return 0;
186
+
}
187
+
188
+
static bool mmc5633_is_support_hdr(struct mmc5633_data *data)
189
+
{
190
+
if (!data->i3cdev)
191
+
return false;
192
+
193
+
return i3c_device_get_supported_xfer_mode(data->i3cdev) & BIT(I3C_HDR_DDR);
194
+
}
195
+
196
+
static int mmc5633_read_measurement(struct mmc5633_data *data, int address, void *buf, size_t sz)
197
+
{
198
+
struct device *dev = regmap_get_device(data->regmap);
199
+
u8 data_cmd[2], status[2];
200
+
unsigned int val, ready;
201
+
int ret;
202
+
203
+
if (mmc5633_is_support_hdr(data)) {
204
+
struct i3c_xfer xfers_wr_cmd[] = {
205
+
{
206
+
.cmd = 0x3b,
207
+
.len = 2,
208
+
.data.out = data_cmd,
209
+
}
210
+
};
211
+
struct i3c_xfer xfers_rd_sta_cmd[] = {
212
+
{
213
+
.cmd = 0x23 | BIT(7), /* RDSTA CMD */
214
+
.len = 2,
215
+
.data.in = status,
216
+
},
217
+
};
218
+
struct i3c_xfer xfers_rd_data_cmd[] = {
219
+
{
220
+
.cmd = 0x22 | BIT(7), /* RDLONG CMD */
221
+
.len = sz,
222
+
.data.in = buf,
223
+
},
224
+
};
225
+
226
+
data_cmd[0] = 0;
227
+
data_cmd[1] = (address == MMC5633_TEMPERATURE) ?
228
+
MMC5633_HDR_CTRL0_MEAS_T : MMC5633_HDR_CTRL0_MEAS_M;
229
+
230
+
ret = i3c_device_do_xfers(data->i3cdev, xfers_wr_cmd,
231
+
ARRAY_SIZE(xfers_wr_cmd), I3C_HDR_DDR);
232
+
if (ret < 0)
233
+
return ret;
234
+
235
+
ready = (address == MMC5633_TEMPERATURE) ?
236
+
MMC5633_STATUS1_MEAS_T_DONE_BIT : MMC5633_STATUS1_MEAS_M_DONE_BIT;
237
+
ret = read_poll_timeout(i3c_device_do_xfers, val,
238
+
val || (status[0] & ready),
239
+
10 * USEC_PER_MSEC,
240
+
100 * 10 * USEC_PER_MSEC, 0,
241
+
data->i3cdev, xfers_rd_sta_cmd,
242
+
ARRAY_SIZE(xfers_rd_sta_cmd), I3C_HDR_DDR);
243
+
if (ret) {
244
+
dev_err(dev, "data not ready\n");
245
+
return ret;
246
+
}
247
+
if (val) {
248
+
dev_err(dev, "i3c transfer error\n");
249
+
return val;
250
+
}
251
+
return i3c_device_do_xfers(data->i3cdev, xfers_rd_data_cmd,
252
+
ARRAY_SIZE(xfers_rd_data_cmd), I3C_HDR_DDR);
253
+
}
254
+
255
+
/* Fallback to use SDR/I2C mode */
256
+
ret = mmc5633_take_measurement(data, address);
257
+
if (ret < 0)
258
+
return ret;
259
+
260
+
if (address == MMC5633_TEMPERATURE)
261
+
/*
262
+
* Put tempeature to last byte of buff to align HDR case.
263
+
* I3C will early terminate data read if previous data is not
264
+
* available.
265
+
*/
266
+
return regmap_bulk_read(data->regmap, MMC5633_REG_TOUT, buf + sz - 1, 1);
267
+
268
+
return regmap_bulk_read(data->regmap, MMC5633_REG_XOUT0, buf, sz);
269
+
}
270
+
271
+
/* X,Y,Z 3 channels, each channel has 3 byte and TEMP */
272
+
#define MMC5633_ALL_SIZE (3 * 3 + 1)
273
+
274
+
static int mmc5633_get_raw(struct mmc5633_data *data, int index, unsigned char *buf, int *val)
275
+
{
276
+
if (index == MMC5633_TEMPERATURE) {
277
+
*val = buf[MMC5633_ALL_SIZE - 1];
278
+
return 0;
279
+
}
280
+
/*
281
+
* X[19..12] X[11..4] Y[19..12] Y[11..4] Z[19..12] Z[11..4] X[3..0] Y[3..0] Z[3..0]
282
+
*/
283
+
*val = get_unaligned_be16(buf + 2 * index) << 4;
284
+
*val |= buf[index + 6] >> 4;
285
+
286
+
return 0;
287
+
}
288
+
289
+
static int mmc5633_read_raw(struct iio_dev *indio_dev,
290
+
struct iio_chan_spec const *chan, int *val,
291
+
int *val2, long mask)
292
+
{
293
+
struct mmc5633_data *data = iio_priv(indio_dev);
294
+
char buf[MMC5633_ALL_SIZE];
295
+
unsigned int reg, i;
296
+
int ret;
297
+
298
+
switch (mask) {
299
+
case IIO_CHAN_INFO_RAW:
300
+
scoped_guard(mutex, &data->mutex) {
301
+
ret = mmc5633_read_measurement(data, chan->address, buf, MMC5633_ALL_SIZE);
302
+
if (ret < 0)
303
+
return ret;
304
+
}
305
+
306
+
ret = mmc5633_get_raw(data, chan->address, buf, val);
307
+
if (ret < 0)
308
+
return ret;
309
+
return IIO_VAL_INT;
310
+
case IIO_CHAN_INFO_SCALE:
311
+
if (chan->type == IIO_MAGN) {
312
+
*val = 0;
313
+
*val2 = 62500;
314
+
} else {
315
+
*val = 0;
316
+
*val2 = 800000000; /* 0.8C */
317
+
}
318
+
return IIO_VAL_INT_PLUS_NANO;
319
+
case IIO_CHAN_INFO_OFFSET:
320
+
if (chan->type == IIO_TEMP) {
321
+
*val = -75;
322
+
return IIO_VAL_INT;
323
+
}
324
+
return -EINVAL;
325
+
case IIO_CHAN_INFO_SAMP_FREQ:
326
+
scoped_guard(mutex, &data->mutex) {
327
+
ret = regmap_read(data->regmap, MMC5633_REG_CTRL1, ®);
328
+
if (ret < 0)
329
+
return ret;
330
+
}
331
+
332
+
i = FIELD_GET(MMC5633_CTRL1_BW_MASK, reg);
333
+
if (i >= ARRAY_SIZE(mmc5633_samp_freq))
334
+
return -EINVAL;
335
+
336
+
*val = mmc5633_samp_freq[i][0];
337
+
*val2 = mmc5633_samp_freq[i][1];
338
+
return IIO_VAL_INT_PLUS_MICRO;
339
+
default:
340
+
return -EINVAL;
341
+
}
342
+
}
343
+
344
+
static int mmc5633_write_raw(struct iio_dev *indio_dev,
345
+
struct iio_chan_spec const *chan, int val,
346
+
int val2, long mask)
347
+
{
348
+
struct mmc5633_data *data = iio_priv(indio_dev);
349
+
int ret;
350
+
351
+
switch (mask) {
352
+
case IIO_CHAN_INFO_SAMP_FREQ: {
353
+
ret = mmc5633_get_samp_freq_index(data, val, val2);
354
+
if (ret < 0)
355
+
return ret;
356
+
357
+
guard(mutex)(&data->mutex);
358
+
359
+
return regmap_update_bits(data->regmap, MMC5633_REG_CTRL1,
360
+
MMC5633_CTRL1_BW_MASK,
361
+
FIELD_PREP(MMC5633_CTRL1_BW_MASK, ret));
362
+
}
363
+
default:
364
+
return -EINVAL;
365
+
}
366
+
}
367
+
368
+
static int mmc5633_read_avail(struct iio_dev *indio_dev,
369
+
struct iio_chan_spec const *chan,
370
+
const int **vals, int *type, int *length,
371
+
long mask)
372
+
{
373
+
switch (mask) {
374
+
case IIO_CHAN_INFO_SAMP_FREQ:
375
+
*vals = (const int *)mmc5633_samp_freq;
376
+
*length = ARRAY_SIZE(mmc5633_samp_freq) * 2;
377
+
*type = IIO_VAL_INT_PLUS_MICRO;
378
+
return IIO_AVAIL_LIST;
379
+
default:
380
+
return -EINVAL;
381
+
}
382
+
}
383
+
384
+
static const struct iio_info mmc5633_info = {
385
+
.read_raw = mmc5633_read_raw,
386
+
.write_raw = mmc5633_write_raw,
387
+
.read_avail = mmc5633_read_avail,
388
+
};
389
+
390
+
static bool mmc5633_is_writeable_reg(struct device *dev, unsigned int reg)
391
+
{
392
+
switch (reg) {
393
+
case MMC5633_REG_CTRL0:
394
+
case MMC5633_REG_CTRL1:
395
+
return true;
396
+
default:
397
+
return false;
398
+
}
399
+
}
400
+
401
+
static bool mmc5633_is_readable_reg(struct device *dev, unsigned int reg)
402
+
{
403
+
switch (reg) {
404
+
case MMC5633_REG_XOUT0:
405
+
case MMC5633_REG_XOUT1:
406
+
case MMC5633_REG_YOUT0:
407
+
case MMC5633_REG_YOUT1:
408
+
case MMC5633_REG_ZOUT0:
409
+
case MMC5633_REG_ZOUT1:
410
+
case MMC5633_REG_XOUT2:
411
+
case MMC5633_REG_YOUT2:
412
+
case MMC5633_REG_ZOUT2:
413
+
case MMC5633_REG_TOUT:
414
+
case MMC5633_REG_STATUS1:
415
+
case MMC5633_REG_ID:
416
+
return true;
417
+
default:
418
+
return false;
419
+
}
420
+
}
421
+
422
+
static bool mmc5633_is_volatile_reg(struct device *dev, unsigned int reg)
423
+
{
424
+
switch (reg) {
425
+
case MMC5633_REG_CTRL0:
426
+
case MMC5633_REG_CTRL1:
427
+
return false;
428
+
default:
429
+
return true;
430
+
}
431
+
}
432
+
433
+
static const struct reg_default mmc5633_reg_defaults[] = {
434
+
{ MMC5633_REG_CTRL0, 0x00 },
435
+
{ MMC5633_REG_CTRL1, 0x00 },
436
+
};
437
+
438
+
static const struct regmap_config mmc5633_regmap_config = {
439
+
.name = "mmc5633_regmap",
440
+
441
+
.reg_bits = 8,
442
+
.val_bits = 8,
443
+
444
+
.max_register = MMC5633_REG_ID,
445
+
.cache_type = REGCACHE_MAPLE,
446
+
447
+
.writeable_reg = mmc5633_is_writeable_reg,
448
+
.readable_reg = mmc5633_is_readable_reg,
449
+
.volatile_reg = mmc5633_is_volatile_reg,
450
+
451
+
.reg_defaults = mmc5633_reg_defaults,
452
+
.num_reg_defaults = ARRAY_SIZE(mmc5633_reg_defaults),
453
+
};
454
+
455
+
static int mmc5633_common_probe(struct regmap *regmap, char *name,
456
+
struct i3c_device *i3cdev)
457
+
{
458
+
struct device *dev = regmap_get_device(regmap);
459
+
struct mmc5633_data *data;
460
+
struct iio_dev *indio_dev;
461
+
int ret;
462
+
463
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
464
+
if (!indio_dev)
465
+
return -ENOMEM;
466
+
467
+
data = iio_priv(indio_dev);
468
+
469
+
data->regmap = regmap;
470
+
data->i3cdev = i3cdev;
471
+
472
+
ret = devm_mutex_init(dev, &data->mutex);
473
+
if (ret)
474
+
return ret;
475
+
476
+
indio_dev->info = &mmc5633_info;
477
+
indio_dev->name = name;
478
+
indio_dev->channels = mmc5633_channels;
479
+
indio_dev->num_channels = ARRAY_SIZE(mmc5633_channels);
480
+
indio_dev->modes = INDIO_DIRECT_MODE;
481
+
482
+
ret = mmc5633_init(data);
483
+
if (ret < 0)
484
+
return dev_err_probe(dev, ret, "mmc5633 chip init failed\n");
485
+
486
+
return devm_iio_device_register(dev, indio_dev);
487
+
}
488
+
489
+
static int mmc5633_suspend(struct device *dev)
490
+
{
491
+
struct regmap *regmap = dev_get_regmap(dev, NULL);
492
+
493
+
regcache_cache_only(regmap, true);
494
+
495
+
return 0;
496
+
}
497
+
498
+
static int mmc5633_resume(struct device *dev)
499
+
{
500
+
struct regmap *regmap = dev_get_regmap(dev, NULL);
501
+
int ret;
502
+
503
+
regcache_mark_dirty(regmap);
504
+
ret = regcache_sync_region(regmap, MMC5633_REG_CTRL0, MMC5633_REG_CTRL1);
505
+
if (ret)
506
+
dev_err(dev, "Failed to restore control registers\n");
507
+
508
+
regcache_cache_only(regmap, false);
509
+
510
+
return 0;
511
+
}
512
+
513
+
static int mmc5633_i2c_probe(struct i2c_client *client)
514
+
{
515
+
struct device *dev = &client->dev;
516
+
struct regmap *regmap;
517
+
518
+
regmap = devm_regmap_init_i2c(client, &mmc5633_regmap_config);
519
+
if (IS_ERR(regmap))
520
+
return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n");
521
+
522
+
return mmc5633_common_probe(regmap, client->name, NULL);
523
+
}
524
+
525
+
static DEFINE_SIMPLE_DEV_PM_OPS(mmc5633_pm_ops, mmc5633_suspend, mmc5633_resume);
526
+
527
+
static const struct of_device_id mmc5633_of_match[] = {
528
+
{ .compatible = "memsic,mmc5603" },
529
+
{ .compatible = "memsic,mmc5633" },
530
+
{ }
531
+
};
532
+
MODULE_DEVICE_TABLE(of, mmc5633_of_match);
533
+
534
+
static const struct i2c_device_id mmc5633_i2c_id[] = {
535
+
{ "mmc5603" },
536
+
{ "mmc5633" },
537
+
{ }
538
+
};
539
+
MODULE_DEVICE_TABLE(i2c, mmc5633_i2c_id);
540
+
541
+
static struct i2c_driver mmc5633_i2c_driver = {
542
+
.driver = {
543
+
.name = "mmc5633_i2c",
544
+
.of_match_table = mmc5633_of_match,
545
+
.pm = pm_sleep_ptr(&mmc5633_pm_ops),
546
+
},
547
+
.probe = mmc5633_i2c_probe,
548
+
.id_table = mmc5633_i2c_id,
549
+
};
550
+
551
+
static const struct i3c_device_id mmc5633_i3c_ids[] = {
552
+
I3C_DEVICE(0x0251, 0x0000, NULL),
553
+
{ }
554
+
};
555
+
MODULE_DEVICE_TABLE(i3c, mmc5633_i3c_ids);
556
+
557
+
static int mmc5633_i3c_probe(struct i3c_device *i3cdev)
558
+
{
559
+
struct device *dev = i3cdev_to_dev(i3cdev);
560
+
struct regmap *regmap;
561
+
char *name;
562
+
563
+
name = devm_kasprintf(dev, GFP_KERNEL, "mmc5633_%s", dev_name(dev));
564
+
if (!name)
565
+
return -ENOMEM;
566
+
567
+
regmap = devm_regmap_init_i3c(i3cdev, &mmc5633_regmap_config);
568
+
if (IS_ERR(regmap))
569
+
return dev_err_probe(dev, PTR_ERR(regmap),
570
+
"Failed to register i3c regmap\n");
571
+
572
+
return mmc5633_common_probe(regmap, name, i3cdev);
573
+
}
574
+
575
+
static struct i3c_driver mmc5633_i3c_driver = {
576
+
.driver = {
577
+
.name = "mmc5633_i3c",
578
+
},
579
+
.probe = mmc5633_i3c_probe,
580
+
.id_table = mmc5633_i3c_ids,
581
+
};
582
+
module_i3c_i2c_driver(mmc5633_i3c_driver, &mmc5633_i2c_driver)
583
+
584
+
MODULE_AUTHOR("Frank Li <Frank.li@nxp.com>");
585
+
MODULE_DESCRIPTION("MEMSIC MMC5633 magnetic sensor driver");
586
+
MODULE_LICENSE("GPL");
+48
-15
drivers/iio/pressure/Kconfig
+48
-15
drivers/iio/pressure/Kconfig
···
16
16
To compile this driver as a module, choose M here: the module
17
17
will be called abp060mg.
18
18
19
+
config ABP2030PA
20
+
tristate
21
+
select IIO_BUFFER
22
+
select IIO_TRIGGERED_BUFFER
23
+
24
+
config ABP2030PA_I2C
25
+
tristate "Honeywell ABP2 pressure sensor series I2C driver"
26
+
depends on I2C
27
+
select ABP2030PA
28
+
help
29
+
Say Y here to build I2C bus support for the Honeywell ABP2
30
+
series pressure and temperature digital sensor.
31
+
32
+
To compile this driver as a module, choose M here: the module
33
+
will be called abp2030pa_i2c and you will also get abp2030pa
34
+
for the core module.
35
+
36
+
config ABP2030PA_SPI
37
+
tristate "Honeywell ABP2 pressure sensor series SPI driver"
38
+
depends on SPI_MASTER
39
+
select ABP2030PA
40
+
help
41
+
Say Y here to build SPI bus support for the Honeywell ABP2
42
+
series pressure and temperature digital sensor.
43
+
44
+
To compile this driver as a module, choose M here: the module
45
+
will be called abp2030pa_spi and you will also get abp2030pa
46
+
for the core module.
47
+
19
48
config ROHM_BM1390
20
49
tristate "ROHM BM1390GLV-Z pressure sensor driver"
21
50
depends on I2C
···
216
187
will be called mpl3115.
217
188
218
189
config MPRLS0025PA
219
-
tristate "Honeywell MPRLS0025PA (MicroPressure sensors series)"
220
-
depends on (I2C || SPI_MASTER)
221
-
select MPRLS0025PA_I2C if I2C
222
-
select MPRLS0025PA_SPI if SPI_MASTER
190
+
tristate
223
191
select IIO_BUFFER
224
192
select IIO_TRIGGERED_BUFFER
225
-
help
226
-
Say Y here to build support for the Honeywell MicroPressure pressure
227
-
sensor series. There are many different types with different pressure
228
-
range. These ranges can be set up in the device tree.
229
-
230
-
To compile this driver as a module, choose M here: the module will be
231
-
called mprls0025pa.
232
193
233
194
config MPRLS0025PA_I2C
234
-
tristate
235
-
depends on MPRLS0025PA
195
+
tristate "Honeywell MPR pressure sensor series I2C driver"
236
196
depends on I2C
197
+
select MPRLS0025PA
198
+
help
199
+
Say Y here to build I2C bus support for the Honeywell MicroPressure
200
+
series sensor.
201
+
202
+
To compile this driver as a module, choose M here: the module
203
+
will be called mprls0025pa_i2c and you will also get mprls0025pa
204
+
for the core module.
237
205
238
206
config MPRLS0025PA_SPI
239
-
tristate
240
-
depends on MPRLS0025PA
207
+
tristate "Honeywell MPR pressure sensor series SPI driver"
241
208
depends on SPI_MASTER
209
+
select MPRLS0025PA
210
+
help
211
+
Say Y here to build SPI bus support for the Honeywell MicroPressure
212
+
series sensor.
213
+
214
+
To compile this driver as a module, choose M here: the module
215
+
will be called mprls0025pa_spi and you will also get mprls0025pa
216
+
for the core module.
242
217
243
218
config MS5611
244
219
tristate "Measurement Specialties MS5611 pressure sensor driver"
+3
drivers/iio/pressure/Makefile
+3
drivers/iio/pressure/Makefile
···
5
5
6
6
# When adding new entries keep the list in alphabetical order
7
7
obj-$(CONFIG_ABP060MG) += abp060mg.o
8
+
obj-$(CONFIG_ABP2030PA) += abp2030pa.o
9
+
obj-$(CONFIG_ABP2030PA_I2C) += abp2030pa_i2c.o
10
+
obj-$(CONFIG_ABP2030PA_SPI) += abp2030pa_spi.o
8
11
obj-$(CONFIG_ADP810) += adp810.o
9
12
obj-$(CONFIG_ROHM_BM1390) += rohm-bm1390.o
10
13
obj-$(CONFIG_BMP280) += bmp280.o
+544
drivers/iio/pressure/abp2030pa.c
+544
drivers/iio/pressure/abp2030pa.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Honeywell ABP2 series pressure sensor driver
4
+
*
5
+
* Copyright (c) 2025 Petre Rodan <petre.rodan@subdimension.ro>
6
+
*
7
+
* Datasheet: https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/basic-abp2-series/documents/sps-siot-abp2-series-datasheet-32350268-en.pdf
8
+
*/
9
+
10
+
#include <linux/array_size.h>
11
+
#include <linux/bits.h>
12
+
#include <linux/completion.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/dev_printk.h>
15
+
#include <linux/device.h>
16
+
#include <linux/errno.h>
17
+
#include <linux/export.h>
18
+
#include <linux/gpio/consumer.h>
19
+
#include <linux/interrupt.h>
20
+
#include <linux/jiffies.h>
21
+
#include <linux/math64.h>
22
+
#include <linux/module.h>
23
+
#include <linux/property.h>
24
+
#include <linux/regulator/consumer.h>
25
+
#include <linux/string.h>
26
+
#include <linux/time.h>
27
+
#include <linux/types.h>
28
+
#include <linux/unaligned.h>
29
+
#include <linux/units.h>
30
+
31
+
#include <linux/iio/buffer.h>
32
+
#include <linux/iio/iio.h>
33
+
#include <linux/iio/trigger_consumer.h>
34
+
#include <linux/iio/triggered_buffer.h>
35
+
36
+
#include "abp2030pa.h"
37
+
38
+
/* Status byte flags */
39
+
#define ABP2_ST_POWER BIT(6) /* 1 if device is powered */
40
+
#define ABP2_ST_BUSY BIT(5) /* 1 if device is busy */
41
+
42
+
#define ABP2_CMD_NOP 0xf0
43
+
#define ABP2_CMD_SYNC 0xaa
44
+
#define ABP2_PKT_SYNC_LEN 3
45
+
#define ABP2_PKT_NOP_LEN ABP2_MEASUREMENT_RD_SIZE
46
+
47
+
struct abp2_func_spec {
48
+
u32 output_min;
49
+
u32 output_max;
50
+
};
51
+
52
+
/* transfer function A: 10% to 90% of 2^24 */
53
+
static const struct abp2_func_spec abp2_func_spec[] = {
54
+
[ABP2_FUNCTION_A] = { .output_min = 1677722, .output_max = 15099494 },
55
+
};
56
+
57
+
enum abp2_variants {
58
+
ABP2001BA, ABP21_6BA, ABP22_5BA, ABP2004BA, ABP2006BA, ABP2008BA,
59
+
ABP2010BA, ABP2012BA, ABP2001BD, ABP21_6BD, ABP22_5BD, ABP2004BD,
60
+
ABP2001BG, ABP21_6BG, ABP22_5BG, ABP2004BG, ABP2006BG, ABP2008BG,
61
+
ABP2010BG, ABP2012BG, ABP2001GG, ABP21_2GG, ABP2100KA, ABP2160KA,
62
+
ABP2250KA, ABP2001KD, ABP21_6KD, ABP22_5KD, ABP2004KD, ABP2006KD,
63
+
ABP2010KD, ABP2016KD, ABP2025KD, ABP2040KD, ABP2060KD, ABP2100KD,
64
+
ABP2160KD, ABP2250KD, ABP2400KD, ABP2001KG, ABP21_6KG, ABP22_5KG,
65
+
ABP2004KG, ABP2006KG, ABP2010KG, ABP2016KG, ABP2025KG, ABP2040KG,
66
+
ABP2060KG, ABP2100KG, ABP2160KG, ABP2250KG, ABP2400KG, ABP2600KG,
67
+
ABP2800KG, ABP2250LD, ABP2600LD, ABP2600LG, ABP22_5MD, ABP2006MD,
68
+
ABP2010MD, ABP2016MD, ABP2025MD, ABP2040MD, ABP2060MD, ABP2100MD,
69
+
ABP2160MD, ABP2250MD, ABP2400MD, ABP2600MD, ABP2006MG, ABP2010MG,
70
+
ABP2016MG, ABP2025MG, ABP2040MG, ABP2060MG, ABP2100MG, ABP2160MG,
71
+
ABP2250MG, ABP2400MG, ABP2600MG, ABP2001ND, ABP2002ND, ABP2004ND,
72
+
ABP2005ND, ABP2010ND, ABP2020ND, ABP2030ND, ABP2002NG, ABP2004NG,
73
+
ABP2005NG, ABP2010NG, ABP2020NG, ABP2030NG, ABP2015PA, ABP2030PA,
74
+
ABP2060PA, ABP2100PA, ABP2150PA, ABP2175PA, ABP2001PD, ABP2005PD,
75
+
ABP2015PD, ABP2030PD, ABP2060PD, ABP2001PG, ABP2005PG, ABP2015PG,
76
+
ABP2030PG, ABP2060PG, ABP2100PG, ABP2150PG, ABP2175PG,
77
+
};
78
+
79
+
static const char * const abp2_triplet_variants[] = {
80
+
[ABP2001BA] = "001BA", [ABP21_6BA] = "1.6BA", [ABP22_5BA] = "2.5BA",
81
+
[ABP2004BA] = "004BA", [ABP2006BA] = "006BA", [ABP2008BA] = "008BA",
82
+
[ABP2010BA] = "010BA", [ABP2012BA] = "012BA", [ABP2001BD] = "001BD",
83
+
[ABP21_6BD] = "1.6BD", [ABP22_5BD] = "2.5BD", [ABP2004BD] = "004BD",
84
+
[ABP2001BG] = "001BG", [ABP21_6BG] = "1.6BG", [ABP22_5BG] = "2.5BG",
85
+
[ABP2004BG] = "004BG", [ABP2006BG] = "006BG", [ABP2008BG] = "008BG",
86
+
[ABP2010BG] = "010BG", [ABP2012BG] = "012BG", [ABP2001GG] = "001GG",
87
+
[ABP21_2GG] = "1.2GG", [ABP2100KA] = "100KA", [ABP2160KA] = "160KA",
88
+
[ABP2250KA] = "250KA", [ABP2001KD] = "001KD", [ABP21_6KD] = "1.6KD",
89
+
[ABP22_5KD] = "2.5KD", [ABP2004KD] = "004KD", [ABP2006KD] = "006KD",
90
+
[ABP2010KD] = "010KD", [ABP2016KD] = "016KD", [ABP2025KD] = "025KD",
91
+
[ABP2040KD] = "040KD", [ABP2060KD] = "060KD", [ABP2100KD] = "100KD",
92
+
[ABP2160KD] = "160KD", [ABP2250KD] = "250KD", [ABP2400KD] = "400KD",
93
+
[ABP2001KG] = "001KG", [ABP21_6KG] = "1.6KG", [ABP22_5KG] = "2.5KG",
94
+
[ABP2004KG] = "004KG", [ABP2006KG] = "006KG", [ABP2010KG] = "010KG",
95
+
[ABP2016KG] = "016KG", [ABP2025KG] = "025KG", [ABP2040KG] = "040KG",
96
+
[ABP2060KG] = "060KG", [ABP2100KG] = "100KG", [ABP2160KG] = "160KG",
97
+
[ABP2250KG] = "250KG", [ABP2400KG] = "400KG", [ABP2600KG] = "600KG",
98
+
[ABP2800KG] = "800KG", [ABP2250LD] = "250LD", [ABP2600LD] = "600LD",
99
+
[ABP2600LG] = "600LG", [ABP22_5MD] = "2.5MD", [ABP2006MD] = "006MD",
100
+
[ABP2010MD] = "010MD", [ABP2016MD] = "016MD", [ABP2025MD] = "025MD",
101
+
[ABP2040MD] = "040MD", [ABP2060MD] = "060MD", [ABP2100MD] = "100MD",
102
+
[ABP2160MD] = "160MD", [ABP2250MD] = "250MD", [ABP2400MD] = "400MD",
103
+
[ABP2600MD] = "600MD", [ABP2006MG] = "006MG", [ABP2010MG] = "010MG",
104
+
[ABP2016MG] = "016MG", [ABP2025MG] = "025MG", [ABP2040MG] = "040MG",
105
+
[ABP2060MG] = "060MG", [ABP2100MG] = "100MG", [ABP2160MG] = "160MG",
106
+
[ABP2250MG] = "250MG", [ABP2400MG] = "400MG", [ABP2600MG] = "600MG",
107
+
[ABP2001ND] = "001ND", [ABP2002ND] = "002ND", [ABP2004ND] = "004ND",
108
+
[ABP2005ND] = "005ND", [ABP2010ND] = "010ND", [ABP2020ND] = "020ND",
109
+
[ABP2030ND] = "030ND", [ABP2002NG] = "002NG", [ABP2004NG] = "004NG",
110
+
[ABP2005NG] = "005NG", [ABP2010NG] = "010NG", [ABP2020NG] = "020NG",
111
+
[ABP2030NG] = "030NG", [ABP2015PA] = "015PA", [ABP2030PA] = "030PA",
112
+
[ABP2060PA] = "060PA", [ABP2100PA] = "100PA", [ABP2150PA] = "150PA",
113
+
[ABP2175PA] = "175PA", [ABP2001PD] = "001PD", [ABP2005PD] = "005PD",
114
+
[ABP2015PD] = "015PD", [ABP2030PD] = "030PD", [ABP2060PD] = "060PD",
115
+
[ABP2001PG] = "001PG", [ABP2005PG] = "005PG", [ABP2015PG] = "015PG",
116
+
[ABP2030PG] = "030PG", [ABP2060PG] = "060PG", [ABP2100PG] = "100PG",
117
+
[ABP2150PG] = "150PG", [ABP2175PG] = "175PG",
118
+
};
119
+
120
+
/**
121
+
* struct abp2_range_config - list of pressure ranges based on nomenclature
122
+
* @pmin: lowest pressure that can be measured
123
+
* @pmax: highest pressure that can be measured
124
+
*/
125
+
struct abp2_range_config {
126
+
s32 pmin;
127
+
s32 pmax;
128
+
};
129
+
130
+
/* All min max limits have been converted to pascals */
131
+
static const struct abp2_range_config abp2_range_config[] = {
132
+
[ABP2001BA] = { .pmin = 0, .pmax = 100000 },
133
+
[ABP21_6BA] = { .pmin = 0, .pmax = 160000 },
134
+
[ABP22_5BA] = { .pmin = 0, .pmax = 250000 },
135
+
[ABP2004BA] = { .pmin = 0, .pmax = 400000 },
136
+
[ABP2006BA] = { .pmin = 0, .pmax = 600000 },
137
+
[ABP2008BA] = { .pmin = 0, .pmax = 800000 },
138
+
[ABP2010BA] = { .pmin = 0, .pmax = 1000000 },
139
+
[ABP2012BA] = { .pmin = 0, .pmax = 1200000 },
140
+
[ABP2001BD] = { .pmin = -100000, .pmax = 100000 },
141
+
[ABP21_6BD] = { .pmin = -160000, .pmax = 160000 },
142
+
[ABP22_5BD] = { .pmin = -250000, .pmax = 250000 },
143
+
[ABP2004BD] = { .pmin = -400000, .pmax = 400000 },
144
+
[ABP2001BG] = { .pmin = 0, .pmax = 100000 },
145
+
[ABP21_6BG] = { .pmin = 0, .pmax = 160000 },
146
+
[ABP22_5BG] = { .pmin = 0, .pmax = 250000 },
147
+
[ABP2004BG] = { .pmin = 0, .pmax = 400000 },
148
+
[ABP2006BG] = { .pmin = 0, .pmax = 600000 },
149
+
[ABP2008BG] = { .pmin = 0, .pmax = 800000 },
150
+
[ABP2010BG] = { .pmin = 0, .pmax = 1000000 },
151
+
[ABP2012BG] = { .pmin = 0, .pmax = 1200000 },
152
+
[ABP2001GG] = { .pmin = 0, .pmax = 1000000 },
153
+
[ABP21_2GG] = { .pmin = 0, .pmax = 1200000 },
154
+
[ABP2100KA] = { .pmin = 0, .pmax = 100000 },
155
+
[ABP2160KA] = { .pmin = 0, .pmax = 160000 },
156
+
[ABP2250KA] = { .pmin = 0, .pmax = 250000 },
157
+
[ABP2001KD] = { .pmin = -1000, .pmax = 1000 },
158
+
[ABP21_6KD] = { .pmin = -1600, .pmax = 1600 },
159
+
[ABP22_5KD] = { .pmin = -2500, .pmax = 2500 },
160
+
[ABP2004KD] = { .pmin = -4000, .pmax = 4000 },
161
+
[ABP2006KD] = { .pmin = -6000, .pmax = 6000 },
162
+
[ABP2010KD] = { .pmin = -10000, .pmax = 10000 },
163
+
[ABP2016KD] = { .pmin = -16000, .pmax = 16000 },
164
+
[ABP2025KD] = { .pmin = -25000, .pmax = 25000 },
165
+
[ABP2040KD] = { .pmin = -40000, .pmax = 40000 },
166
+
[ABP2060KD] = { .pmin = -60000, .pmax = 60000 },
167
+
[ABP2100KD] = { .pmin = -100000, .pmax = 100000 },
168
+
[ABP2160KD] = { .pmin = -160000, .pmax = 160000 },
169
+
[ABP2250KD] = { .pmin = -250000, .pmax = 250000 },
170
+
[ABP2400KD] = { .pmin = -400000, .pmax = 400000 },
171
+
[ABP2001KG] = { .pmin = 0, .pmax = 1000 },
172
+
[ABP21_6KG] = { .pmin = 0, .pmax = 1600 },
173
+
[ABP22_5KG] = { .pmin = 0, .pmax = 2500 },
174
+
[ABP2004KG] = { .pmin = 0, .pmax = 4000 },
175
+
[ABP2006KG] = { .pmin = 0, .pmax = 6000 },
176
+
[ABP2010KG] = { .pmin = 0, .pmax = 10000 },
177
+
[ABP2016KG] = { .pmin = 0, .pmax = 16000 },
178
+
[ABP2025KG] = { .pmin = 0, .pmax = 25000 },
179
+
[ABP2040KG] = { .pmin = 0, .pmax = 40000 },
180
+
[ABP2060KG] = { .pmin = 0, .pmax = 60000 },
181
+
[ABP2100KG] = { .pmin = 0, .pmax = 100000 },
182
+
[ABP2160KG] = { .pmin = 0, .pmax = 160000 },
183
+
[ABP2250KG] = { .pmin = 0, .pmax = 250000 },
184
+
[ABP2400KG] = { .pmin = 0, .pmax = 400000 },
185
+
[ABP2600KG] = { .pmin = 0, .pmax = 600000 },
186
+
[ABP2800KG] = { .pmin = 0, .pmax = 800000 },
187
+
[ABP2250LD] = { .pmin = -250, .pmax = 250 },
188
+
[ABP2600LD] = { .pmin = -600, .pmax = 600 },
189
+
[ABP2600LG] = { .pmin = 0, .pmax = 600 },
190
+
[ABP22_5MD] = { .pmin = -250, .pmax = 250 },
191
+
[ABP2006MD] = { .pmin = -600, .pmax = 600 },
192
+
[ABP2010MD] = { .pmin = -1000, .pmax = 1000 },
193
+
[ABP2016MD] = { .pmin = -1600, .pmax = 1600 },
194
+
[ABP2025MD] = { .pmin = -2500, .pmax = 2500 },
195
+
[ABP2040MD] = { .pmin = -4000, .pmax = 4000 },
196
+
[ABP2060MD] = { .pmin = -6000, .pmax = 6000 },
197
+
[ABP2100MD] = { .pmin = -10000, .pmax = 10000 },
198
+
[ABP2160MD] = { .pmin = -16000, .pmax = 16000 },
199
+
[ABP2250MD] = { .pmin = -25000, .pmax = 25000 },
200
+
[ABP2400MD] = { .pmin = -40000, .pmax = 40000 },
201
+
[ABP2600MD] = { .pmin = -60000, .pmax = 60000 },
202
+
[ABP2006MG] = { .pmin = 0, .pmax = 600 },
203
+
[ABP2010MG] = { .pmin = 0, .pmax = 1000 },
204
+
[ABP2016MG] = { .pmin = 0, .pmax = 1600 },
205
+
[ABP2025MG] = { .pmin = 0, .pmax = 2500 },
206
+
[ABP2040MG] = { .pmin = 0, .pmax = 4000 },
207
+
[ABP2060MG] = { .pmin = 0, .pmax = 6000 },
208
+
[ABP2100MG] = { .pmin = 0, .pmax = 10000 },
209
+
[ABP2160MG] = { .pmin = 0, .pmax = 16000 },
210
+
[ABP2250MG] = { .pmin = 0, .pmax = 25000 },
211
+
[ABP2400MG] = { .pmin = 0, .pmax = 40000 },
212
+
[ABP2600MG] = { .pmin = 0, .pmax = 60000 },
213
+
[ABP2001ND] = { .pmin = -249, .pmax = 249 },
214
+
[ABP2002ND] = { .pmin = -498, .pmax = 498 },
215
+
[ABP2004ND] = { .pmin = -996, .pmax = 996 },
216
+
[ABP2005ND] = { .pmin = -1245, .pmax = 1245 },
217
+
[ABP2010ND] = { .pmin = -2491, .pmax = 2491 },
218
+
[ABP2020ND] = { .pmin = -4982, .pmax = 4982 },
219
+
[ABP2030ND] = { .pmin = -7473, .pmax = 7473 },
220
+
[ABP2002NG] = { .pmin = 0, .pmax = 498 },
221
+
[ABP2004NG] = { .pmin = 0, .pmax = 996 },
222
+
[ABP2005NG] = { .pmin = 0, .pmax = 1245 },
223
+
[ABP2010NG] = { .pmin = 0, .pmax = 2491 },
224
+
[ABP2020NG] = { .pmin = 0, .pmax = 4982 },
225
+
[ABP2030NG] = { .pmin = 0, .pmax = 7473 },
226
+
[ABP2015PA] = { .pmin = 0, .pmax = 103421 },
227
+
[ABP2030PA] = { .pmin = 0, .pmax = 206843 },
228
+
[ABP2060PA] = { .pmin = 0, .pmax = 413685 },
229
+
[ABP2100PA] = { .pmin = 0, .pmax = 689476 },
230
+
[ABP2150PA] = { .pmin = 0, .pmax = 1034214 },
231
+
[ABP2175PA] = { .pmin = 0, .pmax = 1206583 },
232
+
[ABP2001PD] = { .pmin = -6895, .pmax = 6895 },
233
+
[ABP2005PD] = { .pmin = -34474, .pmax = 34474 },
234
+
[ABP2015PD] = { .pmin = -103421, .pmax = 103421 },
235
+
[ABP2030PD] = { .pmin = -206843, .pmax = 206843 },
236
+
[ABP2060PD] = { .pmin = -413685, .pmax = 413685 },
237
+
[ABP2001PG] = { .pmin = 0, .pmax = 6895 },
238
+
[ABP2005PG] = { .pmin = 0, .pmax = 34474 },
239
+
[ABP2015PG] = { .pmin = 0, .pmax = 103421 },
240
+
[ABP2030PG] = { .pmin = 0, .pmax = 206843 },
241
+
[ABP2060PG] = { .pmin = 0, .pmax = 413685 },
242
+
[ABP2100PG] = { .pmin = 0, .pmax = 689476 },
243
+
[ABP2150PG] = { .pmin = 0, .pmax = 1034214 },
244
+
[ABP2175PG] = { .pmin = 0, .pmax = 1206583 },
245
+
};
246
+
247
+
static_assert(ARRAY_SIZE(abp2_triplet_variants) == ARRAY_SIZE(abp2_range_config));
248
+
249
+
static int abp2_get_measurement(struct abp2_data *data)
250
+
{
251
+
struct device *dev = data->dev;
252
+
int ret;
253
+
254
+
reinit_completion(&data->completion);
255
+
256
+
ret = data->ops->write(data, ABP2_CMD_SYNC, ABP2_PKT_SYNC_LEN);
257
+
if (ret < 0)
258
+
return ret;
259
+
260
+
if (data->irq > 0) {
261
+
ret = wait_for_completion_timeout(&data->completion, HZ);
262
+
if (!ret) {
263
+
dev_err(dev, "timeout waiting for EOC interrupt\n");
264
+
return -ETIMEDOUT;
265
+
}
266
+
} else {
267
+
fsleep(5 * USEC_PER_MSEC);
268
+
}
269
+
270
+
memset(data->rx_buf, 0, sizeof(data->rx_buf));
271
+
ret = data->ops->read(data, ABP2_CMD_NOP, ABP2_PKT_NOP_LEN);
272
+
if (ret < 0)
273
+
return ret;
274
+
275
+
/*
276
+
* Status byte flags
277
+
* bit7 SANITY_CHK - must always be 0
278
+
* bit6 ABP2_ST_POWER - 1 if device is powered
279
+
* bit5 ABP2_ST_BUSY - 1 if device has no new conversion ready
280
+
* bit4 SANITY_CHK - must always be 0
281
+
* bit3 SANITY_CHK - must always be 0
282
+
* bit2 MEMORY_ERR - 1 if integrity test has failed
283
+
* bit1 SANITY_CHK - must always be 0
284
+
* bit0 MATH_ERR - 1 during internal math saturation error
285
+
*/
286
+
287
+
if (data->rx_buf[0] == (ABP2_ST_POWER | ABP2_ST_BUSY))
288
+
return -EBUSY;
289
+
290
+
/*
291
+
* The ABP2 sensor series seem to have a noticeable latch-up sensitivity.
292
+
* A partial latch-up condition manifests as either
293
+
* - output of invalid status bytes
294
+
* - zeroed out conversions (despite a normal status byte)
295
+
* - the MOSI line being pulled low randomly in sync with the SCLK
296
+
* signal (visible during the ABP2_CMD_NOP command).
297
+
* https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1588325/am3358-spi-tx-data-corruption
298
+
*/
299
+
300
+
if (data->rx_buf[0] != ABP2_ST_POWER) {
301
+
dev_err(data->dev,
302
+
"unexpected status byte 0x%02x\n", data->rx_buf[0]);
303
+
return -EIO;
304
+
}
305
+
306
+
return 0;
307
+
}
308
+
309
+
static irqreturn_t abp2_eoc_handler(int irq, void *private)
310
+
{
311
+
struct abp2_data *data = private;
312
+
313
+
complete(&data->completion);
314
+
315
+
return IRQ_HANDLED;
316
+
}
317
+
318
+
static irqreturn_t abp2_trigger_handler(int irq, void *private)
319
+
{
320
+
int ret;
321
+
struct iio_poll_func *pf = private;
322
+
struct iio_dev *indio_dev = pf->indio_dev;
323
+
struct abp2_data *data = iio_priv(indio_dev);
324
+
325
+
ret = abp2_get_measurement(data);
326
+
if (ret < 0)
327
+
goto out_notify_done;
328
+
329
+
data->scan.chan[0] = get_unaligned_be24(&data->rx_buf[1]);
330
+
data->scan.chan[1] = get_unaligned_be24(&data->rx_buf[4]);
331
+
332
+
iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan),
333
+
iio_get_time_ns(indio_dev));
334
+
335
+
out_notify_done:
336
+
iio_trigger_notify_done(indio_dev->trig);
337
+
338
+
return IRQ_HANDLED;
339
+
}
340
+
341
+
/*
342
+
* IIO ABI expects
343
+
* value = (conv + offset) * scale
344
+
*
345
+
* temp[C] = conv * a + b
346
+
* where a = 200/16777215; b = -50
347
+
*
348
+
* temp[C] = (conv + (b/a)) * a * (1000)
349
+
* =>
350
+
* scale = a * 1000 = .0000119209296 * 1000 = .01192092966562
351
+
* offset = b/a = -50 * 16777215 / 200 = -4194303.75
352
+
*
353
+
* pressure = (conv - Omin) * Q + Pmin =
354
+
* ((conv - Omin) + Pmin/Q) * Q
355
+
* =>
356
+
* scale = Q = (Pmax - Pmin) / (Omax - Omin)
357
+
* offset = Pmin/Q - Omin = Pmin * (Omax - Omin) / (Pmax - Pmin) - Omin
358
+
*/
359
+
static int abp2_read_raw(struct iio_dev *indio_dev,
360
+
struct iio_chan_spec const *channel, int *val,
361
+
int *val2, long mask)
362
+
{
363
+
struct abp2_data *data = iio_priv(indio_dev);
364
+
int ret;
365
+
366
+
switch (mask) {
367
+
case IIO_CHAN_INFO_RAW:
368
+
ret = abp2_get_measurement(data);
369
+
if (ret < 0)
370
+
return ret;
371
+
372
+
switch (channel->type) {
373
+
case IIO_PRESSURE:
374
+
*val = get_unaligned_be24(&data->rx_buf[1]);
375
+
return IIO_VAL_INT;
376
+
case IIO_TEMP:
377
+
*val = get_unaligned_be24(&data->rx_buf[4]);
378
+
return IIO_VAL_INT;
379
+
default:
380
+
return -EINVAL;
381
+
}
382
+
return IIO_VAL_INT;
383
+
384
+
case IIO_CHAN_INFO_SCALE:
385
+
switch (channel->type) {
386
+
case IIO_TEMP:
387
+
*val = 0;
388
+
*val2 = 11920929;
389
+
return IIO_VAL_INT_PLUS_NANO;
390
+
case IIO_PRESSURE:
391
+
*val = data->p_scale;
392
+
*val2 = data->p_scale_dec;
393
+
return IIO_VAL_INT_PLUS_NANO;
394
+
default:
395
+
return -EINVAL;
396
+
}
397
+
398
+
case IIO_CHAN_INFO_OFFSET:
399
+
switch (channel->type) {
400
+
case IIO_TEMP:
401
+
*val = -4194304;
402
+
return IIO_VAL_INT;
403
+
case IIO_PRESSURE:
404
+
*val = data->p_offset;
405
+
return IIO_VAL_INT;
406
+
default:
407
+
return -EINVAL;
408
+
}
409
+
410
+
default:
411
+
return -EINVAL;
412
+
}
413
+
}
414
+
415
+
static const struct iio_info abp2_info = {
416
+
.read_raw = &abp2_read_raw,
417
+
};
418
+
419
+
static const unsigned long abp2_scan_masks[] = {0x3, 0};
420
+
421
+
static const struct iio_chan_spec abp2_channels[] = {
422
+
{
423
+
.type = IIO_PRESSURE,
424
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
425
+
BIT(IIO_CHAN_INFO_SCALE) |
426
+
BIT(IIO_CHAN_INFO_OFFSET),
427
+
.scan_index = 0,
428
+
.scan_type = {
429
+
.sign = 'u',
430
+
.realbits = 24,
431
+
.storagebits = 32,
432
+
.endianness = IIO_CPU,
433
+
},
434
+
},
435
+
{
436
+
.type = IIO_TEMP,
437
+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
438
+
BIT(IIO_CHAN_INFO_SCALE) |
439
+
BIT(IIO_CHAN_INFO_OFFSET),
440
+
.scan_index = 1,
441
+
.scan_type = {
442
+
.sign = 'u',
443
+
.realbits = 24,
444
+
.storagebits = 32,
445
+
.endianness = IIO_CPU,
446
+
},
447
+
},
448
+
IIO_CHAN_SOFT_TIMESTAMP(2),
449
+
};
450
+
451
+
int abp2_common_probe(struct device *dev, const struct abp2_ops *ops, int irq)
452
+
{
453
+
int ret;
454
+
struct abp2_data *data;
455
+
struct iio_dev *indio_dev;
456
+
const char *triplet;
457
+
s32 tmp;
458
+
s64 odelta, pdelta;
459
+
460
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
461
+
if (!indio_dev)
462
+
return -ENOMEM;
463
+
464
+
data = iio_priv(indio_dev);
465
+
data->dev = dev;
466
+
data->ops = ops;
467
+
data->irq = irq;
468
+
469
+
init_completion(&data->completion);
470
+
471
+
indio_dev->name = "abp2030pa";
472
+
indio_dev->info = &abp2_info;
473
+
indio_dev->channels = abp2_channels;
474
+
indio_dev->num_channels = ARRAY_SIZE(abp2_channels);
475
+
indio_dev->modes = INDIO_DIRECT_MODE;
476
+
indio_dev->available_scan_masks = abp2_scan_masks;
477
+
478
+
ret = devm_regulator_get_enable(dev, "vdd");
479
+
if (ret)
480
+
return dev_err_probe(dev, ret, "can't get and enable vdd supply\n");
481
+
482
+
ret = device_property_read_string(dev, "honeywell,pressure-triplet",
483
+
&triplet);
484
+
if (ret) {
485
+
ret = device_property_read_u32(dev, "honeywell,pmin-pascal",
486
+
&data->pmin);
487
+
if (ret)
488
+
return dev_err_probe(dev, ret,
489
+
"honeywell,pmin-pascal could not be read\n");
490
+
491
+
ret = device_property_read_u32(dev, "honeywell,pmax-pascal",
492
+
&data->pmax);
493
+
if (ret)
494
+
return dev_err_probe(dev, ret,
495
+
"honeywell,pmax-pascal could not be read\n");
496
+
} else {
497
+
ret = device_property_match_property_string(dev,
498
+
"honeywell,pressure-triplet",
499
+
abp2_triplet_variants,
500
+
ARRAY_SIZE(abp2_triplet_variants));
501
+
if (ret < 0)
502
+
return dev_err_probe(dev, -EINVAL, "honeywell,pressure-triplet is invalid\n");
503
+
504
+
data->pmin = abp2_range_config[ret].pmin;
505
+
data->pmax = abp2_range_config[ret].pmax;
506
+
}
507
+
508
+
if (data->pmin >= data->pmax)
509
+
return dev_err_probe(dev, -EINVAL, "pressure limits are invalid\n");
510
+
511
+
data->outmin = abp2_func_spec[data->function].output_min;
512
+
data->outmax = abp2_func_spec[data->function].output_max;
513
+
514
+
odelta = data->outmax - data->outmin;
515
+
pdelta = data->pmax - data->pmin;
516
+
517
+
data->p_scale = div_s64_rem(div_s64(pdelta * NANO, odelta), NANO, &tmp);
518
+
data->p_scale_dec = tmp;
519
+
520
+
data->p_offset = div_s64(odelta * data->pmin, pdelta) - data->outmin;
521
+
522
+
if (data->irq > 0) {
523
+
ret = devm_request_irq(dev, irq, abp2_eoc_handler, IRQF_ONESHOT,
524
+
dev_name(dev), data);
525
+
if (ret)
526
+
return ret;
527
+
}
528
+
529
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
530
+
abp2_trigger_handler, NULL);
531
+
if (ret)
532
+
return dev_err_probe(dev, ret, "iio triggered buffer setup failed\n");
533
+
534
+
ret = devm_iio_device_register(dev, indio_dev);
535
+
if (ret)
536
+
return dev_err_probe(dev, ret, "unable to register iio device\n");
537
+
538
+
return 0;
539
+
}
540
+
EXPORT_SYMBOL_NS_GPL(abp2_common_probe, "IIO_HONEYWELL_ABP2030PA");
541
+
542
+
MODULE_AUTHOR("Petre Rodan <petre.rodan@subdimension.ro>");
543
+
MODULE_DESCRIPTION("Honeywell ABP2 pressure sensor core driver");
544
+
MODULE_LICENSE("GPL");
+73
drivers/iio/pressure/abp2030pa.h
+73
drivers/iio/pressure/abp2030pa.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Honeywell ABP2 series pressure sensor driver
4
+
*
5
+
* Copyright (c) 2025 Petre Rodan <petre.rodan@subdimension.ro>
6
+
*/
7
+
8
+
#ifndef _ABP2030PA_H
9
+
#define _ABP2030PA_H
10
+
11
+
#include <linux/completion.h>
12
+
#include <linux/types.h>
13
+
14
+
#include <linux/iio/iio.h>
15
+
16
+
#define ABP2_MEASUREMENT_RD_SIZE 7
17
+
18
+
struct device;
19
+
20
+
struct abp2_data;
21
+
struct abp2_ops;
22
+
23
+
enum abp2_func_id {
24
+
ABP2_FUNCTION_A,
25
+
};
26
+
27
+
/**
28
+
* struct abp2_data
29
+
* @dev: current device structure
30
+
* @ops: pointers for bus specific read and write functions
31
+
* @pmin: minimal pressure in pascal
32
+
* @pmax: maximal pressure in pascal
33
+
* @outmin: minimum raw pressure in counts (based on transfer function)
34
+
* @outmax: maximum raw pressure in counts (based on transfer function)
35
+
* @function: transfer function
36
+
* @p_scale: pressure scale
37
+
* @p_scale_dec: pressure scale, decimal number
38
+
* @p_offset: pressure offset
39
+
* @irq: end of conversion - applies only to the i2c sensor
40
+
* @completion: handshake from irq to read
41
+
* @scan: channel values for buffered mode
42
+
* @tx_buf: transmit buffer used during the SPI communication
43
+
* @rx_buf: raw data provided by sensor
44
+
*/
45
+
struct abp2_data {
46
+
struct device *dev;
47
+
const struct abp2_ops *ops;
48
+
s32 pmin;
49
+
s32 pmax;
50
+
u32 outmin;
51
+
u32 outmax;
52
+
enum abp2_func_id function;
53
+
int p_scale;
54
+
int p_scale_dec;
55
+
int p_offset;
56
+
int irq;
57
+
struct completion completion;
58
+
struct {
59
+
u32 chan[2];
60
+
aligned_s64 timestamp;
61
+
} scan;
62
+
u8 rx_buf[ABP2_MEASUREMENT_RD_SIZE] __aligned(IIO_DMA_MINALIGN);
63
+
u8 tx_buf[ABP2_MEASUREMENT_RD_SIZE];
64
+
};
65
+
66
+
struct abp2_ops {
67
+
int (*read)(struct abp2_data *data, u8 cmd, u8 nbytes);
68
+
int (*write)(struct abp2_data *data, u8 cmd, u8 nbytes);
69
+
};
70
+
71
+
int abp2_common_probe(struct device *dev, const struct abp2_ops *ops, int irq);
72
+
73
+
#endif
+90
drivers/iio/pressure/abp2030pa_i2c.c
+90
drivers/iio/pressure/abp2030pa_i2c.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Honeywell ABP2 series pressure sensor driver
4
+
*
5
+
* Copyright (c) 2025 Petre Rodan <petre.rodan@subdimension.ro>
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/errno.h>
10
+
#include <linux/i2c.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
+
#include <linux/types.h>
14
+
15
+
#include "abp2030pa.h"
16
+
17
+
static int abp2_i2c_read(struct abp2_data *data, u8 unused, u8 nbytes)
18
+
{
19
+
struct i2c_client *client = to_i2c_client(data->dev);
20
+
int ret;
21
+
22
+
if (nbytes > ABP2_MEASUREMENT_RD_SIZE)
23
+
return -EOVERFLOW;
24
+
25
+
ret = i2c_master_recv(client, data->rx_buf, nbytes);
26
+
if (ret < 0)
27
+
return ret;
28
+
if (ret != nbytes)
29
+
return -EIO;
30
+
31
+
return 0;
32
+
}
33
+
34
+
static int abp2_i2c_write(struct abp2_data *data, u8 cmd, u8 nbytes)
35
+
{
36
+
struct i2c_client *client = to_i2c_client(data->dev);
37
+
int ret;
38
+
39
+
if (nbytes > ABP2_MEASUREMENT_RD_SIZE)
40
+
return -EOVERFLOW;
41
+
42
+
data->tx_buf[0] = cmd;
43
+
ret = i2c_master_send(client, data->tx_buf, nbytes);
44
+
if (ret < 0)
45
+
return ret;
46
+
if (ret != nbytes)
47
+
return -EIO;
48
+
49
+
return 0;
50
+
}
51
+
52
+
static const struct abp2_ops abp2_i2c_ops = {
53
+
.read = abp2_i2c_read,
54
+
.write = abp2_i2c_write,
55
+
};
56
+
57
+
static int abp2_i2c_probe(struct i2c_client *client)
58
+
{
59
+
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
60
+
return -EOPNOTSUPP;
61
+
62
+
return abp2_common_probe(&client->dev, &abp2_i2c_ops, client->irq);
63
+
}
64
+
65
+
static const struct of_device_id abp2_i2c_match[] = {
66
+
{ .compatible = "honeywell,abp2030pa" },
67
+
{ }
68
+
};
69
+
MODULE_DEVICE_TABLE(of, abp2_i2c_match);
70
+
71
+
static const struct i2c_device_id abp2_i2c_id[] = {
72
+
{ "abp2030pa" },
73
+
{ }
74
+
};
75
+
MODULE_DEVICE_TABLE(i2c, abp2_i2c_id);
76
+
77
+
static struct i2c_driver abp2_i2c_driver = {
78
+
.driver = {
79
+
.name = "abp2030pa",
80
+
.of_match_table = abp2_i2c_match,
81
+
},
82
+
.probe = abp2_i2c_probe,
83
+
.id_table = abp2_i2c_id,
84
+
};
85
+
module_i2c_driver(abp2_i2c_driver);
86
+
87
+
MODULE_AUTHOR("Petre Rodan <petre.rodan@subdimension.ro>");
88
+
MODULE_DESCRIPTION("Honeywell ABP2 pressure sensor i2c driver");
89
+
MODULE_LICENSE("GPL");
90
+
MODULE_IMPORT_NS("IIO_HONEYWELL_ABP2030PA");
+67
drivers/iio/pressure/abp2030pa_spi.c
+67
drivers/iio/pressure/abp2030pa_spi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Honeywell ABP2 series pressure sensor driver
4
+
*
5
+
* Copyright (c) 2025 Petre Rodan <petre.rodan@subdimension.ro>
6
+
*/
7
+
8
+
#include <linux/errno.h>
9
+
#include <linux/mod_devicetable.h>
10
+
#include <linux/module.h>
11
+
#include <linux/spi/spi.h>
12
+
#include <linux/types.h>
13
+
14
+
#include "abp2030pa.h"
15
+
16
+
static int abp2_spi_xfer(struct abp2_data *data, u8 cmd, u8 nbytes)
17
+
{
18
+
struct spi_device *spi = to_spi_device(data->dev);
19
+
struct spi_transfer xfer = { };
20
+
21
+
if (nbytes > ABP2_MEASUREMENT_RD_SIZE)
22
+
return -EOVERFLOW;
23
+
24
+
data->tx_buf[0] = cmd;
25
+
xfer.tx_buf = data->tx_buf;
26
+
xfer.rx_buf = data->rx_buf;
27
+
xfer.len = nbytes;
28
+
29
+
return spi_sync_transfer(spi, &xfer, 1);
30
+
}
31
+
32
+
static const struct abp2_ops abp2_spi_ops = {
33
+
.read = abp2_spi_xfer,
34
+
.write = abp2_spi_xfer,
35
+
};
36
+
37
+
static int abp2_spi_probe(struct spi_device *spi)
38
+
{
39
+
return abp2_common_probe(&spi->dev, &abp2_spi_ops, spi->irq);
40
+
}
41
+
42
+
static const struct of_device_id abp2_spi_match[] = {
43
+
{ .compatible = "honeywell,abp2030pa" },
44
+
{ }
45
+
};
46
+
MODULE_DEVICE_TABLE(of, abp2_spi_match);
47
+
48
+
static const struct spi_device_id abp2_spi_id[] = {
49
+
{ "abp2030pa" },
50
+
{ }
51
+
};
52
+
MODULE_DEVICE_TABLE(spi, abp2_spi_id);
53
+
54
+
static struct spi_driver abp2_spi_driver = {
55
+
.driver = {
56
+
.name = "abp2030pa",
57
+
.of_match_table = abp2_spi_match,
58
+
},
59
+
.probe = abp2_spi_probe,
60
+
.id_table = abp2_spi_id,
61
+
};
62
+
module_spi_driver(abp2_spi_driver);
63
+
64
+
MODULE_AUTHOR("Petre Rodan <petre.rodan@subdimension.ro>");
65
+
MODULE_DESCRIPTION("Honeywell ABP2 pressure sensor spi driver");
66
+
MODULE_LICENSE("GPL");
67
+
MODULE_IMPORT_NS("IIO_HONEYWELL_ABP2030PA");
+3
-4
drivers/iio/pressure/dlhl60d.c
+3
-4
drivers/iio/pressure/dlhl60d.c
···
306
306
indio_dev->num_channels = ARRAY_SIZE(dlh_channels);
307
307
308
308
if (client->irq > 0) {
309
-
ret = devm_request_threaded_irq(&client->dev, client->irq,
310
-
dlh_interrupt, NULL,
311
-
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
312
-
st->info->name, indio_dev);
309
+
ret = devm_request_irq(&client->dev, client->irq, dlh_interrupt,
310
+
IRQF_TRIGGER_RISING | IRQF_NO_THREAD,
311
+
st->info->name, indio_dev);
313
312
if (ret) {
314
313
dev_err(&client->dev, "failed to allocate threaded irq");
315
314
return ret;
+53
-64
drivers/iio/pressure/mprls0025pa.c
+53
-64
drivers/iio/pressure/mprls0025pa.c
···
3
3
* MPRLS0025PA - Honeywell MicroPressure pressure sensor series driver
4
4
*
5
5
* Copyright (c) Andreas Klinger <ak@it-klinger.de>
6
+
* Copyright (c) 2023-2025 Petre Rodan <petre.rodan@subdimension.ro>
6
7
*
7
8
* Data sheet:
8
9
* https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/micropressure-mpr-series/documents/sps-siot-mpr-series-datasheet-32332628-ciid-172626.pdf
···
13
12
#include <linux/array_size.h>
14
13
#include <linux/bitfield.h>
15
14
#include <linux/bits.h>
15
+
#include <linux/completion.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/errno.h>
18
+
#include <linux/export.h>
19
+
#include <linux/interrupt.h>
20
+
#include <linux/jiffies.h>
16
21
#include <linux/math64.h>
17
22
#include <linux/mod_devicetable.h>
18
23
#include <linux/module.h>
19
24
#include <linux/property.h>
25
+
#include <linux/string.h>
26
+
#include <linux/time.h>
20
27
#include <linux/units.h>
21
28
22
29
#include <linux/gpio/consumer.h>
23
30
24
31
#include <linux/iio/buffer.h>
32
+
#include <linux/iio/iio.h>
25
33
#include <linux/iio/trigger_consumer.h>
26
34
#include <linux/iio/triggered_buffer.h>
27
35
···
43
33
/* bits in status byte */
44
34
#define MPR_ST_POWER BIT(6) /* device is powered */
45
35
#define MPR_ST_BUSY BIT(5) /* device is busy */
46
-
#define MPR_ST_MEMORY BIT(2) /* integrity test passed */
47
-
#define MPR_ST_MATH BIT(0) /* internal math saturation */
48
-
49
-
#define MPR_ST_ERR_FLAG (MPR_ST_BUSY | MPR_ST_MEMORY | MPR_ST_MATH)
50
36
51
37
/*
52
38
* support _RAW sysfs interface:
···
65
59
*
66
60
* Values given to the userspace in sysfs interface:
67
61
* * raw - press_cnt
68
-
* * offset - (-1 * outputmin) - pmin / scale
62
+
* * offset - (-1 * outputmin) + pmin / scale
69
63
* note: With all sensors from the datasheet pmin = 0
70
64
* which reduces the offset to (-1 * outputmin)
71
65
*/
···
166
160
BIT(IIO_CHAN_INFO_OFFSET),
167
161
.scan_index = 0,
168
162
.scan_type = {
169
-
.sign = 's',
170
-
.realbits = 32,
163
+
.sign = 'u',
164
+
.realbits = 24,
171
165
.storagebits = 32,
172
166
.endianness = IIO_CPU,
173
167
},
···
196
190
*
197
191
* Context: The function can sleep and data->lock should be held when calling it
198
192
* Return:
199
-
* * 0 - OK, the pressure value could be read
200
-
* * -ETIMEDOUT - Timeout while waiting for the EOC interrupt or busy flag is
201
-
* still set after nloops attempts of reading
193
+
* * 0 - OK, the pressure value could be read
194
+
* * -EBUSY - Sensor does not have a new conversion ready
195
+
* * -ETIMEDOUT - Timeout while waiting for the EOC interrupt
196
+
* * -EIO - Invalid status byte received from sensor
202
197
*/
203
198
static int mpr_read_pressure(struct mpr_data *data, s32 *press)
204
199
{
205
200
struct device *dev = data->dev;
206
-
int ret, i;
207
-
int nloops = 10;
201
+
int ret;
208
202
209
203
reinit_completion(&data->completion);
210
204
···
221
215
return -ETIMEDOUT;
222
216
}
223
217
} else {
224
-
/* wait until status indicates data is ready */
225
-
for (i = 0; i < nloops; i++) {
226
-
/*
227
-
* datasheet only says to wait at least 5 ms for the
228
-
* data but leave the maximum response time open
229
-
* --> let's try it nloops (10) times which seems to be
230
-
* quite long
231
-
*/
232
-
usleep_range(5000, 10000);
233
-
ret = data->ops->read(data, MPR_CMD_NOP, 1);
234
-
if (ret < 0) {
235
-
dev_err(dev,
236
-
"error while reading, status: %d\n",
237
-
ret);
238
-
return ret;
239
-
}
240
-
if (!(data->buffer[0] & MPR_ST_ERR_FLAG))
241
-
break;
242
-
}
243
-
if (i == nloops) {
244
-
dev_err(dev, "timeout while reading\n");
245
-
return -ETIMEDOUT;
246
-
}
218
+
fsleep(5 * USEC_PER_MSEC);
247
219
}
248
220
221
+
memset(data->rx_buf, 0, sizeof(data->rx_buf));
249
222
ret = data->ops->read(data, MPR_CMD_NOP, MPR_PKT_NOP_LEN);
250
223
if (ret < 0)
251
224
return ret;
252
225
253
-
if (data->buffer[0] & MPR_ST_ERR_FLAG) {
226
+
/*
227
+
* Status byte flags
228
+
* bit7 SANITY_CHK - must always be 0
229
+
* bit6 MPR_ST_POWER - 1 if device is powered
230
+
* bit5 MPR_ST_BUSY - 1 if device has no new conversion ready
231
+
* bit4 SANITY_CHK - must always be 0
232
+
* bit3 SANITY_CHK - must always be 0
233
+
* bit2 MEMORY_ERR - 1 if integrity test has failed
234
+
* bit1 SANITY_CHK - must always be 0
235
+
* bit0 MATH_ERR - 1 during internal math saturation error
236
+
*/
237
+
238
+
if (data->rx_buf[0] == (MPR_ST_POWER | MPR_ST_BUSY))
239
+
return -EBUSY;
240
+
241
+
if (data->rx_buf[0] != MPR_ST_POWER) {
254
242
dev_err(data->dev,
255
-
"unexpected status byte %02x\n", data->buffer[0]);
256
-
return -ETIMEDOUT;
243
+
"unexpected status byte 0x%02x\n", data->rx_buf[0]);
244
+
return -EIO;
257
245
}
258
246
259
-
*press = get_unaligned_be24(&data->buffer[1]);
247
+
*press = get_unaligned_be24(&data->rx_buf[1]);
260
248
261
-
dev_dbg(dev, "received: %*ph cnt: %d\n", ret, data->buffer, *press);
249
+
dev_dbg(dev, "received: %*ph cnt: %d\n", ret, data->rx_buf, *press);
262
250
263
251
return 0;
264
252
}
···
313
313
return IIO_VAL_INT_PLUS_NANO;
314
314
case IIO_CHAN_INFO_OFFSET:
315
315
*val = data->offset;
316
-
*val2 = data->offset2;
317
-
return IIO_VAL_INT_PLUS_NANO;
316
+
return IIO_VAL_INT;
318
317
default:
319
318
return -EINVAL;
320
319
}
···
329
330
struct mpr_data *data;
330
331
struct iio_dev *indio_dev;
331
332
const char *triplet;
332
-
s64 scale, offset;
333
+
s64 odelta, pdelta;
333
334
u32 func;
335
+
s32 tmp;
334
336
335
337
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
336
338
if (!indio_dev)
···
355
355
if (ret)
356
356
return dev_err_probe(dev, ret,
357
357
"can't get and enable vdd supply\n");
358
-
359
-
ret = data->ops->init(data->dev);
360
-
if (ret)
361
-
return ret;
362
358
363
359
ret = device_property_read_u32(dev,
364
360
"honeywell,transfer-function", &func);
···
401
405
data->outmin = mpr_func_spec[data->function].output_min;
402
406
data->outmax = mpr_func_spec[data->function].output_max;
403
407
404
-
/* use 64 bit calculation for preserving a reasonable precision */
405
-
scale = div_s64(((s64)(data->pmax - data->pmin)) * NANO,
406
-
data->outmax - data->outmin);
407
-
data->scale = div_s64_rem(scale, NANO, &data->scale2);
408
-
/*
409
-
* multiply with NANO before dividing by scale and later divide by NANO
410
-
* again.
411
-
*/
412
-
offset = ((-1LL) * (s64)data->outmin) * NANO -
413
-
div_s64(div_s64((s64)data->pmin * NANO, scale), NANO);
414
-
data->offset = div_s64_rem(offset, NANO, &data->offset2);
408
+
odelta = data->outmax - data->outmin;
409
+
pdelta = data->pmax - data->pmin;
410
+
411
+
data->scale = div_s64_rem(div_s64(pdelta * NANO, odelta), NANO, &tmp);
412
+
data->scale2 = tmp;
413
+
414
+
data->offset = div_s64(odelta * data->pmin, pdelta) - data->outmin;
415
415
416
416
if (data->irq > 0) {
417
-
ret = devm_request_irq(dev, data->irq, mpr_eoc_handler,
418
-
IRQF_TRIGGER_RISING,
419
-
dev_name(dev),
420
-
data);
417
+
ret = devm_request_irq(dev, data->irq, mpr_eoc_handler, 0,
418
+
dev_name(dev), data);
421
419
if (ret)
422
-
return dev_err_probe(dev, ret,
423
-
"request irq %d failed\n", data->irq);
420
+
return ret;
424
421
}
425
422
426
423
data->gpiod_reset = devm_gpiod_get_optional(dev, "reset",
+4
-11
drivers/iio/pressure/mprls0025pa.h
+4
-11
drivers/iio/pressure/mprls0025pa.h
···
12
12
#define _MPRLS0025PA_H
13
13
14
14
#include <linux/completion.h>
15
-
#include <linux/delay.h>
16
-
#include <linux/device.h>
17
15
#include <linux/mutex.h>
18
-
#include <linux/stddef.h>
19
16
#include <linux/types.h>
20
17
21
18
#include <linux/iio/iio.h>
···
24
27
#define MPR_PKT_SYNC_LEN 3
25
28
26
29
struct device;
27
-
28
-
struct iio_chan_spec;
29
-
struct iio_dev;
30
30
31
31
struct mpr_data;
32
32
struct mpr_ops;
···
47
53
* @scale: pressure scale
48
54
* @scale2: pressure scale, decimal number
49
55
* @offset: pressure offset
50
-
* @offset2: pressure offset, decimal number
51
56
* @gpiod_reset: reset
52
57
* @irq: end of conversion irq. used to distinguish between irq mode and
53
58
* reading in a loop until data is ready
···
54
61
* @chan: channel values for buffered mode
55
62
* @chan.pres: pressure value
56
63
* @chan.ts: timestamp
57
-
* @buffer: raw conversion data
64
+
* @rx_buf: raw conversion data
65
+
* @tx_buf: output buffer
58
66
*/
59
67
struct mpr_data {
60
68
struct device *dev;
···
69
75
int scale;
70
76
int scale2;
71
77
int offset;
72
-
int offset2;
73
78
struct gpio_desc *gpiod_reset;
74
79
int irq;
75
80
struct completion completion;
···
76
83
s32 pres;
77
84
aligned_s64 ts;
78
85
} chan;
79
-
u8 buffer[MPR_MEASUREMENT_RD_SIZE] __aligned(IIO_DMA_MINALIGN);
86
+
u8 rx_buf[MPR_MEASUREMENT_RD_SIZE] __aligned(IIO_DMA_MINALIGN);
87
+
u8 tx_buf[MPR_MEASUREMENT_RD_SIZE];
80
88
};
81
89
82
90
struct mpr_ops {
83
-
int (*init)(struct device *dev);
84
91
int (*read)(struct mpr_data *data, const u8 cmd, const u8 cnt);
85
92
int (*write)(struct mpr_data *data, const u8 cmd, const u8 cnt);
86
93
};
+3
-10
drivers/iio/pressure/mprls0025pa_i2c.c
+3
-10
drivers/iio/pressure/mprls0025pa_i2c.c
···
17
17
18
18
#include "mprls0025pa.h"
19
19
20
-
static int mpr_i2c_init(struct device *unused)
21
-
{
22
-
return 0;
23
-
}
24
-
25
20
static int mpr_i2c_read(struct mpr_data *data, const u8 unused, const u8 cnt)
26
21
{
27
22
int ret;
···
25
30
if (cnt > MPR_MEASUREMENT_RD_SIZE)
26
31
return -EOVERFLOW;
27
32
28
-
memset(data->buffer, 0, MPR_MEASUREMENT_RD_SIZE);
29
-
ret = i2c_master_recv(client, data->buffer, cnt);
33
+
ret = i2c_master_recv(client, data->rx_buf, cnt);
30
34
if (ret < 0)
31
35
return ret;
32
36
else if (ret != cnt)
···
38
44
{
39
45
int ret;
40
46
struct i2c_client *client = to_i2c_client(data->dev);
41
-
u8 wdata[MPR_PKT_SYNC_LEN] = { cmd };
42
47
43
-
ret = i2c_master_send(client, wdata, MPR_PKT_SYNC_LEN);
48
+
data->tx_buf[0] = cmd;
49
+
ret = i2c_master_send(client, data->tx_buf, MPR_PKT_SYNC_LEN);
44
50
if (ret < 0)
45
51
return ret;
46
52
else if (ret != MPR_PKT_SYNC_LEN)
···
50
56
}
51
57
52
58
static const struct mpr_ops mpr_i2c_ops = {
53
-
.init = mpr_i2c_init,
54
59
.read = mpr_i2c_read,
55
60
.write = mpr_i2c_write,
56
61
};
+15
-26
drivers/iio/pressure/mprls0025pa_spi.c
+15
-26
drivers/iio/pressure/mprls0025pa_spi.c
···
8
8
* https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/micropressure-mpr-series/documents/sps-siot-mpr-series-datasheet-32332628-ciid-172626.pdf
9
9
*/
10
10
11
+
#include <linux/array_size.h>
11
12
#include <linux/device.h>
12
13
#include <linux/errno.h>
13
14
#include <linux/mod_devicetable.h>
···
19
18
20
19
#include "mprls0025pa.h"
21
20
22
-
struct mpr_spi_buf {
23
-
u8 tx[MPR_MEASUREMENT_RD_SIZE] __aligned(IIO_DMA_MINALIGN);
24
-
};
25
-
26
-
static int mpr_spi_init(struct device *dev)
27
-
{
28
-
struct spi_device *spi = to_spi_device(dev);
29
-
struct mpr_spi_buf *buf;
30
-
31
-
buf = devm_kzalloc(dev, sizeof(*buf), GFP_KERNEL);
32
-
if (!buf)
33
-
return -ENOMEM;
34
-
35
-
spi_set_drvdata(spi, buf);
36
-
37
-
return 0;
38
-
}
39
-
40
21
static int mpr_spi_xfer(struct mpr_data *data, const u8 cmd, const u8 pkt_len)
41
22
{
42
23
struct spi_device *spi = to_spi_device(data->dev);
43
-
struct mpr_spi_buf *buf = spi_get_drvdata(spi);
44
-
struct spi_transfer xfer;
24
+
struct spi_transfer xfers[2] = { };
45
25
46
26
if (pkt_len > MPR_MEASUREMENT_RD_SIZE)
47
27
return -EOVERFLOW;
48
28
49
-
buf->tx[0] = cmd;
50
-
xfer.tx_buf = buf->tx;
51
-
xfer.rx_buf = data->buffer;
52
-
xfer.len = pkt_len;
29
+
data->tx_buf[0] = cmd;
53
30
54
-
return spi_sync_transfer(spi, &xfer, 1);
31
+
/*
32
+
* Dummy transfer with no data, just cause a 2.5us+ delay between the CS assert
33
+
* and the first clock edge as per the datasheet tHDSS timing requirement.
34
+
*/
35
+
xfers[0].delay.value = 2500;
36
+
xfers[0].delay.unit = SPI_DELAY_UNIT_NSECS;
37
+
38
+
xfers[1].tx_buf = data->tx_buf;
39
+
xfers[1].rx_buf = data->rx_buf;
40
+
xfers[1].len = pkt_len;
41
+
42
+
return spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
55
43
}
56
44
57
45
static const struct mpr_ops mpr_spi_ops = {
58
-
.init = mpr_spi_init,
59
46
.read = mpr_spi_xfer,
60
47
.write = mpr_spi_xfer,
61
48
};
+158
-27
drivers/iio/proximity/rfd77402.c
+158
-27
drivers/iio/proximity/rfd77402.c
···
6
6
*
7
7
* 7-bit I2C slave address 0x4c
8
8
*
9
-
* TODO: interrupt
10
9
* https://media.digikey.com/pdf/Data%20Sheets/RF%20Digital%20PDFs/RFD77402.pdf
11
10
*/
12
11
13
-
#include <linux/module.h>
14
-
#include <linux/i2c.h>
12
+
#include <linux/bits.h>
13
+
#include <linux/completion.h>
15
14
#include <linux/delay.h>
15
+
#include <linux/dev_printk.h>
16
+
#include <linux/errno.h>
17
+
#include <linux/i2c.h>
18
+
#include <linux/interrupt.h>
19
+
#include <linux/iopoll.h>
20
+
#include <linux/jiffies.h>
21
+
#include <linux/module.h>
22
+
#include <linux/types.h>
16
23
17
24
#include <linux/iio/iio.h>
18
25
19
26
#define RFD77402_DRV_NAME "rfd77402"
20
27
21
28
#define RFD77402_ICSR 0x00 /* Interrupt Control Status Register */
29
+
#define RFD77402_ICSR_CLR_CFG BIT(0)
30
+
#define RFD77402_ICSR_CLR_TYPE BIT(1)
22
31
#define RFD77402_ICSR_INT_MODE BIT(2)
23
32
#define RFD77402_ICSR_INT_POL BIT(3)
24
33
#define RFD77402_ICSR_RESULT BIT(4)
25
34
#define RFD77402_ICSR_M2H_MSG BIT(5)
26
35
#define RFD77402_ICSR_H2M_MSG BIT(6)
27
36
#define RFD77402_ICSR_RESET BIT(7)
37
+
38
+
#define RFD77402_IER 0x02
39
+
#define RFD77402_IER_RESULT BIT(0)
40
+
#define RFD77402_IER_M2H_MSG BIT(1)
41
+
#define RFD77402_IER_H2M_MSG BIT(2)
42
+
#define RFD77402_IER_RESET BIT(3)
28
43
29
44
#define RFD77402_CMD_R 0x04
30
45
#define RFD77402_CMD_SINGLE 0x01
···
91
76
{RFD77402_HFCFG_3, 0x45d4},
92
77
};
93
78
79
+
/**
80
+
* struct rfd77402_data - device-specific data for the RFD77402 sensor
81
+
* @client: I2C client handle
82
+
* @lock: mutex to serialize sensor reads
83
+
* @completion: completion used for interrupt-driven measurements
84
+
* @irq_en: indicates whether interrupt mode is enabled
85
+
*/
94
86
struct rfd77402_data {
95
87
struct i2c_client *client;
96
-
/* Serialize reads from the sensor */
97
88
struct mutex lock;
89
+
struct completion completion;
90
+
bool irq_en;
98
91
};
99
92
100
93
static const struct iio_chan_spec rfd77402_channels[] = {
···
112
89
BIT(IIO_CHAN_INFO_SCALE),
113
90
},
114
91
};
92
+
93
+
static irqreturn_t rfd77402_interrupt_handler(int irq, void *pdata)
94
+
{
95
+
struct rfd77402_data *data = pdata;
96
+
int ret;
97
+
98
+
ret = i2c_smbus_read_byte_data(data->client, RFD77402_ICSR);
99
+
if (ret < 0)
100
+
return IRQ_NONE;
101
+
102
+
/* Check if the interrupt is from our device */
103
+
if (!(ret & RFD77402_ICSR_RESULT))
104
+
return IRQ_NONE;
105
+
106
+
/* Signal completion of measurement */
107
+
complete(&data->completion);
108
+
return IRQ_HANDLED;
109
+
}
110
+
111
+
static int rfd77402_wait_for_irq(struct rfd77402_data *data)
112
+
{
113
+
int ret;
114
+
115
+
/*
116
+
* According to RFD77402 Datasheet v1.8,
117
+
* Section 3.1.1 "Single Measure" (Figure: Single Measure Flow Chart),
118
+
* the suggested timeout for single measure is 100 ms.
119
+
*/
120
+
ret = wait_for_completion_timeout(&data->completion,
121
+
msecs_to_jiffies(100));
122
+
if (ret == 0)
123
+
return -ETIMEDOUT;
124
+
125
+
return 0;
126
+
}
115
127
116
128
static int rfd77402_set_state(struct i2c_client *client, u8 state, u16 check)
117
129
{
···
168
110
return 0;
169
111
}
170
112
171
-
static int rfd77402_measure(struct i2c_client *client)
113
+
static int rfd77402_wait_for_result(struct rfd77402_data *data)
172
114
{
115
+
struct i2c_client *client = data->client;
116
+
int val, ret;
117
+
118
+
if (data->irq_en) {
119
+
reinit_completion(&data->completion);
120
+
return rfd77402_wait_for_irq(data);
121
+
}
122
+
123
+
/*
124
+
* As per RFD77402 datasheet section '3.1.1 Single Measure', the
125
+
* suggested timeout value for single measure is 100ms.
126
+
*/
127
+
ret = read_poll_timeout(i2c_smbus_read_byte_data, val,
128
+
(val < 0) || (val & RFD77402_ICSR_RESULT),
129
+
10 * USEC_PER_MSEC,
130
+
10 * 10 * USEC_PER_MSEC,
131
+
false,
132
+
client, RFD77402_ICSR);
133
+
if (val < 0)
134
+
return val;
135
+
136
+
return ret;
137
+
}
138
+
139
+
static int rfd77402_measure(struct rfd77402_data *data)
140
+
{
141
+
struct i2c_client *client = data->client;
173
142
int ret;
174
-
int tries = 10;
175
143
176
144
ret = rfd77402_set_state(client, RFD77402_CMD_MCPU_ON,
177
145
RFD77402_STATUS_MCPU_ON);
···
210
126
if (ret < 0)
211
127
goto err;
212
128
213
-
while (tries-- > 0) {
214
-
ret = i2c_smbus_read_byte_data(client, RFD77402_ICSR);
215
-
if (ret < 0)
216
-
goto err;
217
-
if (ret & RFD77402_ICSR_RESULT)
218
-
break;
219
-
msleep(20);
220
-
}
221
-
222
-
if (tries < 0) {
223
-
ret = -ETIMEDOUT;
129
+
ret = rfd77402_wait_for_result(data);
130
+
if (ret < 0)
224
131
goto err;
225
-
}
226
132
227
133
ret = i2c_smbus_read_word_data(client, RFD77402_RESULT_R);
228
134
if (ret < 0)
···
242
168
switch (mask) {
243
169
case IIO_CHAN_INFO_RAW:
244
170
mutex_lock(&data->lock);
245
-
ret = rfd77402_measure(data->client);
171
+
ret = rfd77402_measure(data);
246
172
mutex_unlock(&data->lock);
247
173
if (ret < 0)
248
174
return ret;
···
262
188
.read_raw = rfd77402_read_raw,
263
189
};
264
190
265
-
static int rfd77402_init(struct i2c_client *client)
191
+
static int rfd77402_config_irq(struct i2c_client *client, u8 csr, u8 ier)
266
192
{
193
+
int ret;
194
+
195
+
ret = i2c_smbus_write_byte_data(client, RFD77402_ICSR, csr);
196
+
if (ret)
197
+
return ret;
198
+
199
+
return i2c_smbus_write_byte_data(client, RFD77402_IER, ier);
200
+
}
201
+
202
+
static int rfd77402_init(struct rfd77402_data *data)
203
+
{
204
+
struct i2c_client *client = data->client;
267
205
int ret, i;
268
206
269
207
ret = rfd77402_set_state(client, RFD77402_CMD_STANDBY,
···
283
197
if (ret < 0)
284
198
return ret;
285
199
286
-
/* configure INT pad as push-pull, active low */
287
-
ret = i2c_smbus_write_byte_data(client, RFD77402_ICSR,
288
-
RFD77402_ICSR_INT_MODE);
289
-
if (ret < 0)
200
+
if (data->irq_en) {
201
+
/*
202
+
* Enable interrupt mode:
203
+
* - Configure ICSR for auto-clear on read and
204
+
* push-pull output
205
+
* - Enable "result ready" interrupt in IER
206
+
*/
207
+
ret = rfd77402_config_irq(client,
208
+
RFD77402_ICSR_CLR_CFG |
209
+
RFD77402_ICSR_INT_MODE,
210
+
RFD77402_IER_RESULT);
211
+
} else {
212
+
/*
213
+
* Disable all interrupts:
214
+
* - Clear ICSR configuration
215
+
* - Disable all interrupts in IER
216
+
*/
217
+
ret = rfd77402_config_irq(client, 0, 0);
218
+
}
219
+
if (ret)
290
220
return ret;
291
221
292
222
/* I2C configuration */
···
377
275
378
276
data = iio_priv(indio_dev);
379
277
data->client = client;
380
-
mutex_init(&data->lock);
278
+
279
+
ret = devm_mutex_init(&client->dev, &data->lock);
280
+
if (ret)
281
+
return ret;
282
+
283
+
init_completion(&data->completion);
284
+
285
+
if (client->irq > 0) {
286
+
ret = devm_request_threaded_irq(&client->dev, client->irq,
287
+
NULL, rfd77402_interrupt_handler,
288
+
IRQF_ONESHOT,
289
+
"rfd77402", data);
290
+
if (ret)
291
+
return ret;
292
+
293
+
data->irq_en = true;
294
+
dev_dbg(&client->dev, "Using interrupt mode\n");
295
+
} else {
296
+
dev_dbg(&client->dev, "Using polling mode\n");
297
+
}
381
298
382
299
indio_dev->info = &rfd77402_info;
383
300
indio_dev->channels = rfd77402_channels;
···
404
283
indio_dev->name = RFD77402_DRV_NAME;
405
284
indio_dev->modes = INDIO_DIRECT_MODE;
406
285
407
-
ret = rfd77402_init(client);
286
+
ret = rfd77402_init(data);
408
287
if (ret < 0)
409
288
return ret;
410
289
···
422
301
423
302
static int rfd77402_resume(struct device *dev)
424
303
{
425
-
return rfd77402_init(to_i2c_client(dev));
304
+
struct iio_dev *indio_dev = dev_get_drvdata(dev);
305
+
struct rfd77402_data *data = iio_priv(indio_dev);
306
+
307
+
return rfd77402_init(data);
426
308
}
427
309
428
310
static DEFINE_SIMPLE_DEV_PM_OPS(rfd77402_pm_ops, rfd77402_suspend,
···
437
313
};
438
314
MODULE_DEVICE_TABLE(i2c, rfd77402_id);
439
315
316
+
static const struct of_device_id rfd77402_of_match[] = {
317
+
{ .compatible = "rfdigital,rfd77402" },
318
+
{ }
319
+
};
320
+
MODULE_DEVICE_TABLE(of, rfd77402_of_match);
321
+
440
322
static struct i2c_driver rfd77402_driver = {
441
323
.driver = {
442
324
.name = RFD77402_DRV_NAME,
443
325
.pm = pm_sleep_ptr(&rfd77402_pm_ops),
326
+
.of_match_table = rfd77402_of_match,
444
327
},
445
328
.probe = rfd77402_probe,
446
329
.id_table = rfd77402_id,
+4
-6
drivers/iio/temperature/tmp006.c
+4
-6
drivers/iio/temperature/tmp006.c
···
356
356
357
357
indio_dev->trig = iio_trigger_get(data->drdy_trig);
358
358
359
-
ret = devm_request_threaded_irq(&client->dev, client->irq,
360
-
iio_trigger_generic_data_rdy_poll,
361
-
NULL,
362
-
IRQF_ONESHOT,
363
-
"tmp006_irq",
364
-
data->drdy_trig);
359
+
ret = devm_request_irq(&client->dev, client->irq,
360
+
iio_trigger_generic_data_rdy_poll,
361
+
IRQF_NO_THREAD, "tmp006_irq",
362
+
data->drdy_trig);
365
363
if (ret < 0)
366
364
return ret;
367
365
}
-1
drivers/iio/test/Kconfig
-1
drivers/iio/test/Kconfig
+1
-1
drivers/staging/iio/addac/adt7316-i2c.c
+1
-1
drivers/staging/iio/addac/adt7316-i2c.c
+1
-1
drivers/staging/iio/addac/adt7316-spi.c
+1
-1
drivers/staging/iio/addac/adt7316-spi.c
+2
-4
drivers/staging/iio/addac/adt7316.c
+2
-4
drivers/staging/iio/addac/adt7316.c
···
2082
2082
.name = "events",
2083
2083
};
2084
2084
2085
-
#ifdef CONFIG_PM_SLEEP
2086
2085
static int adt7316_disable(struct device *dev)
2087
2086
{
2088
2087
struct iio_dev *dev_info = dev_get_drvdata(dev);
···
2097
2098
2098
2099
return _adt7316_store_enabled(chip, 1);
2099
2100
}
2100
-
EXPORT_SYMBOL_GPL(adt7316_pm_ops);
2101
-
SIMPLE_DEV_PM_OPS(adt7316_pm_ops, adt7316_disable, adt7316_enable);
2102
-
#endif
2101
+
2102
+
EXPORT_GPL_SIMPLE_DEV_PM_OPS(adt7316_pm_ops, adt7316_disable, adt7316_enable);
2103
2103
2104
2104
static const struct iio_info adt7316_info = {
2105
2105
.attrs = &adt7316_attribute_group,
+1
-5
drivers/staging/iio/addac/adt7316.h
+1
-5
drivers/staging/iio/addac/adt7316.h
···
22
22
int (*multi_write)(void *client, u8 first_reg, u8 count, u8 *data);
23
23
};
24
24
25
-
#ifdef CONFIG_PM_SLEEP
26
25
extern const struct dev_pm_ops adt7316_pm_ops;
27
-
#define ADT7316_PM_OPS (&adt7316_pm_ops)
28
-
#else
29
-
#define ADT7316_PM_OPS NULL
30
-
#endif
26
+
31
27
int adt7316_probe(struct device *dev, struct adt7316_bus *bus,
32
28
const char *name);
33
29
-37
drivers/staging/iio/frequency/ad9832.c
-37
drivers/staging/iio/frequency/ad9832.c
···
23
23
#include <linux/iio/iio.h>
24
24
#include <linux/iio/sysfs.h>
25
25
26
-
#include "ad9832.h"
27
-
28
26
#include "dds.h"
29
27
30
28
/* Registers */
31
-
32
29
#define AD9832_FREQ0LL 0x0
33
30
#define AD9832_FREQ0HL 0x1
34
31
#define AD9832_FREQ0LM 0x2
···
42
45
#define AD9832_PHASE2H 0xD
43
46
#define AD9832_PHASE3L 0xE
44
47
#define AD9832_PHASE3H 0xF
45
-
46
48
#define AD9832_PHASE_SYM 0x10
47
49
#define AD9832_FREQ_SYM 0x11
48
50
#define AD9832_PINCTRL_EN 0x12
49
51
#define AD9832_OUTPUT_EN 0x13
50
52
51
53
/* Command Control Bits */
52
-
53
54
#define AD9832_CMD_PHA8BITSW 0x1
54
55
#define AD9832_CMD_PHA16BITSW 0x0
55
56
#define AD9832_CMD_FRE8BITSW 0x3
···
87
92
* @phase_data: tuning word spi transmit buffer
88
93
* @freq_data: tuning word spi transmit buffer
89
94
*/
90
-
91
95
struct ad9832_state {
92
96
struct spi_device *spi;
93
97
struct clk *mclk;
···
293
299
294
300
static int ad9832_probe(struct spi_device *spi)
295
301
{
296
-
struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
297
302
struct iio_dev *indio_dev;
298
303
struct ad9832_state *st;
299
304
int ret;
300
-
301
-
if (!pdata) {
302
-
dev_dbg(&spi->dev, "no platform data?\n");
303
-
return -ENODEV;
304
-
}
305
305
306
306
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
307
307
if (!indio_dev)
···
323
335
indio_dev->modes = INDIO_DIRECT_MODE;
324
336
325
337
/* Setup default messages */
326
-
327
338
st->xfer.tx_buf = &st->data;
328
339
st->xfer.len = 2;
329
340
···
365
378
dev_err(&spi->dev, "device init failed\n");
366
379
return ret;
367
380
}
368
-
369
-
ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
370
-
if (ret)
371
-
return ret;
372
-
373
-
ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
374
-
if (ret)
375
-
return ret;
376
-
377
-
ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
378
-
if (ret)
379
-
return ret;
380
-
381
-
ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
382
-
if (ret)
383
-
return ret;
384
-
385
-
ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
386
-
if (ret)
387
-
return ret;
388
-
389
-
ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
390
-
if (ret)
391
-
return ret;
392
381
393
382
return devm_iio_device_register(&spi->dev, indio_dev);
394
383
}
-33
drivers/staging/iio/frequency/ad9832.h
-33
drivers/staging/iio/frequency/ad9832.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0+ */
2
-
/*
3
-
* AD9832 SPI DDS driver
4
-
*
5
-
* Copyright 2011 Analog Devices Inc.
6
-
*/
7
-
#ifndef IIO_DDS_AD9832_H_
8
-
#define IIO_DDS_AD9832_H_
9
-
10
-
/*
11
-
* TODO: struct ad9832_platform_data needs to go into include/linux/iio
12
-
*/
13
-
14
-
/**
15
-
* struct ad9832_platform_data - platform specific information
16
-
* @freq0: power up freq0 tuning word in Hz
17
-
* @freq1: power up freq1 tuning word in Hz
18
-
* @phase0: power up phase0 value [0..4095] correlates with 0..2PI
19
-
* @phase1: power up phase1 value [0..4095] correlates with 0..2PI
20
-
* @phase2: power up phase2 value [0..4095] correlates with 0..2PI
21
-
* @phase3: power up phase3 value [0..4095] correlates with 0..2PI
22
-
*/
23
-
24
-
struct ad9832_platform_data {
25
-
unsigned long freq0;
26
-
unsigned long freq1;
27
-
unsigned short phase0;
28
-
unsigned short phase1;
29
-
unsigned short phase2;
30
-
unsigned short phase3;
31
-
};
32
-
33
-
#endif /* IIO_DDS_AD9832_H_ */
+14
-10
include/linux/i3c/device.h
+14
-10
include/linux/i3c/device.h
···
25
25
* @I3C_ERROR_M2: M2 error
26
26
*
27
27
* These are the standard error codes as defined by the I3C specification.
28
-
* When -EIO is returned by the i3c_device_do_priv_xfers() or
28
+
* When -EIO is returned by the i3c_device_do_i3c_xfers() or
29
29
* i3c_device_send_hdr_cmds() one can check the error code in
30
30
* &struct_i3c_xfer.err or &struct i3c_hdr_cmd.err to get a better idea of
31
31
* what went wrong.
···
78
78
} data;
79
79
enum i3c_error_code err;
80
80
};
81
-
82
-
/* keep back compatible */
83
-
#define i3c_priv_xfer i3c_xfer
84
81
85
82
/**
86
83
* enum i3c_dcr - I3C DCR values
···
305
308
i3c_i2c_driver_unregister, \
306
309
__i2cdrv)
307
310
311
+
#if IS_ENABLED(CONFIG_I3C)
308
312
int i3c_device_do_xfers(struct i3c_device *dev, struct i3c_xfer *xfers,
309
313
int nxfers, enum i3c_xfer_mode mode);
310
-
311
-
static inline int i3c_device_do_priv_xfers(struct i3c_device *dev,
312
-
struct i3c_xfer *xfers,
313
-
int nxfers)
314
+
u32 i3c_device_get_supported_xfer_mode(struct i3c_device *dev);
315
+
#else
316
+
static inline int
317
+
i3c_device_do_xfers(struct i3c_device *dev, struct i3c_xfer *xfers,
318
+
int nxfers, enum i3c_xfer_mode mode)
314
319
{
315
-
return i3c_device_do_xfers(dev, xfers, nxfers, I3C_SDR);
320
+
return -EOPNOTSUPP;
316
321
}
322
+
323
+
static inline u32 i3c_device_get_supported_xfer_mode(struct i3c_device *dev)
324
+
{
325
+
return 0;
326
+
}
327
+
#endif
317
328
318
329
int i3c_device_do_setdasa(struct i3c_device *dev);
319
330
···
363
358
void i3c_device_free_ibi(struct i3c_device *dev);
364
359
int i3c_device_enable_ibi(struct i3c_device *dev);
365
360
int i3c_device_disable_ibi(struct i3c_device *dev);
366
-
u32 i3c_device_get_supported_xfer_mode(struct i3c_device *dev);
367
361
368
362
#endif /* I3C_DEV_H */
+6
include/linux/i3c/master.h
+6
include/linux/i3c/master.h
···
462
462
* @enable_hotjoin: enable hot join event detect.
463
463
* @disable_hotjoin: disable hot join event detect.
464
464
* @set_speed: adjust I3C open drain mode timing.
465
+
* @set_dev_nack_retry: configure device NACK retry count for the master
466
+
* controller.
465
467
*/
466
468
struct i3c_master_controller_ops {
467
469
int (*bus_init)(struct i3c_master_controller *master);
···
493
491
int (*enable_hotjoin)(struct i3c_master_controller *master);
494
492
int (*disable_hotjoin)(struct i3c_master_controller *master);
495
493
int (*set_speed)(struct i3c_master_controller *master, enum i3c_open_drain_speed speed);
494
+
int (*set_dev_nack_retry)(struct i3c_master_controller *master,
495
+
unsigned long dev_nack_retry_cnt);
496
496
};
497
497
498
498
/**
···
518
514
* in a thread context. Typical examples are Hot Join processing which
519
515
* requires taking the bus lock in maintenance, which in turn, can only
520
516
* be done from a sleep-able context
517
+
* @dev_nack_retry_count: retry count when slave device nack
521
518
*
522
519
* A &struct i3c_master_controller has to be registered to the I3C subsystem
523
520
* through i3c_master_register(). None of &struct i3c_master_controller fields
···
539
534
} boardinfo;
540
535
struct i3c_bus bus;
541
536
struct workqueue_struct *wq;
537
+
unsigned int dev_nack_retry_count;
542
538
};
543
539
544
540
/**
+12
-8
include/linux/iio/buffer-dma.h
+12
-8
include/linux/iio/buffer-dma.h
···
119
119
struct device *dev;
120
120
const struct iio_dma_buffer_ops *ops;
121
121
122
+
/*
123
+
* A mutex to protect accessing, configuring (eg: enqueuing DMA blocks)
124
+
* and do file IO on struct iio_dma_buffer_queue objects.
125
+
*/
122
126
struct mutex lock;
127
+
/* A spin lock to protect adding/removing blocks to the queue list */
123
128
spinlock_t list_lock;
124
129
struct list_head incoming;
125
130
···
141
136
*/
142
137
struct iio_dma_buffer_ops {
143
138
int (*submit)(struct iio_dma_buffer_queue *queue,
144
-
struct iio_dma_buffer_block *block);
139
+
struct iio_dma_buffer_block *block);
145
140
void (*abort)(struct iio_dma_buffer_queue *queue);
146
141
};
147
142
148
143
void iio_dma_buffer_block_done(struct iio_dma_buffer_block *block);
149
144
void iio_dma_buffer_block_list_abort(struct iio_dma_buffer_queue *queue,
150
-
struct list_head *list);
145
+
struct list_head *list);
151
146
152
-
int iio_dma_buffer_enable(struct iio_buffer *buffer,
153
-
struct iio_dev *indio_dev);
147
+
int iio_dma_buffer_enable(struct iio_buffer *buffer, struct iio_dev *indio_dev);
154
148
int iio_dma_buffer_disable(struct iio_buffer *buffer,
155
-
struct iio_dev *indio_dev);
149
+
struct iio_dev *indio_dev);
156
150
int iio_dma_buffer_read(struct iio_buffer *buffer, size_t n,
157
-
char __user *user_buffer);
151
+
char __user *user_buffer);
158
152
int iio_dma_buffer_write(struct iio_buffer *buffer, size_t n,
159
153
const char __user *user_buffer);
160
154
size_t iio_dma_buffer_usage(struct iio_buffer *buffer);
···
161
157
int iio_dma_buffer_set_length(struct iio_buffer *buffer, unsigned int length);
162
158
int iio_dma_buffer_request_update(struct iio_buffer *buffer);
163
159
164
-
int iio_dma_buffer_init(struct iio_dma_buffer_queue *queue,
165
-
struct device *dma_dev, const struct iio_dma_buffer_ops *ops);
160
+
void iio_dma_buffer_init(struct iio_dma_buffer_queue *queue, struct device *dev,
161
+
const struct iio_dma_buffer_ops *ops);
166
162
void iio_dma_buffer_exit(struct iio_dma_buffer_queue *queue);
167
163
void iio_dma_buffer_release(struct iio_dma_buffer_queue *queue);
168
164
+5
-3
include/linux/iio/buffer_impl.h
+5
-3
include/linux/iio/buffer_impl.h
···
113
113
/** @flags: File ops flags including busy flag. */
114
114
unsigned long flags;
115
115
116
-
/** @bytes_per_datum: Size of individual datum including timestamp. */
116
+
/** @bytes_per_datum: Size of individual datum including timestamp. */
117
117
size_t bytes_per_datum;
118
118
119
-
/* @direction: Direction of the data stream (in/out). */
119
+
/** @direction: Direction of the data stream (in/out). */
120
120
enum iio_buffer_direction direction;
121
121
122
122
/**
···
178
178
* @insert_buffer: buffer to insert
179
179
* @remove_buffer: buffer_to_remove
180
180
*
181
-
* Note this will tear down the all buffering and build it up again
181
+
* Note this will tear down all the buffering and build it up again
182
+
*
183
+
* Returns: 0 on success or -errno on error
182
184
*/
183
185
int iio_update_buffers(struct iio_dev *indio_dev,
184
186
struct iio_buffer *insert_buffer,
+1
-1
include/linux/iio/frequency/ad9523.h
+1
-1
include/linux/iio/frequency/ad9523.h
···
45
45
* @output_dis: Disables, powers down the entire channel.
46
46
* @driver_mode: Output driver mode (logic level family).
47
47
* @divider_phase: Divider initial phase after a SYNC. Range 0..63
48
-
LSB = 1/2 of a period of the divider input clock.
48
+
* LSB = 1/2 of a period of the divider input clock.
49
49
* @channel_divider: 10-bit channel divider.
50
50
* @extended_name: Optional descriptive channel name.
51
51
*/
+127
-12
include/linux/iio/iio.h
+127
-12
include/linux/iio/iio.h
···
10
10
#include <linux/align.h>
11
11
#include <linux/device.h>
12
12
#include <linux/cdev.h>
13
+
#include <linux/cleanup.h>
13
14
#include <linux/compiler_types.h>
14
15
#include <linux/minmax.h>
15
16
#include <linux/slab.h>
···
662
661
int __devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev,
663
662
struct module *this_mod);
664
663
int iio_push_event(struct iio_dev *indio_dev, u64 ev_code, s64 timestamp);
665
-
bool __iio_device_claim_direct(struct iio_dev *indio_dev);
666
-
void __iio_device_release_direct(struct iio_dev *indio_dev);
664
+
665
+
void __iio_dev_mode_lock(struct iio_dev *indio_dev) __acquires(indio_dev);
666
+
void __iio_dev_mode_unlock(struct iio_dev *indio_dev) __releases(indio_dev);
667
667
668
668
/*
669
669
* Helper functions that allow claim and release of direct mode
670
670
* in a fashion that doesn't generate many false positives from sparse.
671
671
* Note this must remain static inline in the header so that sparse
672
-
* can see the __acquire() marking. Revisit when sparse supports
673
-
* __cond_acquires()
672
+
* can see the __acquires() and __releases() annotations.
673
+
*/
674
+
675
+
/**
676
+
* iio_device_claim_direct() - Keep device in direct mode
677
+
* @indio_dev: the iio_dev associated with the device
678
+
*
679
+
* If the device is in direct mode it is guaranteed to stay
680
+
* that way until iio_device_release_direct() is called.
681
+
*
682
+
* Use with iio_device_release_direct().
683
+
*
684
+
* Returns: true on success, false on failure.
674
685
*/
675
686
static inline bool iio_device_claim_direct(struct iio_dev *indio_dev)
676
687
{
677
-
if (!__iio_device_claim_direct(indio_dev))
678
-
return false;
688
+
__iio_dev_mode_lock(indio_dev);
679
689
680
-
__acquire(iio_dev);
690
+
if (iio_buffer_enabled(indio_dev)) {
691
+
__iio_dev_mode_unlock(indio_dev);
692
+
return false;
693
+
}
681
694
682
695
return true;
683
696
}
684
697
685
-
static inline void iio_device_release_direct(struct iio_dev *indio_dev)
698
+
/**
699
+
* iio_device_release_direct() - Releases claim on direct mode
700
+
* @indio_dev: the iio_dev associated with the device
701
+
*
702
+
* Release the claim. Device is no longer guaranteed to stay
703
+
* in direct mode.
704
+
*
705
+
* Use with iio_device_claim_direct().
706
+
*/
707
+
#define iio_device_release_direct(indio_dev) __iio_dev_mode_unlock(indio_dev)
708
+
709
+
/**
710
+
* iio_device_try_claim_buffer_mode() - Keep device in buffer mode
711
+
* @indio_dev: the iio_dev associated with the device
712
+
*
713
+
* If the device is in buffer mode it is guaranteed to stay
714
+
* that way until iio_device_release_buffer_mode() is called.
715
+
*
716
+
* Use with iio_device_release_buffer_mode().
717
+
*
718
+
* Returns: true on success, false on failure.
719
+
*/
720
+
static inline bool iio_device_try_claim_buffer_mode(struct iio_dev *indio_dev)
686
721
{
687
-
__iio_device_release_direct(indio_dev);
688
-
__release(indio_dev);
722
+
__iio_dev_mode_lock(indio_dev);
723
+
724
+
if (!iio_buffer_enabled(indio_dev)) {
725
+
__iio_dev_mode_unlock(indio_dev);
726
+
return false;
727
+
}
728
+
729
+
return true;
689
730
}
690
731
691
-
int iio_device_claim_buffer_mode(struct iio_dev *indio_dev);
692
-
void iio_device_release_buffer_mode(struct iio_dev *indio_dev);
732
+
/**
733
+
* iio_device_release_buffer_mode() - releases claim on buffer mode
734
+
* @indio_dev: the iio_dev associated with the device
735
+
*
736
+
* Release the claim. Device is no longer guaranteed to stay
737
+
* in buffer mode.
738
+
*
739
+
* Use with iio_device_try_claim_buffer_mode().
740
+
*/
741
+
#define iio_device_release_buffer_mode(indio_dev) __iio_dev_mode_unlock(indio_dev)
742
+
743
+
/*
744
+
* These classes are not meant to be used directly by drivers (hence the
745
+
* __priv__ prefix). Instead, documented wrapper macros are provided below to
746
+
* enforce the use of ACQUIRE() or guard() semantics and avoid the problematic
747
+
* scoped guard variants.
748
+
*/
749
+
DEFINE_GUARD(__priv__iio_dev_mode_lock, struct iio_dev *,
750
+
__iio_dev_mode_lock(_T), __iio_dev_mode_unlock(_T));
751
+
DEFINE_GUARD_COND(__priv__iio_dev_mode_lock, _try_direct,
752
+
iio_device_claim_direct(_T));
753
+
754
+
/**
755
+
* IIO_DEV_ACQUIRE_DIRECT_MODE() - Tries to acquire the direct mode lock with
756
+
* automatic release
757
+
* @dev: IIO device instance
758
+
* @claim: Variable identifier to store acquire result
759
+
*
760
+
* Tries to acquire the direct mode lock with cleanup ACQUIRE() semantics and
761
+
* automatically releases it at the end of the scope. It most be always paired
762
+
* with IIO_DEV_ACQUIRE_ERR(), for example (notice the scope braces)::
763
+
*
764
+
* switch() {
765
+
* case IIO_CHAN_INFO_RAW: {
766
+
* IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
767
+
* if (IIO_DEV_ACQUIRE_FAILED(claim))
768
+
* return -EBUSY;
769
+
*
770
+
* ...
771
+
* }
772
+
* case IIO_CHAN_INFO_SCALE:
773
+
* ...
774
+
* ...
775
+
* }
776
+
*
777
+
* Context: Can sleep
778
+
*/
779
+
#define IIO_DEV_ACQUIRE_DIRECT_MODE(dev, claim) \
780
+
ACQUIRE(__priv__iio_dev_mode_lock_try_direct, claim)(dev)
781
+
782
+
/**
783
+
* IIO_DEV_ACQUIRE_FAILED() - ACQUIRE_ERR() wrapper
784
+
* @claim: The claim variable passed to IIO_DEV_ACQUIRE_*_MODE()
785
+
*
786
+
* Return: true if failed to acquire the mode, otherwise false.
787
+
*/
788
+
#define IIO_DEV_ACQUIRE_FAILED(claim) \
789
+
ACQUIRE_ERR(__priv__iio_dev_mode_lock_try_direct, &(claim))
790
+
791
+
/**
792
+
* IIO_DEV_GUARD_CURRENT_MODE() - Acquires the mode lock with automatic release
793
+
* @dev: IIO device instance
794
+
*
795
+
* Acquires the mode lock with cleanup guard() semantics. It is usually paired
796
+
* with iio_buffer_enabled().
797
+
*
798
+
* This should *not* be used to protect internal driver state and it's use in
799
+
* general is *strongly* discouraged. Use any of the IIO_DEV_ACQUIRE_*_MODE()
800
+
* variants.
801
+
*
802
+
* Context: Can sleep
803
+
*/
804
+
#define IIO_DEV_GUARD_CURRENT_MODE(dev) \
805
+
guard(__priv__iio_dev_mode_lock)(dev)
693
806
694
807
extern const struct bus_type iio_bus_type;
695
808
+9
-3
include/linux/platform_data/cros_ec_commands.h
+9
-3
include/linux/platform_data/cros_ec_commands.h
···
2598
2598
2599
2599
/*
2600
2600
* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA
2601
-
* and MOTIONSENSE_CMD_PERFORM_CALIB.
2602
2601
*/
2603
2602
struct __ec_todo_unpacked {
2604
2603
uint8_t sensor_num;
2605
-
} info, info_3, data, fifo_flush, perform_calib,
2606
-
list_activities;
2604
+
} info, info_3, data, fifo_flush, list_activities;
2607
2605
2606
+
/*
2607
+
* Used for MOTIONSENSE_CMD_PERFORM_CALIB:
2608
+
* Allow entering/exiting the calibration mode.
2609
+
*/
2610
+
struct __ec_todo_unpacked {
2611
+
uint8_t sensor_num;
2612
+
uint8_t enable;
2613
+
} perform_calib;
2608
2614
/*
2609
2615
* Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR
2610
2616
* and MOTIONSENSE_CMD_SENSOR_RANGE.
+19
include/linux/units.h
+19
include/linux/units.h
···
21
21
#define PICO 1000000000000ULL
22
22
#define FEMTO 1000000000000000ULL
23
23
24
+
/*
25
+
* Percentage and related scaling units
26
+
*
27
+
* These macros define scaling factors used to convert between ratio and
28
+
* percentage-based representations with different decimal resolutions.
29
+
* They are used for precise fractional calculations in engineering, finance,
30
+
* and measurement applications.
31
+
*
32
+
* Examples:
33
+
* 1% = 0.01 = 1 / PERCENT
34
+
* 0.1% = 0.001 = 1 / PERMILLE
35
+
* 0.01% = 0.0001 = 1 / PERMYRIAD (1 basis point)
36
+
* 0.001% = 0.00001 = 1 / PERCENTMILLE
37
+
*/
38
+
#define PERCENT 100
39
+
#define PERMILLE 1000
40
+
#define PERMYRIAD 10000
41
+
#define PERCENTMILLE 100000
42
+
24
43
#define NANOHZ_PER_HZ 1000000000UL
25
44
#define MICROHZ_PER_HZ 1000000UL
26
45
#define MILLIHZ_PER_HZ 1000UL