Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (23 commits)
sh: Make intc messages consistent via pr_fmt.
sh: make sure static declaration on ms7724se
sh: make sure static declaration on mach-migor
sh: make sure static declaration on mach-ecovec24
sh: make sure static declaration on mach-ap325rxa
clocksource: sh_cmt: compute mult and shift before registration
clocksource: sh_tmu: compute mult and shift before registration
sh: PIO disabling for x3proto and urquell.
sh: mach-sdk7786: conditionally disable PIO support.
sh: support for platforms without PIO.
usb: r8a66597-hcd pio to mmio accessor conversion.
usb: gadget: r8a66597-udc pio to mmio accessor conversion.
usb: gadget: m66592-udc pio to mmio accessor conversion.
sh: add romImage MMCIF boot for sh7724 and Ecovec V2
sh: add boot code to MMCIF driver header
sh: prepare MMCIF driver header file
sh: allow romImage data between head.S and the zero page
sh: Add support MMCIF for ecovec
sh: remove duplicated #include
input: serio: disable i8042 for non-cayman sh platforms.
...
+642
-204
+15
-1
arch/sh/Kconfig
+15
-1
arch/sh/Kconfig
···
9
9
def_bool y
10
10
select EMBEDDED
11
11
select HAVE_CLK
12
-
select HAVE_IDE
12
+
select HAVE_IDE if HAS_IOPORT
13
13
select HAVE_LMB
14
14
select HAVE_OPROFILE
15
15
select HAVE_GENERIC_DMA_COHERENT
···
173
173
174
174
config ARCH_HAS_CPU_IDLE_WAIT
175
175
def_bool y
176
+
177
+
config NO_IOPORT
178
+
bool
176
179
177
180
config IO_TRAPPED
178
181
bool
···
778
775
default "0x00004000" if PAGE_SIZE_16KB
779
776
default "0x00010000" if PAGE_SIZE_64KB
780
777
default "0x00000000"
778
+
779
+
config ROMIMAGE_MMCIF
780
+
bool "Include MMCIF loader in romImage (EXPERIMENTAL)"
781
+
depends on CPU_SUBTYPE_SH7724 && EXPERIMENTAL
782
+
help
783
+
Say Y here to include experimental MMCIF loading code in
784
+
romImage. With this enabled it is possible to write the romImage
785
+
kernel image to an MMC card and boot the kernel straight from
786
+
the reset vector. At reset the processor Mask ROM will load the
787
+
first part of the romImage which in turn loads the rest the kernel
788
+
image to RAM using the MMCIF hardware block.
781
789
782
790
choice
783
791
prompt "Kernel command line"
+3
arch/sh/boards/Kconfig
+3
arch/sh/boards/Kconfig
···
154
154
bool "SDK7786"
155
155
depends on CPU_SUBTYPE_SH7786
156
156
select SYS_SUPPORTS_PCI
157
+
select NO_IOPORT if !PCI
157
158
help
158
159
Select SDK7786 if configuring for a Renesas Technology Europe
159
160
SH7786-65nm board.
···
191
190
depends on CPU_SUBTYPE_SH7786
192
191
select ARCH_REQUIRE_GPIOLIB
193
192
select SYS_SUPPORTS_PCI
193
+
select NO_IOPORT if !PCI
194
194
195
195
config SH_MIGOR
196
196
bool "Migo-R"
···
288
286
config SH_X3PROTO
289
287
bool "SH-X3 Prototype board"
290
288
depends on CPU_SUBTYPE_SHX3
289
+
select NO_IOPORT if !PCI
291
290
292
291
config SH_MAGIC_PANEL_R2
293
292
bool "Magic Panel R2"
+1
-1
arch/sh/boards/mach-ap325rxa/setup.c
+1
-1
arch/sh/boards/mach-ap325rxa/setup.c
+91
-10
arch/sh/boards/mach-ecovec24/setup.c
+91
-10
arch/sh/boards/mach-ecovec24/setup.c
···
12
12
#include <linux/device.h>
13
13
#include <linux/platform_device.h>
14
14
#include <linux/mfd/sh_mobile_sdhi.h>
15
+
#include <linux/mmc/host.h>
16
+
#include <linux/mmc/sh_mmcif.h>
15
17
#include <linux/mtd/physmap.h>
16
18
#include <linux/gpio.h>
17
19
#include <linux/interrupt.h>
···
28
26
#include <linux/mmc/host.h>
29
27
#include <linux/input.h>
30
28
#include <linux/input/sh_keysc.h>
31
-
#include <linux/mfd/sh_mobile_sdhi.h>
32
29
#include <video/sh_mobile_lcdc.h>
33
30
#include <sound/sh_fsi.h>
34
31
#include <media/sh_mobile_ceu.h>
···
140
139
},
141
140
};
142
141
143
-
struct sh_eth_plat_data sh_eth_plat = {
142
+
static struct sh_eth_plat_data sh_eth_plat = {
144
143
.phy = 0x1f, /* SMSC LAN8700 */
145
144
.edmac_endian = EDMAC_LITTLE_ENDIAN,
146
145
.ether_link_active_low = 1
···
160
159
};
161
160
162
161
/* USB0 host */
163
-
void usb0_port_power(int port, int power)
162
+
static void usb0_port_power(int port, int power)
164
163
{
165
164
gpio_set_value(GPIO_PTB4, power);
166
165
}
···
196
195
};
197
196
198
197
/* USB1 host/function */
199
-
void usb1_port_power(int port, int power)
198
+
static void usb1_port_power(int port, int power)
200
199
{
201
200
gpio_set_value(GPIO_PTB5, power);
202
201
}
···
422
421
return 0;
423
422
}
424
423
425
-
struct tsc2007_platform_data tsc2007_info = {
424
+
static struct tsc2007_platform_data tsc2007_info = {
426
425
.model = 2007,
427
426
.x_plate_ohms = 180,
428
427
.get_pendown_state = ts_get_pendown_state,
···
437
436
};
438
437
439
438
#ifdef CONFIG_MFD_SH_MOBILE_SDHI
440
-
/* SHDI0 */
439
+
/* SDHI0 */
441
440
static void sdhi0_set_pwr(struct platform_device *pdev, int state)
442
441
{
443
442
gpio_set_value(GPIO_PTB6, state);
···
475
474
},
476
475
};
477
476
478
-
/* SHDI1 */
477
+
#if !defined(CONFIG_MMC_SH_MMCIF)
478
+
/* SDHI1 */
479
479
static void sdhi1_set_pwr(struct platform_device *pdev, int state)
480
480
{
481
481
gpio_set_value(GPIO_PTB7, state);
···
513
511
.hwblk_id = HWBLK_SDHI1,
514
512
},
515
513
};
514
+
#endif /* CONFIG_MMC_SH_MMCIF */
516
515
517
516
#else
518
517
···
723
720
.rate = 0, /* unknown */
724
721
};
725
722
726
-
struct sh_fsi_platform_info fsi_info = {
723
+
static struct sh_fsi_platform_info fsi_info = {
727
724
.portb_flags = SH_FSI_BRS_INV |
728
725
SH_FSI_OUT_SLAVE_MODE |
729
726
SH_FSI_IN_SLAVE_MODE |
···
780
777
#include <media/ak881x.h>
781
778
#include <media/sh_vou.h>
782
779
783
-
struct ak881x_pdata ak881x_pdata = {
780
+
static struct ak881x_pdata ak881x_pdata = {
784
781
.flags = AK881X_IF_MODE_SLAVE,
785
782
};
786
783
···
789
786
.platform_data = &ak881x_pdata,
790
787
};
791
788
792
-
struct sh_vou_pdata sh_vou_pdata = {
789
+
static struct sh_vou_pdata sh_vou_pdata = {
793
790
.bus_fmt = SH_VOU_BUS_8BIT,
794
791
.flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
795
792
.board_info = &ak8813,
···
822
819
},
823
820
};
824
821
822
+
#if defined(CONFIG_MMC_SH_MMCIF)
823
+
/* SH_MMCIF */
824
+
static void mmcif_set_pwr(struct platform_device *pdev, int state)
825
+
{
826
+
gpio_set_value(GPIO_PTB7, state);
827
+
}
828
+
829
+
static void mmcif_down_pwr(struct platform_device *pdev)
830
+
{
831
+
gpio_set_value(GPIO_PTB7, 0);
832
+
}
833
+
834
+
static struct resource sh_mmcif_resources[] = {
835
+
[0] = {
836
+
.name = "SH_MMCIF",
837
+
.start = 0xA4CA0000,
838
+
.end = 0xA4CA00FF,
839
+
.flags = IORESOURCE_MEM,
840
+
},
841
+
[1] = {
842
+
/* MMC2I */
843
+
.start = 29,
844
+
.flags = IORESOURCE_IRQ,
845
+
},
846
+
[2] = {
847
+
/* MMC3I */
848
+
.start = 30,
849
+
.flags = IORESOURCE_IRQ,
850
+
},
851
+
};
852
+
853
+
static struct sh_mmcif_plat_data sh_mmcif_plat = {
854
+
.set_pwr = mmcif_set_pwr,
855
+
.down_pwr = mmcif_down_pwr,
856
+
.sup_pclk = 0, /* SH7724: Max Pclk/2 */
857
+
.caps = MMC_CAP_4_BIT_DATA |
858
+
MMC_CAP_8_BIT_DATA |
859
+
MMC_CAP_NEEDS_POLL,
860
+
.ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
861
+
};
862
+
863
+
static struct platform_device sh_mmcif_device = {
864
+
.name = "sh_mmcif",
865
+
.id = 0,
866
+
.dev = {
867
+
.platform_data = &sh_mmcif_plat,
868
+
},
869
+
.num_resources = ARRAY_SIZE(sh_mmcif_resources),
870
+
.resource = sh_mmcif_resources,
871
+
};
872
+
#endif
873
+
825
874
static struct platform_device *ecovec_devices[] __initdata = {
826
875
&heartbeat_device,
827
876
&nor_flash_device,
···
886
831
&keysc_device,
887
832
#ifdef CONFIG_MFD_SH_MOBILE_SDHI
888
833
&sdhi0_device,
834
+
#if !defined(CONFIG_MMC_SH_MMCIF)
889
835
&sdhi1_device,
836
+
#endif
890
837
#else
891
838
&msiof0_device,
892
839
#endif
···
898
841
&fsi_device,
899
842
&irda_device,
900
843
&vou_device,
844
+
#if defined(CONFIG_MMC_SH_MMCIF)
845
+
&sh_mmcif_device,
846
+
#endif
901
847
};
902
848
903
849
#ifdef CONFIG_I2C
···
1194
1134
gpio_request(GPIO_PTB6, NULL);
1195
1135
gpio_direction_output(GPIO_PTB6, 0);
1196
1136
1137
+
#if !defined(CONFIG_MMC_SH_MMCIF)
1197
1138
/* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
1198
1139
gpio_request(GPIO_FN_SDHI1CD, NULL);
1199
1140
gpio_request(GPIO_FN_SDHI1WP, NULL);
···
1209
1148
1210
1149
/* I/O buffer drive ability is high for SDHI1 */
1211
1150
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1151
+
#endif /* CONFIG_MMC_SH_MMCIF */
1212
1152
#else
1213
1153
/* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
1214
1154
gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
···
1284
1222
gpio_request(GPIO_FN_IRDA_IN, NULL);
1285
1223
gpio_request(GPIO_PTU5, NULL);
1286
1224
gpio_direction_output(GPIO_PTU5, 0);
1225
+
1226
+
#if defined(CONFIG_MMC_SH_MMCIF)
1227
+
/* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
1228
+
gpio_request(GPIO_FN_MMC_D7, NULL);
1229
+
gpio_request(GPIO_FN_MMC_D6, NULL);
1230
+
gpio_request(GPIO_FN_MMC_D5, NULL);
1231
+
gpio_request(GPIO_FN_MMC_D4, NULL);
1232
+
gpio_request(GPIO_FN_MMC_D3, NULL);
1233
+
gpio_request(GPIO_FN_MMC_D2, NULL);
1234
+
gpio_request(GPIO_FN_MMC_D1, NULL);
1235
+
gpio_request(GPIO_FN_MMC_D0, NULL);
1236
+
gpio_request(GPIO_FN_MMC_CLK, NULL);
1237
+
gpio_request(GPIO_FN_MMC_CMD, NULL);
1238
+
gpio_request(GPIO_PTB7, NULL);
1239
+
gpio_direction_output(GPIO_PTB7, 0);
1240
+
1241
+
/* I/O buffer drive ability is high for MMCIF */
1242
+
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1243
+
#endif
1287
1244
1288
1245
/* enable I2C device */
1289
1246
i2c_register_board_info(0, i2c0_devices,
+1
-1
arch/sh/boards/mach-migor/setup.c
+1
-1
arch/sh/boards/mach-migor/setup.c
+4
-4
arch/sh/boards/mach-se/7724/setup.c
+4
-4
arch/sh/boards/mach-se/7724/setup.c
···
283
283
};
284
284
285
285
/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
286
-
struct sh_fsi_platform_info fsi_info = {
286
+
static struct sh_fsi_platform_info fsi_info = {
287
287
.porta_flags = SH_FSI_BRS_INV |
288
288
SH_FSI_OUT_SLAVE_MODE |
289
289
SH_FSI_IN_SLAVE_MODE |
···
371
371
},
372
372
};
373
373
374
-
struct sh_eth_plat_data sh_eth_plat = {
374
+
static struct sh_eth_plat_data sh_eth_plat = {
375
375
.phy = 0x1f, /* SMSC LAN8187 */
376
376
.edmac_endian = EDMAC_LITTLE_ENDIAN,
377
377
};
···
535
535
#include <media/ak881x.h>
536
536
#include <media/sh_vou.h>
537
537
538
-
struct ak881x_pdata ak881x_pdata = {
538
+
static struct ak881x_pdata ak881x_pdata = {
539
539
.flags = AK881X_IF_MODE_SLAVE,
540
540
};
541
541
···
545
545
.platform_data = &ak881x_pdata,
546
546
};
547
547
548
-
struct sh_vou_pdata sh_vou_pdata = {
548
+
static struct sh_vou_pdata sh_vou_pdata = {
549
549
.bus_fmt = SH_VOU_BUS_8BIT,
550
550
.flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
551
551
.board_info = &ak8813,
+9
-4
arch/sh/boot/romimage/Makefile
+9
-4
arch/sh/boot/romimage/Makefile
···
1
1
#
2
2
# linux/arch/sh/boot/romimage/Makefile
3
3
#
4
-
# create an image suitable for burning to flash from zImage
4
+
# create an romImage file suitable for burning to flash/mmc from zImage
5
5
#
6
6
7
7
targets := vmlinux head.o zeropage.bin piggy.o
8
+
load-y := 0
8
9
9
-
OBJECTS = $(obj)/head.o
10
-
LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext 0 -e romstart \
10
+
mmcif-load-$(CONFIG_CPU_SUBTYPE_SH7724) := 0xe5200000 # ILRAM
11
+
mmcif-obj-$(CONFIG_CPU_SUBTYPE_SH7724) := $(obj)/mmcif-sh7724.o
12
+
load-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-load-y)
13
+
obj-$(CONFIG_ROMIMAGE_MMCIF) := $(mmcif-obj-y)
14
+
15
+
LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(load-y) -e romstart \
11
16
-T $(obj)/../../kernel/vmlinux.lds
12
17
13
-
$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o FORCE
18
+
$(obj)/vmlinux: $(obj)/head.o $(obj-y) $(obj)/piggy.o FORCE
14
19
$(call if_changed,ld)
15
20
@:
16
21
+39
-3
arch/sh/boot/romimage/head.S
+39
-3
arch/sh/boot/romimage/head.S
···
12
12
/* include board specific setup code */
13
13
#include <mach/romimage.h>
14
14
15
+
#ifdef CONFIG_ROMIMAGE_MMCIF
16
+
/* load the romImage to above the empty zero page */
17
+
mov.l empty_zero_page_dst, r4
18
+
mov.l empty_zero_page_dst_adj, r5
19
+
add r5, r4
20
+
mov.l bytes_to_load, r5
21
+
mov.l loader_function, r7
22
+
jsr @r7
23
+
mov r4, r15
24
+
25
+
mov.l empty_zero_page_dst, r4
26
+
mov.l empty_zero_page_dst_adj, r5
27
+
add r5, r4
28
+
mov.l loaded_code_offs, r5
29
+
add r5, r4
30
+
jmp @r4
31
+
nop
32
+
33
+
.balign 4
34
+
empty_zero_page_dst_adj:
35
+
.long PAGE_SIZE
36
+
bytes_to_load:
37
+
.long end_data - romstart
38
+
loader_function:
39
+
.long mmcif_loader
40
+
loaded_code_offs:
41
+
.long loaded_code - romstart
42
+
loaded_code:
43
+
#endif /* CONFIG_ROMIMAGE_MMCIF */
44
+
15
45
/* copy the empty_zero_page contents to where vmlinux expects it */
16
-
mova empty_zero_page_src, r0
46
+
mova extra_data_pos, r0
47
+
mov.l extra_data_size, r1
48
+
add r1, r0
17
49
mov.l empty_zero_page_dst, r1
18
50
mov #(PAGE_SHIFT - 4), r4
19
51
mov #1, r3
···
69
37
mov #PAGE_SHIFT, r4
70
38
mov #1, r1
71
39
shld r4, r1
72
-
mova empty_zero_page_src, r0
40
+
mova extra_data_pos, r0
41
+
add r1, r0
42
+
mov.l extra_data_size, r1
73
43
add r1, r0
74
44
jmp @r0
75
45
nop
···
79
45
.align 2
80
46
empty_zero_page_dst:
81
47
.long _text
82
-
empty_zero_page_src:
48
+
extra_data_pos:
49
+
extra_data_size:
50
+
.long zero_page_pos - extra_data_pos
+72
arch/sh/boot/romimage/mmcif-sh7724.c
+72
arch/sh/boot/romimage/mmcif-sh7724.c
···
1
+
/*
2
+
* sh7724 MMCIF loader
3
+
*
4
+
* Copyright (C) 2010 Magnus Damm
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
11
+
#include <linux/mmc/sh_mmcif.h>
12
+
#include <mach/romimage.h>
13
+
14
+
#define MMCIF_BASE (void __iomem *)0xa4ca0000
15
+
16
+
#define MSTPCR2 0xa4150038
17
+
#define PTWCR 0xa4050146
18
+
#define PTXCR 0xa4050148
19
+
#define PSELA 0xa405014e
20
+
#define PSELE 0xa4050156
21
+
#define HIZCRC 0xa405015c
22
+
#define DRVCRA 0xa405018a
23
+
24
+
enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
25
+
MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
26
+
27
+
/* SH7724 specific MMCIF loader
28
+
*
29
+
* loads the romImage from an MMC card starting from block 512
30
+
* use the following line to write the romImage to an MMC card
31
+
* # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
32
+
*/
33
+
asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
34
+
{
35
+
mmcif_update_progress(MMCIF_PROGRESS_ENTER);
36
+
37
+
/* enable clock to the MMCIF hardware block */
38
+
__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
39
+
40
+
/* setup pins D7-D0 */
41
+
__raw_writew(0x0000, PTWCR);
42
+
43
+
/* setup pins MMC_CLK, MMC_CMD */
44
+
__raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
45
+
46
+
/* select D3-D0 pin function */
47
+
__raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
48
+
49
+
/* select D7-D4 pin function */
50
+
__raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
51
+
52
+
/* disable Hi-Z for the MMC pins */
53
+
__raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
54
+
55
+
/* high drive capability for MMC pins */
56
+
__raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
57
+
58
+
mmcif_update_progress(MMCIF_PROGRESS_INIT);
59
+
60
+
/* setup MMCIF hardware */
61
+
sh_mmcif_boot_init(MMCIF_BASE);
62
+
63
+
mmcif_update_progress(MMCIF_PROGRESS_LOAD);
64
+
65
+
/* load kernel via MMCIF interface */
66
+
sh_mmcif_boot_slurp(MMCIF_BASE, buf, no_bytes);
67
+
68
+
/* disable clock to the MMCIF hardware block */
69
+
__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
70
+
71
+
mmcif_update_progress(MMCIF_PROGRESS_DONE);
72
+
}
+2
arch/sh/boot/romimage/vmlinux.scr
+2
arch/sh/boot/romimage/vmlinux.scr
+8
arch/sh/include/asm/io.h
+8
arch/sh/include/asm/io.h
···
39
39
#include <asm/io_generic.h>
40
40
#include <asm/io_trapped.h>
41
41
42
+
#ifdef CONFIG_HAS_IOPORT
43
+
42
44
#define inb(p) sh_mv.mv_inb((p))
43
45
#define inw(p) sh_mv.mv_inw((p))
44
46
#define inl(p) sh_mv.mv_inl((p))
···
61
59
#define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
62
60
#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
63
61
#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
62
+
63
+
#endif
64
64
65
65
#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
66
66
#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
···
244
240
245
241
#define IO_SPACE_LIMIT 0xffffffff
246
242
243
+
#ifdef CONFIG_HAS_IOPORT
244
+
247
245
/*
248
246
* This function provides a method for the generic case where a
249
247
* board-specific ioport_map simply needs to return the port + some
···
260
254
}
261
255
262
256
#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
257
+
258
+
#endif
263
259
264
260
/* We really want to try and get these to memcpy etc */
265
261
void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
+5
-4
arch/sh/include/asm/machvec.h
+5
-4
arch/sh/include/asm/machvec.h
···
19
19
const char *mv_name;
20
20
int mv_nr_irqs;
21
21
22
+
int (*mv_irq_demux)(int irq);
23
+
void (*mv_init_irq)(void);
24
+
25
+
#ifdef CONFIG_HAS_IOPORT
22
26
u8 (*mv_inb)(unsigned long);
23
27
u16 (*mv_inw)(unsigned long);
24
28
u32 (*mv_inl)(unsigned long);
···
44
40
void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
45
41
void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
46
42
47
-
int (*mv_irq_demux)(int irq);
48
-
49
-
void (*mv_init_irq)(void);
50
-
51
43
void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
52
44
void (*mv_ioport_unmap)(void __iomem *);
45
+
#endif
53
46
54
47
int (*mv_clk_init)(void);
55
48
int (*mv_mode_pins)(void);
+1
arch/sh/include/cpu-sh4/cpu/sh7724.h
+1
arch/sh/include/cpu-sh4/cpu/sh7724.h
+10
arch/sh/include/mach-common/mach/romimage.h
+10
arch/sh/include/mach-common/mach/romimage.h
+27
arch/sh/include/mach-ecovec24/mach/romimage.h
+27
arch/sh/include/mach-ecovec24/mach/romimage.h
···
1
+
#ifdef __ASSEMBLY__
2
+
1
3
/* EcoVec board specific boot code:
2
4
* converts the "partner-jet-script.txt" script into assembly
3
5
* the assembly code is the first code to be executed in the romImage
···
20
18
.align 2
21
19
1 : .long 0xa8000000
22
20
2 :
21
+
22
+
#else /* __ASSEMBLY__ */
23
+
24
+
/* Ecovec board specific information:
25
+
*
26
+
* Set the following to enable MMCIF boot from the MMC card in CN12:
27
+
*
28
+
* DS1.5 = OFF (SH BOOT pin set to L)
29
+
* DS2.6 = OFF (Select MMCIF on CN12 instead of SDHI1)
30
+
* DS2.7 = ON (Select MMCIF on CN12 instead of SDHI1)
31
+
*
32
+
*/
33
+
#define HIZCRA 0xa4050158
34
+
#define PGDR 0xa405012c
35
+
36
+
extern inline void mmcif_update_progress(int nr)
37
+
{
38
+
/* disable Hi-Z for LED pins */
39
+
__raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
40
+
41
+
/* update progress on LED4, LED5, LED6 and LED7 */
42
+
__raw_writeb(1 << (nr - 1), PGDR);
43
+
}
44
+
45
+
#endif /* __ASSEMBLY__ */
+10
arch/sh/include/mach-kfr2r09/mach/romimage.h
+10
arch/sh/include/mach-kfr2r09/mach/romimage.h
···
1
+
#ifdef __ASSEMBLY__
2
+
1
3
/* kfr2r09 board specific boot code:
2
4
* converts the "partner-jet-script.txt" script into assembly
3
5
* the assembly code is the first code to be executed in the romImage
···
20
18
.align 2
21
19
1: .long 0xa8000000
22
20
2:
21
+
22
+
#else /* __ASSEMBLY__ */
23
+
24
+
extern inline void mmcif_update_progress(int nr)
25
+
{
26
+
}
27
+
28
+
#endif /* __ASSEMBLY__ */
+2
-1
arch/sh/kernel/Makefile
+2
-1
arch/sh/kernel/Makefile
···
12
12
CFLAGS_REMOVE_return_address.o = -pg
13
13
14
14
obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
15
-
idle.o io.o io_generic.o irq.o \
15
+
idle.o io.o irq.o \
16
16
irq_$(BITS).o machvec.o nmi_debug.o process.o \
17
17
process_$(BITS).o ptrace_$(BITS).o \
18
18
reboot.o return_address.o \
···
39
39
obj-$(CONFIG_HIBERNATION) += swsusp.o
40
40
obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
41
41
obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o
42
+
obj-$(CONFIG_HAS_IOPORT) += io_generic.o
42
43
43
44
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
44
45
obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
+17
-2
arch/sh/kernel/dwarf.c
+17
-2
arch/sh/kernel/dwarf.c
···
49
49
50
50
static struct dwarf_cie *cached_cie;
51
51
52
+
static unsigned int dwarf_unwinder_ready;
53
+
52
54
/**
53
55
* dwarf_frame_alloc_reg - allocate memory for a DWARF register
54
56
* @frame: the DWARF frame whose list of registers we insert on
···
582
580
struct dwarf_fde *fde;
583
581
struct dwarf_reg *reg;
584
582
unsigned long addr;
583
+
584
+
/*
585
+
* If we've been called in to before initialization has
586
+
* completed, bail out immediately.
587
+
*/
588
+
if (!dwarf_unwinder_ready)
589
+
return NULL;
585
590
586
591
/*
587
592
* If we're starting at the top of the stack we need get the
···
1176
1167
*/
1177
1168
static int __init dwarf_unwinder_init(void)
1178
1169
{
1179
-
int err;
1170
+
int err = -ENOMEM;
1180
1171
1181
1172
dwarf_frame_cachep = kmem_cache_create("dwarf_frames",
1182
1173
sizeof(struct dwarf_frame), 0,
···
1190
1181
mempool_alloc_slab,
1191
1182
mempool_free_slab,
1192
1183
dwarf_frame_cachep);
1184
+
if (!dwarf_frame_pool)
1185
+
goto out;
1193
1186
1194
1187
dwarf_reg_pool = mempool_create(DWARF_REG_MIN_REQ,
1195
1188
mempool_alloc_slab,
1196
1189
mempool_free_slab,
1197
1190
dwarf_reg_cachep);
1191
+
if (!dwarf_reg_pool)
1192
+
goto out;
1198
1193
1199
1194
err = dwarf_parse_section(__start_eh_frame, __stop_eh_frame, NULL);
1200
1195
if (err)
···
1208
1195
if (err)
1209
1196
goto out;
1210
1197
1198
+
dwarf_unwinder_ready = 1;
1199
+
1211
1200
return 0;
1212
1201
1213
1202
out:
1214
1203
printk(KERN_ERR "Failed to initialise DWARF unwinder: %d\n", err);
1215
1204
dwarf_unwinder_cleanup();
1216
-
return -EINVAL;
1205
+
return err;
1217
1206
}
1218
1207
early_initcall(dwarf_unwinder_init);
-22
arch/sh/kernel/io.c
-22
arch/sh/kernel/io.c
···
112
112
}
113
113
}
114
114
EXPORT_SYMBOL(memset_io);
115
-
116
-
#ifndef CONFIG_GENERIC_IOMAP
117
-
118
-
void __iomem *ioport_map(unsigned long port, unsigned int nr)
119
-
{
120
-
void __iomem *ret;
121
-
122
-
ret = __ioport_map_trapped(port, nr);
123
-
if (ret)
124
-
return ret;
125
-
126
-
return __ioport_map(port, nr);
127
-
}
128
-
EXPORT_SYMBOL(ioport_map);
129
-
130
-
void ioport_unmap(void __iomem *addr)
131
-
{
132
-
sh_mv.mv_ioport_unmap(addr);
133
-
}
134
-
EXPORT_SYMBOL(ioport_unmap);
135
-
136
-
#endif /* CONFIG_GENERIC_IOMAP */
+20
arch/sh/kernel/io_generic.c
+20
arch/sh/kernel/io_generic.c
···
158
158
void generic_ioport_unmap(void __iomem *addr)
159
159
{
160
160
}
161
+
162
+
#ifndef CONFIG_GENERIC_IOMAP
163
+
void __iomem *ioport_map(unsigned long port, unsigned int nr)
164
+
{
165
+
void __iomem *ret;
166
+
167
+
ret = __ioport_map_trapped(port, nr);
168
+
if (ret)
169
+
return ret;
170
+
171
+
return __ioport_map(port, nr);
172
+
}
173
+
EXPORT_SYMBOL(ioport_map);
174
+
175
+
void ioport_unmap(void __iomem *addr)
176
+
{
177
+
sh_mv.mv_ioport_unmap(addr);
178
+
}
179
+
EXPORT_SYMBOL(ioport_unmap);
180
+
#endif /* CONFIG_GENERIC_IOMAP */
+4
arch/sh/kernel/io_trapped.c
+4
arch/sh/kernel/io_trapped.c
···
91
91
tiop->magic = IO_TRAPPED_MAGIC;
92
92
INIT_LIST_HEAD(&tiop->list);
93
93
spin_lock_irq(&trapped_lock);
94
+
#ifdef CONFIG_HAS_IOPORT
94
95
if (flags & IORESOURCE_IO)
95
96
list_add(&tiop->list, &trapped_io);
97
+
#endif
98
+
#ifdef CONFIG_HAS_IOMEM
96
99
if (flags & IORESOURCE_MEM)
97
100
list_add(&tiop->list, &trapped_mem);
101
+
#endif
98
102
spin_unlock_irq(&trapped_lock);
99
103
100
104
return 0;
+11
-6
arch/sh/kernel/machvec.c
+11
-6
arch/sh/kernel/machvec.c
···
118
118
sh_mv.mv_##elem = generic_##elem; \
119
119
} while (0)
120
120
121
+
#ifdef CONFIG_HAS_IOPORT
122
+
123
+
#ifdef P2SEG
124
+
__set_io_port_base(P2SEG);
125
+
#else
126
+
__set_io_port_base(0);
127
+
#endif
128
+
121
129
mv_set(inb); mv_set(inw); mv_set(inl);
122
130
mv_set(outb); mv_set(outw); mv_set(outl);
123
131
···
137
129
138
130
mv_set(ioport_map);
139
131
mv_set(ioport_unmap);
132
+
133
+
#endif
134
+
140
135
mv_set(irq_demux);
141
136
mv_set(mode_pins);
142
137
mv_set(mem_init);
143
138
144
139
if (!sh_mv.mv_nr_irqs)
145
140
sh_mv.mv_nr_irqs = NR_IRQS;
146
-
147
-
#ifdef P2SEG
148
-
__set_io_port_base(P2SEG);
149
-
#else
150
-
__set_io_port_base(0);
151
-
#endif
152
141
}
+2
arch/sh/kernel/return_address.c
+2
arch/sh/kernel/return_address.c
+13
-9
drivers/clocksource/sh_cmt.c
+13
-9
drivers/clocksource/sh_cmt.c
···
412
412
static int sh_cmt_clocksource_enable(struct clocksource *cs)
413
413
{
414
414
struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
415
-
int ret;
416
415
417
416
p->total_cycles = 0;
418
417
419
-
ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
420
-
if (ret)
421
-
return ret;
422
-
423
-
/* TODO: calculate good shift from rate and counter bit width */
424
-
cs->shift = 0;
425
-
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
426
-
return 0;
418
+
return sh_cmt_start(p, FLAG_CLOCKSOURCE);
427
419
}
428
420
429
421
static void sh_cmt_clocksource_disable(struct clocksource *cs)
···
442
450
cs->resume = sh_cmt_clocksource_resume;
443
451
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
444
452
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
453
+
454
+
/* clk_get_rate() needs an enabled clock */
455
+
clk_enable(p->clk);
456
+
p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8;
457
+
clk_disable(p->clk);
458
+
459
+
/* TODO: calculate good shift from rate and counter bit width */
460
+
cs->shift = 10;
461
+
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
462
+
445
463
dev_info(&p->pdev->dev, "used as clock source\n");
464
+
446
465
clocksource_register(cs);
466
+
447
467
return 0;
448
468
}
449
469
+11
-9
drivers/clocksource/sh_tmu.c
+11
-9
drivers/clocksource/sh_tmu.c
···
199
199
static int sh_tmu_clocksource_enable(struct clocksource *cs)
200
200
{
201
201
struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
202
-
int ret;
203
202
204
-
ret = sh_tmu_enable(p);
205
-
if (ret)
206
-
return ret;
207
-
208
-
/* TODO: calculate good shift from rate and counter bit width */
209
-
cs->shift = 10;
210
-
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
211
-
return 0;
203
+
return sh_tmu_enable(p);
212
204
}
213
205
214
206
static void sh_tmu_clocksource_disable(struct clocksource *cs)
···
220
228
cs->disable = sh_tmu_clocksource_disable;
221
229
cs->mask = CLOCKSOURCE_MASK(32);
222
230
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
231
+
232
+
/* clk_get_rate() needs an enabled clock */
233
+
clk_enable(p->clk);
234
+
/* channel will be configured at parent clock / 4 */
235
+
p->rate = clk_get_rate(p->clk) / 4;
236
+
clk_disable(p->clk);
237
+
/* TODO: calculate good shift from rate and counter bit width */
238
+
cs->shift = 10;
239
+
cs->mult = clocksource_hz2mult(p->rate, cs->shift);
240
+
223
241
dev_info(&p->pdev->dev, "used as clock source\n");
224
242
clocksource_register(cs);
225
243
return 0;
+2
-1
drivers/input/serio/Kconfig
+2
-1
drivers/input/serio/Kconfig
···
21
21
config SERIO_I8042
22
22
tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
23
23
default y
24
-
depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K && !BLACKFIN
24
+
depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && \
25
+
(!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN
25
26
help
26
27
i8042 is the chip over which the standard AT keyboard and PS/2
27
28
mouse are connected to the computer. If you use these devices,
+50
-75
drivers/mmc/host/sh_mmcif.c
+50
-75
drivers/mmc/host/sh_mmcif.c
···
30
30
#define DRIVER_NAME "sh_mmcif"
31
31
#define DRIVER_VERSION "2010-04-28"
32
32
33
-
#define MMCIF_CE_CMD_SET 0x00000000
34
-
#define MMCIF_CE_ARG 0x00000008
35
-
#define MMCIF_CE_ARG_CMD12 0x0000000C
36
-
#define MMCIF_CE_CMD_CTRL 0x00000010
37
-
#define MMCIF_CE_BLOCK_SET 0x00000014
38
-
#define MMCIF_CE_CLK_CTRL 0x00000018
39
-
#define MMCIF_CE_BUF_ACC 0x0000001C
40
-
#define MMCIF_CE_RESP3 0x00000020
41
-
#define MMCIF_CE_RESP2 0x00000024
42
-
#define MMCIF_CE_RESP1 0x00000028
43
-
#define MMCIF_CE_RESP0 0x0000002C
44
-
#define MMCIF_CE_RESP_CMD12 0x00000030
45
-
#define MMCIF_CE_DATA 0x00000034
46
-
#define MMCIF_CE_INT 0x00000040
47
-
#define MMCIF_CE_INT_MASK 0x00000044
48
-
#define MMCIF_CE_HOST_STS1 0x00000048
49
-
#define MMCIF_CE_HOST_STS2 0x0000004C
50
-
#define MMCIF_CE_VERSION 0x0000007C
51
-
52
33
/* CE_CMD_SET */
53
34
#define CMD_MASK 0x3f000000
54
35
#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
···
188
207
wait_queue_head_t intr_wait;
189
208
};
190
209
191
-
static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg)
192
-
{
193
-
return readl(host->addr + reg);
194
-
}
195
-
196
-
static inline void sh_mmcif_writel(struct sh_mmcif_host *host,
197
-
unsigned int reg, u32 val)
198
-
{
199
-
writel(val, host->addr + reg);
200
-
}
201
210
202
211
static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
203
212
unsigned int reg, u32 val)
204
213
{
205
-
writel(val | sh_mmcif_readl(host, reg), host->addr + reg);
214
+
writel(val | readl(host->addr + reg), host->addr + reg);
206
215
}
207
216
208
217
static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
209
218
unsigned int reg, u32 val)
210
219
{
211
-
writel(~val & sh_mmcif_readl(host, reg), host->addr + reg);
220
+
writel(~val & readl(host->addr + reg), host->addr + reg);
212
221
}
213
222
214
223
···
224
253
{
225
254
u32 tmp;
226
255
227
-
tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL);
256
+
tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
228
257
229
-
sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON);
230
-
sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF);
258
+
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
259
+
sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
231
260
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
232
261
SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
233
262
/* byte swap on */
···
242
271
host->sd_error = 0;
243
272
host->wait_int = 0;
244
273
245
-
state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1);
246
-
state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2);
247
-
pr_debug("%s: ERR HOST_STS1 = %08x\n", \
248
-
DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1));
249
-
pr_debug("%s: ERR HOST_STS2 = %08x\n", \
250
-
DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2));
274
+
state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
275
+
state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
276
+
pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
277
+
pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
251
278
252
279
if (state1 & STS1_CMDSEQ) {
253
280
sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
···
257
288
"command sequence timeout err\n");
258
289
return -EIO;
259
290
}
260
-
if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)
291
+
if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
261
292
& STS1_CMDSEQ))
262
293
break;
263
294
mdelay(1);
···
299
330
300
331
host->wait_int = 0;
301
332
blocksize = (BLOCK_SIZE_MASK &
302
-
sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3;
333
+
sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
303
334
for (i = 0; i < blocksize / 4; i++)
304
-
*p++ = sh_mmcif_readl(host, MMCIF_CE_DATA);
335
+
*p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
305
336
306
337
/* buffer read end */
307
338
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
···
322
353
long time;
323
354
u32 blocksize, i, j, sec, *p;
324
355
325
-
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET);
356
+
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
357
+
MMCIF_CE_BLOCK_SET);
326
358
for (j = 0; j < data->sg_len; j++) {
327
359
p = sg_virt(data->sg);
328
360
host->wait_int = 0;
···
340
370
341
371
host->wait_int = 0;
342
372
for (i = 0; i < blocksize / 4; i++)
343
-
*p++ = sh_mmcif_readl(host, MMCIF_CE_DATA);
373
+
*p++ = sh_mmcif_readl(host->addr,
374
+
MMCIF_CE_DATA);
344
375
}
345
376
if (j < data->sg_len - 1)
346
377
data->sg++;
···
368
397
369
398
host->wait_int = 0;
370
399
blocksize = (BLOCK_SIZE_MASK &
371
-
sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3;
400
+
sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
372
401
for (i = 0; i < blocksize / 4; i++)
373
-
sh_mmcif_writel(host, MMCIF_CE_DATA, *p++);
402
+
sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
374
403
375
404
/* buffer write end */
376
405
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
···
392
421
long time;
393
422
u32 i, sec, j, blocksize, *p;
394
423
395
-
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET);
424
+
blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
425
+
MMCIF_CE_BLOCK_SET);
396
426
397
427
for (j = 0; j < data->sg_len; j++) {
398
428
p = sg_virt(data->sg);
···
411
439
412
440
host->wait_int = 0;
413
441
for (i = 0; i < blocksize / 4; i++)
414
-
sh_mmcif_writel(host, MMCIF_CE_DATA, *p++);
442
+
sh_mmcif_writel(host->addr,
443
+
MMCIF_CE_DATA, *p++);
415
444
}
416
445
if (j < data->sg_len - 1)
417
446
data->sg++;
···
424
451
struct mmc_command *cmd)
425
452
{
426
453
if (cmd->flags & MMC_RSP_136) {
427
-
cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3);
428
-
cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2);
429
-
cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1);
430
-
cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0);
454
+
cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
455
+
cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
456
+
cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
457
+
cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
431
458
} else
432
-
cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0);
459
+
cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
433
460
}
434
461
435
462
static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
436
463
struct mmc_command *cmd)
437
464
{
438
-
cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12);
465
+
cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
439
466
}
440
467
441
468
static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
···
569
596
MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
570
597
571
598
if (host->data) {
572
-
sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0);
573
-
sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz);
599
+
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
600
+
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
601
+
mrq->data->blksz);
574
602
}
575
603
opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
576
604
577
-
sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0);
578
-
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask);
605
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
606
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
579
607
/* set arg */
580
-
sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg);
608
+
sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
581
609
host->wait_int = 0;
582
610
/* set cmd */
583
-
sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc);
611
+
sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
584
612
585
613
time = wait_event_interruptible_timeout(host->intr_wait,
586
614
host->wait_int == 1 || host->sd_error == 1, host->timeout);
···
726
752
u32 state = 0;
727
753
int err = 0;
728
754
729
-
state = sh_mmcif_readl(host, MMCIF_CE_INT);
755
+
state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
730
756
731
757
if (state & INT_RBSYE) {
732
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE));
758
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
759
+
~(INT_RBSYE | INT_CRSPE));
733
760
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
734
761
} else if (state & INT_CRSPE) {
735
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE);
762
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
736
763
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
737
764
} else if (state & INT_BUFREN) {
738
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN);
765
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
739
766
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
740
767
} else if (state & INT_BUFWEN) {
741
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN);
768
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
742
769
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
743
770
} else if (state & INT_CMD12DRE) {
744
-
sh_mmcif_writel(host, MMCIF_CE_INT,
771
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
745
772
~(INT_CMD12DRE | INT_CMD12RBE |
746
773
INT_CMD12CRE | INT_BUFRE));
747
774
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
748
775
} else if (state & INT_BUFRE) {
749
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE);
776
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
750
777
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
751
778
} else if (state & INT_DTRANE) {
752
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE);
779
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
753
780
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
754
781
} else if (state & INT_CMD12RBE) {
755
-
sh_mmcif_writel(host, MMCIF_CE_INT,
782
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
756
783
~(INT_CMD12RBE | INT_CMD12CRE));
757
784
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
758
785
} else if (state & INT_ERR_STS) {
759
786
/* err interrupts */
760
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~state);
787
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
761
788
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
762
789
err = 1;
763
790
} else {
764
791
pr_debug("%s: Not support int\n", DRIVER_NAME);
765
-
sh_mmcif_writel(host, MMCIF_CE_INT, ~state);
792
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
766
793
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
767
794
err = 1;
768
795
}
···
869
894
goto clean_up2;
870
895
}
871
896
872
-
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL);
897
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
873
898
sh_mmcif_detect(host->mmc);
874
899
875
900
pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
876
901
pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
877
-
sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff);
902
+
sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
878
903
return ret;
879
904
880
905
clean_up2:
···
892
917
struct sh_mmcif_host *host = platform_get_drvdata(pdev);
893
918
int irq[2];
894
919
895
-
sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL);
920
+
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
896
921
897
922
irq[0] = platform_get_irq(pdev, 0);
898
923
irq[1] = platform_get_irq(pdev, 1);
+7
-5
drivers/sh/intc.c
+7
-5
drivers/sh/intc.c
···
16
16
* License. See the file "COPYING" in the main directory of this archive
17
17
* for more details.
18
18
*/
19
+
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
+
19
21
#include <linux/init.h>
20
22
#include <linux/irq.h>
21
23
#include <linux/module.h>
···
857
855
primary = 1;
858
856
859
857
if (!data[0] && !data[1])
860
-
pr_warning("intc: missing unique irq mask for "
861
-
"irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
858
+
pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
859
+
irq, irq2evt(irq));
862
860
863
861
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
864
862
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
···
954
952
struct intc_desc_int *d;
955
953
struct resource *res;
956
954
957
-
pr_info("intc: Registered controller '%s' with %u IRQs\n",
955
+
pr_info("Registered controller '%s' with %u IRQs\n",
958
956
desc->name, hw->nr_vectors);
959
957
960
958
d = kzalloc(sizeof(*d), GFP_NOWAIT);
···
1150
1148
if (unlikely(!uimask))
1151
1149
return -ENOMEM;
1152
1150
1153
-
pr_info("intc: userimask support registered for levels 0 -> %d\n",
1151
+
pr_info("userimask support registered for levels 0 -> %d\n",
1154
1152
default_prio_level - 1);
1155
1153
1156
1154
return 0;
···
1288
1286
}
1289
1287
1290
1288
if (error)
1291
-
pr_err("intc: sysdev registration error\n");
1289
+
pr_err("sysdev registration error\n");
1292
1290
1293
1291
return error;
1294
1292
}
+11
-11
drivers/usb/gadget/m66592-udc.h
+11
-11
drivers/usb/gadget/m66592-udc.h
···
537
537
/*-------------------------------------------------------------------------*/
538
538
static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
539
539
{
540
-
return inw((unsigned long)m66592->reg + offset);
540
+
return ioread16(m66592->reg + offset);
541
541
}
542
542
543
543
static inline void m66592_read_fifo(struct m66592 *m66592,
544
544
unsigned long offset,
545
545
void *buf, unsigned long len)
546
546
{
547
-
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
547
+
void __iomem *fifoaddr = m66592->reg + offset;
548
548
549
549
if (m66592->pdata->on_chip) {
550
550
len = (len + 3) / 4;
551
-
insl(fifoaddr, buf, len);
551
+
ioread32_rep(fifoaddr, buf, len);
552
552
} else {
553
553
len = (len + 1) / 2;
554
-
insw(fifoaddr, buf, len);
554
+
ioread16_rep(fifoaddr, buf, len);
555
555
}
556
556
}
557
557
558
558
static inline void m66592_write(struct m66592 *m66592, u16 val,
559
559
unsigned long offset)
560
560
{
561
-
outw(val, (unsigned long)m66592->reg + offset);
561
+
iowrite16(val, m66592->reg + offset);
562
562
}
563
563
564
564
static inline void m66592_write_fifo(struct m66592 *m66592,
565
565
unsigned long offset,
566
566
void *buf, unsigned long len)
567
567
{
568
-
unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
568
+
void __iomem *fifoaddr = m66592->reg + offset;
569
569
570
570
if (m66592->pdata->on_chip) {
571
571
unsigned long count;
···
573
573
int i;
574
574
575
575
count = len / 4;
576
-
outsl(fifoaddr, buf, count);
576
+
iowrite32_rep(fifoaddr, buf, count);
577
577
578
578
if (len & 0x00000003) {
579
579
pb = buf + count * 4;
580
580
for (i = 0; i < (len & 0x00000003); i++) {
581
581
if (m66592_read(m66592, M66592_CFBCFG)) /* le */
582
-
outb(pb[i], fifoaddr + (3 - i));
582
+
iowrite8(pb[i], fifoaddr + (3 - i));
583
583
else
584
-
outb(pb[i], fifoaddr + i);
584
+
iowrite8(pb[i], fifoaddr + i);
585
585
}
586
586
}
587
587
} else {
588
588
unsigned long odd = len & 0x0001;
589
589
590
590
len = len / 2;
591
-
outsw(fifoaddr, buf, len);
591
+
iowrite16_rep(fifoaddr, buf, len);
592
592
if (odd) {
593
593
unsigned char *p = buf + len*2;
594
-
outb(*p, fifoaddr);
594
+
iowrite8(*p, fifoaddr);
595
595
}
596
596
}
597
597
}
+2
-2
drivers/usb/gadget/r8a66597-udc.c
+2
-2
drivers/usb/gadget/r8a66597-udc.c
···
1500
1500
struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
1501
1501
1502
1502
del_timer_sync(&r8a66597->timer);
1503
-
iounmap((void *)r8a66597->reg);
1503
+
iounmap(r8a66597->reg);
1504
1504
free_irq(platform_get_irq(pdev, 0), r8a66597);
1505
1505
r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
1506
1506
#ifdef CONFIG_HAVE_CLK
···
1578
1578
init_timer(&r8a66597->timer);
1579
1579
r8a66597->timer.function = r8a66597_timer;
1580
1580
r8a66597->timer.data = (unsigned long)r8a66597;
1581
-
r8a66597->reg = (unsigned long)reg;
1581
+
r8a66597->reg = reg;
1582
1582
1583
1583
#ifdef CONFIG_HAVE_CLK
1584
1584
if (r8a66597->pdata->on_chip) {
+12
-12
drivers/usb/gadget/r8a66597-udc.h
+12
-12
drivers/usb/gadget/r8a66597-udc.h
···
91
91
92
92
struct r8a66597 {
93
93
spinlock_t lock;
94
-
unsigned long reg;
94
+
void __iomem *reg;
95
95
96
96
#ifdef CONFIG_HAVE_CLK
97
97
struct clk *clk;
···
127
127
128
128
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
129
129
{
130
-
return inw(r8a66597->reg + offset);
130
+
return ioread16(r8a66597->reg + offset);
131
131
}
132
132
133
133
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
···
135
135
unsigned char *buf,
136
136
int len)
137
137
{
138
-
unsigned long fifoaddr = r8a66597->reg + offset;
138
+
void __iomem *fifoaddr = r8a66597->reg + offset;
139
139
unsigned int data;
140
140
int i;
141
141
···
144
144
145
145
/* aligned buf case */
146
146
if (len >= 4 && !((unsigned long)buf & 0x03)) {
147
-
insl(fifoaddr, buf, len / 4);
147
+
ioread32_rep(fifoaddr, buf, len / 4);
148
148
buf += len & ~0x03;
149
149
len &= 0x03;
150
150
}
···
152
152
/* unaligned buf case */
153
153
for (i = 0; i < len; i++) {
154
154
if (!(i & 0x03))
155
-
data = inl(fifoaddr);
155
+
data = ioread32(fifoaddr);
156
156
157
157
buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
158
158
}
···
161
161
162
162
/* aligned buf case */
163
163
if (len >= 2 && !((unsigned long)buf & 0x01)) {
164
-
insw(fifoaddr, buf, len / 2);
164
+
ioread16_rep(fifoaddr, buf, len / 2);
165
165
buf += len & ~0x01;
166
166
len &= 0x01;
167
167
}
···
169
169
/* unaligned buf case */
170
170
for (i = 0; i < len; i++) {
171
171
if (!(i & 0x01))
172
-
data = inw(fifoaddr);
172
+
data = ioread16(fifoaddr);
173
173
174
174
buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
175
175
}
···
179
179
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
180
180
unsigned long offset)
181
181
{
182
-
outw(val, r8a66597->reg + offset);
182
+
iowrite16(val, r8a66597->reg + offset);
183
183
}
184
184
185
185
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
···
187
187
unsigned char *buf,
188
188
int len)
189
189
{
190
-
unsigned long fifoaddr = r8a66597->reg + offset;
190
+
void __iomem *fifoaddr = r8a66597->reg + offset;
191
191
int adj = 0;
192
192
int i;
193
193
194
194
if (r8a66597->pdata->on_chip) {
195
195
/* 32-bit access only if buf is 32-bit aligned */
196
196
if (len >= 4 && !((unsigned long)buf & 0x03)) {
197
-
outsl(fifoaddr, buf, len / 4);
197
+
iowrite32_rep(fifoaddr, buf, len / 4);
198
198
buf += len & ~0x03;
199
199
len &= 0x03;
200
200
}
201
201
} else {
202
202
/* 16-bit access only if buf is 16-bit aligned */
203
203
if (len >= 2 && !((unsigned long)buf & 0x01)) {
204
-
outsw(fifoaddr, buf, len / 2);
204
+
iowrite16_rep(fifoaddr, buf, len / 2);
205
205
buf += len & ~0x01;
206
206
len &= 0x01;
207
207
}
···
216
216
}
217
217
218
218
for (i = 0; i < len; i++)
219
-
outb(buf[i], fifoaddr + adj - (i & adj));
219
+
iowrite8(buf[i], fifoaddr + adj - (i & adj));
220
220
}
221
221
222
222
static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
+2
-2
drivers/usb/host/r8a66597-hcd.c
+2
-2
drivers/usb/host/r8a66597-hcd.c
···
2404
2404
2405
2405
del_timer_sync(&r8a66597->rh_timer);
2406
2406
usb_remove_hcd(hcd);
2407
-
iounmap((void *)r8a66597->reg);
2407
+
iounmap(r8a66597->reg);
2408
2408
#ifdef CONFIG_HAVE_CLK
2409
2409
if (r8a66597->pdata->on_chip)
2410
2410
clk_put(r8a66597->clk);
···
2496
2496
init_timer(&r8a66597->rh_timer);
2497
2497
r8a66597->rh_timer.function = r8a66597_timer;
2498
2498
r8a66597->rh_timer.data = (unsigned long)r8a66597;
2499
-
r8a66597->reg = (unsigned long)reg;
2499
+
r8a66597->reg = reg;
2500
2500
2501
2501
/* make sure no interrupts are pending */
2502
2502
ret = r8a66597_clock_enable(r8a66597);
+13
-13
drivers/usb/host/r8a66597.h
+13
-13
drivers/usb/host/r8a66597.h
···
112
112
113
113
struct r8a66597 {
114
114
spinlock_t lock;
115
-
unsigned long reg;
115
+
void __iomem *reg;
116
116
#ifdef CONFIG_HAVE_CLK
117
117
struct clk *clk;
118
118
#endif
···
170
170
171
171
static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
172
172
{
173
-
return inw(r8a66597->reg + offset);
173
+
return ioread16(r8a66597->reg + offset);
174
174
}
175
175
176
176
static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
177
177
unsigned long offset, u16 *buf,
178
178
int len)
179
179
{
180
-
unsigned long fifoaddr = r8a66597->reg + offset;
180
+
void __iomem *fifoaddr = r8a66597->reg + offset;
181
181
unsigned long count;
182
182
183
183
if (r8a66597->pdata->on_chip) {
184
184
count = len / 4;
185
-
insl(fifoaddr, buf, count);
185
+
ioread32_rep(fifoaddr, buf, count);
186
186
187
187
if (len & 0x00000003) {
188
-
unsigned long tmp = inl(fifoaddr);
188
+
unsigned long tmp = ioread32(fifoaddr);
189
189
memcpy((unsigned char *)buf + count * 4, &tmp,
190
190
len & 0x03);
191
191
}
192
192
} else {
193
193
len = (len + 1) / 2;
194
-
insw(fifoaddr, buf, len);
194
+
ioread16_rep(fifoaddr, buf, len);
195
195
}
196
196
}
197
197
198
198
static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
199
199
unsigned long offset)
200
200
{
201
-
outw(val, r8a66597->reg + offset);
201
+
iowrite16(val, r8a66597->reg + offset);
202
202
}
203
203
204
204
static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
205
205
unsigned long offset, u16 *buf,
206
206
int len)
207
207
{
208
-
unsigned long fifoaddr = r8a66597->reg + offset;
208
+
void __iomem *fifoaddr = r8a66597->reg + offset;
209
209
unsigned long count;
210
210
unsigned char *pb;
211
211
int i;
212
212
213
213
if (r8a66597->pdata->on_chip) {
214
214
count = len / 4;
215
-
outsl(fifoaddr, buf, count);
215
+
iowrite32_rep(fifoaddr, buf, count);
216
216
217
217
if (len & 0x00000003) {
218
218
pb = (unsigned char *)buf + count * 4;
219
219
for (i = 0; i < (len & 0x00000003); i++) {
220
220
if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
221
-
outb(pb[i], fifoaddr + i);
221
+
iowrite8(pb[i], fifoaddr + i);
222
222
else
223
-
outb(pb[i], fifoaddr + 3 - i);
223
+
iowrite8(pb[i], fifoaddr + 3 - i);
224
224
}
225
225
}
226
226
} else {
227
227
int odd = len & 0x0001;
228
228
229
229
len = len / 2;
230
-
outsw(fifoaddr, buf, len);
230
+
ioread16_rep(fifoaddr, buf, len);
231
231
if (unlikely(odd)) {
232
232
buf = &buf[len];
233
-
outb((unsigned char)*buf, fifoaddr);
233
+
iowrite8((unsigned char)*buf, fifoaddr);
234
234
}
235
235
}
236
236
}
+3
-3
drivers/video/sh_mobile_lcdcfb.c
+3
-3
drivers/video/sh_mobile_lcdcfb.c
···
991
991
priv->ch[j].lcdc = priv;
992
992
memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
993
993
994
-
error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
994
+
error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
995
995
if (error) {
996
996
dev_err(&pdev->dev, "unsupported interface type\n");
997
997
goto err1;
998
998
}
999
-
init_waitqueue_head(&priv->ch[i].frame_end_wait);
1000
-
init_completion(&priv->ch[i].vsync_completion);
999
+
init_waitqueue_head(&priv->ch[j].frame_end_wait);
1000
+
init_completion(&priv->ch[j].vsync_completion);
1001
1001
priv->ch[j].pan_offset = 0;
1002
1002
1003
1003
switch (pdata->ch[i].chan) {
+161
include/linux/mmc/sh_mmcif.h
+161
include/linux/mmc/sh_mmcif.h
···
14
14
#ifndef __SH_MMCIF_H__
15
15
#define __SH_MMCIF_H__
16
16
17
+
#include <linux/platform_device.h>
18
+
#include <linux/io.h>
19
+
17
20
/*
18
21
* MMCIF : CE_CLK_CTRL [19:16]
19
22
* 1000 : Peripheral clock / 512
···
38
35
unsigned long caps;
39
36
u32 ocr;
40
37
};
38
+
39
+
#define MMCIF_CE_CMD_SET 0x00000000
40
+
#define MMCIF_CE_ARG 0x00000008
41
+
#define MMCIF_CE_ARG_CMD12 0x0000000C
42
+
#define MMCIF_CE_CMD_CTRL 0x00000010
43
+
#define MMCIF_CE_BLOCK_SET 0x00000014
44
+
#define MMCIF_CE_CLK_CTRL 0x00000018
45
+
#define MMCIF_CE_BUF_ACC 0x0000001C
46
+
#define MMCIF_CE_RESP3 0x00000020
47
+
#define MMCIF_CE_RESP2 0x00000024
48
+
#define MMCIF_CE_RESP1 0x00000028
49
+
#define MMCIF_CE_RESP0 0x0000002C
50
+
#define MMCIF_CE_RESP_CMD12 0x00000030
51
+
#define MMCIF_CE_DATA 0x00000034
52
+
#define MMCIF_CE_INT 0x00000040
53
+
#define MMCIF_CE_INT_MASK 0x00000044
54
+
#define MMCIF_CE_HOST_STS1 0x00000048
55
+
#define MMCIF_CE_HOST_STS2 0x0000004C
56
+
#define MMCIF_CE_VERSION 0x0000007C
57
+
58
+
extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
59
+
{
60
+
return readl(addr + reg);
61
+
}
62
+
63
+
extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
64
+
{
65
+
writel(val, addr + reg);
66
+
}
67
+
68
+
#define SH_MMCIF_BBS 512 /* boot block size */
69
+
70
+
extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
71
+
unsigned long cmd, unsigned long arg)
72
+
{
73
+
sh_mmcif_writel(base, MMCIF_CE_INT, 0);
74
+
sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
75
+
sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
76
+
}
77
+
78
+
extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
79
+
{
80
+
unsigned long tmp;
81
+
int cnt;
82
+
83
+
for (cnt = 0; cnt < 1000000; cnt++) {
84
+
tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
85
+
if (tmp & mask) {
86
+
sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
87
+
return 0;
88
+
}
89
+
}
90
+
91
+
return -1;
92
+
}
93
+
94
+
extern inline int sh_mmcif_boot_cmd(void __iomem *base,
95
+
unsigned long cmd, unsigned long arg)
96
+
{
97
+
sh_mmcif_boot_cmd_send(base, cmd, arg);
98
+
return sh_mmcif_boot_cmd_poll(base, 0x00010000);
99
+
}
100
+
101
+
extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
102
+
unsigned int block_nr,
103
+
unsigned long *buf)
104
+
{
105
+
int k;
106
+
107
+
/* CMD13 - Status */
108
+
sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
109
+
110
+
if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
111
+
return -1;
112
+
113
+
/* CMD17 - Read */
114
+
sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
115
+
if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
116
+
return -1;
117
+
118
+
for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
119
+
buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
120
+
121
+
return 0;
122
+
}
123
+
124
+
extern inline int sh_mmcif_boot_do_read(void __iomem *base,
125
+
unsigned long first_block,
126
+
unsigned long nr_blocks,
127
+
void *buf)
128
+
{
129
+
unsigned long k;
130
+
int ret = 0;
131
+
132
+
/* CMD16 - Set the block size */
133
+
sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
134
+
135
+
for (k = 0; !ret && k < nr_blocks; k++)
136
+
ret = sh_mmcif_boot_do_read_single(base, first_block + k,
137
+
buf + (k * SH_MMCIF_BBS));
138
+
139
+
return ret;
140
+
}
141
+
142
+
extern inline void sh_mmcif_boot_init(void __iomem *base)
143
+
{
144
+
unsigned long tmp;
145
+
146
+
/* reset */
147
+
tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
148
+
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
149
+
sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
150
+
151
+
/* byte swap */
152
+
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
153
+
154
+
/* Set block size in MMCIF hardware */
155
+
sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
156
+
157
+
/* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
158
+
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
159
+
160
+
/* CMD0 */
161
+
sh_mmcif_boot_cmd(base, 0x00000040, 0);
162
+
163
+
/* CMD1 - Get OCR */
164
+
do {
165
+
sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
166
+
} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
167
+
!= 0x80000000);
168
+
169
+
/* CMD2 - Get CID */
170
+
sh_mmcif_boot_cmd(base, 0x02806040, 0);
171
+
172
+
/* CMD3 - Set card relative address */
173
+
sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
174
+
}
175
+
176
+
extern inline void sh_mmcif_boot_slurp(void __iomem *base,
177
+
unsigned char *buf,
178
+
unsigned long no_bytes)
179
+
{
180
+
unsigned long tmp;
181
+
182
+
/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
183
+
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
184
+
185
+
/* CMD9 - Get CSD */
186
+
sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
187
+
188
+
/* CMD7 - Select the card */
189
+
sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
190
+
191
+
tmp = no_bytes / SH_MMCIF_BBS;
192
+
tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
193
+
194
+
sh_mmcif_boot_do_read(base, 512, tmp, buf);
195
+
}
41
196
42
197
#endif /* __SH_MMCIF_H__ */
+1
-3
include/linux/serial_sci.h
+1
-3
include/linux/serial_sci.h