tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge branch 'net-phy-micrel-lan8842-erratas'

Horatiu Vultur says:

====================
net: phy: micrel: lan8842 erratas

Add two erratas to the lan8842. The errata document can be found here [1]
The two erratas are:
- module 2 ("Analog front-end not optimized for PHY-side shorted center taps").
- module 7 ("1000BASE-T PMA EEE TX wake timer is non-compliant")
====================

Link: https://patch.msgid.link/20251031121629.814935-1-horatiu.vultur@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 99ae0675 7942602b

+163
+163
drivers/net/phy/micrel.c
··· 466 466 u16 rev; 467 467 }; 468 468 469 + struct lanphy_reg_data { 470 + int page; 471 + u16 addr; 472 + u16 val; 473 + }; 474 + 469 475 static const struct kszphy_type lan8814_type = { 470 476 .led_mode_reg = ~LAN8814_LED_CTRL_1, 471 477 .cable_diag_reg = LAN8814_CABLE_DIAG, ··· 2842 2836 #define LAN8814_PAGE_PCS_DIGITAL 2 2843 2837 2844 2838 /** 2839 + * LAN8814_PAGE_EEE - Selects Extended Page 3. 2840 + * 2841 + * This page contains EEE registers 2842 + */ 2843 + #define LAN8814_PAGE_EEE 3 2844 + 2845 + /** 2845 2846 * LAN8814_PAGE_COMMON_REGS - Selects Extended Page 4. 2846 2847 * 2847 2848 * This page contains device-common registers that affect the entire chip. ··· 2865 2852 * rate adaptation FIFOs, and the per-port 1588 TSU block. 2866 2853 */ 2867 2854 #define LAN8814_PAGE_PORT_REGS 5 2855 + 2856 + /** 2857 + * LAN8814_PAGE_POWER_REGS - Selects Extended Page 28. 2858 + * 2859 + * This page contains analog control registers and power mode registers. 2860 + */ 2861 + #define LAN8814_PAGE_POWER_REGS 28 2868 2862 2869 2863 /** 2870 2864 * LAN8814_PAGE_SYSTEM_CTRL - Selects Extended Page 31. ··· 5904 5884 return 0; 5905 5885 } 5906 5886 5887 + #define LAN8814_POWER_MGMT_MODE_3_ANEG_MDI 0x13 5888 + #define LAN8814_POWER_MGMT_MODE_4_ANEG_MDIX 0x14 5889 + #define LAN8814_POWER_MGMT_MODE_5_10BT_MDI 0x15 5890 + #define LAN8814_POWER_MGMT_MODE_6_10BT_MDIX 0x16 5891 + #define LAN8814_POWER_MGMT_MODE_7_100BT_TRAIN 0x17 5892 + #define LAN8814_POWER_MGMT_MODE_8_100BT_MDI 0x18 5893 + #define LAN8814_POWER_MGMT_MODE_9_100BT_EEE_MDI_TX 0x19 5894 + #define LAN8814_POWER_MGMT_MODE_10_100BT_EEE_MDI_RX 0x1a 5895 + #define LAN8814_POWER_MGMT_MODE_11_100BT_MDIX 0x1b 5896 + #define LAN8814_POWER_MGMT_MODE_12_100BT_EEE_MDIX_TX 0x1c 5897 + #define LAN8814_POWER_MGMT_MODE_13_100BT_EEE_MDIX_RX 0x1d 5898 + #define LAN8814_POWER_MGMT_MODE_14_100BTX_EEE_TX_RX 0x1e 5899 + 5900 + #define LAN8814_POWER_MGMT_DLLPD_D BIT(0) 5901 + #define LAN8814_POWER_MGMT_ADCPD_D BIT(1) 5902 + #define LAN8814_POWER_MGMT_PGAPD_D BIT(2) 5903 + #define LAN8814_POWER_MGMT_TXPD_D BIT(3) 5904 + #define LAN8814_POWER_MGMT_DLLPD_C BIT(4) 5905 + #define LAN8814_POWER_MGMT_ADCPD_C BIT(5) 5906 + #define LAN8814_POWER_MGMT_PGAPD_C BIT(6) 5907 + #define LAN8814_POWER_MGMT_TXPD_C BIT(7) 5908 + #define LAN8814_POWER_MGMT_DLLPD_B BIT(8) 5909 + #define LAN8814_POWER_MGMT_ADCPD_B BIT(9) 5910 + #define LAN8814_POWER_MGMT_PGAPD_B BIT(10) 5911 + #define LAN8814_POWER_MGMT_TXPD_B BIT(11) 5912 + #define LAN8814_POWER_MGMT_DLLPD_A BIT(12) 5913 + #define LAN8814_POWER_MGMT_ADCPD_A BIT(13) 5914 + #define LAN8814_POWER_MGMT_PGAPD_A BIT(14) 5915 + #define LAN8814_POWER_MGMT_TXPD_A BIT(15) 5916 + 5917 + #define LAN8814_POWER_MGMT_C_D (LAN8814_POWER_MGMT_DLLPD_D | \ 5918 + LAN8814_POWER_MGMT_ADCPD_D | \ 5919 + LAN8814_POWER_MGMT_PGAPD_D | \ 5920 + LAN8814_POWER_MGMT_DLLPD_C | \ 5921 + LAN8814_POWER_MGMT_ADCPD_C | \ 5922 + LAN8814_POWER_MGMT_PGAPD_C) 5923 + 5924 + #define LAN8814_POWER_MGMT_B_C_D (LAN8814_POWER_MGMT_C_D | \ 5925 + LAN8814_POWER_MGMT_DLLPD_B | \ 5926 + LAN8814_POWER_MGMT_ADCPD_B | \ 5927 + LAN8814_POWER_MGMT_PGAPD_B) 5928 + 5929 + #define LAN8814_POWER_MGMT_VAL1 (LAN8814_POWER_MGMT_C_D | \ 5930 + LAN8814_POWER_MGMT_ADCPD_B | \ 5931 + LAN8814_POWER_MGMT_PGAPD_B | \ 5932 + LAN8814_POWER_MGMT_ADCPD_A | \ 5933 + LAN8814_POWER_MGMT_PGAPD_A) 5934 + 5935 + #define LAN8814_POWER_MGMT_VAL2 LAN8814_POWER_MGMT_C_D 5936 + 5937 + #define LAN8814_POWER_MGMT_VAL3 (LAN8814_POWER_MGMT_C_D | \ 5938 + LAN8814_POWER_MGMT_DLLPD_B | \ 5939 + LAN8814_POWER_MGMT_ADCPD_B | \ 5940 + LAN8814_POWER_MGMT_PGAPD_A) 5941 + 5942 + #define LAN8814_POWER_MGMT_VAL4 (LAN8814_POWER_MGMT_B_C_D | \ 5943 + LAN8814_POWER_MGMT_ADCPD_A | \ 5944 + LAN8814_POWER_MGMT_PGAPD_A) 5945 + 5946 + #define LAN8814_POWER_MGMT_VAL5 LAN8814_POWER_MGMT_B_C_D 5947 + 5948 + #define LAN8814_EEE_WAKE_TX_TIMER 0x0e 5949 + #define LAN8814_EEE_WAKE_TX_TIMER_MAX_VAL 0x1f 5950 + 5951 + static const struct lanphy_reg_data short_center_tap_errata[] = { 5952 + { LAN8814_PAGE_POWER_REGS, 5953 + LAN8814_POWER_MGMT_MODE_3_ANEG_MDI, 5954 + LAN8814_POWER_MGMT_VAL1 }, 5955 + { LAN8814_PAGE_POWER_REGS, 5956 + LAN8814_POWER_MGMT_MODE_4_ANEG_MDIX, 5957 + LAN8814_POWER_MGMT_VAL1 }, 5958 + { LAN8814_PAGE_POWER_REGS, 5959 + LAN8814_POWER_MGMT_MODE_5_10BT_MDI, 5960 + LAN8814_POWER_MGMT_VAL1 }, 5961 + { LAN8814_PAGE_POWER_REGS, 5962 + LAN8814_POWER_MGMT_MODE_6_10BT_MDIX, 5963 + LAN8814_POWER_MGMT_VAL1 }, 5964 + { LAN8814_PAGE_POWER_REGS, 5965 + LAN8814_POWER_MGMT_MODE_7_100BT_TRAIN, 5966 + LAN8814_POWER_MGMT_VAL2 }, 5967 + { LAN8814_PAGE_POWER_REGS, 5968 + LAN8814_POWER_MGMT_MODE_8_100BT_MDI, 5969 + LAN8814_POWER_MGMT_VAL3 }, 5970 + { LAN8814_PAGE_POWER_REGS, 5971 + LAN8814_POWER_MGMT_MODE_9_100BT_EEE_MDI_TX, 5972 + LAN8814_POWER_MGMT_VAL3 }, 5973 + { LAN8814_PAGE_POWER_REGS, 5974 + LAN8814_POWER_MGMT_MODE_10_100BT_EEE_MDI_RX, 5975 + LAN8814_POWER_MGMT_VAL4 }, 5976 + { LAN8814_PAGE_POWER_REGS, 5977 + LAN8814_POWER_MGMT_MODE_11_100BT_MDIX, 5978 + LAN8814_POWER_MGMT_VAL5 }, 5979 + { LAN8814_PAGE_POWER_REGS, 5980 + LAN8814_POWER_MGMT_MODE_12_100BT_EEE_MDIX_TX, 5981 + LAN8814_POWER_MGMT_VAL5 }, 5982 + { LAN8814_PAGE_POWER_REGS, 5983 + LAN8814_POWER_MGMT_MODE_13_100BT_EEE_MDIX_RX, 5984 + LAN8814_POWER_MGMT_VAL4 }, 5985 + { LAN8814_PAGE_POWER_REGS, 5986 + LAN8814_POWER_MGMT_MODE_14_100BTX_EEE_TX_RX, 5987 + LAN8814_POWER_MGMT_VAL4 }, 5988 + }; 5989 + 5990 + static const struct lanphy_reg_data waketx_timer_errata[] = { 5991 + { LAN8814_PAGE_EEE, 5992 + LAN8814_EEE_WAKE_TX_TIMER, 5993 + LAN8814_EEE_WAKE_TX_TIMER_MAX_VAL }, 5994 + }; 5995 + 5996 + static int lanphy_write_reg_data(struct phy_device *phydev, 5997 + const struct lanphy_reg_data *data, 5998 + size_t num) 5999 + { 6000 + int ret = 0; 6001 + 6002 + while (num--) { 6003 + ret = lanphy_write_page_reg(phydev, data->page, data->addr, 6004 + data->val); 6005 + if (ret) 6006 + break; 6007 + } 6008 + 6009 + return ret; 6010 + } 6011 + 6012 + static int lan8842_erratas(struct phy_device *phydev) 6013 + { 6014 + int ret; 6015 + 6016 + ret = lanphy_write_reg_data(phydev, short_center_tap_errata, 6017 + ARRAY_SIZE(short_center_tap_errata)); 6018 + if (ret) 6019 + return ret; 6020 + 6021 + return lanphy_write_reg_data(phydev, waketx_timer_errata, 6022 + ARRAY_SIZE(waketx_timer_errata)); 6023 + } 6024 + 5907 6025 static int lan8842_config_init(struct phy_device *phydev) 5908 6026 { 5909 6027 int ret; ··· 6051 5893 LAN8814_QSGMII_SOFT_RESET, 6052 5894 LAN8814_QSGMII_SOFT_RESET_BIT, 6053 5895 LAN8814_QSGMII_SOFT_RESET_BIT); 5896 + if (ret < 0) 5897 + return ret; 5898 + 5899 + /* Apply the erratas for this device */ 5900 + ret = lan8842_erratas(phydev); 6054 5901 if (ret < 0) 6055 5902 return ret; 6056 5903