Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.7-rc6' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes frlm Dave Airlie:
"Just some AMD and Intel fixes, the AMD ones are further production
Polaris fixes, and the Intel ones fix some early timeouts, some PCI ID
changes and a couple of other fixes.
Still a bit Internet challenged here, hopefully end of next week will
solve it"
* tag 'drm-fixes-for-v4.7-rc6' of git://people.freedesktop.org/~airlied/linux:
drm/i915: Fix missing unlock on error in i915_ppgtt_info()
drm/amd/powerplay: workaround for UVD clock issue
drm/amdgpu: add ACLK_CNTL setting for polaris10
drm/amd/powerplay: fix issue uvd dpm can't enabled on Polaris11.
drm/amd/powerplay: Workaround for Memory EDC Error on Polaris10.
drm/i915: Removing PCI IDs that are no longer listed as Kabylake.
drm/i915: Add more Kabylake PCI IDs.
drm/i915: Avoid early timeout during AUX transfers
drm/i915/hsw: Avoid early timeout during LCPLL disable/restore
drm/i915/lpt: Avoid early timeout during FDI PHY reset
drm/i915/bxt: Avoid early timeout during PLL enable
drm/i915: Refresh cached DP port register value on resume
drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation
drm/amd/powerplay: disable FFC.
drm/amd/powerplay: add some definition for FFC feature on polaris.
+160
-78
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
···
1106
1106
if (fences == 0 && handles == 0) {
1107
1107
if (adev->pm.dpm_enabled) {
1108
1108
amdgpu_dpm_enable_uvd(adev, false);
1109
+
/* just work around for uvd clock remain high even
1110
+
* when uvd dpm disabled on Polaris10 */
1111
+
if (adev->asic_type == CHIP_POLARIS10)
1112
+
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1109
1113
} else {
1110
1114
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1111
1115
}
+3
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+3
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
47
47
#include "dce/dce_10_0_d.h"
48
48
#include "dce/dce_10_0_sh_mask.h"
49
49
50
+
#include "smu/smu_7_1_3_d.h"
51
+
50
52
#define GFX8_NUM_GFX_RINGS 1
51
53
#define GFX8_NUM_COMPUTE_RINGS 8
52
54
···
695
693
amdgpu_program_register_sequence(adev,
696
694
polaris10_golden_common_all,
697
695
(const u32)ARRAY_SIZE(polaris10_golden_common_all));
696
+
WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
698
697
break;
699
698
case CHIP_CARRIZO:
700
699
amdgpu_program_register_sequence(adev,
+124
-55
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+124
-55
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
···
98
98
#define PCIE_BUS_CLK 10000
99
99
#define TCLK (PCIE_BUS_CLK / 10)
100
100
101
+
#define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
101
102
102
103
static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103
104
{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
···
1423
1422
1424
1423
table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1425
1424
1426
-
if (!data->sclk_dpm_key_disabled) {
1427
-
/* Get MinVoltage and Frequency from DPM0,
1428
-
* already converted to SMC_UL */
1429
-
sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1430
-
result = polaris10_get_dependency_volt_by_clk(hwmgr,
1431
-
table_info->vdd_dep_on_sclk,
1432
-
table->ACPILevel.SclkFrequency,
1433
-
&table->ACPILevel.MinVoltage, &mvdd);
1434
-
PP_ASSERT_WITH_CODE((0 == result),
1435
-
"Cannot find ACPI VDDC voltage value "
1436
-
"in Clock Dependency Table", );
1437
-
} else {
1438
-
sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1439
-
table->ACPILevel.MinVoltage =
1440
-
data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1441
-
}
1425
+
1426
+
/* Get MinVoltage and Frequency from DPM0,
1427
+
* already converted to SMC_UL */
1428
+
sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1429
+
result = polaris10_get_dependency_volt_by_clk(hwmgr,
1430
+
table_info->vdd_dep_on_sclk,
1431
+
sclk_frequency,
1432
+
&table->ACPILevel.MinVoltage, &mvdd);
1433
+
PP_ASSERT_WITH_CODE((0 == result),
1434
+
"Cannot find ACPI VDDC voltage value "
1435
+
"in Clock Dependency Table",
1436
+
);
1437
+
1442
1438
1443
1439
result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1444
1440
PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
···
1460
1462
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1461
1463
CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1462
1464
1463
-
if (!data->mclk_dpm_key_disabled) {
1464
-
/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1465
-
table->MemoryACPILevel.MclkFrequency =
1466
-
data->dpm_table.mclk_table.dpm_levels[0].value;
1467
-
result = polaris10_get_dependency_volt_by_clk(hwmgr,
1468
-
table_info->vdd_dep_on_mclk,
1469
-
table->MemoryACPILevel.MclkFrequency,
1470
-
&table->MemoryACPILevel.MinVoltage, &mvdd);
1471
-
PP_ASSERT_WITH_CODE((0 == result),
1472
-
"Cannot find ACPI VDDCI voltage value "
1473
-
"in Clock Dependency Table",
1474
-
);
1475
-
} else {
1476
-
table->MemoryACPILevel.MclkFrequency =
1477
-
data->vbios_boot_state.mclk_bootup_value;
1478
-
table->MemoryACPILevel.MinVoltage =
1479
-
data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1480
-
}
1465
+
1466
+
/* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1467
+
table->MemoryACPILevel.MclkFrequency =
1468
+
data->dpm_table.mclk_table.dpm_levels[0].value;
1469
+
result = polaris10_get_dependency_volt_by_clk(hwmgr,
1470
+
table_info->vdd_dep_on_mclk,
1471
+
table->MemoryACPILevel.MclkFrequency,
1472
+
&table->MemoryACPILevel.MinVoltage, &mvdd);
1473
+
PP_ASSERT_WITH_CODE((0 == result),
1474
+
"Cannot find ACPI VDDCI voltage value "
1475
+
"in Clock Dependency Table",
1476
+
);
1481
1477
1482
1478
us_mvdd = 0;
1483
1479
if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
···
1516
1524
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1517
1525
table_info->mm_dep_table;
1518
1526
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1527
+
uint32_t vddci;
1519
1528
1520
1529
table->VceLevelCount = (uint8_t)(mm_table->count);
1521
1530
table->VceBootLevel = 0;
···
1526
1533
table->VceLevel[count].MinVoltage = 0;
1527
1534
table->VceLevel[count].MinVoltage |=
1528
1535
(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1536
+
1537
+
if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1538
+
vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1539
+
mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1540
+
else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1541
+
vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1542
+
else
1543
+
vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1544
+
1545
+
1529
1546
table->VceLevel[count].MinVoltage |=
1530
-
((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1531
-
VOLTAGE_SCALE) << VDDCI_SHIFT;
1547
+
(vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1532
1548
table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1533
1549
1534
1550
/*retrieve divider value for VBIOS */
···
1566
1564
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1567
1565
table_info->mm_dep_table;
1568
1566
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1567
+
uint32_t vddci;
1569
1568
1570
1569
table->SamuBootLevel = 0;
1571
1570
table->SamuLevelCount = (uint8_t)(mm_table->count);
···
1577
1574
table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1578
1575
table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1579
1576
VOLTAGE_SCALE) << VDDC_SHIFT;
1580
-
table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1581
-
data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1577
+
1578
+
if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1579
+
vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1580
+
mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1581
+
else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1582
+
vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1583
+
else
1584
+
vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1585
+
1586
+
table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1582
1587
table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1583
1588
1584
1589
/* retrieve divider value for VBIOS */
···
1669
1658
struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1670
1659
table_info->mm_dep_table;
1671
1660
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1661
+
uint32_t vddci;
1672
1662
1673
1663
table->UvdLevelCount = (uint8_t)(mm_table->count);
1674
1664
table->UvdBootLevel = 0;
···
1680
1668
table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1681
1669
table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1682
1670
VOLTAGE_SCALE) << VDDC_SHIFT;
1683
-
table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1684
-
data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1671
+
1672
+
if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1673
+
vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1674
+
mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1675
+
else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1676
+
vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1677
+
else
1678
+
vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1679
+
1680
+
table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1685
1681
table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1686
1682
1687
1683
/* retrieve divider value for VBIOS */
···
1710
1690
CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1711
1691
CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1712
1692
CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1713
-
1714
1693
}
1694
+
1715
1695
return result;
1716
1696
}
1717
1697
···
1807
1787
1808
1788
ro = efuse * (max -min)/255 + min;
1809
1789
1810
-
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1790
+
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
1791
+
* there is a little difference in calculating
1792
+
* volt_with_cks with windows */
1811
1793
for (i = 0; i < sclk_table->count; i++) {
1812
1794
data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1813
1795
sclk_table->entries[i].cks_enable << i;
1814
-
1815
-
volt_without_cks = (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1816
-
(sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1817
-
1818
-
volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1819
-
(sclk_table->entries[i].clk/10000 * 649434 /1000 - 18005)/10);
1796
+
if (hwmgr->chip_id == CHIP_POLARIS10) {
1797
+
volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1798
+
(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1799
+
volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
1800
+
(252248000 - sclk_table->entries[i].clk/100 * 115764));
1801
+
} else {
1802
+
volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1803
+
(2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
1804
+
volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
1805
+
(3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
1806
+
}
1820
1807
1821
1808
if (volt_without_cks >= volt_with_cks)
1822
-
volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1823
-
sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1809
+
volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
1810
+
sclk_table->entries[i].cks_voffset) * 100 / 625);
1824
1811
1825
1812
data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1826
1813
}
1827
1814
1815
+
data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1828
1816
/* Populate CKS Lookup Table */
1829
1817
if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1830
1818
stretch_amount2 = 0;
···
2515
2487
PP_ASSERT_WITH_CODE((0 == tmp_result),
2516
2488
"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2517
2489
2490
+
smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2491
+
2518
2492
tmp_result = polaris10_enable_sclk_control(hwmgr);
2519
2493
PP_ASSERT_WITH_CODE((0 == tmp_result),
2520
2494
"Failed to enable SCLK control!", result = tmp_result);
···
2943
2913
return 0;
2944
2914
}
2945
2915
2916
+
int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2917
+
{
2918
+
struct phm_ppt_v1_information *table_info =
2919
+
(struct phm_ppt_v1_information *)(hwmgr->pptable);
2920
+
struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
2921
+
table_info->vdd_dep_on_mclk;
2922
+
struct phm_ppt_v1_voltage_lookup_table *lookup_table =
2923
+
table_info->vddc_lookup_table;
2924
+
uint32_t i;
2925
+
2926
+
if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) {
2927
+
if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2928
+
return 0;
2929
+
2930
+
for (i = 0; i < lookup_table->count; i++) {
2931
+
if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2932
+
dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2933
+
return 0;
2934
+
}
2935
+
}
2936
+
}
2937
+
return 0;
2938
+
}
2939
+
2940
+
2946
2941
int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2947
2942
{
2948
2943
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
···
3045
2990
3046
2991
polaris10_set_features_platform_caps(hwmgr);
3047
2992
2993
+
polaris10_patch_voltage_workaround(hwmgr);
3048
2994
polaris10_init_dpm_defaults(hwmgr);
3049
2995
3050
2996
/* Get leakage voltage based on leakage ID. */
···
4415
4359
return 0;
4416
4360
}
4417
4361
4362
+
static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4363
+
{
4364
+
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4365
+
4366
+
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4367
+
(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4368
+
return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
4369
+
}
4370
+
4418
4371
static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4419
4372
{
4420
4373
int tmp_result, result = 0;
···
4472
4407
"Failed to program memory timing parameters!",
4473
4408
result = tmp_result);
4474
4409
4410
+
tmp_result = polaris10_notify_smc_display(hwmgr);
4411
+
PP_ASSERT_WITH_CODE((0 == tmp_result),
4412
+
"Failed to notify smc display settings!",
4413
+
result = tmp_result);
4414
+
4475
4415
tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4476
4416
PP_ASSERT_WITH_CODE((0 == tmp_result),
4477
4417
"Failed to unfreeze SCLK MCLK DPM!",
···
4511
4441
PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4512
4442
}
4513
4443
4444
+
4514
4445
int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4515
4446
{
4516
4447
PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
···
4531
4460
4532
4461
if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4533
4462
polaris10_notify_smc_display_change(hwmgr, false);
4534
-
else
4535
-
polaris10_notify_smc_display_change(hwmgr, true);
4536
4463
4537
4464
return 0;
4538
4465
}
···
4571
4502
frame_time_in_us = 1000000 / refresh_rate;
4572
4503
4573
4504
pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4505
+
data->frame_time_x2 = frame_time_in_us * 2 / 100;
4506
+
4574
4507
display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4575
4508
4576
4509
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
···
4580
4509
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4581
4510
4582
4511
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4583
-
4584
-
polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4585
4512
4586
4513
return 0;
4587
4514
}
···
4692
4623
return 0;
4693
4624
}
4694
4625
4695
-
data->need_long_memory_training = true;
4626
+
data->need_long_memory_training = false;
4696
4627
4697
4628
/*
4698
4629
* PPMCME_FirmwareDescriptorEntry *pfd = NULL;
+1
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+1
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+2
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+2
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+2
drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
+2
drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h
···
392
392
#define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300)
393
393
#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301)
394
394
395
+
#define PPSMC_MSG_SetVBITimeout ((uint16_t) 0x306)
396
+
395
397
#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600)
396
398
#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601)
397
399
#define PPSMC_MSG_SetAddress ((uint16_t) 0x800)
+2
-1
drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
+2
-1
drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
+2
-2
drivers/gpu/drm/i915/i915_debugfs.c
+2
-2
drivers/gpu/drm/i915/i915_debugfs.c
···
2365
2365
task = get_pid_task(file->pid, PIDTYPE_PID);
2366
2366
if (!task) {
2367
2367
ret = -ESRCH;
2368
-
goto out_put;
2368
+
goto out_unlock;
2369
2369
}
2370
2370
seq_printf(m, "\nproc: %s\n", task->comm);
2371
2371
put_task_struct(task);
2372
2372
idr_for_each(&file_priv->context_idr, per_file_ctx,
2373
2373
(void *)(unsigned long)m);
2374
2374
}
2375
+
out_unlock:
2375
2376
mutex_unlock(&dev->filelist_mutex);
2376
2377
2377
-
out_put:
2378
2378
intel_runtime_pm_put(dev_priv);
2379
2379
mutex_unlock(&dev->struct_mutex);
2380
2380
+8
-8
drivers/gpu/drm/i915/intel_display.c
+8
-8
drivers/gpu/drm/i915/intel_display.c
···
8447
8447
tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8448
8448
I915_WRITE(SOUTH_CHICKEN2, tmp);
8449
8449
8450
-
if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8451
-
FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8450
+
if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
8451
+
FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8452
8452
DRM_ERROR("FDI mPHY reset assert timeout\n");
8453
8453
8454
8454
tmp = I915_READ(SOUTH_CHICKEN2);
8455
8455
tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8456
8456
I915_WRITE(SOUTH_CHICKEN2, tmp);
8457
8457
8458
-
if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8459
-
FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8458
+
if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
8459
+
FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8460
8460
DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8461
8461
}
8462
8462
···
9440
9440
val |= LCPLL_CD_SOURCE_FCLK;
9441
9441
I915_WRITE(LCPLL_CTL, val);
9442
9442
9443
-
if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9444
-
LCPLL_CD_SOURCE_FCLK_DONE, 1))
9443
+
if (wait_for_us(I915_READ(LCPLL_CTL) &
9444
+
LCPLL_CD_SOURCE_FCLK_DONE, 1))
9445
9445
DRM_ERROR("Switching to FCLK failed\n");
9446
9446
9447
9447
val = I915_READ(LCPLL_CTL);
···
9514
9514
val &= ~LCPLL_CD_SOURCE_FCLK;
9515
9515
I915_WRITE(LCPLL_CTL, val);
9516
9516
9517
-
if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9518
-
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9517
+
if (wait_for_us((I915_READ(LCPLL_CTL) &
9518
+
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9519
9519
DRM_ERROR("Switching back to LCPLL failed\n");
9520
9520
}
9521
9521
+6
-4
drivers/gpu/drm/i915/intel_dp.c
+6
-4
drivers/gpu/drm/i915/intel_dp.c
···
663
663
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
664
664
msecs_to_jiffies_timeout(10));
665
665
else
666
-
done = wait_for_atomic(C, 10) == 0;
666
+
done = wait_for(C, 10) == 0;
667
667
if (!done)
668
668
DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
669
669
has_aux_irq);
···
4899
4899
4900
4900
void intel_dp_encoder_reset(struct drm_encoder *encoder)
4901
4901
{
4902
-
struct intel_dp *intel_dp;
4902
+
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4903
+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4904
+
4905
+
if (!HAS_DDI(dev_priv))
4906
+
intel_dp->DP = I915_READ(intel_dp->output_reg);
4903
4907
4904
4908
if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4905
4909
return;
4906
-
4907
-
intel_dp = enc_to_intel_dp(encoder);
4908
4910
4909
4911
pps_lock(intel_dp);
4910
4912
+2
-2
drivers/gpu/drm/i915/intel_dpll_mgr.c
+2
-2
drivers/gpu/drm/i915/intel_dpll_mgr.c
···
1377
1377
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1378
1378
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1379
1379
1380
-
if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1381
-
PORT_PLL_LOCK), 200))
1380
+
if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1381
+
200))
1382
1382
DRM_ERROR("PLL %d not locked\n", port);
1383
1383
1384
1384
/*
+4
-6
include/drm/i915_pciids.h
+4
-6
include/drm/i915_pciids.h
···
309
309
INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
310
310
INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
311
311
INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
312
+
INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
312
313
INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
313
314
INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
314
315
···
323
322
INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
324
323
325
324
#define INTEL_KBL_GT3_IDS(info) \
325
+
INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
326
326
INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
327
-
INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
328
-
INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
327
+
INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
329
328
330
329
#define INTEL_KBL_GT4_IDS(info) \
331
-
INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \
332
-
INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
333
-
INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
334
-
INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */
330
+
INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
335
331
336
332
#define INTEL_KBL_IDS(info) \
337
333
INTEL_KBL_GT1_IDS(info), \