tjh.dev / kernel
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crypto: qat - count QAT GEN4 errors

Add logic to count correctable, non fatal and fatal error for QAT GEN4
devices.
These counters are reported through sysfs attributes in the group
qat_ras.

Signed-off-by: Shashank Gupta <shashank.gupta@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Tero Kristo <tero.kristo@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Shashank Gupta and committed by
Herbert Xu 99b1c982 532d7f6b

+166 -16
+166 -16
drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c
··· 3 3 #include "adf_common_drv.h" 4 4 #include "adf_gen4_hw_data.h" 5 5 #include "adf_gen4_ras.h" 6 + #include "adf_sysfs_ras_counters.h" 7 + 8 + #define BITS_PER_REG(_n_) (sizeof(_n_) * BITS_PER_BYTE) 6 9 7 10 static void enable_errsou_reporting(void __iomem *csr) 8 11 { ··· 358 355 "Correctable error detected in AE: 0x%x\n", 359 356 aecorrerr); 360 357 358 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR); 359 + 361 360 /* Clear interrupt from ERRSOU0 */ 362 361 ADF_CSR_WR(csr, ADF_GEN4_HIAECORERRLOG_CPP0, aecorrerr); 363 362 } ··· 378 373 dev_err(&GET_DEV(accel_dev), 379 374 "Uncorrectable error detected in AE: 0x%x\n", 380 375 aeuncorerr); 376 + 377 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 381 378 382 379 ADF_CSR_WR(csr, ADF_GEN4_HIAEUNCERRLOG_CPP0, aeuncorerr); 383 380 ··· 402 395 "HI CPP agent command parity error: 0x%x\n", 403 396 cmdparerr); 404 397 398 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 399 + 405 400 ADF_CSR_WR(csr, ADF_GEN4_HICPPAGENTCMDPARERRLOG, cmdparerr); 406 401 407 402 return true; ··· 422 413 rimem_parerr_sts &= ADF_GEN4_RIMEM_PARERR_STS_UNCERR_BITMASK | 423 414 ADF_GEN4_RIMEM_PARERR_STS_FATAL_BITMASK; 424 415 425 - if (rimem_parerr_sts & ADF_GEN4_RIMEM_PARERR_STS_UNCERR_BITMASK) 416 + if (rimem_parerr_sts & ADF_GEN4_RIMEM_PARERR_STS_UNCERR_BITMASK) { 426 417 dev_err(&GET_DEV(accel_dev), 427 418 "RI Memory Parity uncorrectable error: 0x%x\n", 428 419 rimem_parerr_sts); 420 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 421 + } 429 422 430 423 if (rimem_parerr_sts & ADF_GEN4_RIMEM_PARERR_STS_FATAL_BITMASK) { 431 424 dev_err(&GET_DEV(accel_dev), 432 425 "RI Memory Parity fatal error: 0x%x\n", 433 426 rimem_parerr_sts); 427 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 434 428 reset_required = true; 435 429 } 436 430 ··· 457 445 dev_err(&GET_DEV(accel_dev), 458 446 "TI Memory Parity Error: 0x%x\n", ti_ci_par_sts); 459 447 ADF_CSR_WR(csr, ADF_GEN4_TI_CI_PAR_STS, ti_ci_par_sts); 448 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 460 449 } 461 450 462 451 return false; ··· 480 467 481 468 ADF_CSR_WR(csr, ADF_GEN4_TI_PULL0FUB_PAR_STS, 482 469 ti_pullfub_par_sts); 470 + 471 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 483 472 } 484 473 485 474 return false; ··· 501 486 if (ti_pushfub_par_sts) { 502 487 dev_err(&GET_DEV(accel_dev), 503 488 "TI Push Parity Error: 0x%x\n", ti_pushfub_par_sts); 489 + 490 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 504 491 505 492 ADF_CSR_WR(csr, ADF_GEN4_TI_PUSHFUB_PAR_STS, 506 493 ti_pushfub_par_sts); ··· 526 509 dev_err(&GET_DEV(accel_dev), 527 510 "TI CD Parity Error: 0x%x\n", ti_cd_par_sts); 528 511 512 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 513 + 529 514 ADF_CSR_WR(csr, ADF_GEN4_TI_CD_PAR_STS, ti_cd_par_sts); 530 515 } 531 516 ··· 549 530 dev_err(&GET_DEV(accel_dev), 550 531 "TI TRNSB Parity Error: 0x%x\n", ti_trnsb_par_sts); 551 532 533 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 534 + 552 535 ADF_CSR_WR(csr, ADF_GEN4_TI_TRNSB_PAR_STS, ti_trnsb_par_sts); 553 536 } 554 537 ··· 571 550 dev_err(&GET_DEV(accel_dev), 572 551 "Command Parity error detected on IOSFP: 0x%x\n", 573 552 rimiscsts); 553 + 554 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 574 555 575 556 ADF_CSR_WR(csr, ADF_GEN4_RIMISCSTS, rimiscsts); 576 557 ··· 609 586 "Uncorrectable error on ssm shared memory: 0x%x\n", 610 587 reg); 611 588 589 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 590 + 612 591 ADF_CSR_WR(csr, ADF_GEN4_UERRSSMSH, reg); 613 592 614 593 return false; ··· 630 605 dev_warn(&GET_DEV(accel_dev), 631 606 "Correctable error on ssm shared memory: 0x%x\n", 632 607 reg); 608 + 609 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR); 633 610 634 611 ADF_CSR_WR(csr, ADF_GEN4_CERRSSMSH, reg); 635 612 ··· 653 626 "Uncorrectable error CPP transaction on memory target: 0x%x\n", 654 627 reg); 655 628 629 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 630 + 656 631 ADF_CSR_WR(csr, ADF_GEN4_PPERR, reg); 657 632 658 633 return false; ··· 671 642 672 643 dev_err(&GET_DEV(accel_dev), 673 644 "Slice %s hang error encountered\n", slice_name); 645 + 646 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 674 647 } 675 648 676 649 static bool adf_handle_slice_hang_error(struct adf_accel_dev *accel_dev, ··· 713 682 dev_err(&GET_DEV(accel_dev), 714 683 "SPP pull command fatal error ATH_CPH: 0x%x\n", reg); 715 684 685 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 686 + 716 687 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_ATH_CPH, reg); 717 688 718 689 reset_required = true; ··· 725 692 if (reg) { 726 693 dev_err(&GET_DEV(accel_dev), 727 694 "SPP pull command fatal error CPR_XLT: 0x%x\n", reg); 695 + 696 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 728 697 729 698 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_CPR_XLT, reg); 730 699 ··· 739 704 dev_err(&GET_DEV(accel_dev), 740 705 "SPP pull command fatal error DCPR_UCS: 0x%x\n", reg); 741 706 707 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 708 + 742 709 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_DCPR_UCS, reg); 743 710 744 711 reset_required = true; ··· 751 714 if (reg) { 752 715 dev_err(&GET_DEV(accel_dev), 753 716 "SPP pull command fatal error PKE: 0x%x\n", reg); 717 + 718 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 754 719 755 720 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_PKE, reg); 756 721 ··· 765 726 if (reg) { 766 727 dev_err(&GET_DEV(accel_dev), 767 728 "SPP pull command fatal error WAT_WCP: 0x%x\n", reg); 729 + 730 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 768 731 769 732 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLCMDPARERR_WAT_WCP, reg); 770 733 ··· 789 748 dev_err(&GET_DEV(accel_dev), 790 749 "SPP pull data err ATH_CPH: 0x%x\n", reg); 791 750 751 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 752 + 792 753 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_ATH_CPH, reg); 793 754 } 794 755 ··· 799 756 if (reg) { 800 757 dev_err(&GET_DEV(accel_dev), 801 758 "SPP pull data err CPR_XLT: 0x%x\n", reg); 759 + 760 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 802 761 803 762 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_CPR_XLT, reg); 804 763 } ··· 811 766 dev_err(&GET_DEV(accel_dev), 812 767 "SPP pull data err DCPR_UCS: 0x%x\n", reg); 813 768 769 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 770 + 814 771 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_DCPR_UCS, reg); 815 772 } 816 773 ··· 821 774 if (reg) { 822 775 dev_err(&GET_DEV(accel_dev), 823 776 "SPP pull data err PKE: 0x%x\n", reg); 777 + 778 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 824 779 825 780 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_PKE, reg); 826 781 } ··· 833 784 if (reg) { 834 785 dev_err(&GET_DEV(accel_dev), 835 786 "SPP pull data err WAT_WCP: 0x%x\n", reg); 787 + 788 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 836 789 837 790 ADF_CSR_WR(csr, ADF_GEN4_SPPPULLDATAPARERR_WAT_WCP, reg); 838 791 } ··· 856 805 dev_err(&GET_DEV(accel_dev), 857 806 "SPP push command fatal error ATH_CPH: 0x%x\n", reg); 858 807 808 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 809 + 859 810 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_ATH_CPH, reg); 860 811 861 812 reset_required = true; ··· 869 816 dev_err(&GET_DEV(accel_dev), 870 817 "SPP push command fatal error CPR_XLT: 0x%x\n", reg); 871 818 819 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 820 + 872 821 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_CPR_XLT, reg); 873 822 874 823 reset_required = true; ··· 881 826 if (reg) { 882 827 dev_err(&GET_DEV(accel_dev), 883 828 "SPP push command fatal error DCPR_UCS: 0x%x\n", reg); 829 + 830 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 884 831 885 832 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_DCPR_UCS, reg); 886 833 ··· 896 839 "SPP push command fatal error PKE: 0x%x\n", 897 840 reg); 898 841 842 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 843 + 899 844 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_PKE, reg); 900 845 901 846 reset_required = true; ··· 909 850 if (reg) { 910 851 dev_err(&GET_DEV(accel_dev), 911 852 "SPP push command fatal error WAT_WCP: 0x%x\n", reg); 853 + 854 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 912 855 913 856 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHCMDPARERR_WAT_WCP, reg); 914 857 ··· 933 872 dev_err(&GET_DEV(accel_dev), 934 873 "SPP push data err ATH_CPH: 0x%x\n", reg); 935 874 875 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 876 + 936 877 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_ATH_CPH, reg); 937 878 } 938 879 ··· 943 880 if (reg) { 944 881 dev_err(&GET_DEV(accel_dev), 945 882 "SPP push data err CPR_XLT: 0x%x\n", reg); 883 + 884 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 946 885 947 886 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_CPR_XLT, reg); 948 887 } ··· 955 890 dev_err(&GET_DEV(accel_dev), 956 891 "SPP push data err DCPR_UCS: 0x%x\n", reg); 957 892 893 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 894 + 958 895 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_DCPR_UCS, reg); 959 896 } 960 897 ··· 965 898 if (reg) { 966 899 dev_err(&GET_DEV(accel_dev), 967 900 "SPP push data err PKE: 0x%x\n", reg); 901 + 902 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 968 903 969 904 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_PKE, reg); 970 905 } ··· 977 908 if (reg) { 978 909 dev_err(&GET_DEV(accel_dev), 979 910 "SPP push data err WAT_WCP: 0x%x\n", reg); 911 + 912 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 980 913 981 914 ADF_CSR_WR(csr, ADF_GEN4_SPPPUSHDATAPARERR_WAT_WCP, 982 915 reg); ··· 1007 936 static bool adf_handle_ssmcpppar_err(struct adf_accel_dev *accel_dev, 1008 937 void __iomem *csr, u32 iastatssm) 1009 938 { 939 + u32 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMCPPERR); 940 + u32 bits_num = BITS_PER_REG(reg); 1010 941 bool reset_required = false; 1011 - u32 reg; 942 + unsigned long errs_bits; 943 + u32 bit_iterator; 1012 944 1013 945 if (!(iastatssm & ADF_GEN4_IAINTSTATSSM_SSMCPPERR_BIT)) 1014 946 return false; ··· 1022 948 dev_err(&GET_DEV(accel_dev), 1023 949 "Fatal SSM CPP parity error: 0x%x\n", reg); 1024 950 951 + errs_bits = reg & ADF_GEN4_SSMCPPERR_FATAL_BITMASK; 952 + for_each_set_bit(bit_iterator, &errs_bits, bits_num) { 953 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 954 + } 1025 955 reset_required = true; 1026 956 } 1027 957 1028 - if (reg & ADF_GEN4_SSMCPPERR_UNCERR_BITMASK) 958 + if (reg & ADF_GEN4_SSMCPPERR_UNCERR_BITMASK) { 1029 959 dev_err(&GET_DEV(accel_dev), 1030 960 "non-Fatal SSM CPP parity error: 0x%x\n", reg); 961 + errs_bits = reg & ADF_GEN4_SSMCPPERR_UNCERR_BITMASK; 962 + 963 + for_each_set_bit(bit_iterator, &errs_bits, bits_num) { 964 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 965 + } 966 + } 1031 967 1032 968 ADF_CSR_WR(csr, ADF_GEN4_SSMCPPERR, reg); 1033 969 ··· 1055 971 1056 972 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_SRC); 1057 973 reg &= ADF_GEN4_SSMSOFTERRORPARITY_SRC_BIT; 1058 - if (reg) 974 + if (reg) { 975 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1059 976 ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_SRC, reg); 977 + } 1060 978 1061 979 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_ATH_CPH); 1062 980 reg &= err_mask->parerr_ath_cph_mask; 1063 - if (reg) 981 + if (reg) { 982 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1064 983 ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_ATH_CPH, reg); 984 + } 1065 985 1066 986 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_CPR_XLT); 1067 987 reg &= err_mask->parerr_cpr_xlt_mask; 1068 - if (reg) 988 + if (reg) { 989 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1069 990 ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_CPR_XLT, reg); 991 + } 1070 992 1071 993 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_DCPR_UCS); 1072 994 reg &= err_mask->parerr_dcpr_ucs_mask; 1073 - if (reg) 995 + if (reg) { 996 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1074 997 ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_DCPR_UCS, reg); 998 + } 1075 999 1076 1000 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_PKE); 1077 1001 reg &= err_mask->parerr_pke_mask; 1078 - if (reg) 1002 + if (reg) { 1003 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1079 1004 ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_PKE, reg); 1005 + } 1080 1006 1081 1007 if (err_mask->parerr_wat_wcp_mask) { 1082 1008 reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_WAT_WCP); 1083 1009 reg &= err_mask->parerr_wat_wcp_mask; 1084 - if (reg) 1010 + if (reg) { 1011 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1085 1012 ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_WAT_WCP, 1086 1013 reg); 1014 + } 1087 1015 } 1088 1016 1089 1017 dev_err(&GET_DEV(accel_dev), "Slice ssm soft parity error reported"); ··· 1106 1010 static bool adf_handle_ser_err_ssmsh(struct adf_accel_dev *accel_dev, 1107 1011 void __iomem *csr, u32 iastatssm) 1108 1012 { 1013 + u32 reg = ADF_CSR_RD(csr, ADF_GEN4_SER_ERR_SSMSH); 1014 + u32 bits_num = BITS_PER_REG(reg); 1109 1015 bool reset_required = false; 1110 - u32 reg; 1016 + unsigned long errs_bits; 1017 + u32 bit_iterator; 1111 1018 1112 1019 if (!(iastatssm & (ADF_GEN4_IAINTSTATSSM_SER_ERR_SSMSH_CERR_BIT | 1113 1020 ADF_GEN4_IAINTSTATSSM_SER_ERR_SSMSH_UNCERR_BIT))) ··· 1124 1025 dev_err(&GET_DEV(accel_dev), 1125 1026 "Fatal SER_SSMSH_ERR: 0x%x\n", reg); 1126 1027 1028 + errs_bits = reg & ADF_GEN4_SER_ERR_SSMSH_FATAL_BITMASK; 1029 + for_each_set_bit(bit_iterator, &errs_bits, bits_num) { 1030 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 1031 + } 1032 + 1127 1033 reset_required = true; 1128 1034 } 1129 1035 1130 - if (reg & ADF_GEN4_SER_ERR_SSMSH_UNCERR_BITMASK) 1036 + if (reg & ADF_GEN4_SER_ERR_SSMSH_UNCERR_BITMASK) { 1131 1037 dev_err(&GET_DEV(accel_dev), 1132 1038 "non-fatal SER_SSMSH_ERR: 0x%x\n", reg); 1133 1039 1134 - if (reg & ADF_GEN4_SER_ERR_SSMSH_CERR_BITMASK) 1040 + errs_bits = reg & ADF_GEN4_SER_ERR_SSMSH_UNCERR_BITMASK; 1041 + for_each_set_bit(bit_iterator, &errs_bits, bits_num) { 1042 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1043 + } 1044 + } 1045 + 1046 + if (reg & ADF_GEN4_SER_ERR_SSMSH_CERR_BITMASK) { 1135 1047 dev_warn(&GET_DEV(accel_dev), 1136 1048 "Correctable SER_SSMSH_ERR: 0x%x\n", reg); 1049 + 1050 + errs_bits = reg & ADF_GEN4_SER_ERR_SSMSH_CERR_BITMASK; 1051 + for_each_set_bit(bit_iterator, &errs_bits, bits_num) { 1052 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR); 1053 + } 1054 + } 1137 1055 1138 1056 ADF_CSR_WR(csr, ADF_GEN4_SER_ERR_SSMSH, reg); 1139 1057 ··· 1193 1077 dev_err(&GET_DEV(accel_dev), 1194 1078 "Uncorrectable error exception in SSM CMP: 0x%x", reg); 1195 1079 1080 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1081 + 1196 1082 ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMCPR, reg); 1197 1083 1198 1084 return false; ··· 1210 1092 if (!reg) 1211 1093 return false; 1212 1094 1213 - if (reg & ADF_GEN4_EXPRPSSMXLT_UNCERR_BITMASK) 1095 + if (reg & ADF_GEN4_EXPRPSSMXLT_UNCERR_BITMASK) { 1214 1096 dev_err(&GET_DEV(accel_dev), 1215 1097 "Uncorrectable error exception in SSM XLT: 0x%x", reg); 1216 1098 1217 - if (reg & ADF_GEN4_EXPRPSSMXLT_CERR_BIT) 1099 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1100 + } 1101 + 1102 + if (reg & ADF_GEN4_EXPRPSSMXLT_CERR_BIT) { 1218 1103 dev_warn(&GET_DEV(accel_dev), 1219 1104 "Correctable error exception in SSM XLT: 0x%x", reg); 1105 + 1106 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR); 1107 + } 1220 1108 1221 1109 ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMXLT, reg); 1222 1110 ··· 1242 1118 if (!reg) 1243 1119 continue; 1244 1120 1245 - if (reg & ADF_GEN4_EXPRPSSMDCPR_UNCERR_BITMASK) 1121 + if (reg & ADF_GEN4_EXPRPSSMDCPR_UNCERR_BITMASK) { 1246 1122 dev_err(&GET_DEV(accel_dev), 1247 1123 "Uncorrectable error exception in SSM DCMP: 0x%x", reg); 1248 1124 1249 - if (reg & ADF_GEN4_EXPRPSSMDCPR_CERR_BITMASK) 1125 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1126 + } 1127 + 1128 + if (reg & ADF_GEN4_EXPRPSSMDCPR_CERR_BITMASK) { 1250 1129 dev_warn(&GET_DEV(accel_dev), 1251 1130 "Correctable error exception in SSM DCMP: 0x%x", reg); 1131 + 1132 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR); 1133 + } 1252 1134 1253 1135 ADF_CSR_WR(csr, ADF_GEN4_EXPRPSSMDCPR(i), reg); 1254 1136 } ··· 1291 1161 if (reg & ADF_GEN4_CPP_CFC_ERR_STATUS_DATAPAR_BIT) { 1292 1162 dev_err(&GET_DEV(accel_dev), 1293 1163 "CPP_CFC_ERR: data parity: 0x%x", reg); 1164 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1294 1165 } 1295 1166 1296 1167 if (reg & ADF_GEN4_CPP_CFC_ERR_STATUS_CMDPAR_BIT) { 1297 1168 dev_err(&GET_DEV(accel_dev), 1298 1169 "CPP_CFC_ERR: command parity: 0x%x", reg); 1170 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 1299 1171 1300 1172 reset_required = true; 1301 1173 } ··· 1305 1173 if (reg & ADF_GEN4_CPP_CFC_ERR_STATUS_MERR_BIT) { 1306 1174 dev_err(&GET_DEV(accel_dev), 1307 1175 "CPP_CFC_ERR: multiple errors: 0x%x", reg); 1176 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 1308 1177 1309 1178 reset_required = true; 1310 1179 } ··· 1337 1204 dev_err(&GET_DEV(accel_dev), 1338 1205 "Fatal error in Transmit Interface: 0x%x\n", timiscsts); 1339 1206 1207 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 1208 + 1340 1209 return true; 1341 1210 } 1342 1211 ··· 1355 1220 1356 1221 dev_err(&GET_DEV(accel_dev), 1357 1222 "RI CPP Uncorrectable Error: 0x%x\n", ricppintsts); 1223 + 1224 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1358 1225 1359 1226 ADF_CSR_WR(csr, ADF_GEN4_RICPPINTSTS, ricppintsts); 1360 1227 ··· 1377 1240 dev_err(&GET_DEV(accel_dev), 1378 1241 "TI CPP Uncorrectable Error: 0x%x\n", ticppintsts); 1379 1242 1243 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1244 + 1380 1245 ADF_CSR_WR(csr, ADF_GEN4_TICPPINTSTS, ticppintsts); 1381 1246 1382 1247 return false; ··· 1397 1258 1398 1259 dev_warn(&GET_DEV(accel_dev), 1399 1260 "ARAM correctable error : 0x%x\n", aram_cerr); 1261 + 1262 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_CORR); 1400 1263 1401 1264 aram_cerr |= ADF_GEN4_REG_ARAMCERR_EN_BITMASK; 1402 1265 ··· 1427 1286 dev_err(&GET_DEV(accel_dev), 1428 1287 "ARAM multiple uncorrectable errors: 0x%x\n", aramuerr); 1429 1288 1289 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 1290 + 1430 1291 reset_required = true; 1431 1292 } else { 1432 1293 dev_err(&GET_DEV(accel_dev), 1433 1294 "ARAM uncorrectable error: 0x%x\n", aramuerr); 1295 + 1296 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1434 1297 } 1435 1298 1436 1299 aramuerr |= ADF_GEN4_REG_ARAMUERR_EN_BITMASK; ··· 1464 1319 "Misc memory target multiple uncorrectable errors: 0x%x\n", 1465 1320 cppmemtgterr); 1466 1321 1322 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL); 1323 + 1467 1324 reset_required = true; 1468 1325 } else { 1469 1326 dev_err(&GET_DEV(accel_dev), 1470 1327 "Misc memory target uncorrectable error: 0x%x\n", cppmemtgterr); 1328 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1471 1329 } 1472 1330 1473 1331 cppmemtgterr |= ADF_GEN4_REG_CPPMEMTGTERR_EN_BITMASK; ··· 1498 1350 dev_err(&GET_DEV(accel_dev), 1499 1351 "Ring Pair (%u) ATU detected fault: 0x%x\n", i, 1500 1352 atufaultstatus); 1353 + 1354 + ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR); 1501 1355 1502 1356 ADF_CSR_WR(csr, ADF_GEN4_ATUFAULTSTATUS(i), atufaultstatus); 1503 1357 }