Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mailbox-v6.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:
- tegra: support for Tegra264
- broadcom: convert bcm2835 bindings from txt to yaml bcm2835
- qcom: support for IPQ5018
- ti: always zero TX data fields
* tag 'mailbox-v6.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
mailbox: ti-msgmgr: Fill non-message tx data fields with 0x0
mailbox: tegra: add support for Tegra264
dt-bindings: mailbox: tegra: Document Tegra264 HSP
dt-bindings: mailbox: convert bcm2835-mbox bindings to YAML
dt-bindings: mailbox: qcom: Add IPQ5018 APCS compatible
+65
-31
-26
Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt
-26
Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt
···
1
-
Broadcom BCM2835 VideoCore mailbox IPC
2
-
3
-
Required properties:
4
-
5
-
- compatible: Should be "brcm,bcm2835-mbox"
6
-
- reg: Specifies base physical address and size of the registers
7
-
- interrupts: The interrupt number
8
-
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
9
-
- #mbox-cells: Specifies the number of cells needed to encode a mailbox
10
-
channel. The value shall be 0, since there is only one
11
-
mailbox channel implemented by the device.
12
-
13
-
Example:
14
-
15
-
mailbox: mailbox@7e00b880 {
16
-
compatible = "brcm,bcm2835-mbox";
17
-
reg = <0x7e00b880 0x40>;
18
-
interrupts = <0 1>;
19
-
#mbox-cells = <0>;
20
-
};
21
-
22
-
firmware: firmware {
23
-
compatible = "raspberrypi,firmware";
24
-
mboxes = <&mailbox>;
25
-
#power-domain-cells = <1>;
26
-
};
+40
Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.yaml
+40
Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mailbox/brcm,bcm2835-mbox.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom BCM2835 VideoCore mailbox IPC
8
+
9
+
maintainers:
10
+
- Stefan Wahren <stefan.wahren@i2se.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: brcm,bcm2835-mbox
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
interrupts:
20
+
maxItems: 1
21
+
22
+
"#mbox-cells":
23
+
const: 0
24
+
25
+
required:
26
+
- compatible
27
+
- reg
28
+
- interrupts
29
+
- "#mbox-cells"
30
+
31
+
additionalProperties: false
32
+
33
+
examples:
34
+
- |
35
+
mailbox@7e00b880 {
36
+
compatible = "brcm,bcm2835-mbox";
37
+
reg = <0x7e00b880 0x40>;
38
+
interrupts = <0 1>;
39
+
#mbox-cells = <0>;
40
+
};
+1
Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+1
Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+1
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+1
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+14
-2
drivers/mailbox/tegra-hsp.c
+14
-2
drivers/mailbox/tegra-hsp.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <linux/delay.h>
···
97
97
const struct tegra_hsp_db_map *map;
98
98
bool has_per_mb_ie;
99
99
bool has_128_bit_mb;
100
+
unsigned int reg_stride;
100
101
};
101
102
102
103
struct tegra_hsp {
···
280
279
return ERR_PTR(-ENOMEM);
281
280
282
281
offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
283
-
offset += index * 0x100;
282
+
offset += index * hsp->soc->reg_stride;
284
283
285
284
db->channel.regs = hsp->regs + offset;
286
285
db->channel.hsp = hsp;
···
917
916
.map = tegra186_hsp_db_map,
918
917
.has_per_mb_ie = false,
919
918
.has_128_bit_mb = false,
919
+
.reg_stride = 0x100,
920
920
};
921
921
922
922
static const struct tegra_hsp_soc tegra194_hsp_soc = {
923
923
.map = tegra186_hsp_db_map,
924
924
.has_per_mb_ie = true,
925
925
.has_128_bit_mb = false,
926
+
.reg_stride = 0x100,
926
927
};
927
928
928
929
static const struct tegra_hsp_soc tegra234_hsp_soc = {
929
930
.map = tegra186_hsp_db_map,
930
931
.has_per_mb_ie = false,
931
932
.has_128_bit_mb = true,
933
+
.reg_stride = 0x100,
934
+
};
935
+
936
+
static const struct tegra_hsp_soc tegra264_hsp_soc = {
937
+
.map = tegra186_hsp_db_map,
938
+
.has_per_mb_ie = false,
939
+
.has_128_bit_mb = true,
940
+
.reg_stride = 0x1000,
932
941
};
933
942
934
943
static const struct of_device_id tegra_hsp_match[] = {
935
944
{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
936
945
{ .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
937
946
{ .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
947
+
{ .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc },
938
948
{ }
939
949
};
940
950
+9
-3
drivers/mailbox/ti-msgmgr.c
+9
-3
drivers/mailbox/ti-msgmgr.c
···
430
430
/* Ensure all unused data is 0 */
431
431
data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes));
432
432
writel(data_trail, data_reg);
433
-
data_reg++;
433
+
data_reg += sizeof(u32);
434
434
}
435
+
435
436
/*
436
437
* 'data_reg' indicates next register to write. If we did not already
437
438
* write on tx complete reg(last reg), we must do so for transmit
439
+
* In addition, we also need to make sure all intermediate data
440
+
* registers(if any required), are reset to 0 for TISCI backward
441
+
* compatibility to be maintained.
438
442
*/
439
-
if (data_reg <= qinst->queue_buff_end)
440
-
writel(0, qinst->queue_buff_end);
443
+
while (data_reg <= qinst->queue_buff_end) {
444
+
writel(0, data_reg);
445
+
data_reg += sizeof(u32);
446
+
}
441
447
442
448
/* If we are in polled mode, wait for a response before proceeding */
443
449
if (ti_msgmgr_chan_has_polled_queue_rx(message->chan_rx))