Merge tag 'i2c-for-7.0-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+2

Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml

··· 28 28 - enum: 29 29 - qcom,kaanapali-cci 30 30 - qcom,qcm2290-cci 31 + - qcom,qcs8300-cci 31 32 - qcom,sa8775p-cci 32 33 - qcom,sc7280-cci 33 34 - qcom,sc8280xp-cci ··· 134 133 enum: 135 134 - qcom,kaanapali-cci 136 135 - qcom,qcm2290-cci 136 + - qcom,qcs8300-cci 137 137 - qcom,sm8750-cci 138 138 then: 139 139 properties:

+100

Documentation/devicetree/bindings/i2c/silabs,cp2112.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/silabs,cp2112.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: CP2112 HID USB to SMBus/I2C Bridge 8 + 9 + maintainers: 10 + - Danny Kaehn <danny.kaehn@plexus.com> 11 + 12 + description: 13 + The CP2112 is a USB HID device which includes an integrated I2C controller 14 + and 8 GPIO pins. Its GPIO pins can each be configured as inputs, open-drain 15 + outputs, or push-pull outputs. 16 + 17 + properties: 18 + compatible: 19 + const: usb10c4,ea90 20 + 21 + reg: 22 + maxItems: 1 23 + description: The USB port number 24 + 25 + interrupt-controller: true 26 + "#interrupt-cells": 27 + const: 2 28 + 29 + gpio-controller: true 30 + "#gpio-cells": 31 + const: 2 32 + 33 + gpio-line-names: 34 + minItems: 1 35 + maxItems: 8 36 + 37 + i2c: 38 + description: The SMBus/I2C controller node for the CP2112 39 + $ref: /schemas/i2c/i2c-controller.yaml# 40 + unevaluatedProperties: false 41 + 42 + properties: 43 + clock-frequency: 44 + minimum: 10000 45 + default: 100000 46 + maximum: 400000 47 + 48 + patternProperties: 49 + "-hog(-[0-9]+)?$": 50 + type: object 51 + 52 + required: 53 + - gpio-hog 54 + 55 + required: 56 + - compatible 57 + - reg 58 + 59 + additionalProperties: false 60 + 61 + examples: 62 + - | 63 + #include <dt-bindings/interrupt-controller/irq.h> 64 + #include <dt-bindings/gpio/gpio.h> 65 + 66 + usb { 67 + #address-cells = <1>; 68 + #size-cells = <0>; 69 + 70 + cp2112: device@1 { 71 + compatible = "usb10c4,ea90"; 72 + reg = <1>; 73 + 74 + gpio-controller; 75 + interrupt-controller; 76 + #interrupt-cells = <2>; 77 + #gpio-cells = <2>; 78 + gpio-line-names = "CP2112_SDA", "CP2112_SCL", "TEST2", 79 + "TEST3","TEST4", "TEST5", "TEST6"; 80 + 81 + fan-rst-hog { 82 + gpio-hog; 83 + gpios = <7 GPIO_ACTIVE_HIGH>; 84 + output-high; 85 + line-name = "FAN_RST"; 86 + }; 87 + 88 + i2c { 89 + #address-cells = <1>; 90 + #size-cells = <0>; 91 + sda-gpios = <&cp2112 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 92 + scl-gpios = <&cp2112 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 93 + 94 + temp@48 { 95 + compatible = "national,lm75"; 96 + reg = <0x48>; 97 + }; 98 + }; 99 + }; 100 + };

+9 -21

drivers/i2c/busses/i2c-amd8111.c

··· 17 17 #include <linux/io.h> 18 18 19 19 MODULE_LICENSE("GPL"); 20 - MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>"); 20 + MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 21 21 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver"); 22 22 23 23 struct amd_smbus { ··· 417 417 { 0, } 418 418 }; 419 419 420 - MODULE_DEVICE_TABLE (pci, amd8111_ids); 420 + MODULE_DEVICE_TABLE(pci, amd8111_ids); 421 421 422 422 static int amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id) 423 423 { ··· 427 427 if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO)) 428 428 return -ENODEV; 429 429 430 - smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL); 430 + smbus = devm_kzalloc(&dev->dev, sizeof(struct amd_smbus), GFP_KERNEL); 431 431 if (!smbus) 432 432 return -ENOMEM; 433 433 ··· 436 436 smbus->size = pci_resource_len(dev, 0); 437 437 438 438 error = acpi_check_resource_conflict(&dev->resource[0]); 439 - if (error) { 440 - error = -ENODEV; 441 - goto out_kfree; 442 - } 439 + if (error) 440 + return -ENODEV; 443 441 444 - if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) { 445 - error = -EBUSY; 446 - goto out_kfree; 447 - } 442 + if (!devm_request_region(&dev->dev, smbus->base, smbus->size, amd8111_driver.name)) 443 + return -EBUSY; 448 444 449 445 smbus->adapter.owner = THIS_MODULE; 450 446 snprintf(smbus->adapter.name, sizeof(smbus->adapter.name), 451 - "SMBus2 AMD8111 adapter at %04x", smbus->base); 447 + "SMBus2 AMD8111 adapter at %04x", smbus->base); 452 448 smbus->adapter.class = I2C_CLASS_HWMON; 453 449 smbus->adapter.algo = &smbus_algorithm; 454 450 smbus->adapter.algo_data = smbus; ··· 455 459 pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0); 456 460 error = i2c_add_adapter(&smbus->adapter); 457 461 if (error) 458 - goto out_release_region; 462 + return error; 459 463 460 464 pci_set_drvdata(dev, smbus); 461 465 return 0; 462 - 463 - out_release_region: 464 - release_region(smbus->base, smbus->size); 465 - out_kfree: 466 - kfree(smbus); 467 - return error; 468 466 } 469 467 470 468 static void amd8111_remove(struct pci_dev *dev) ··· 466 476 struct amd_smbus *smbus = pci_get_drvdata(dev); 467 477 468 478 i2c_del_adapter(&smbus->adapter); 469 - release_region(smbus->base, smbus->size); 470 - kfree(smbus); 471 479 } 472 480 473 481 static struct pci_driver amd8111_driver = {

+1 -12

drivers/i2c/busses/i2c-designware-amdisp.c

··· 18 18 static void amd_isp_dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *i2c_dev) 19 19 { 20 20 pm_runtime_disable(i2c_dev->dev); 21 - 22 - if (i2c_dev->shared_with_punit) 23 - pm_runtime_put_noidle(i2c_dev->dev); 24 21 } 25 22 26 23 static inline u32 amd_isp_dw_i2c_get_clk_rate(struct dw_i2c_dev *i2c_dev) ··· 76 79 77 80 device_enable_async_suspend(&pdev->dev); 78 81 79 - if (isp_i2c_dev->shared_with_punit) 80 - pm_runtime_get_noresume(&pdev->dev); 81 - 82 82 pm_runtime_enable(&pdev->dev); 83 83 pm_runtime_get_sync(&pdev->dev); 84 84 ··· 124 130 { 125 131 struct dw_i2c_dev *i_dev = dev_get_drvdata(dev); 126 132 127 - if (i_dev->shared_with_punit) 128 - return 0; 129 - 130 133 i2c_dw_disable(i_dev); 131 134 i2c_dw_prepare_clk(i_dev, false); 132 135 ··· 152 161 if (!i_dev) 153 162 return -ENODEV; 154 163 155 - if (!i_dev->shared_with_punit) 156 - i2c_dw_prepare_clk(i_dev, true); 157 - 164 + i2c_dw_prepare_clk(i_dev, true); 158 165 i2c_dw_init(i_dev); 159 166 160 167 return 0;

+20

drivers/i2c/busses/i2c-designware-common.c

··· 492 492 493 493 dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized"); 494 494 495 + /* Mobileye controllers do not hold the clock on empty FIFO */ 496 + if (device_is_compatible(device, "mobileye,eyeq6lplus-i2c")) 497 + dev->emptyfifo_hold_master = false; 498 + else 499 + dev->emptyfifo_hold_master = true; 500 + 495 501 i2c_dw_adjust_bus_speed(dev); 496 502 497 503 if (is_of_node(fwnode)) ··· 923 917 irq_flags = IRQF_NO_SUSPEND; 924 918 else 925 919 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 920 + 921 + /* 922 + * The first writing to TX FIFO buffer causes transmission start. 923 + * If IC_EMPTYFIFO_HOLD_MASTER_EN is not set, when TX FIFO gets 924 + * empty, I2C controller finishes the transaction. If writing to 925 + * FIFO is interrupted, FIFO can get empty and the transaction will 926 + * be finished prematurely. FIFO buffer is filled in IRQ handler, 927 + * but in PREEMPT_RT kernel IRQ handler by default is executed 928 + * in thread that can be preempted with another higher priority 929 + * thread or an interrupt. So, IRQF_NO_THREAD flag is required in 930 + * order to prevent any preemption when filling the FIFO. 931 + */ 932 + if (!dev->emptyfifo_hold_master) 933 + irq_flags |= IRQF_NO_THREAD; 926 934 927 935 ret = i2c_dw_acquire_lock(dev); 928 936 if (ret)

+3

drivers/i2c/busses/i2c-designware-core.h

··· 260 260 * @clk_freq_optimized: if this value is true, it means the hardware reduces 261 261 * its internal clock frequency by reducing the internal latency required 262 262 * to generate the high period and low period of SCL line. 263 + * @emptyfifo_hold_master: true if the controller acting as master holds 264 + * the clock when the Tx FIFO is empty instead of emitting a stop. 263 265 * 264 266 * HCNT and LCNT parameters can be used if the platform knows more accurate 265 267 * values than the one computed based only on the input clock frequency. ··· 320 318 struct i2c_bus_recovery_info rinfo; 321 319 u32 bus_capacitance_pF; 322 320 bool clk_freq_optimized; 321 + bool emptyfifo_hold_master; 323 322 }; 324 323 325 324 #define ACCESS_INTR_MASK BIT(0)

+117 -45

drivers/i2c/busses/i2c-designware-master.c

··· 296 296 u8 *tx_buf; 297 297 unsigned int val; 298 298 299 - ACQUIRE(pm_runtime_active_auto_try, pm)(dev->dev); 300 - if (ACQUIRE_ERR(pm_runtime_active_auto_try, &pm)) 299 + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev->dev, pm); 300 + if (PM_RUNTIME_ACQUIRE_ERR(&pm)) 301 301 return -ENXIO; 302 302 303 303 /* ··· 377 377 struct i2c_msg *msgs = dev->msgs; 378 378 u32 intr_mask; 379 379 int tx_limit, rx_limit; 380 - u32 addr = msgs[dev->msg_write_idx].addr; 381 380 u32 buf_len = dev->tx_buf_len; 382 381 u8 *buf = dev->tx_buf; 383 382 bool need_restart = false; ··· 386 387 387 388 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { 388 389 u32 flags = msgs[dev->msg_write_idx].flags; 389 - 390 - /* 391 - * If target address has changed, we need to 392 - * reprogram the target address in the I2C 393 - * adapter when we are done with this transfer. 394 - */ 395 - if (msgs[dev->msg_write_idx].addr != addr) { 396 - dev_err(dev->dev, 397 - "%s: invalid target address\n", __func__); 398 - dev->msg_err = -EINVAL; 399 - break; 400 - } 401 390 402 391 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { 403 392 /* new i2c_msg */ ··· 652 665 if (stat & DW_IC_INTR_TX_EMPTY) 653 666 i2c_dw_xfer_msg(dev); 654 667 668 + /* Abort if we detect a STOP in the middle of a read or a write */ 669 + if ((stat & DW_IC_INTR_STOP_DET) && 670 + (dev->status & (STATUS_READ_IN_PROGRESS | STATUS_WRITE_IN_PROGRESS))) { 671 + dev_err(dev->dev, "spurious STOP detected\n"); 672 + dev->rx_outstanding = 0; 673 + dev->msg_err = -EIO; 674 + } 675 + 655 676 /* 656 677 * No need to modify or disable the interrupt mask here. 657 678 * i2c_dw_xfer_msg() will take care of it according to ··· 741 746 } 742 747 743 748 /* 744 - * Prepare controller for a transaction and call i2c_dw_xfer_msg. 749 + * Prepare controller for a transaction, start the transfer of the @msgs 750 + * and wait for completion, either a STOP or a error. 751 + * Return: 0 or a negative error code. 745 752 */ 746 753 static int 747 - i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num) 754 + __i2c_dw_xfer_one_part(struct dw_i2c_dev *dev, struct i2c_msg *msgs, size_t num) 748 755 { 749 756 int ret; 750 - 751 - dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 752 - 753 - pm_runtime_get_sync(dev->dev); 754 757 755 758 reinit_completion(&dev->cmd_complete); 756 759 dev->msgs = msgs; ··· 761 768 dev->abort_source = 0; 762 769 dev->rx_outstanding = 0; 763 770 764 - ret = i2c_dw_acquire_lock(dev); 765 - if (ret) 766 - goto done_nolock; 767 - 768 771 ret = i2c_dw_wait_bus_not_busy(dev); 769 772 if (ret < 0) 770 - goto done; 773 + return ret; 771 774 772 775 /* Start the transfers */ 773 776 i2c_dw_xfer_init(dev); ··· 775 786 /* i2c_dw_init() implicitly disables the adapter */ 776 787 i2c_recover_bus(&dev->adapter); 777 788 i2c_dw_init(dev); 778 - goto done; 789 + return ret; 779 790 } 780 791 781 792 /* ··· 798 809 */ 799 810 __i2c_dw_disable_nowait(dev); 800 811 801 - if (dev->msg_err) { 802 - ret = dev->msg_err; 803 - goto done; 804 - } 812 + if (dev->msg_err) 813 + return dev->msg_err; 805 814 806 815 /* No error */ 807 - if (likely(!dev->cmd_err && !dev->status)) { 808 - ret = num; 809 - goto done; 810 - } 816 + if (likely(!dev->cmd_err && !dev->status)) 817 + return 0; 811 818 812 819 /* We have an error */ 813 - if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { 814 - ret = i2c_dw_handle_tx_abort(dev); 815 - goto done; 816 - } 820 + if (dev->cmd_err == DW_IC_ERR_TX_ABRT) 821 + return i2c_dw_handle_tx_abort(dev); 817 822 818 823 if (dev->status) 819 824 dev_err(dev->dev, 820 825 "transfer terminated early - interrupt latency too high?\n"); 821 826 822 - ret = -EIO; 827 + return -EIO; 828 + } 823 829 824 - done: 830 + /* 831 + * Verify that the message at index @idx can be processed as part 832 + * of a single transaction. The @msgs array contains the messages 833 + * of the transaction. The message is checked against its predecessor 834 + * to ensure that it respects the limitation of the controller. 835 + * Return: true if the message can be processed, false otherwise. 836 + */ 837 + static bool 838 + i2c_dw_msg_is_valid(struct dw_i2c_dev *dev, const struct i2c_msg *msgs, size_t idx) 839 + { 840 + /* 841 + * The first message of a transaction is valid, 842 + * no constraints from a previous message. 843 + */ 844 + if (!idx) 845 + return true; 846 + 847 + /* 848 + * We cannot change the target address during a transaction, so make 849 + * sure the address is identical to the one of the previous message. 850 + */ 851 + if (msgs[idx - 1].addr != msgs[idx].addr) { 852 + dev_err(dev->dev, "invalid target address\n"); 853 + return false; 854 + } 855 + 856 + /* 857 + * Make sure we don't need explicit RESTART between two messages 858 + * in the same direction for controllers that cannot emit them. 859 + */ 860 + if (!dev->emptyfifo_hold_master && 861 + (msgs[idx - 1].flags & I2C_M_RD) == (msgs[idx].flags & I2C_M_RD)) { 862 + dev_err(dev->dev, "cannot emit RESTART\n"); 863 + return false; 864 + } 865 + 866 + return true; 867 + } 868 + 869 + static int 870 + i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num) 871 + { 872 + struct i2c_msg *msgs_part; 873 + size_t cnt; 874 + int ret; 875 + 876 + dev_dbg(dev->dev, "msgs: %d\n", num); 877 + 878 + PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev->dev, pm); 879 + if (PM_RUNTIME_ACQUIRE_ERR(&pm)) 880 + return -ENXIO; 881 + 882 + ret = i2c_dw_acquire_lock(dev); 883 + if (ret) 884 + return ret; 885 + 886 + /* 887 + * If the I2C_M_STOP is present in some the messages, 888 + * we do one transaction for each part up to the STOP. 889 + */ 890 + for (msgs_part = msgs; msgs_part < msgs + num; msgs_part += cnt) { 891 + /* 892 + * Count the messages in a transaction, up to a STOP or 893 + * the end of the msgs. The last if below guarantees that 894 + * we check all messages and that msg_parts and cnt are 895 + * in-bounds of msgs and num. 896 + */ 897 + for (cnt = 1; ; cnt++) { 898 + if (!i2c_dw_msg_is_valid(dev, msgs_part, cnt - 1)) { 899 + ret = -EINVAL; 900 + break; 901 + } 902 + 903 + if ((msgs_part[cnt - 1].flags & I2C_M_STOP) || 904 + (msgs_part + cnt == msgs + num)) 905 + break; 906 + } 907 + if (ret < 0) 908 + break; 909 + 910 + /* transfer one part up to a STOP */ 911 + ret = __i2c_dw_xfer_one_part(dev, msgs_part, cnt); 912 + if (ret < 0) 913 + break; 914 + } 915 + 825 916 i2c_dw_set_mode(dev, DW_IC_SLAVE); 826 917 827 918 i2c_dw_release_lock(dev); 828 919 829 - done_nolock: 830 - pm_runtime_put_autosuspend(dev->dev); 831 - 832 - return ret; 920 + if (ret < 0) 921 + return ret; 922 + return num; 833 923 } 834 924 835 925 int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) ··· 926 858 struct i2c_timings *t = &dev->timings; 927 859 928 860 dev->functionality |= I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; 861 + 862 + /* amd_i2c_dw_xfer_quirk() does not implement protocol mangling */ 863 + if ((dev->flags & MODEL_MASK) != MODEL_AMD_NAVI_GPU) 864 + dev->functionality |= I2C_FUNC_PROTOCOL_MANGLING; 929 865 930 866 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 931 867 DW_IC_CON_RESTART_EN;

+14 -28

drivers/i2c/busses/i2c-designware-platdrv.c

··· 160 160 if (ret) 161 161 return ret; 162 162 163 - dev->rst = devm_reset_control_get_optional_exclusive(device, NULL); 163 + dev->rst = devm_reset_control_get_optional_exclusive_deasserted(device, NULL); 164 164 if (IS_ERR(dev->rst)) 165 165 return dev_err_probe(device, PTR_ERR(dev->rst), "failed to acquire reset\n"); 166 166 167 - reset_control_deassert(dev->rst); 168 - 169 167 ret = i2c_dw_fw_parse_and_configure(dev); 170 168 if (ret) 171 - goto exit_reset; 169 + return ret; 172 170 173 171 ret = i2c_dw_probe_lock_support(dev); 174 - if (ret) { 175 - dev_err_probe(device, ret, "failed to probe lock support\n"); 176 - goto exit_reset; 177 - } 172 + if (ret) 173 + return dev_err_probe(device, ret, "failed to probe lock support\n"); 178 174 179 175 i2c_dw_configure(dev); 180 176 181 177 /* Optional interface clock */ 182 178 dev->pclk = devm_clk_get_optional(device, "pclk"); 183 - if (IS_ERR(dev->pclk)) { 184 - ret = dev_err_probe(device, PTR_ERR(dev->pclk), "failed to acquire pclk\n"); 185 - goto exit_reset; 186 - } 179 + if (IS_ERR(dev->pclk)) 180 + return dev_err_probe(device, PTR_ERR(dev->pclk), "failed to acquire pclk\n"); 187 181 188 182 dev->clk = devm_clk_get_optional(device, NULL); 189 - if (IS_ERR(dev->clk)) { 190 - ret = dev_err_probe(device, PTR_ERR(dev->clk), "failed to acquire clock\n"); 191 - goto exit_reset; 192 - } 183 + if (IS_ERR(dev->clk)) 184 + return dev_err_probe(device, PTR_ERR(dev->clk), "failed to acquire clock\n"); 193 185 194 186 ret = i2c_dw_prepare_clk(dev, true); 195 187 if (ret) 196 - goto exit_reset; 188 + return ret; 197 189 198 190 if (dev->clk) { 199 191 struct i2c_timings *t = &dev->timings; ··· 225 233 pm_runtime_enable(device); 226 234 227 235 ret = i2c_dw_probe(dev); 228 - if (ret) 229 - goto exit_probe; 236 + if (ret) { 237 + dw_i2c_plat_pm_cleanup(dev); 238 + i2c_dw_prepare_clk(dev, false); 239 + } 230 240 231 - return ret; 232 - 233 - exit_probe: 234 - dw_i2c_plat_pm_cleanup(dev); 235 - i2c_dw_prepare_clk(dev, false); 236 - exit_reset: 237 - reset_control_assert(dev->rst); 238 241 return ret; 239 242 } 240 243 ··· 249 262 dw_i2c_plat_pm_cleanup(dev); 250 263 251 264 i2c_dw_prepare_clk(dev, false); 252 - 253 - reset_control_assert(dev->rst); 254 265 } 255 266 256 267 static const struct of_device_id dw_i2c_of_match[] = { 268 + { .compatible = "mobileye,eyeq6lplus-i2c" }, 257 269 { .compatible = "mscc,ocelot-i2c" }, 258 270 { .compatible = "snps,designware-i2c" }, 259 271 {}

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