Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Add audio support for the MediaTek Genio 350-evk
Merge series from Alexandre Mergnat <amergnat@baylibre.com>:
This serie aim to add the following audio support for the Genio 350-evk:
- Playback
- 2ch Headset Jack (Earphone)
- 1ch Line-out Jack (Speaker)
- 8ch HDMI Tx
- Capture
- 1ch DMIC (On-board Digital Microphone)
- 1ch AMIC (On-board Analogic Microphone)
- 1ch Headset Jack (External Analogic Microphone)
Of course, HDMI playback need the MT8365 display patches [1] and a DTS
change documented in "mediatek,mt8365-mt6357.yaml".
Applied patch:
- mfd: mt6397-core: register mt6357 sound codec
Test passed:
- mixer-test log: [3]
- pcm-test log: [4]
[1]: https://lore.kernel.org/all/20231023-display-support-v1-0-5c860ed5c33b@baylibre.com/
[2]: https://lore.kernel.org/all/20240313110147.1267793-1-angelogioacchino.delregno@collabora.com/
[3]: https://pastebin.com/pc43AVrT
[4]: https://pastebin.com/cCtGhDpg
[5]: https://gitlab.baylibre.com/baylibre/mediatek/bsp/linux/-/commits/sound/for-next/add-i350-audio-support
+6565
+21
Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml
+21
Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml
···
37
37
"#interrupt-cells":
38
38
const: 2
39
39
40
+
mediatek,hp-pull-down:
41
+
description:
42
+
Earphone driver positive output stage short to
43
+
the audio reference ground.
44
+
type: boolean
45
+
46
+
mediatek,micbias0-microvolt:
47
+
description: Selects MIC Bias 0 output voltage.
48
+
enum: [1700000, 1800000, 1900000, 2000000,
49
+
2100000, 2500000, 2600000, 2700000]
50
+
default: 1700000
51
+
52
+
mediatek,micbias1-microvolt:
53
+
description: Selects MIC Bias 1 output voltage.
54
+
enum: [1700000, 1800000, 1900000, 2000000,
55
+
2100000, 2500000, 2600000, 2700000]
56
+
default: 1700000
57
+
40
58
regulators:
41
59
type: object
42
60
$ref: /schemas/regulator/mediatek,mt6357-regulator.yaml
···
100
82
interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
101
83
interrupt-controller;
102
84
#interrupt-cells = <2>;
85
+
86
+
mediatek,micbias0-microvolt = <1700000>;
87
+
mediatek,micbias1-microvolt = <1700000>;
103
88
104
89
regulators {
105
90
mt6357_vproc_reg: buck-vproc {
+130
Documentation/devicetree/bindings/sound/mediatek,mt8365-afe.yaml
+130
Documentation/devicetree/bindings/sound/mediatek,mt8365-afe.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/sound/mediatek,mt8365-afe.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek Audio Front End PCM controller for MT8365
8
+
9
+
maintainers:
10
+
- Alexandre Mergnat <amergnat@baylibre.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: mediatek,mt8365-afe-pcm
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
"#sound-dai-cells":
20
+
const: 0
21
+
22
+
clocks:
23
+
items:
24
+
- description: 26M clock
25
+
- description: mux for audio clock
26
+
- description: audio i2s0 mck
27
+
- description: audio i2s1 mck
28
+
- description: audio i2s2 mck
29
+
- description: audio i2s3 mck
30
+
- description: engen 1 clock
31
+
- description: engen 2 clock
32
+
- description: audio 1 clock
33
+
- description: audio 2 clock
34
+
- description: mux for i2s0
35
+
- description: mux for i2s1
36
+
- description: mux for i2s2
37
+
- description: mux for i2s3
38
+
39
+
clock-names:
40
+
items:
41
+
- const: top_clk26m_clk
42
+
- const: top_audio_sel
43
+
- const: audio_i2s0_m
44
+
- const: audio_i2s1_m
45
+
- const: audio_i2s2_m
46
+
- const: audio_i2s3_m
47
+
- const: engen1
48
+
- const: engen2
49
+
- const: aud1
50
+
- const: aud2
51
+
- const: i2s0_m_sel
52
+
- const: i2s1_m_sel
53
+
- const: i2s2_m_sel
54
+
- const: i2s3_m_sel
55
+
56
+
interrupts:
57
+
maxItems: 1
58
+
59
+
power-domains:
60
+
maxItems: 1
61
+
62
+
mediatek,dmic-mode:
63
+
$ref: /schemas/types.yaml#/definitions/uint32
64
+
description:
65
+
Indicates how many data pins are used to transmit two channels of PDM
66
+
signal. 1 means two wires, 0 means one wire. Default value is 0.
67
+
enum:
68
+
- 0 # one wire
69
+
- 1 # two wires
70
+
71
+
required:
72
+
- compatible
73
+
- reg
74
+
- clocks
75
+
- clock-names
76
+
- interrupts
77
+
- power-domains
78
+
79
+
additionalProperties: false
80
+
81
+
examples:
82
+
- |
83
+
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
84
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
85
+
#include <dt-bindings/interrupt-controller/irq.h>
86
+
#include <dt-bindings/power/mediatek,mt8365-power.h>
87
+
88
+
soc {
89
+
#address-cells = <2>;
90
+
#size-cells = <2>;
91
+
92
+
audio-controller@11220000 {
93
+
compatible = "mediatek,mt8365-afe-pcm";
94
+
reg = <0 0x11220000 0 0x1000>;
95
+
#sound-dai-cells = <0>;
96
+
clocks = <&clk26m>,
97
+
<&topckgen CLK_TOP_AUDIO_SEL>,
98
+
<&topckgen CLK_TOP_AUD_I2S0_M>,
99
+
<&topckgen CLK_TOP_AUD_I2S1_M>,
100
+
<&topckgen CLK_TOP_AUD_I2S2_M>,
101
+
<&topckgen CLK_TOP_AUD_I2S3_M>,
102
+
<&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
103
+
<&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
104
+
<&topckgen CLK_TOP_AUD_1_SEL>,
105
+
<&topckgen CLK_TOP_AUD_2_SEL>,
106
+
<&topckgen CLK_TOP_APLL_I2S0_SEL>,
107
+
<&topckgen CLK_TOP_APLL_I2S1_SEL>,
108
+
<&topckgen CLK_TOP_APLL_I2S2_SEL>,
109
+
<&topckgen CLK_TOP_APLL_I2S3_SEL>;
110
+
clock-names = "top_clk26m_clk",
111
+
"top_audio_sel",
112
+
"audio_i2s0_m",
113
+
"audio_i2s1_m",
114
+
"audio_i2s2_m",
115
+
"audio_i2s3_m",
116
+
"engen1",
117
+
"engen2",
118
+
"aud1",
119
+
"aud2",
120
+
"i2s0_m_sel",
121
+
"i2s1_m_sel",
122
+
"i2s2_m_sel",
123
+
"i2s3_m_sel";
124
+
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
125
+
power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>;
126
+
mediatek,dmic-mode = <1>;
127
+
};
128
+
};
129
+
130
+
...
+107
Documentation/devicetree/bindings/sound/mediatek,mt8365-mt6357.yaml
+107
Documentation/devicetree/bindings/sound/mediatek,mt8365-mt6357.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/sound/mediatek,mt8365-mt6357.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MT8365 ASoC sound card
8
+
9
+
maintainers:
10
+
- Alexandre Mergnat <amergnat@baylibre.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: mediatek,mt8365-mt6357
15
+
16
+
pinctrl-names:
17
+
minItems: 1
18
+
items:
19
+
- const: default
20
+
- const: dmic
21
+
- const: miso_off
22
+
- const: miso_on
23
+
- const: mosi_off
24
+
- const: mosi_on
25
+
26
+
mediatek,platform:
27
+
$ref: /schemas/types.yaml#/definitions/phandle
28
+
description: The phandle of MT8365 ASoC platform.
29
+
30
+
patternProperties:
31
+
"^dai-link-[0-9]+$":
32
+
type: object
33
+
description:
34
+
Container for dai-link level properties and CODEC sub-nodes.
35
+
36
+
properties:
37
+
codec:
38
+
type: object
39
+
description: Holds subnode which indicates codec dai.
40
+
41
+
properties:
42
+
sound-dai:
43
+
maxItems: 1
44
+
description: phandle of the codec DAI
45
+
46
+
additionalProperties: false
47
+
48
+
link-name:
49
+
description: Indicates dai-link name and PCM stream name
50
+
enum:
51
+
- I2S_IN_BE
52
+
- I2S_OUT_BE
53
+
- PCM1_BE
54
+
- PDM1_BE
55
+
- PDM2_BE
56
+
- PDM3_BE
57
+
- PDM4_BE
58
+
- SPDIF_IN_BE
59
+
- SPDIF_OUT_BE
60
+
- TDM_IN_BE
61
+
- TDM_OUT_BE
62
+
63
+
sound-dai:
64
+
maxItems: 1
65
+
description: phandle of the CPU DAI
66
+
67
+
required:
68
+
- link-name
69
+
- sound-dai
70
+
71
+
additionalProperties: false
72
+
73
+
required:
74
+
- compatible
75
+
- pinctrl-names
76
+
- mediatek,platform
77
+
78
+
additionalProperties: false
79
+
80
+
examples:
81
+
- |
82
+
sound {
83
+
compatible = "mediatek,mt8365-mt6357";
84
+
pinctrl-names = "default",
85
+
"dmic",
86
+
"miso_off",
87
+
"miso_on",
88
+
"mosi_off",
89
+
"mosi_on";
90
+
pinctrl-0 = <&aud_default_pins>;
91
+
pinctrl-1 = <&aud_dmic_pins>;
92
+
pinctrl-2 = <&aud_miso_off_pins>;
93
+
pinctrl-3 = <&aud_miso_on_pins>;
94
+
pinctrl-4 = <&aud_mosi_off_pins>;
95
+
pinctrl-5 = <&aud_mosi_on_pins>;
96
+
mediatek,platform = <&afe>;
97
+
98
+
/* hdmi interface */
99
+
dai-link-0 {
100
+
link-name = "I2S_OUT_BE";
101
+
sound-dai = <&afe>;
102
+
103
+
codec {
104
+
sound-dai = <&it66121hdmitx>;
105
+
};
106
+
};
107
+
};
+421
sound/soc/mediatek/mt8365/mt8365-afe-clk.c
+421
sound/soc/mediatek/mt8365/mt8365-afe-clk.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek 8365 AFE clock control
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#include "mt8365-afe-clk.h"
11
+
#include "mt8365-afe-common.h"
12
+
#include "mt8365-reg.h"
13
+
#include "../common/mtk-base-afe.h"
14
+
#include <linux/device.h>
15
+
#include <linux/mfd/syscon.h>
16
+
17
+
static const char *aud_clks[MT8365_CLK_NUM] = {
18
+
[MT8365_CLK_TOP_AUD_SEL] = "top_audio_sel",
19
+
[MT8365_CLK_AUD_I2S0_M] = "audio_i2s0_m",
20
+
[MT8365_CLK_AUD_I2S1_M] = "audio_i2s1_m",
21
+
[MT8365_CLK_AUD_I2S2_M] = "audio_i2s2_m",
22
+
[MT8365_CLK_AUD_I2S3_M] = "audio_i2s3_m",
23
+
[MT8365_CLK_ENGEN1] = "engen1",
24
+
[MT8365_CLK_ENGEN2] = "engen2",
25
+
[MT8365_CLK_AUD1] = "aud1",
26
+
[MT8365_CLK_AUD2] = "aud2",
27
+
[MT8365_CLK_I2S0_M_SEL] = "i2s0_m_sel",
28
+
[MT8365_CLK_I2S1_M_SEL] = "i2s1_m_sel",
29
+
[MT8365_CLK_I2S2_M_SEL] = "i2s2_m_sel",
30
+
[MT8365_CLK_I2S3_M_SEL] = "i2s3_m_sel",
31
+
[MT8365_CLK_CLK26M] = "top_clk26m_clk",
32
+
};
33
+
34
+
int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe)
35
+
{
36
+
size_t i;
37
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
38
+
39
+
for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
40
+
afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
41
+
if (IS_ERR(afe_priv->clocks[i])) {
42
+
dev_err(afe->dev, "%s devm_clk_get %s fail\n",
43
+
__func__, aud_clks[i]);
44
+
return PTR_ERR(afe_priv->clocks[i]);
45
+
}
46
+
}
47
+
return 0;
48
+
}
49
+
50
+
void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
51
+
{
52
+
if (clk)
53
+
clk_disable_unprepare(clk);
54
+
}
55
+
56
+
int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
57
+
unsigned int rate)
58
+
{
59
+
int ret;
60
+
61
+
if (clk) {
62
+
ret = clk_set_rate(clk, rate);
63
+
if (ret) {
64
+
dev_err(afe->dev, "Failed to set rate\n");
65
+
return ret;
66
+
}
67
+
}
68
+
return 0;
69
+
}
70
+
71
+
int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
72
+
struct clk *parent)
73
+
{
74
+
int ret;
75
+
76
+
if (clk && parent) {
77
+
ret = clk_set_parent(clk, parent);
78
+
if (ret) {
79
+
dev_err(afe->dev, "Failed to set parent\n");
80
+
return ret;
81
+
}
82
+
}
83
+
return 0;
84
+
}
85
+
86
+
static unsigned int get_top_cg_reg(unsigned int cg_type)
87
+
{
88
+
switch (cg_type) {
89
+
case MT8365_TOP_CG_AFE:
90
+
case MT8365_TOP_CG_I2S_IN:
91
+
case MT8365_TOP_CG_22M:
92
+
case MT8365_TOP_CG_24M:
93
+
case MT8365_TOP_CG_INTDIR_CK:
94
+
case MT8365_TOP_CG_APLL2_TUNER:
95
+
case MT8365_TOP_CG_APLL_TUNER:
96
+
case MT8365_TOP_CG_SPDIF:
97
+
case MT8365_TOP_CG_TDM_OUT:
98
+
case MT8365_TOP_CG_TDM_IN:
99
+
case MT8365_TOP_CG_ADC:
100
+
case MT8365_TOP_CG_DAC:
101
+
case MT8365_TOP_CG_DAC_PREDIS:
102
+
case MT8365_TOP_CG_TML:
103
+
return AUDIO_TOP_CON0;
104
+
case MT8365_TOP_CG_I2S1_BCLK:
105
+
case MT8365_TOP_CG_I2S2_BCLK:
106
+
case MT8365_TOP_CG_I2S3_BCLK:
107
+
case MT8365_TOP_CG_I2S4_BCLK:
108
+
case MT8365_TOP_CG_DMIC0_ADC:
109
+
case MT8365_TOP_CG_DMIC1_ADC:
110
+
case MT8365_TOP_CG_DMIC2_ADC:
111
+
case MT8365_TOP_CG_DMIC3_ADC:
112
+
case MT8365_TOP_CG_CONNSYS_I2S_ASRC:
113
+
case MT8365_TOP_CG_GENERAL1_ASRC:
114
+
case MT8365_TOP_CG_GENERAL2_ASRC:
115
+
case MT8365_TOP_CG_TDM_ASRC:
116
+
return AUDIO_TOP_CON1;
117
+
default:
118
+
return 0;
119
+
}
120
+
}
121
+
122
+
static unsigned int get_top_cg_mask(unsigned int cg_type)
123
+
{
124
+
switch (cg_type) {
125
+
case MT8365_TOP_CG_AFE:
126
+
return AUD_TCON0_PDN_AFE;
127
+
case MT8365_TOP_CG_I2S_IN:
128
+
return AUD_TCON0_PDN_I2S_IN;
129
+
case MT8365_TOP_CG_22M:
130
+
return AUD_TCON0_PDN_22M;
131
+
case MT8365_TOP_CG_24M:
132
+
return AUD_TCON0_PDN_24M;
133
+
case MT8365_TOP_CG_INTDIR_CK:
134
+
return AUD_TCON0_PDN_INTDIR;
135
+
case MT8365_TOP_CG_APLL2_TUNER:
136
+
return AUD_TCON0_PDN_APLL2_TUNER;
137
+
case MT8365_TOP_CG_APLL_TUNER:
138
+
return AUD_TCON0_PDN_APLL_TUNER;
139
+
case MT8365_TOP_CG_SPDIF:
140
+
return AUD_TCON0_PDN_SPDIF;
141
+
case MT8365_TOP_CG_TDM_OUT:
142
+
return AUD_TCON0_PDN_TDM_OUT;
143
+
case MT8365_TOP_CG_TDM_IN:
144
+
return AUD_TCON0_PDN_TDM_IN;
145
+
case MT8365_TOP_CG_ADC:
146
+
return AUD_TCON0_PDN_ADC;
147
+
case MT8365_TOP_CG_DAC:
148
+
return AUD_TCON0_PDN_DAC;
149
+
case MT8365_TOP_CG_DAC_PREDIS:
150
+
return AUD_TCON0_PDN_DAC_PREDIS;
151
+
case MT8365_TOP_CG_TML:
152
+
return AUD_TCON0_PDN_TML;
153
+
case MT8365_TOP_CG_I2S1_BCLK:
154
+
return AUD_TCON1_PDN_I2S1_BCLK;
155
+
case MT8365_TOP_CG_I2S2_BCLK:
156
+
return AUD_TCON1_PDN_I2S2_BCLK;
157
+
case MT8365_TOP_CG_I2S3_BCLK:
158
+
return AUD_TCON1_PDN_I2S3_BCLK;
159
+
case MT8365_TOP_CG_I2S4_BCLK:
160
+
return AUD_TCON1_PDN_I2S4_BCLK;
161
+
case MT8365_TOP_CG_DMIC0_ADC:
162
+
return AUD_TCON1_PDN_DMIC0_ADC;
163
+
case MT8365_TOP_CG_DMIC1_ADC:
164
+
return AUD_TCON1_PDN_DMIC1_ADC;
165
+
case MT8365_TOP_CG_DMIC2_ADC:
166
+
return AUD_TCON1_PDN_DMIC2_ADC;
167
+
case MT8365_TOP_CG_DMIC3_ADC:
168
+
return AUD_TCON1_PDN_DMIC3_ADC;
169
+
case MT8365_TOP_CG_CONNSYS_I2S_ASRC:
170
+
return AUD_TCON1_PDN_CONNSYS_I2S_ASRC;
171
+
case MT8365_TOP_CG_GENERAL1_ASRC:
172
+
return AUD_TCON1_PDN_GENERAL1_ASRC;
173
+
case MT8365_TOP_CG_GENERAL2_ASRC:
174
+
return AUD_TCON1_PDN_GENERAL2_ASRC;
175
+
case MT8365_TOP_CG_TDM_ASRC:
176
+
return AUD_TCON1_PDN_TDM_ASRC;
177
+
default:
178
+
return 0;
179
+
}
180
+
}
181
+
182
+
static unsigned int get_top_cg_on_val(unsigned int cg_type)
183
+
{
184
+
return 0;
185
+
}
186
+
187
+
static unsigned int get_top_cg_off_val(unsigned int cg_type)
188
+
{
189
+
return get_top_cg_mask(cg_type);
190
+
}
191
+
192
+
int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
193
+
{
194
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
195
+
unsigned int reg = get_top_cg_reg(cg_type);
196
+
unsigned int mask = get_top_cg_mask(cg_type);
197
+
unsigned int val = get_top_cg_on_val(cg_type);
198
+
unsigned long flags;
199
+
200
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
201
+
202
+
afe_priv->top_cg_ref_cnt[cg_type]++;
203
+
if (afe_priv->top_cg_ref_cnt[cg_type] == 1)
204
+
regmap_update_bits(afe->regmap, reg, mask, val);
205
+
206
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
207
+
208
+
return 0;
209
+
}
210
+
211
+
int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
212
+
{
213
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
214
+
unsigned int reg = get_top_cg_reg(cg_type);
215
+
unsigned int mask = get_top_cg_mask(cg_type);
216
+
unsigned int val = get_top_cg_off_val(cg_type);
217
+
unsigned long flags;
218
+
219
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
220
+
221
+
afe_priv->top_cg_ref_cnt[cg_type]--;
222
+
if (afe_priv->top_cg_ref_cnt[cg_type] == 0)
223
+
regmap_update_bits(afe->regmap, reg, mask, val);
224
+
else if (afe_priv->top_cg_ref_cnt[cg_type] < 0)
225
+
afe_priv->top_cg_ref_cnt[cg_type] = 0;
226
+
227
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
228
+
229
+
return 0;
230
+
}
231
+
232
+
int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe)
233
+
{
234
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
235
+
236
+
clk_prepare_enable(afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
237
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);
238
+
mt8365_afe_enable_afe_on(afe);
239
+
240
+
return 0;
241
+
}
242
+
243
+
int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe)
244
+
{
245
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
246
+
247
+
mt8365_afe_disable_afe_on(afe);
248
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);
249
+
mt8365_afe_disable_clk(afe, afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL]);
250
+
251
+
return 0;
252
+
}
253
+
254
+
int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe)
255
+
{
256
+
return 0;
257
+
}
258
+
259
+
int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe)
260
+
{
261
+
return 0;
262
+
}
263
+
264
+
int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe)
265
+
{
266
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
267
+
unsigned long flags;
268
+
269
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
270
+
271
+
afe_priv->afe_on_ref_cnt++;
272
+
if (afe_priv->afe_on_ref_cnt == 1)
273
+
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
274
+
275
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
276
+
277
+
return 0;
278
+
}
279
+
280
+
int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)
281
+
{
282
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
283
+
unsigned long flags;
284
+
285
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
286
+
287
+
afe_priv->afe_on_ref_cnt--;
288
+
if (afe_priv->afe_on_ref_cnt == 0)
289
+
regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
290
+
else if (afe_priv->afe_on_ref_cnt < 0)
291
+
afe_priv->afe_on_ref_cnt = 0;
292
+
293
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
294
+
295
+
return 0;
296
+
}
297
+
298
+
int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
299
+
{
300
+
if (apll1)
301
+
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
302
+
AFE_22M_PLL_EN, AFE_22M_PLL_EN);
303
+
else
304
+
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
305
+
AFE_24M_PLL_EN, AFE_24M_PLL_EN);
306
+
307
+
return 0;
308
+
}
309
+
310
+
int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
311
+
{
312
+
if (apll1)
313
+
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
314
+
AFE_22M_PLL_EN, ~AFE_22M_PLL_EN);
315
+
else
316
+
regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
317
+
AFE_24M_PLL_EN, ~AFE_24M_PLL_EN);
318
+
319
+
return 0;
320
+
}
321
+
322
+
int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
323
+
{
324
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
325
+
326
+
mutex_lock(&afe_priv->afe_clk_mutex);
327
+
328
+
afe_priv->apll_tuner_ref_cnt[apll]++;
329
+
if (afe_priv->apll_tuner_ref_cnt[apll] != 1) {
330
+
mutex_unlock(&afe_priv->afe_clk_mutex);
331
+
return 0;
332
+
}
333
+
334
+
if (apll == MT8365_AFE_APLL1) {
335
+
regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
336
+
AFE_APLL_TUNER_CFG_MASK, 0x432);
337
+
regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
338
+
AFE_APLL_TUNER_CFG_EN_MASK, 0x1);
339
+
} else {
340
+
regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
341
+
AFE_APLL_TUNER_CFG1_MASK, 0x434);
342
+
regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
343
+
AFE_APLL_TUNER_CFG1_EN_MASK, 0x1);
344
+
}
345
+
346
+
mutex_unlock(&afe_priv->afe_clk_mutex);
347
+
return 0;
348
+
}
349
+
350
+
int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll)
351
+
{
352
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
353
+
354
+
mutex_lock(&afe_priv->afe_clk_mutex);
355
+
356
+
afe_priv->apll_tuner_ref_cnt[apll]--;
357
+
if (afe_priv->apll_tuner_ref_cnt[apll] == 0) {
358
+
if (apll == MT8365_AFE_APLL1)
359
+
regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG,
360
+
AFE_APLL_TUNER_CFG_EN_MASK, 0x0);
361
+
else
362
+
regmap_update_bits(afe->regmap, AFE_APLL_TUNER_CFG1,
363
+
AFE_APLL_TUNER_CFG1_EN_MASK, 0x0);
364
+
365
+
} else if (afe_priv->apll_tuner_ref_cnt[apll] < 0) {
366
+
afe_priv->apll_tuner_ref_cnt[apll] = 0;
367
+
}
368
+
369
+
mutex_unlock(&afe_priv->afe_clk_mutex);
370
+
return 0;
371
+
}
372
+
373
+
int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
374
+
{
375
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
376
+
377
+
if (apll == MT8365_AFE_APLL1) {
378
+
if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN1])) {
379
+
dev_info(afe->dev, "%s Failed to enable ENGEN1 clk\n",
380
+
__func__);
381
+
return 0;
382
+
}
383
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_22M);
384
+
mt8365_afe_hd_engen_enable(afe, true);
385
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
386
+
mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
387
+
} else {
388
+
if (clk_prepare_enable(afe_priv->clocks[MT8365_CLK_ENGEN2])) {
389
+
dev_info(afe->dev, "%s Failed to enable ENGEN2 clk\n",
390
+
__func__);
391
+
return 0;
392
+
}
393
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_24M);
394
+
mt8365_afe_hd_engen_enable(afe, false);
395
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
396
+
mt8365_afe_enable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
397
+
}
398
+
399
+
return 0;
400
+
}
401
+
402
+
int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll)
403
+
{
404
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
405
+
406
+
if (apll == MT8365_AFE_APLL1) {
407
+
mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL1);
408
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL_TUNER);
409
+
mt8365_afe_hd_engen_disable(afe, true);
410
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_22M);
411
+
clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN1]);
412
+
} else {
413
+
mt8365_afe_disable_apll_tuner_cfg(afe, MT8365_AFE_APLL2);
414
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_APLL2_TUNER);
415
+
mt8365_afe_hd_engen_disable(afe, false);
416
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_24M);
417
+
clk_disable_unprepare(afe_priv->clocks[MT8365_CLK_ENGEN2]);
418
+
}
419
+
420
+
return 0;
421
+
}
+32
sound/soc/mediatek/mt8365/mt8365-afe-clk.h
+32
sound/soc/mediatek/mt8365/mt8365-afe-clk.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0
2
+
*
3
+
* MediaTek 8365 AFE clock control definitions
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#ifndef _MT8365_AFE_UTILS_H_
11
+
#define _MT8365_AFE_UTILS_H_
12
+
13
+
struct mtk_base_afe;
14
+
struct clk;
15
+
16
+
int mt8365_afe_init_audio_clk(struct mtk_base_afe *afe);
17
+
void mt8365_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
18
+
int mt8365_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, unsigned int rate);
19
+
int mt8365_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, struct clk *parent);
20
+
int mt8365_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);
21
+
int mt8365_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type);
22
+
int mt8365_afe_enable_main_clk(struct mtk_base_afe *afe);
23
+
int mt8365_afe_disable_main_clk(struct mtk_base_afe *afe);
24
+
int mt8365_afe_emi_clk_on(struct mtk_base_afe *afe);
25
+
int mt8365_afe_emi_clk_off(struct mtk_base_afe *afe);
26
+
int mt8365_afe_enable_afe_on(struct mtk_base_afe *afe);
27
+
int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe);
28
+
int mt8365_afe_enable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
29
+
int mt8365_afe_disable_apll_tuner_cfg(struct mtk_base_afe *afe, unsigned int apll);
30
+
int mt8365_afe_enable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
31
+
int mt8365_afe_disable_apll_associated_cfg(struct mtk_base_afe *afe, unsigned int apll);
32
+
#endif
+449
sound/soc/mediatek/mt8365/mt8365-afe-common.h
+449
sound/soc/mediatek/mt8365/mt8365-afe-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0
2
+
*
3
+
* MediaTek 8365 audio driver common definitions
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#ifndef _MT8365_AFE_COMMON_H_
11
+
#define _MT8365_AFE_COMMON_H_
12
+
13
+
#include <linux/clk.h>
14
+
#include <linux/list.h>
15
+
#include <linux/regmap.h>
16
+
#include <sound/soc.h>
17
+
#include <sound/asound.h>
18
+
#include "../common/mtk-base-afe.h"
19
+
#include "mt8365-reg.h"
20
+
21
+
enum {
22
+
MT8365_AFE_MEMIF_DL1,
23
+
MT8365_AFE_MEMIF_DL2,
24
+
MT8365_AFE_MEMIF_TDM_OUT,
25
+
/*
26
+
* MT8365_AFE_MEMIF_SPDIF_OUT,
27
+
*/
28
+
MT8365_AFE_MEMIF_AWB,
29
+
MT8365_AFE_MEMIF_VUL,
30
+
MT8365_AFE_MEMIF_VUL2,
31
+
MT8365_AFE_MEMIF_VUL3,
32
+
MT8365_AFE_MEMIF_TDM_IN,
33
+
/*
34
+
* MT8365_AFE_MEMIF_SPDIF_IN,
35
+
*/
36
+
MT8365_AFE_MEMIF_NUM,
37
+
MT8365_AFE_BACKEND_BASE = MT8365_AFE_MEMIF_NUM,
38
+
MT8365_AFE_IO_TDM_OUT = MT8365_AFE_BACKEND_BASE,
39
+
MT8365_AFE_IO_TDM_IN,
40
+
MT8365_AFE_IO_I2S,
41
+
MT8365_AFE_IO_2ND_I2S,
42
+
MT8365_AFE_IO_PCM1,
43
+
MT8365_AFE_IO_VIRTUAL_DL_SRC,
44
+
MT8365_AFE_IO_VIRTUAL_TDM_OUT_SRC,
45
+
MT8365_AFE_IO_VIRTUAL_FM,
46
+
MT8365_AFE_IO_DMIC,
47
+
MT8365_AFE_IO_INT_ADDA,
48
+
MT8365_AFE_IO_GASRC1,
49
+
MT8365_AFE_IO_GASRC2,
50
+
MT8365_AFE_IO_TDM_ASRC,
51
+
MT8365_AFE_IO_HW_GAIN1,
52
+
MT8365_AFE_IO_HW_GAIN2,
53
+
MT8365_AFE_BACKEND_END,
54
+
MT8365_AFE_BACKEND_NUM = (MT8365_AFE_BACKEND_END -
55
+
MT8365_AFE_BACKEND_BASE),
56
+
};
57
+
58
+
enum {
59
+
MT8365_AFE_IRQ1,
60
+
MT8365_AFE_IRQ2,
61
+
MT8365_AFE_IRQ3,
62
+
MT8365_AFE_IRQ4,
63
+
MT8365_AFE_IRQ5,
64
+
MT8365_AFE_IRQ6,
65
+
MT8365_AFE_IRQ7,
66
+
MT8365_AFE_IRQ8,
67
+
MT8365_AFE_IRQ9,
68
+
MT8365_AFE_IRQ10,
69
+
MT8365_AFE_IRQ_NUM,
70
+
};
71
+
72
+
enum {
73
+
MT8365_TOP_CG_AFE,
74
+
MT8365_TOP_CG_I2S_IN,
75
+
MT8365_TOP_CG_22M,
76
+
MT8365_TOP_CG_24M,
77
+
MT8365_TOP_CG_INTDIR_CK,
78
+
MT8365_TOP_CG_APLL2_TUNER,
79
+
MT8365_TOP_CG_APLL_TUNER,
80
+
MT8365_TOP_CG_SPDIF,
81
+
MT8365_TOP_CG_TDM_OUT,
82
+
MT8365_TOP_CG_TDM_IN,
83
+
MT8365_TOP_CG_ADC,
84
+
MT8365_TOP_CG_DAC,
85
+
MT8365_TOP_CG_DAC_PREDIS,
86
+
MT8365_TOP_CG_TML,
87
+
MT8365_TOP_CG_I2S1_BCLK,
88
+
MT8365_TOP_CG_I2S2_BCLK,
89
+
MT8365_TOP_CG_I2S3_BCLK,
90
+
MT8365_TOP_CG_I2S4_BCLK,
91
+
MT8365_TOP_CG_DMIC0_ADC,
92
+
MT8365_TOP_CG_DMIC1_ADC,
93
+
MT8365_TOP_CG_DMIC2_ADC,
94
+
MT8365_TOP_CG_DMIC3_ADC,
95
+
MT8365_TOP_CG_CONNSYS_I2S_ASRC,
96
+
MT8365_TOP_CG_GENERAL1_ASRC,
97
+
MT8365_TOP_CG_GENERAL2_ASRC,
98
+
MT8365_TOP_CG_TDM_ASRC,
99
+
MT8365_TOP_CG_NUM
100
+
};
101
+
102
+
enum {
103
+
MT8365_CLK_TOP_AUD_SEL,
104
+
MT8365_CLK_AUD_I2S0_M,
105
+
MT8365_CLK_AUD_I2S1_M,
106
+
MT8365_CLK_AUD_I2S2_M,
107
+
MT8365_CLK_AUD_I2S3_M,
108
+
MT8365_CLK_ENGEN1,
109
+
MT8365_CLK_ENGEN2,
110
+
MT8365_CLK_AUD1,
111
+
MT8365_CLK_AUD2,
112
+
MT8365_CLK_I2S0_M_SEL,
113
+
MT8365_CLK_I2S1_M_SEL,
114
+
MT8365_CLK_I2S2_M_SEL,
115
+
MT8365_CLK_I2S3_M_SEL,
116
+
MT8365_CLK_CLK26M,
117
+
MT8365_CLK_NUM
118
+
};
119
+
120
+
enum {
121
+
MT8365_AFE_APLL1 = 0,
122
+
MT8365_AFE_APLL2,
123
+
MT8365_AFE_APLL_NUM,
124
+
};
125
+
126
+
enum {
127
+
MT8365_AFE_1ST_I2S = 0,
128
+
MT8365_AFE_2ND_I2S,
129
+
MT8365_AFE_I2S_SETS,
130
+
};
131
+
132
+
enum {
133
+
MT8365_AFE_I2S_SEPARATE_CLOCK = 0,
134
+
MT8365_AFE_I2S_SHARED_CLOCK,
135
+
};
136
+
137
+
enum {
138
+
MT8365_AFE_TDM_OUT_I2S = 0,
139
+
MT8365_AFE_TDM_OUT_TDM,
140
+
MT8365_AFE_TDM_OUT_I2S_32BITS,
141
+
};
142
+
143
+
enum mt8365_afe_tdm_ch_start {
144
+
AFE_TDM_CH_START_O28_O29 = 0,
145
+
AFE_TDM_CH_START_O30_O31,
146
+
AFE_TDM_CH_START_O32_O33,
147
+
AFE_TDM_CH_START_O34_O35,
148
+
AFE_TDM_CH_ZERO,
149
+
};
150
+
151
+
enum {
152
+
MT8365_PCM_FORMAT_I2S = 0,
153
+
MT8365_PCM_FORMAT_EIAJ,
154
+
MT8365_PCM_FORMAT_PCMA,
155
+
MT8365_PCM_FORMAT_PCMB,
156
+
};
157
+
158
+
enum {
159
+
MT8365_FS_8K = 0,
160
+
MT8365_FS_11D025K,
161
+
MT8365_FS_12K,
162
+
MT8365_FS_384K,
163
+
MT8365_FS_16K,
164
+
MT8365_FS_22D05K,
165
+
MT8365_FS_24K,
166
+
MT8365_FS_130K,
167
+
MT8365_FS_32K,
168
+
MT8365_FS_44D1K,
169
+
MT8365_FS_48K,
170
+
MT8365_FS_88D2K,
171
+
MT8365_FS_96K,
172
+
MT8365_FS_176D4K,
173
+
MT8365_FS_192K,
174
+
};
175
+
176
+
enum {
177
+
FS_8000HZ = 0, /* 0000b */
178
+
FS_11025HZ = 1, /* 0001b */
179
+
FS_12000HZ = 2, /* 0010b */
180
+
FS_384000HZ = 3, /* 0011b */
181
+
FS_16000HZ = 4, /* 0100b */
182
+
FS_22050HZ = 5, /* 0101b */
183
+
FS_24000HZ = 6, /* 0110b */
184
+
FS_130000HZ = 7, /* 0111b */
185
+
FS_32000HZ = 8, /* 1000b */
186
+
FS_44100HZ = 9, /* 1001b */
187
+
FS_48000HZ = 10, /* 1010b */
188
+
FS_88200HZ = 11, /* 1011b */
189
+
FS_96000HZ = 12, /* 1100b */
190
+
FS_176400HZ = 13, /* 1101b */
191
+
FS_192000HZ = 14, /* 1110b */
192
+
FS_260000HZ = 15, /* 1111b */
193
+
};
194
+
195
+
enum {
196
+
MT8365_AFE_DEBUGFS_AFE,
197
+
MT8365_AFE_DEBUGFS_MEMIF,
198
+
MT8365_AFE_DEBUGFS_IRQ,
199
+
MT8365_AFE_DEBUGFS_CONN,
200
+
MT8365_AFE_DEBUGFS_DBG,
201
+
MT8365_AFE_DEBUGFS_NUM,
202
+
};
203
+
204
+
enum {
205
+
MT8365_AFE_IRQ_DIR_MCU = 0,
206
+
MT8365_AFE_IRQ_DIR_DSP,
207
+
MT8365_AFE_IRQ_DIR_BOTH,
208
+
};
209
+
210
+
/* MCLK */
211
+
enum {
212
+
MT8365_I2S0_MCK = 0,
213
+
MT8365_I2S3_MCK,
214
+
MT8365_MCK_NUM,
215
+
};
216
+
217
+
struct mt8365_fe_dai_data {
218
+
bool use_sram;
219
+
unsigned int sram_phy_addr;
220
+
void __iomem *sram_vir_addr;
221
+
unsigned int sram_size;
222
+
};
223
+
224
+
struct mt8365_be_dai_data {
225
+
bool prepared[SNDRV_PCM_STREAM_LAST + 1];
226
+
unsigned int fmt_mode;
227
+
};
228
+
229
+
#define MT8365_CLK_26M 26000000
230
+
#define MT8365_CLK_24M 24000000
231
+
#define MT8365_CLK_22M 22000000
232
+
#define MT8365_CM_UPDATA_CNT_SET 8
233
+
234
+
enum mt8365_cm_num {
235
+
MT8365_CM1 = 0,
236
+
MT8365_CM2,
237
+
MT8365_CM_NUM,
238
+
};
239
+
240
+
enum mt8365_cm2_mux_in {
241
+
MT8365_FROM_GASRC1 = 1,
242
+
MT8365_FROM_GASRC2,
243
+
MT8365_FROM_TDM_ASRC,
244
+
MT8365_CM_MUX_NUM,
245
+
};
246
+
247
+
enum cm2_mux_conn_in {
248
+
GENERAL2_ASRC_OUT_LCH = 0,
249
+
GENERAL2_ASRC_OUT_RCH = 1,
250
+
TDM_IN_CH0 = 2,
251
+
TDM_IN_CH1 = 3,
252
+
TDM_IN_CH2 = 4,
253
+
TDM_IN_CH3 = 5,
254
+
TDM_IN_CH4 = 6,
255
+
TDM_IN_CH5 = 7,
256
+
TDM_IN_CH6 = 8,
257
+
TDM_IN_CH7 = 9,
258
+
GENERAL1_ASRC_OUT_LCH = 10,
259
+
GENERAL1_ASRC_OUT_RCH = 11,
260
+
TDM_OUT_ASRC_CH0 = 12,
261
+
TDM_OUT_ASRC_CH1 = 13,
262
+
TDM_OUT_ASRC_CH2 = 14,
263
+
TDM_OUT_ASRC_CH3 = 15,
264
+
TDM_OUT_ASRC_CH4 = 16,
265
+
TDM_OUT_ASRC_CH5 = 17,
266
+
TDM_OUT_ASRC_CH6 = 18,
267
+
TDM_OUT_ASRC_CH7 = 19
268
+
};
269
+
270
+
struct mt8365_cm_ctrl_reg {
271
+
unsigned int con0;
272
+
unsigned int con1;
273
+
unsigned int con2;
274
+
unsigned int con3;
275
+
unsigned int con4;
276
+
};
277
+
278
+
struct mt8365_control_data {
279
+
bool bypass_cm1;
280
+
bool bypass_cm2;
281
+
unsigned int loopback_type;
282
+
};
283
+
284
+
enum dmic_input_mode {
285
+
DMIC_MODE_3P25M = 0,
286
+
DMIC_MODE_1P625M,
287
+
DMIC_MODE_812P5K,
288
+
DMIC_MODE_406P25K,
289
+
};
290
+
291
+
enum iir_mode {
292
+
IIR_MODE0 = 0,
293
+
IIR_MODE1,
294
+
IIR_MODE2,
295
+
IIR_MODE3,
296
+
IIR_MODE4,
297
+
IIR_MODE5,
298
+
};
299
+
300
+
enum {
301
+
MT8365_GASRC1 = 0,
302
+
MT8365_GASRC2,
303
+
MT8365_GASRC_NUM,
304
+
MT8365_TDM_ASRC1 = MT8365_GASRC_NUM,
305
+
MT8365_TDM_ASRC2,
306
+
MT8365_TDM_ASRC3,
307
+
MT8365_TDM_ASRC4,
308
+
MT8365_TDM_ASRC_NUM,
309
+
};
310
+
311
+
struct mt8365_gasrc_ctrl_reg {
312
+
unsigned int con0;
313
+
unsigned int con2;
314
+
unsigned int con3;
315
+
unsigned int con4;
316
+
unsigned int con5;
317
+
unsigned int con6;
318
+
unsigned int con9;
319
+
unsigned int con10;
320
+
unsigned int con12;
321
+
unsigned int con13;
322
+
};
323
+
324
+
struct mt8365_gasrc_data {
325
+
bool duplex;
326
+
bool tx_mode;
327
+
bool cali_on;
328
+
bool tdm_asrc_out_cm2;
329
+
bool iir_on;
330
+
};
331
+
332
+
struct mt8365_afe_private {
333
+
struct clk *clocks[MT8365_CLK_NUM];
334
+
struct regmap *topckgen;
335
+
struct mt8365_fe_dai_data fe_data[MT8365_AFE_MEMIF_NUM];
336
+
struct mt8365_be_dai_data be_data[MT8365_AFE_BACKEND_NUM];
337
+
struct mt8365_control_data ctrl_data;
338
+
struct mt8365_gasrc_data gasrc_data[MT8365_TDM_ASRC_NUM];
339
+
int afe_on_ref_cnt;
340
+
int top_cg_ref_cnt[MT8365_TOP_CG_NUM];
341
+
void __iomem *afe_sram_vir_addr;
342
+
unsigned int afe_sram_phy_addr;
343
+
unsigned int afe_sram_size;
344
+
/* locks */
345
+
spinlock_t afe_ctrl_lock;
346
+
struct mutex afe_clk_mutex; /* Protect & sync APLL TUNER registers access*/
347
+
#ifdef CONFIG_DEBUG_FS
348
+
struct dentry *debugfs_dentry[MT8365_AFE_DEBUGFS_NUM];
349
+
#endif
350
+
int apll_tuner_ref_cnt[MT8365_AFE_APLL_NUM];
351
+
unsigned int tdm_out_mode;
352
+
unsigned int cm2_mux_input;
353
+
354
+
/* dai */
355
+
bool dai_on[MT8365_AFE_BACKEND_END];
356
+
void *dai_priv[MT8365_AFE_BACKEND_END];
357
+
};
358
+
359
+
static inline u32 rx_frequency_palette(unsigned int fs)
360
+
{
361
+
/* *
362
+
* A = (26M / fs) * 64
363
+
* B = 8125 / A
364
+
* return = DEC2HEX(B * 2^23)
365
+
*/
366
+
switch (fs) {
367
+
case FS_8000HZ: return 0x050000;
368
+
case FS_11025HZ: return 0x06E400;
369
+
case FS_12000HZ: return 0x078000;
370
+
case FS_16000HZ: return 0x0A0000;
371
+
case FS_22050HZ: return 0x0DC800;
372
+
case FS_24000HZ: return 0x0F0000;
373
+
case FS_32000HZ: return 0x140000;
374
+
case FS_44100HZ: return 0x1B9000;
375
+
case FS_48000HZ: return 0x1E0000;
376
+
case FS_88200HZ: return 0x372000;
377
+
case FS_96000HZ: return 0x3C0000;
378
+
case FS_176400HZ: return 0x6E4000;
379
+
case FS_192000HZ: return 0x780000;
380
+
default: return 0x0;
381
+
}
382
+
}
383
+
384
+
static inline u32 AutoRstThHi(unsigned int fs)
385
+
{
386
+
switch (fs) {
387
+
case FS_8000HZ: return 0x36000;
388
+
case FS_11025HZ: return 0x27000;
389
+
case FS_12000HZ: return 0x24000;
390
+
case FS_16000HZ: return 0x1B000;
391
+
case FS_22050HZ: return 0x14000;
392
+
case FS_24000HZ: return 0x12000;
393
+
case FS_32000HZ: return 0x0D800;
394
+
case FS_44100HZ: return 0x09D00;
395
+
case FS_48000HZ: return 0x08E00;
396
+
case FS_88200HZ: return 0x04E00;
397
+
case FS_96000HZ: return 0x04800;
398
+
case FS_176400HZ: return 0x02700;
399
+
case FS_192000HZ: return 0x02400;
400
+
default: return 0x0;
401
+
}
402
+
}
403
+
404
+
static inline u32 AutoRstThLo(unsigned int fs)
405
+
{
406
+
switch (fs) {
407
+
case FS_8000HZ: return 0x30000;
408
+
case FS_11025HZ: return 0x23000;
409
+
case FS_12000HZ: return 0x20000;
410
+
case FS_16000HZ: return 0x18000;
411
+
case FS_22050HZ: return 0x11000;
412
+
case FS_24000HZ: return 0x0FE00;
413
+
case FS_32000HZ: return 0x0BE00;
414
+
case FS_44100HZ: return 0x08A00;
415
+
case FS_48000HZ: return 0x07F00;
416
+
case FS_88200HZ: return 0x04500;
417
+
case FS_96000HZ: return 0x04000;
418
+
case FS_176400HZ: return 0x02300;
419
+
case FS_192000HZ: return 0x02000;
420
+
default: return 0x0;
421
+
}
422
+
}
423
+
424
+
bool mt8365_afe_clk_group_48k(int sample_rate);
425
+
bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id);
426
+
bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id);
427
+
428
+
int mt8365_dai_i2s_register(struct mtk_base_afe *afe);
429
+
int mt8365_dai_set_priv(struct mtk_base_afe *afe,
430
+
int id,
431
+
int priv_size,
432
+
const void *priv_data);
433
+
434
+
int mt8365_afe_fs_timing(unsigned int rate);
435
+
436
+
void mt8365_afe_set_i2s_out_enable(struct mtk_base_afe *afe, bool enable);
437
+
int mt8365_afe_set_i2s_out(struct mtk_base_afe *afe, unsigned int rate, int bit_width);
438
+
439
+
int mt8365_dai_adda_register(struct mtk_base_afe *afe);
440
+
int mt8365_dai_enable_adda_on(struct mtk_base_afe *afe);
441
+
int mt8365_dai_disable_adda_on(struct mtk_base_afe *afe);
442
+
443
+
int mt8365_dai_dmic_register(struct mtk_base_afe *afe);
444
+
445
+
int mt8365_dai_pcm_register(struct mtk_base_afe *afe);
446
+
447
+
int mt8365_dai_tdm_register(struct mtk_base_afe *afe);
448
+
449
+
#endif
+2275
sound/soc/mediatek/mt8365/mt8365-afe-pcm.c
+2275
sound/soc/mediatek/mt8365/mt8365-afe-pcm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek 8365 ALSA SoC AFE platform driver
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#include <linux/delay.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_address.h>
14
+
#include <linux/dma-mapping.h>
15
+
#include <linux/pm_runtime.h>
16
+
#include <sound/soc.h>
17
+
#include <sound/pcm_params.h>
18
+
#include "mt8365-afe-common.h"
19
+
#include "mt8365-afe-clk.h"
20
+
#include "mt8365-reg.h"
21
+
#include "../common/mtk-base-afe.h"
22
+
#include "../common/mtk-afe-platform-driver.h"
23
+
#include "../common/mtk-afe-fe-dai.h"
24
+
25
+
#define AFE_BASE_END_OFFSET 8
26
+
27
+
static unsigned int mCM2Input;
28
+
29
+
static const unsigned int mt8365_afe_backup_list[] = {
30
+
AUDIO_TOP_CON0,
31
+
AFE_CONN0,
32
+
AFE_CONN1,
33
+
AFE_CONN3,
34
+
AFE_CONN4,
35
+
AFE_CONN5,
36
+
AFE_CONN6,
37
+
AFE_CONN7,
38
+
AFE_CONN8,
39
+
AFE_CONN9,
40
+
AFE_CONN10,
41
+
AFE_CONN11,
42
+
AFE_CONN12,
43
+
AFE_CONN13,
44
+
AFE_CONN14,
45
+
AFE_CONN15,
46
+
AFE_CONN16,
47
+
AFE_CONN17,
48
+
AFE_CONN18,
49
+
AFE_CONN19,
50
+
AFE_CONN20,
51
+
AFE_CONN21,
52
+
AFE_CONN26,
53
+
AFE_CONN27,
54
+
AFE_CONN28,
55
+
AFE_CONN29,
56
+
AFE_CONN30,
57
+
AFE_CONN31,
58
+
AFE_CONN32,
59
+
AFE_CONN33,
60
+
AFE_CONN34,
61
+
AFE_CONN35,
62
+
AFE_CONN36,
63
+
AFE_CONN_24BIT,
64
+
AFE_CONN_24BIT_1,
65
+
AFE_DAC_CON0,
66
+
AFE_DAC_CON1,
67
+
AFE_DL1_BASE,
68
+
AFE_DL1_END,
69
+
AFE_DL2_BASE,
70
+
AFE_DL2_END,
71
+
AFE_VUL_BASE,
72
+
AFE_VUL_END,
73
+
AFE_AWB_BASE,
74
+
AFE_AWB_END,
75
+
AFE_VUL3_BASE,
76
+
AFE_VUL3_END,
77
+
AFE_HDMI_OUT_BASE,
78
+
AFE_HDMI_OUT_END,
79
+
AFE_HDMI_IN_2CH_BASE,
80
+
AFE_HDMI_IN_2CH_END,
81
+
AFE_ADDA_UL_DL_CON0,
82
+
AFE_ADDA_DL_SRC2_CON0,
83
+
AFE_ADDA_DL_SRC2_CON1,
84
+
AFE_I2S_CON,
85
+
AFE_I2S_CON1,
86
+
AFE_I2S_CON2,
87
+
AFE_I2S_CON3,
88
+
AFE_ADDA_UL_SRC_CON0,
89
+
AFE_AUD_PAD_TOP,
90
+
AFE_HD_ENGEN_ENABLE,
91
+
};
92
+
93
+
static const struct snd_pcm_hardware mt8365_afe_hardware = {
94
+
.info = (SNDRV_PCM_INFO_MMAP |
95
+
SNDRV_PCM_INFO_INTERLEAVED |
96
+
SNDRV_PCM_INFO_MMAP_VALID),
97
+
.buffer_bytes_max = 256 * 1024,
98
+
.period_bytes_min = 512,
99
+
.period_bytes_max = 128 * 1024,
100
+
.periods_min = 2,
101
+
.periods_max = 256,
102
+
.fifo_size = 0,
103
+
};
104
+
105
+
struct mt8365_afe_rate {
106
+
unsigned int rate;
107
+
unsigned int reg_val;
108
+
};
109
+
110
+
static const struct mt8365_afe_rate mt8365_afe_fs_rates[] = {
111
+
{ .rate = 8000, .reg_val = MT8365_FS_8K },
112
+
{ .rate = 11025, .reg_val = MT8365_FS_11D025K },
113
+
{ .rate = 12000, .reg_val = MT8365_FS_12K },
114
+
{ .rate = 16000, .reg_val = MT8365_FS_16K },
115
+
{ .rate = 22050, .reg_val = MT8365_FS_22D05K },
116
+
{ .rate = 24000, .reg_val = MT8365_FS_24K },
117
+
{ .rate = 32000, .reg_val = MT8365_FS_32K },
118
+
{ .rate = 44100, .reg_val = MT8365_FS_44D1K },
119
+
{ .rate = 48000, .reg_val = MT8365_FS_48K },
120
+
{ .rate = 88200, .reg_val = MT8365_FS_88D2K },
121
+
{ .rate = 96000, .reg_val = MT8365_FS_96K },
122
+
{ .rate = 176400, .reg_val = MT8365_FS_176D4K },
123
+
{ .rate = 192000, .reg_val = MT8365_FS_192K },
124
+
};
125
+
126
+
int mt8365_afe_fs_timing(unsigned int rate)
127
+
{
128
+
int i;
129
+
130
+
for (i = 0; i < ARRAY_SIZE(mt8365_afe_fs_rates); i++)
131
+
if (mt8365_afe_fs_rates[i].rate == rate)
132
+
return mt8365_afe_fs_rates[i].reg_val;
133
+
134
+
return -EINVAL;
135
+
}
136
+
137
+
bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id)
138
+
{
139
+
switch (id) {
140
+
case MT8365_AFE_IO_TDM_IN:
141
+
if (rate >= 8000 && rate <= 192000)
142
+
return true;
143
+
break;
144
+
case MT8365_AFE_IO_DMIC:
145
+
if (rate >= 8000 && rate <= 48000)
146
+
return true;
147
+
break;
148
+
default:
149
+
break;
150
+
}
151
+
152
+
return false;
153
+
}
154
+
155
+
bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id)
156
+
{
157
+
switch (id) {
158
+
case MT8365_AFE_IO_TDM_IN:
159
+
if (channel >= 1 && channel <= 8)
160
+
return true;
161
+
break;
162
+
case MT8365_AFE_IO_DMIC:
163
+
if (channel >= 1 && channel <= 8)
164
+
return true;
165
+
break;
166
+
default:
167
+
break;
168
+
}
169
+
170
+
return false;
171
+
}
172
+
173
+
bool mt8365_afe_clk_group_44k(int sample_rate)
174
+
{
175
+
if (sample_rate == 11025 ||
176
+
sample_rate == 22050 ||
177
+
sample_rate == 44100 ||
178
+
sample_rate == 88200 ||
179
+
sample_rate == 176400)
180
+
return true;
181
+
else
182
+
return false;
183
+
}
184
+
185
+
bool mt8365_afe_clk_group_48k(int sample_rate)
186
+
{
187
+
return (!mt8365_afe_clk_group_44k(sample_rate));
188
+
}
189
+
190
+
int mt8365_dai_set_priv(struct mtk_base_afe *afe, int id,
191
+
int priv_size, const void *priv_data)
192
+
{
193
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
194
+
void *temp_data;
195
+
196
+
temp_data = devm_kzalloc(afe->dev, priv_size, GFP_KERNEL);
197
+
if (!temp_data)
198
+
return -ENOMEM;
199
+
200
+
if (priv_data)
201
+
memcpy(temp_data, priv_data, priv_size);
202
+
203
+
afe_priv->dai_priv[id] = temp_data;
204
+
205
+
return 0;
206
+
}
207
+
208
+
static int mt8365_afe_irq_direction_enable(struct mtk_base_afe *afe,
209
+
int irq_id, int direction)
210
+
{
211
+
struct mtk_base_afe_irq *irq;
212
+
213
+
if (irq_id >= MT8365_AFE_IRQ_NUM)
214
+
return -1;
215
+
216
+
irq = &afe->irqs[irq_id];
217
+
218
+
if (direction == MT8365_AFE_IRQ_DIR_MCU) {
219
+
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN,
220
+
(1 << irq->irq_data->irq_clr_shift),
221
+
0);
222
+
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN,
223
+
(1 << irq->irq_data->irq_clr_shift),
224
+
(1 << irq->irq_data->irq_clr_shift));
225
+
} else if (direction == MT8365_AFE_IRQ_DIR_DSP) {
226
+
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN,
227
+
(1 << irq->irq_data->irq_clr_shift),
228
+
(1 << irq->irq_data->irq_clr_shift));
229
+
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN,
230
+
(1 << irq->irq_data->irq_clr_shift),
231
+
0);
232
+
} else {
233
+
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN,
234
+
(1 << irq->irq_data->irq_clr_shift),
235
+
(1 << irq->irq_data->irq_clr_shift));
236
+
regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN,
237
+
(1 << irq->irq_data->irq_clr_shift),
238
+
(1 << irq->irq_data->irq_clr_shift));
239
+
}
240
+
return 0;
241
+
}
242
+
243
+
static int mt8365_memif_fs(struct snd_pcm_substream *substream,
244
+
unsigned int rate)
245
+
{
246
+
return mt8365_afe_fs_timing(rate);
247
+
}
248
+
249
+
static int mt8365_irq_fs(struct snd_pcm_substream *substream,
250
+
unsigned int rate)
251
+
{
252
+
return mt8365_memif_fs(substream, rate);
253
+
}
254
+
255
+
static const struct mt8365_cm_ctrl_reg cm_ctrl_reg[MT8365_CM_NUM] = {
256
+
[MT8365_CM1] = {
257
+
.con0 = AFE_CM1_CON0,
258
+
.con1 = AFE_CM1_CON1,
259
+
.con2 = AFE_CM1_CON2,
260
+
.con3 = AFE_CM1_CON3,
261
+
.con4 = AFE_CM1_CON4,
262
+
},
263
+
[MT8365_CM2] = {
264
+
.con0 = AFE_CM2_CON0,
265
+
.con1 = AFE_CM2_CON1,
266
+
.con2 = AFE_CM2_CON2,
267
+
.con3 = AFE_CM2_CON3,
268
+
.con4 = AFE_CM2_CON4,
269
+
}
270
+
};
271
+
272
+
static int mt8365_afe_cm2_mux_conn(struct mtk_base_afe *afe)
273
+
{
274
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
275
+
unsigned int input = afe_priv->cm2_mux_input;
276
+
277
+
/* TDM_IN interconnect to CM2 */
278
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
279
+
CM2_AFE_CM2_CONN_CFG1_MASK,
280
+
CM2_AFE_CM2_CONN_CFG1(TDM_IN_CH0));
281
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
282
+
CM2_AFE_CM2_CONN_CFG2_MASK,
283
+
CM2_AFE_CM2_CONN_CFG2(TDM_IN_CH1));
284
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
285
+
CM2_AFE_CM2_CONN_CFG3_MASK,
286
+
CM2_AFE_CM2_CONN_CFG3(TDM_IN_CH2));
287
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
288
+
CM2_AFE_CM2_CONN_CFG4_MASK,
289
+
CM2_AFE_CM2_CONN_CFG4(TDM_IN_CH3));
290
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
291
+
CM2_AFE_CM2_CONN_CFG5_MASK,
292
+
CM2_AFE_CM2_CONN_CFG5(TDM_IN_CH4));
293
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN0,
294
+
CM2_AFE_CM2_CONN_CFG6_MASK,
295
+
CM2_AFE_CM2_CONN_CFG6(TDM_IN_CH5));
296
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
297
+
CM2_AFE_CM2_CONN_CFG7_MASK,
298
+
CM2_AFE_CM2_CONN_CFG7(TDM_IN_CH6));
299
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
300
+
CM2_AFE_CM2_CONN_CFG8_MASK,
301
+
CM2_AFE_CM2_CONN_CFG8(TDM_IN_CH7));
302
+
303
+
/* ref data interconnect to CM2 */
304
+
if (input == MT8365_FROM_GASRC1) {
305
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
306
+
CM2_AFE_CM2_CONN_CFG9_MASK,
307
+
CM2_AFE_CM2_CONN_CFG9(GENERAL1_ASRC_OUT_LCH));
308
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
309
+
CM2_AFE_CM2_CONN_CFG10_MASK,
310
+
CM2_AFE_CM2_CONN_CFG10(GENERAL1_ASRC_OUT_RCH));
311
+
} else if (input == MT8365_FROM_GASRC2) {
312
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
313
+
CM2_AFE_CM2_CONN_CFG9_MASK,
314
+
CM2_AFE_CM2_CONN_CFG9(GENERAL2_ASRC_OUT_LCH));
315
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
316
+
CM2_AFE_CM2_CONN_CFG10_MASK,
317
+
CM2_AFE_CM2_CONN_CFG10(GENERAL2_ASRC_OUT_RCH));
318
+
} else if (input == MT8365_FROM_TDM_ASRC) {
319
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
320
+
CM2_AFE_CM2_CONN_CFG9_MASK,
321
+
CM2_AFE_CM2_CONN_CFG9(TDM_OUT_ASRC_CH0));
322
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
323
+
CM2_AFE_CM2_CONN_CFG10_MASK,
324
+
CM2_AFE_CM2_CONN_CFG10(TDM_OUT_ASRC_CH1));
325
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
326
+
CM2_AFE_CM2_CONN_CFG11_MASK,
327
+
CM2_AFE_CM2_CONN_CFG11(TDM_OUT_ASRC_CH2));
328
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN1,
329
+
CM2_AFE_CM2_CONN_CFG12_MASK,
330
+
CM2_AFE_CM2_CONN_CFG12(TDM_OUT_ASRC_CH3));
331
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
332
+
CM2_AFE_CM2_CONN_CFG13_MASK,
333
+
CM2_AFE_CM2_CONN_CFG13(TDM_OUT_ASRC_CH4));
334
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
335
+
CM2_AFE_CM2_CONN_CFG14_MASK,
336
+
CM2_AFE_CM2_CONN_CFG14(TDM_OUT_ASRC_CH5));
337
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
338
+
CM2_AFE_CM2_CONN_CFG15_MASK,
339
+
CM2_AFE_CM2_CONN_CFG15(TDM_OUT_ASRC_CH6));
340
+
regmap_update_bits(afe->regmap, AFE_CM2_CONN2,
341
+
CM2_AFE_CM2_CONN_CFG16_MASK,
342
+
CM2_AFE_CM2_CONN_CFG16(TDM_OUT_ASRC_CH7));
343
+
} else {
344
+
dev_err(afe->dev, "%s wrong CM2 input %d\n", __func__, input);
345
+
return -1;
346
+
}
347
+
348
+
return 0;
349
+
}
350
+
351
+
static int mt8365_afe_get_cm_update_cnt(struct mtk_base_afe *afe,
352
+
enum mt8365_cm_num cmNum,
353
+
unsigned int rate, unsigned int channel)
354
+
{
355
+
unsigned int total_cnt, div_cnt, ch_pair, best_cnt;
356
+
unsigned int ch_update_cnt[MT8365_CM_UPDATA_CNT_SET];
357
+
int i;
358
+
359
+
/* calculate cm update cnt
360
+
* total_cnt = clk / fs, clk is 26m or 24m or 22m
361
+
* div_cnt = total_cnt / ch_pair, max ch 16ch ,2ch is a set
362
+
* best_cnt < div_cnt ,we set best_cnt = div_cnt -10
363
+
* ch01 = best_cnt, ch23 = 2* ch01_up_cnt
364
+
* ch45 = 3* ch01_up_cnt ...ch1415 = 8* ch01_up_cnt
365
+
*/
366
+
367
+
if (cmNum == MT8365_CM1) {
368
+
total_cnt = MT8365_CLK_26M / rate;
369
+
} else if (cmNum == MT8365_CM2) {
370
+
if (mt8365_afe_clk_group_48k(rate))
371
+
total_cnt = MT8365_CLK_24M / rate;
372
+
else
373
+
total_cnt = MT8365_CLK_22M / rate;
374
+
} else {
375
+
return -1;
376
+
}
377
+
378
+
if (channel % 2)
379
+
ch_pair = (channel / 2) + 1;
380
+
else
381
+
ch_pair = channel / 2;
382
+
383
+
div_cnt = total_cnt / ch_pair;
384
+
best_cnt = div_cnt - 10;
385
+
386
+
if (best_cnt <= 0)
387
+
return -1;
388
+
389
+
for (i = 0; i < ch_pair; i++)
390
+
ch_update_cnt[i] = (i + 1) * best_cnt;
391
+
392
+
switch (channel) {
393
+
case 16:
394
+
fallthrough;
395
+
case 15:
396
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con4,
397
+
CM_AFE_CM_UPDATE_CNT2_MASK,
398
+
CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[7]));
399
+
fallthrough;
400
+
case 14:
401
+
fallthrough;
402
+
case 13:
403
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con4,
404
+
CM_AFE_CM_UPDATE_CNT1_MASK,
405
+
CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[6]));
406
+
fallthrough;
407
+
case 12:
408
+
fallthrough;
409
+
case 11:
410
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con3,
411
+
CM_AFE_CM_UPDATE_CNT2_MASK,
412
+
CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[5]));
413
+
fallthrough;
414
+
case 10:
415
+
fallthrough;
416
+
case 9:
417
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con3,
418
+
CM_AFE_CM_UPDATE_CNT1_MASK,
419
+
CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[4]));
420
+
fallthrough;
421
+
case 8:
422
+
fallthrough;
423
+
case 7:
424
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con2,
425
+
CM_AFE_CM_UPDATE_CNT2_MASK,
426
+
CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[3]));
427
+
fallthrough;
428
+
case 6:
429
+
fallthrough;
430
+
case 5:
431
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con2,
432
+
CM_AFE_CM_UPDATE_CNT1_MASK,
433
+
CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[2]));
434
+
fallthrough;
435
+
case 4:
436
+
fallthrough;
437
+
case 3:
438
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con1,
439
+
CM_AFE_CM_UPDATE_CNT2_MASK,
440
+
CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[1]));
441
+
fallthrough;
442
+
case 2:
443
+
fallthrough;
444
+
case 1:
445
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con1,
446
+
CM_AFE_CM_UPDATE_CNT1_MASK,
447
+
CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[0]));
448
+
break;
449
+
default:
450
+
return -1;
451
+
}
452
+
453
+
return 0;
454
+
}
455
+
456
+
static int mt8365_afe_configure_cm(struct mtk_base_afe *afe,
457
+
enum mt8365_cm_num cmNum,
458
+
unsigned int channels,
459
+
unsigned int rate)
460
+
{
461
+
unsigned int val, mask;
462
+
unsigned int fs = mt8365_afe_fs_timing(rate);
463
+
464
+
val = FIELD_PREP(CM_AFE_CM_CH_NUM_MASK, (channels - 1)) |
465
+
FIELD_PREP(CM_AFE_CM_START_DATA_MASK, 0);
466
+
467
+
mask = CM_AFE_CM_CH_NUM_MASK |
468
+
CM_AFE_CM_START_DATA_MASK;
469
+
470
+
if (cmNum == MT8365_CM1) {
471
+
val |= FIELD_PREP(CM_AFE_CM1_IN_MODE_MASK, fs);
472
+
473
+
mask |= CM_AFE_CM1_VUL_SEL |
474
+
CM_AFE_CM1_IN_MODE_MASK;
475
+
} else if (cmNum == MT8365_CM2) {
476
+
if (mt8365_afe_clk_group_48k(rate))
477
+
val |= FIELD_PREP(CM_AFE_CM2_CLK_SEL, 0);
478
+
else
479
+
val |= FIELD_PREP(CM_AFE_CM2_CLK_SEL, 1);
480
+
481
+
val |= FIELD_PREP(CM_AFE_CM2_TDM_SEL, 1);
482
+
483
+
mask |= CM_AFE_CM2_TDM_SEL |
484
+
CM_AFE_CM1_IN_MODE_MASK |
485
+
CM_AFE_CM2_CLK_SEL;
486
+
487
+
mt8365_afe_cm2_mux_conn(afe);
488
+
} else {
489
+
return -1;
490
+
}
491
+
492
+
regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con0, mask, val);
493
+
494
+
mt8365_afe_get_cm_update_cnt(afe, cmNum, rate, channels);
495
+
496
+
return 0;
497
+
}
498
+
499
+
int mt8365_afe_fe_startup(struct snd_pcm_substream *substream,
500
+
struct snd_soc_dai *dai)
501
+
{
502
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
503
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
504
+
struct snd_pcm_runtime *runtime = substream->runtime;
505
+
int memif_num = snd_soc_rtd_to_cpu(rtd, 0)->id;
506
+
struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
507
+
int ret;
508
+
509
+
memif->substream = substream;
510
+
511
+
snd_pcm_hw_constraint_step(substream->runtime, 0,
512
+
SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);
513
+
514
+
snd_soc_set_runtime_hwparams(substream, afe->mtk_afe_hardware);
515
+
516
+
ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
517
+
if (ret < 0)
518
+
dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
519
+
520
+
mt8365_afe_enable_main_clk(afe);
521
+
return ret;
522
+
}
523
+
524
+
static void mt8365_afe_fe_shutdown(struct snd_pcm_substream *substream,
525
+
struct snd_soc_dai *dai)
526
+
{
527
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
528
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
529
+
int memif_num = snd_soc_rtd_to_cpu(rtd, 0)->id;
530
+
struct mtk_base_afe_memif *memif = &afe->memif[memif_num];
531
+
532
+
memif->substream = NULL;
533
+
534
+
mt8365_afe_disable_main_clk(afe);
535
+
}
536
+
537
+
static int mt8365_afe_fe_hw_params(struct snd_pcm_substream *substream,
538
+
struct snd_pcm_hw_params *params,
539
+
struct snd_soc_dai *dai)
540
+
{
541
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
542
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
543
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
544
+
struct mt8365_control_data *ctrl_data = &afe_priv->ctrl_data;
545
+
int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
546
+
struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
547
+
struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id];
548
+
size_t request_size = params_buffer_bytes(params);
549
+
unsigned int channels = params_channels(params);
550
+
unsigned int rate = params_rate(params);
551
+
unsigned int base_end_offset = 8;
552
+
int ret, fs;
553
+
554
+
dev_info(afe->dev, "%s %s period = %d rate = %d channels = %d\n",
555
+
__func__, memif->data->name, params_period_size(params),
556
+
rate, channels);
557
+
558
+
if (dai_id == MT8365_AFE_MEMIF_VUL2) {
559
+
if (!ctrl_data->bypass_cm1)
560
+
/* configure cm1 */
561
+
mt8365_afe_configure_cm(afe, MT8365_CM1,
562
+
channels, rate);
563
+
else
564
+
regmap_update_bits(afe->regmap, AFE_CM1_CON0,
565
+
CM_AFE_CM1_VUL_SEL,
566
+
CM_AFE_CM1_VUL_SEL);
567
+
} else if (dai_id == MT8365_AFE_MEMIF_TDM_IN) {
568
+
if (!ctrl_data->bypass_cm2)
569
+
/* configure cm2 */
570
+
mt8365_afe_configure_cm(afe, MT8365_CM2,
571
+
channels, rate);
572
+
else
573
+
regmap_update_bits(afe->regmap, AFE_CM2_CON0,
574
+
CM_AFE_CM2_TDM_SEL,
575
+
~CM_AFE_CM2_TDM_SEL);
576
+
577
+
base_end_offset = 4;
578
+
}
579
+
580
+
if (request_size > fe_data->sram_size) {
581
+
ret = snd_pcm_lib_malloc_pages(substream, request_size);
582
+
if (ret < 0) {
583
+
dev_err(afe->dev,
584
+
"%s %s malloc pages %zu bytes failed %d\n",
585
+
__func__, memif->data->name, request_size, ret);
586
+
return ret;
587
+
}
588
+
589
+
fe_data->use_sram = false;
590
+
591
+
mt8365_afe_emi_clk_on(afe);
592
+
} else {
593
+
struct snd_dma_buffer *dma_buf = &substream->dma_buffer;
594
+
595
+
dma_buf->dev.type = SNDRV_DMA_TYPE_DEV;
596
+
dma_buf->dev.dev = substream->pcm->card->dev;
597
+
dma_buf->area = (unsigned char *)fe_data->sram_vir_addr;
598
+
dma_buf->addr = fe_data->sram_phy_addr;
599
+
dma_buf->bytes = request_size;
600
+
snd_pcm_set_runtime_buffer(substream, dma_buf);
601
+
602
+
fe_data->use_sram = true;
603
+
}
604
+
605
+
memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr);
606
+
memif->buffer_size = substream->runtime->dma_bytes;
607
+
608
+
/* start */
609
+
regmap_write(afe->regmap, memif->data->reg_ofs_base,
610
+
memif->phys_buf_addr);
611
+
/* end */
612
+
regmap_write(afe->regmap,
613
+
memif->data->reg_ofs_base + base_end_offset,
614
+
memif->phys_buf_addr + memif->buffer_size - 1);
615
+
616
+
/* set channel */
617
+
if (memif->data->mono_shift >= 0) {
618
+
unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
619
+
620
+
if (memif->data->mono_reg < 0)
621
+
dev_info(afe->dev, "%s mono_reg is NULL\n", __func__);
622
+
else
623
+
regmap_update_bits(afe->regmap, memif->data->mono_reg,
624
+
1 << memif->data->mono_shift,
625
+
mono << memif->data->mono_shift);
626
+
}
627
+
628
+
/* set rate */
629
+
if (memif->data->fs_shift < 0)
630
+
return 0;
631
+
632
+
fs = afe->memif_fs(substream, params_rate(params));
633
+
634
+
if (fs < 0)
635
+
return -EINVAL;
636
+
637
+
if (memif->data->fs_reg < 0)
638
+
dev_info(afe->dev, "%s fs_reg is NULL\n", __func__);
639
+
else
640
+
regmap_update_bits(afe->regmap, memif->data->fs_reg,
641
+
memif->data->fs_maskbit << memif->data->fs_shift,
642
+
fs << memif->data->fs_shift);
643
+
644
+
return 0;
645
+
}
646
+
647
+
static int mt8365_afe_fe_hw_free(struct snd_pcm_substream *substream,
648
+
struct snd_soc_dai *dai)
649
+
{
650
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
651
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
652
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
653
+
int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
654
+
struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
655
+
struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id];
656
+
int ret = 0;
657
+
658
+
if (fe_data->use_sram) {
659
+
snd_pcm_set_runtime_buffer(substream, NULL);
660
+
} else {
661
+
ret = snd_pcm_lib_free_pages(substream);
662
+
663
+
mt8365_afe_emi_clk_off(afe);
664
+
}
665
+
666
+
return ret;
667
+
}
668
+
669
+
static int mt8365_afe_fe_prepare(struct snd_pcm_substream *substream,
670
+
struct snd_soc_dai *dai)
671
+
{
672
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
673
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
674
+
int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
675
+
struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
676
+
677
+
/* set format */
678
+
if (memif->data->hd_reg >= 0) {
679
+
switch (substream->runtime->format) {
680
+
case SNDRV_PCM_FORMAT_S16_LE:
681
+
regmap_update_bits(afe->regmap, memif->data->hd_reg,
682
+
3 << memif->data->hd_shift,
683
+
0 << memif->data->hd_shift);
684
+
break;
685
+
case SNDRV_PCM_FORMAT_S32_LE:
686
+
regmap_update_bits(afe->regmap, memif->data->hd_reg,
687
+
3 << memif->data->hd_shift,
688
+
3 << memif->data->hd_shift);
689
+
690
+
if (dai_id == MT8365_AFE_MEMIF_TDM_IN) {
691
+
regmap_update_bits(afe->regmap,
692
+
memif->data->hd_reg,
693
+
3 << memif->data->hd_shift,
694
+
1 << memif->data->hd_shift);
695
+
regmap_update_bits(afe->regmap,
696
+
memif->data->hd_reg,
697
+
1 << memif->data->hd_align_mshift,
698
+
1 << memif->data->hd_align_mshift);
699
+
}
700
+
break;
701
+
case SNDRV_PCM_FORMAT_S24_LE:
702
+
regmap_update_bits(afe->regmap, memif->data->hd_reg,
703
+
3 << memif->data->hd_shift,
704
+
1 << memif->data->hd_shift);
705
+
break;
706
+
default:
707
+
return -EINVAL;
708
+
}
709
+
}
710
+
711
+
mt8365_afe_irq_direction_enable(afe, memif->irq_usage,
712
+
MT8365_AFE_IRQ_DIR_MCU);
713
+
714
+
return 0;
715
+
}
716
+
717
+
int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
718
+
struct snd_soc_dai *dai)
719
+
{
720
+
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
721
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
722
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
723
+
int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
724
+
struct mt8365_control_data *ctrl_data = &afe_priv->ctrl_data;
725
+
726
+
switch (cmd) {
727
+
case SNDRV_PCM_TRIGGER_START:
728
+
case SNDRV_PCM_TRIGGER_RESUME:
729
+
/* enable channel merge */
730
+
if (dai_id == MT8365_AFE_MEMIF_VUL2 &&
731
+
!ctrl_data->bypass_cm1) {
732
+
regmap_update_bits(afe->regmap, AFE_CM1_CON0,
733
+
CM_AFE_CM_ON, CM_AFE_CM_ON);
734
+
} else if (dai_id == MT8365_AFE_MEMIF_TDM_IN &&
735
+
!ctrl_data->bypass_cm2) {
736
+
regmap_update_bits(afe->regmap, AFE_CM2_CON0,
737
+
CM_AFE_CM_ON, CM_AFE_CM_ON);
738
+
}
739
+
break;
740
+
case SNDRV_PCM_TRIGGER_STOP:
741
+
case SNDRV_PCM_TRIGGER_SUSPEND:
742
+
/* disable channel merge */
743
+
if (dai_id == MT8365_AFE_MEMIF_VUL2 &&
744
+
!ctrl_data->bypass_cm1) {
745
+
regmap_update_bits(afe->regmap, AFE_CM1_CON0,
746
+
CM_AFE_CM_ON, ~CM_AFE_CM_ON);
747
+
} else if (dai_id == MT8365_AFE_MEMIF_TDM_IN &&
748
+
!ctrl_data->bypass_cm2) {
749
+
regmap_update_bits(afe->regmap, AFE_CM2_CON0,
750
+
CM_AFE_CM_ON, ~CM_AFE_CM_ON);
751
+
}
752
+
break;
753
+
default:
754
+
break;
755
+
}
756
+
757
+
return mtk_afe_fe_trigger(substream, cmd, dai);
758
+
}
759
+
760
+
static int mt8365_afe_hw_gain1_startup(struct snd_pcm_substream *substream,
761
+
struct snd_soc_dai *dai)
762
+
{
763
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
764
+
765
+
mt8365_afe_enable_main_clk(afe);
766
+
return 0;
767
+
}
768
+
769
+
static void mt8365_afe_hw_gain1_shutdown(struct snd_pcm_substream *substream,
770
+
struct snd_soc_dai *dai)
771
+
{
772
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
773
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
774
+
struct mt8365_be_dai_data *be =
775
+
&afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
776
+
777
+
if (be->prepared[substream->stream]) {
778
+
regmap_update_bits(afe->regmap, AFE_GAIN1_CON0,
779
+
AFE_GAIN1_CON0_EN_MASK, 0);
780
+
be->prepared[substream->stream] = false;
781
+
}
782
+
mt8365_afe_disable_main_clk(afe);
783
+
}
784
+
785
+
static int mt8365_afe_hw_gain1_prepare(struct snd_pcm_substream *substream,
786
+
struct snd_soc_dai *dai)
787
+
{
788
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
789
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
790
+
struct mt8365_be_dai_data *be =
791
+
&afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
792
+
793
+
int fs;
794
+
unsigned int val1 = 0, val2 = 0;
795
+
796
+
if (be->prepared[substream->stream]) {
797
+
dev_info(afe->dev, "%s prepared already\n", __func__);
798
+
return 0;
799
+
}
800
+
801
+
fs = mt8365_afe_fs_timing(substream->runtime->rate);
802
+
regmap_update_bits(afe->regmap, AFE_GAIN1_CON0,
803
+
AFE_GAIN1_CON0_MODE_MASK, (unsigned int)fs << 4);
804
+
805
+
regmap_read(afe->regmap, AFE_GAIN1_CON1, &val1);
806
+
regmap_read(afe->regmap, AFE_GAIN1_CUR, &val2);
807
+
if ((val1 & AFE_GAIN1_CON1_MASK) != (val2 & AFE_GAIN1_CUR_MASK))
808
+
regmap_update_bits(afe->regmap, AFE_GAIN1_CUR,
809
+
AFE_GAIN1_CUR_MASK, val1);
810
+
811
+
regmap_update_bits(afe->regmap, AFE_GAIN1_CON0,
812
+
AFE_GAIN1_CON0_EN_MASK, 1);
813
+
be->prepared[substream->stream] = true;
814
+
815
+
return 0;
816
+
}
817
+
818
+
static const struct snd_pcm_hardware mt8365_hostless_hardware = {
819
+
.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
820
+
SNDRV_PCM_INFO_MMAP_VALID),
821
+
.period_bytes_min = 256,
822
+
.period_bytes_max = 4 * 48 * 1024,
823
+
.periods_min = 2,
824
+
.periods_max = 256,
825
+
.buffer_bytes_max = 8 * 48 * 1024,
826
+
.fifo_size = 0,
827
+
};
828
+
829
+
/* dai ops */
830
+
static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
831
+
struct snd_soc_dai *dai)
832
+
{
833
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
834
+
struct snd_pcm_runtime *runtime = substream->runtime;
835
+
int ret;
836
+
837
+
snd_soc_set_runtime_hwparams(substream, &mt8365_hostless_hardware);
838
+
839
+
ret = snd_pcm_hw_constraint_integer(runtime,
840
+
SNDRV_PCM_HW_PARAM_PERIODS);
841
+
if (ret < 0)
842
+
dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
843
+
return ret;
844
+
}
845
+
846
+
/* FE DAIs */
847
+
static const struct snd_soc_dai_ops mt8365_afe_fe_dai_ops = {
848
+
.startup = mt8365_afe_fe_startup,
849
+
.shutdown = mt8365_afe_fe_shutdown,
850
+
.hw_params = mt8365_afe_fe_hw_params,
851
+
.hw_free = mt8365_afe_fe_hw_free,
852
+
.prepare = mt8365_afe_fe_prepare,
853
+
.trigger = mt8365_afe_fe_trigger,
854
+
};
855
+
856
+
static const struct snd_soc_dai_ops mt8365_dai_hostless_ops = {
857
+
.startup = mtk_dai_hostless_startup,
858
+
};
859
+
860
+
static const struct snd_soc_dai_ops mt8365_afe_hw_gain1_ops = {
861
+
.startup = mt8365_afe_hw_gain1_startup,
862
+
.shutdown = mt8365_afe_hw_gain1_shutdown,
863
+
.prepare = mt8365_afe_hw_gain1_prepare,
864
+
};
865
+
866
+
static struct snd_soc_dai_driver mt8365_memif_dai_driver[] = {
867
+
/* FE DAIs: memory intefaces to CPU */
868
+
{
869
+
.name = "DL1",
870
+
.id = MT8365_AFE_MEMIF_DL1,
871
+
.playback = {
872
+
.stream_name = "DL1",
873
+
.channels_min = 1,
874
+
.channels_max = 2,
875
+
.rates = SNDRV_PCM_RATE_8000_192000,
876
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
877
+
SNDRV_PCM_FMTBIT_S32_LE,
878
+
},
879
+
.ops = &mt8365_afe_fe_dai_ops,
880
+
}, {
881
+
.name = "DL2",
882
+
.id = MT8365_AFE_MEMIF_DL2,
883
+
.playback = {
884
+
.stream_name = "DL2",
885
+
.channels_min = 1,
886
+
.channels_max = 2,
887
+
.rates = SNDRV_PCM_RATE_8000_192000,
888
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
889
+
SNDRV_PCM_FMTBIT_S32_LE,
890
+
},
891
+
.ops = &mt8365_afe_fe_dai_ops,
892
+
}, {
893
+
.name = "TDM_OUT",
894
+
.id = MT8365_AFE_MEMIF_TDM_OUT,
895
+
.playback = {
896
+
.stream_name = "TDM_OUT",
897
+
.channels_min = 1,
898
+
.channels_max = 8,
899
+
.rates = SNDRV_PCM_RATE_8000_192000,
900
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
901
+
SNDRV_PCM_FMTBIT_S32_LE,
902
+
},
903
+
.ops = &mt8365_afe_fe_dai_ops,
904
+
}, {
905
+
.name = "AWB",
906
+
.id = MT8365_AFE_MEMIF_AWB,
907
+
.capture = {
908
+
.stream_name = "AWB",
909
+
.channels_min = 1,
910
+
.channels_max = 2,
911
+
.rates = SNDRV_PCM_RATE_8000_192000,
912
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
913
+
SNDRV_PCM_FMTBIT_S32_LE,
914
+
},
915
+
.ops = &mt8365_afe_fe_dai_ops,
916
+
}, {
917
+
.name = "VUL",
918
+
.id = MT8365_AFE_MEMIF_VUL,
919
+
.capture = {
920
+
.stream_name = "VUL",
921
+
.channels_min = 1,
922
+
.channels_max = 2,
923
+
.rates = SNDRV_PCM_RATE_8000_192000,
924
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
925
+
SNDRV_PCM_FMTBIT_S32_LE,
926
+
},
927
+
.ops = &mt8365_afe_fe_dai_ops,
928
+
}, {
929
+
.name = "VUL2",
930
+
.id = MT8365_AFE_MEMIF_VUL2,
931
+
.capture = {
932
+
.stream_name = "VUL2",
933
+
.channels_min = 1,
934
+
.channels_max = 16,
935
+
.rates = SNDRV_PCM_RATE_8000_192000,
936
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
937
+
SNDRV_PCM_FMTBIT_S32_LE,
938
+
},
939
+
.ops = &mt8365_afe_fe_dai_ops,
940
+
}, {
941
+
.name = "VUL3",
942
+
.id = MT8365_AFE_MEMIF_VUL3,
943
+
.capture = {
944
+
.stream_name = "VUL3",
945
+
.channels_min = 1,
946
+
.channels_max = 2,
947
+
.rates = SNDRV_PCM_RATE_8000_192000,
948
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
949
+
SNDRV_PCM_FMTBIT_S32_LE,
950
+
},
951
+
.ops = &mt8365_afe_fe_dai_ops,
952
+
}, {
953
+
.name = "TDM_IN",
954
+
.id = MT8365_AFE_MEMIF_TDM_IN,
955
+
.capture = {
956
+
.stream_name = "TDM_IN",
957
+
.channels_min = 1,
958
+
.channels_max = 16,
959
+
.rates = SNDRV_PCM_RATE_8000_192000,
960
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
961
+
SNDRV_PCM_FMTBIT_S32_LE,
962
+
},
963
+
.ops = &mt8365_afe_fe_dai_ops,
964
+
}, {
965
+
.name = "Hostless FM DAI",
966
+
.id = MT8365_AFE_IO_VIRTUAL_FM,
967
+
.playback = {
968
+
.stream_name = "Hostless FM DL",
969
+
.channels_min = 1,
970
+
.channels_max = 2,
971
+
.rates = SNDRV_PCM_RATE_8000_192000,
972
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
973
+
SNDRV_PCM_FMTBIT_S24_LE |
974
+
SNDRV_PCM_FMTBIT_S32_LE,
975
+
},
976
+
.capture = {
977
+
.stream_name = "Hostless FM UL",
978
+
.channels_min = 1,
979
+
.channels_max = 2,
980
+
.rates = SNDRV_PCM_RATE_8000_192000,
981
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
982
+
SNDRV_PCM_FMTBIT_S24_LE |
983
+
SNDRV_PCM_FMTBIT_S32_LE,
984
+
},
985
+
.ops = &mt8365_dai_hostless_ops,
986
+
}, {
987
+
.name = "HW_GAIN1",
988
+
.id = MT8365_AFE_IO_HW_GAIN1,
989
+
.playback = {
990
+
.stream_name = "HW Gain 1 In",
991
+
.channels_min = 1,
992
+
.channels_max = 2,
993
+
.rates = SNDRV_PCM_RATE_8000_192000,
994
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
995
+
SNDRV_PCM_FMTBIT_S24_LE |
996
+
SNDRV_PCM_FMTBIT_S32_LE,
997
+
},
998
+
.capture = {
999
+
.stream_name = "HW Gain 1 Out",
1000
+
.channels_min = 1,
1001
+
.channels_max = 2,
1002
+
.rates = SNDRV_PCM_RATE_8000_192000,
1003
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
1004
+
SNDRV_PCM_FMTBIT_S24_LE |
1005
+
SNDRV_PCM_FMTBIT_S32_LE,
1006
+
},
1007
+
.ops = &mt8365_afe_hw_gain1_ops,
1008
+
.symmetric_rate = 1,
1009
+
.symmetric_channels = 1,
1010
+
.symmetric_sample_bits = 1,
1011
+
},
1012
+
};
1013
+
1014
+
static const struct snd_kcontrol_new mt8365_afe_o00_mix[] = {
1015
+
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN0, 5, 1, 0),
1016
+
SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN0, 7, 1, 0),
1017
+
};
1018
+
1019
+
static const struct snd_kcontrol_new mt8365_afe_o01_mix[] = {
1020
+
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN1, 6, 1, 0),
1021
+
SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN1, 8, 1, 0),
1022
+
};
1023
+
1024
+
static const struct snd_kcontrol_new mt8365_afe_o03_mix[] = {
1025
+
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN3, 5, 1, 0),
1026
+
SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN3, 7, 1, 0),
1027
+
SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN3, 0, 1, 0),
1028
+
SOC_DAPM_SINGLE_AUTODISABLE("I10 Switch", AFE_CONN3, 10, 1, 0),
1029
+
};
1030
+
1031
+
static const struct snd_kcontrol_new mt8365_afe_o04_mix[] = {
1032
+
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN4, 6, 1, 0),
1033
+
SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN4, 8, 1, 0),
1034
+
SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN4, 1, 1, 0),
1035
+
SOC_DAPM_SINGLE_AUTODISABLE("I11 Switch", AFE_CONN4, 11, 1, 0),
1036
+
};
1037
+
1038
+
static const struct snd_kcontrol_new mt8365_afe_o05_mix[] = {
1039
+
SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN5, 0, 1, 0),
1040
+
SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN5, 3, 1, 0),
1041
+
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN5, 5, 1, 0),
1042
+
SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN5, 7, 1, 0),
1043
+
SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN5, 9, 1, 0),
1044
+
SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN5, 14, 1, 0),
1045
+
SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN5, 16, 1, 0),
1046
+
SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN5, 18, 1, 0),
1047
+
SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN5, 20, 1, 0),
1048
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN5, 23, 1, 0),
1049
+
SOC_DAPM_SINGLE_AUTODISABLE("I10L Switch", AFE_CONN5, 10, 1, 0),
1050
+
};
1051
+
1052
+
static const struct snd_kcontrol_new mt8365_afe_o06_mix[] = {
1053
+
SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN6, 1, 1, 0),
1054
+
SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN6, 4, 1, 0),
1055
+
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN6, 6, 1, 0),
1056
+
SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN6, 8, 1, 0),
1057
+
SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN6, 22, 1, 0),
1058
+
SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN6, 15, 1, 0),
1059
+
SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN6, 17, 1, 0),
1060
+
SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN6, 19, 1, 0),
1061
+
SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN6, 21, 1, 0),
1062
+
SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN6, 24, 1, 0),
1063
+
SOC_DAPM_SINGLE_AUTODISABLE("I11L Switch", AFE_CONN6, 11, 1, 0),
1064
+
};
1065
+
1066
+
static const struct snd_kcontrol_new mt8365_afe_o07_mix[] = {
1067
+
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN7, 5, 1, 0),
1068
+
SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN7, 7, 1, 0),
1069
+
};
1070
+
1071
+
static const struct snd_kcontrol_new mt8365_afe_o08_mix[] = {
1072
+
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN8, 6, 1, 0),
1073
+
SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN8, 8, 1, 0),
1074
+
};
1075
+
1076
+
static const struct snd_kcontrol_new mt8365_afe_o09_mix[] = {
1077
+
SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN9, 0, 1, 0),
1078
+
SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN9, 3, 1, 0),
1079
+
SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN9, 9, 1, 0),
1080
+
SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN9, 14, 1, 0),
1081
+
SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN9, 16, 1, 0),
1082
+
SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN9, 18, 1, 0),
1083
+
SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN9, 20, 1, 0),
1084
+
};
1085
+
1086
+
static const struct snd_kcontrol_new mt8365_afe_o10_mix[] = {
1087
+
SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN10, 1, 1, 0),
1088
+
SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN10, 4, 1, 0),
1089
+
SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN10, 22, 1, 0),
1090
+
SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN10, 15, 1, 0),
1091
+
SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN10, 17, 1, 0),
1092
+
SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN10, 19, 1, 0),
1093
+
SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN10, 21, 1, 0),
1094
+
};
1095
+
1096
+
static const struct snd_kcontrol_new mt8365_afe_o11_mix[] = {
1097
+
SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN11, 0, 1, 0),
1098
+
SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN11, 3, 1, 0),
1099
+
SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN11, 9, 1, 0),
1100
+
SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN11, 14, 1, 0),
1101
+
SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN11, 16, 1, 0),
1102
+
SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN11, 18, 1, 0),
1103
+
SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN11, 20, 1, 0),
1104
+
};
1105
+
1106
+
static const struct snd_kcontrol_new mt8365_afe_o12_mix[] = {
1107
+
SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN12, 1, 1, 0),
1108
+
SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN12, 4, 1, 0),
1109
+
SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN12, 22, 1, 0),
1110
+
SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN12, 15, 1, 0),
1111
+
SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN12, 17, 1, 0),
1112
+
SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN12, 19, 1, 0),
1113
+
SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN12, 21, 1, 0),
1114
+
};
1115
+
1116
+
static const struct snd_kcontrol_new mt8365_afe_o13_mix[] = {
1117
+
SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN13, 0, 1, 0),
1118
+
};
1119
+
1120
+
static const struct snd_kcontrol_new mt8365_afe_o14_mix[] = {
1121
+
SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN14, 1, 1, 0),
1122
+
};
1123
+
1124
+
static const struct snd_kcontrol_new mt8365_afe_o15_mix[] = {
1125
+
};
1126
+
1127
+
static const struct snd_kcontrol_new mt8365_afe_o16_mix[] = {
1128
+
};
1129
+
1130
+
static const struct snd_kcontrol_new mt8365_afe_o17_mix[] = {
1131
+
SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN17, 3, 1, 0),
1132
+
SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0),
1133
+
};
1134
+
1135
+
static const struct snd_kcontrol_new mt8365_afe_o18_mix[] = {
1136
+
SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN18, 4, 1, 0),
1137
+
SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0),
1138
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN18, 23, 1, 0),
1139
+
SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN18, 25, 1, 0),
1140
+
};
1141
+
1142
+
static const struct snd_kcontrol_new mt8365_afe_o19_mix[] = {
1143
+
SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN19, 4, 1, 0),
1144
+
SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0),
1145
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN19, 23, 1, 0),
1146
+
SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN19, 24, 1, 0),
1147
+
SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN19, 25, 1, 0),
1148
+
SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN19, 26, 1, 0),
1149
+
};
1150
+
1151
+
static const struct snd_kcontrol_new mt8365_afe_o20_mix[] = {
1152
+
SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0),
1153
+
SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN20, 24, 1, 0),
1154
+
SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN20, 26, 1, 0),
1155
+
};
1156
+
1157
+
static const struct snd_kcontrol_new mt8365_afe_o21_mix[] = {
1158
+
SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0),
1159
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN21, 23, 1, 0),
1160
+
SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN21, 25, 1, 0),
1161
+
};
1162
+
1163
+
static const struct snd_kcontrol_new mt8365_afe_o22_mix[] = {
1164
+
SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0),
1165
+
SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN22, 24, 1, 0),
1166
+
SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN22, 26, 1, 0),
1167
+
};
1168
+
1169
+
static const struct snd_kcontrol_new mt8365_afe_o23_mix[] = {
1170
+
SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0),
1171
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN23, 23, 1, 0),
1172
+
SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN23, 25, 1, 0),
1173
+
};
1174
+
1175
+
static const struct snd_kcontrol_new mt8365_afe_o24_mix[] = {
1176
+
SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0),
1177
+
SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN24, 24, 1, 0),
1178
+
SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN24, 26, 1, 0),
1179
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN24, 23, 1, 0),
1180
+
SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN24, 25, 1, 0),
1181
+
};
1182
+
1183
+
static const struct snd_kcontrol_new mt8365_afe_o25_mix[] = {
1184
+
SOC_DAPM_SINGLE_AUTODISABLE("I27 Switch", AFE_CONN25, 27, 1, 0),
1185
+
SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN25, 23, 1, 0),
1186
+
SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN25, 25, 1, 0),
1187
+
};
1188
+
1189
+
static const struct snd_kcontrol_new mt8365_afe_o26_mix[] = {
1190
+
SOC_DAPM_SINGLE_AUTODISABLE("I28 Switch", AFE_CONN26, 28, 1, 0),
1191
+
SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN26, 24, 1, 0),
1192
+
SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN26, 26, 1, 0),
1193
+
};
1194
+
1195
+
static const struct snd_kcontrol_new mt8365_afe_o27_mix[] = {
1196
+
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN27, 5, 1, 0),
1197
+
SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN27, 7, 1, 0),
1198
+
};
1199
+
1200
+
static const struct snd_kcontrol_new mt8365_afe_o28_mix[] = {
1201
+
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN28, 6, 1, 0),
1202
+
SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN28, 8, 1, 0),
1203
+
};
1204
+
1205
+
static const struct snd_kcontrol_new mt8365_afe_o29_mix[] = {
1206
+
SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN29, 5, 1, 0),
1207
+
SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN29, 7, 1, 0),
1208
+
};
1209
+
1210
+
static const struct snd_kcontrol_new mt8365_afe_o30_mix[] = {
1211
+
SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN30, 6, 1, 0),
1212
+
SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN30, 8, 1, 0),
1213
+
};
1214
+
1215
+
static const struct snd_kcontrol_new mt8365_afe_o31_mix[] = {
1216
+
SOC_DAPM_SINGLE_AUTODISABLE("I29 Switch", AFE_CONN31, 29, 1, 0),
1217
+
};
1218
+
1219
+
static const struct snd_kcontrol_new mt8365_afe_o32_mix[] = {
1220
+
SOC_DAPM_SINGLE_AUTODISABLE("I30 Switch", AFE_CONN32, 30, 1, 0),
1221
+
};
1222
+
1223
+
static const struct snd_kcontrol_new mt8365_afe_o33_mix[] = {
1224
+
SOC_DAPM_SINGLE_AUTODISABLE("I31 Switch", AFE_CONN33, 31, 1, 0),
1225
+
};
1226
+
1227
+
static const struct snd_kcontrol_new mt8365_afe_o34_mix[] = {
1228
+
SOC_DAPM_SINGLE_AUTODISABLE("I32 Switch", AFE_CONN34_1, 0, 1, 0),
1229
+
};
1230
+
1231
+
static const struct snd_kcontrol_new mt8365_afe_o35_mix[] = {
1232
+
SOC_DAPM_SINGLE_AUTODISABLE("I33 Switch", AFE_CONN35_1, 1, 1, 0),
1233
+
};
1234
+
1235
+
static const struct snd_kcontrol_new mt8365_afe_o36_mix[] = {
1236
+
SOC_DAPM_SINGLE_AUTODISABLE("I34 Switch", AFE_CONN36_1, 2, 1, 0),
1237
+
};
1238
+
1239
+
static const struct snd_kcontrol_new mtk_hw_gain1_in_ch1_mix[] = {
1240
+
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN13,
1241
+
0, 1, 0),
1242
+
};
1243
+
1244
+
static const struct snd_kcontrol_new mtk_hw_gain1_in_ch2_mix[] = {
1245
+
SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN14,
1246
+
1, 1, 0),
1247
+
};
1248
+
1249
+
static int mt8365_afe_cm2_io_input_mux_get(struct snd_kcontrol *kcontrol,
1250
+
struct snd_ctl_elem_value *ucontrol)
1251
+
{
1252
+
ucontrol->value.integer.value[0] = mCM2Input;
1253
+
1254
+
return 0;
1255
+
}
1256
+
1257
+
static int mt8365_afe_cm2_io_input_mux_put(struct snd_kcontrol *kcontrol,
1258
+
struct snd_ctl_elem_value *ucontrol)
1259
+
{
1260
+
struct snd_soc_dapm_context *dapm =
1261
+
snd_soc_dapm_kcontrol_dapm(kcontrol);
1262
+
struct snd_soc_component *comp = snd_soc_dapm_to_component(dapm);
1263
+
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(comp);
1264
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
1265
+
int ret;
1266
+
1267
+
mCM2Input = ucontrol->value.enumerated.item[0];
1268
+
1269
+
afe_priv->cm2_mux_input = mCM2Input;
1270
+
ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1271
+
1272
+
return ret;
1273
+
}
1274
+
1275
+
static const char * const fmhwgain_text[] = {
1276
+
"OPEN", "FM_HW_GAIN_IO"
1277
+
};
1278
+
1279
+
static const char * const ain_text[] = {
1280
+
"INT ADC", "EXT ADC",
1281
+
};
1282
+
1283
+
static const char * const vul2_in_input_text[] = {
1284
+
"VUL2_IN_FROM_O17O18", "VUL2_IN_FROM_CM1",
1285
+
};
1286
+
1287
+
static const char * const mt8365_afe_cm2_mux_text[] = {
1288
+
"OPEN", "FROM_GASRC1_OUT", "FROM_GASRC2_OUT", "FROM_TDM_ASRC_OUT",
1289
+
};
1290
+
1291
+
static SOC_ENUM_SINGLE_VIRT_DECL(fmhwgain_enum, fmhwgain_text);
1292
+
static SOC_ENUM_SINGLE_DECL(ain_enum, AFE_ADDA_TOP_CON0, 0, ain_text);
1293
+
static SOC_ENUM_SINGLE_VIRT_DECL(vul2_in_input_enum, vul2_in_input_text);
1294
+
static SOC_ENUM_SINGLE_VIRT_DECL(mt8365_afe_cm2_mux_input_enum,
1295
+
mt8365_afe_cm2_mux_text);
1296
+
1297
+
static const struct snd_kcontrol_new fmhwgain_mux =
1298
+
SOC_DAPM_ENUM("FM HW Gain Source", fmhwgain_enum);
1299
+
1300
+
static const struct snd_kcontrol_new ain_mux =
1301
+
SOC_DAPM_ENUM("AIN Source", ain_enum);
1302
+
1303
+
static const struct snd_kcontrol_new vul2_in_input_mux =
1304
+
SOC_DAPM_ENUM("VUL2 Input", vul2_in_input_enum);
1305
+
1306
+
static const struct snd_kcontrol_new mt8365_afe_cm2_mux_input_mux =
1307
+
SOC_DAPM_ENUM_EXT("CM2_MUX Source", mt8365_afe_cm2_mux_input_enum,
1308
+
mt8365_afe_cm2_io_input_mux_get,
1309
+
mt8365_afe_cm2_io_input_mux_put);
1310
+
1311
+
static const struct snd_soc_dapm_widget mt8365_memif_widgets[] = {
1312
+
/* inter-connections */
1313
+
SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
1314
+
SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0),
1315
+
SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0),
1316
+
SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0),
1317
+
SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
1318
+
SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
1319
+
SND_SOC_DAPM_MIXER("I07", SND_SOC_NOPM, 0, 0, NULL, 0),
1320
+
SND_SOC_DAPM_MIXER("I08", SND_SOC_NOPM, 0, 0, NULL, 0),
1321
+
SND_SOC_DAPM_MIXER("I05L", SND_SOC_NOPM, 0, 0, NULL, 0),
1322
+
SND_SOC_DAPM_MIXER("I06L", SND_SOC_NOPM, 0, 0, NULL, 0),
1323
+
SND_SOC_DAPM_MIXER("I07L", SND_SOC_NOPM, 0, 0, NULL, 0),
1324
+
SND_SOC_DAPM_MIXER("I08L", SND_SOC_NOPM, 0, 0, NULL, 0),
1325
+
SND_SOC_DAPM_MIXER("I09", SND_SOC_NOPM, 0, 0, NULL, 0),
1326
+
SND_SOC_DAPM_MIXER("I10", SND_SOC_NOPM, 0, 0, NULL, 0),
1327
+
SND_SOC_DAPM_MIXER("I11", SND_SOC_NOPM, 0, 0, NULL, 0),
1328
+
SND_SOC_DAPM_MIXER("I10L", SND_SOC_NOPM, 0, 0, NULL, 0),
1329
+
SND_SOC_DAPM_MIXER("I11L", SND_SOC_NOPM, 0, 0, NULL, 0),
1330
+
SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0),
1331
+
SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0),
1332
+
SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0),
1333
+
SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0),
1334
+
SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0),
1335
+
SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
1336
+
SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
1337
+
SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0),
1338
+
SND_SOC_DAPM_MIXER("I20", SND_SOC_NOPM, 0, 0, NULL, 0),
1339
+
SND_SOC_DAPM_MIXER("I21", SND_SOC_NOPM, 0, 0, NULL, 0),
1340
+
SND_SOC_DAPM_MIXER("I22", SND_SOC_NOPM, 0, 0, NULL, 0),
1341
+
SND_SOC_DAPM_MIXER("I23", SND_SOC_NOPM, 0, 0, NULL, 0),
1342
+
SND_SOC_DAPM_MIXER("I24", SND_SOC_NOPM, 0, 0, NULL, 0),
1343
+
SND_SOC_DAPM_MIXER("I25", SND_SOC_NOPM, 0, 0, NULL, 0),
1344
+
SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0),
1345
+
SND_SOC_DAPM_MIXER("I27", SND_SOC_NOPM, 0, 0, NULL, 0),
1346
+
SND_SOC_DAPM_MIXER("I28", SND_SOC_NOPM, 0, 0, NULL, 0),
1347
+
SND_SOC_DAPM_MIXER("I29", SND_SOC_NOPM, 0, 0, NULL, 0),
1348
+
SND_SOC_DAPM_MIXER("I30", SND_SOC_NOPM, 0, 0, NULL, 0),
1349
+
SND_SOC_DAPM_MIXER("I31", SND_SOC_NOPM, 0, 0, NULL, 0),
1350
+
SND_SOC_DAPM_MIXER("I32", SND_SOC_NOPM, 0, 0, NULL, 0),
1351
+
SND_SOC_DAPM_MIXER("I33", SND_SOC_NOPM, 0, 0, NULL, 0),
1352
+
SND_SOC_DAPM_MIXER("I34", SND_SOC_NOPM, 0, 0, NULL, 0),
1353
+
SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0,
1354
+
mt8365_afe_o00_mix, ARRAY_SIZE(mt8365_afe_o00_mix)),
1355
+
SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0,
1356
+
mt8365_afe_o01_mix, ARRAY_SIZE(mt8365_afe_o01_mix)),
1357
+
SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
1358
+
mt8365_afe_o03_mix, ARRAY_SIZE(mt8365_afe_o03_mix)),
1359
+
SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
1360
+
mt8365_afe_o04_mix, ARRAY_SIZE(mt8365_afe_o04_mix)),
1361
+
SND_SOC_DAPM_MIXER("O05", SND_SOC_NOPM, 0, 0,
1362
+
mt8365_afe_o05_mix, ARRAY_SIZE(mt8365_afe_o05_mix)),
1363
+
SND_SOC_DAPM_MIXER("O06", SND_SOC_NOPM, 0, 0,
1364
+
mt8365_afe_o06_mix, ARRAY_SIZE(mt8365_afe_o06_mix)),
1365
+
SND_SOC_DAPM_MIXER("O07", SND_SOC_NOPM, 0, 0,
1366
+
mt8365_afe_o07_mix, ARRAY_SIZE(mt8365_afe_o07_mix)),
1367
+
SND_SOC_DAPM_MIXER("O08", SND_SOC_NOPM, 0, 0,
1368
+
mt8365_afe_o08_mix, ARRAY_SIZE(mt8365_afe_o08_mix)),
1369
+
SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
1370
+
mt8365_afe_o09_mix, ARRAY_SIZE(mt8365_afe_o09_mix)),
1371
+
SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
1372
+
mt8365_afe_o10_mix, ARRAY_SIZE(mt8365_afe_o10_mix)),
1373
+
SND_SOC_DAPM_MIXER("O11", SND_SOC_NOPM, 0, 0,
1374
+
mt8365_afe_o11_mix, ARRAY_SIZE(mt8365_afe_o11_mix)),
1375
+
SND_SOC_DAPM_MIXER("O12", SND_SOC_NOPM, 0, 0,
1376
+
mt8365_afe_o12_mix, ARRAY_SIZE(mt8365_afe_o12_mix)),
1377
+
SND_SOC_DAPM_MIXER("O13", SND_SOC_NOPM, 0, 0,
1378
+
mt8365_afe_o13_mix, ARRAY_SIZE(mt8365_afe_o13_mix)),
1379
+
SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0,
1380
+
mt8365_afe_o14_mix, ARRAY_SIZE(mt8365_afe_o14_mix)),
1381
+
SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0,
1382
+
mt8365_afe_o15_mix, ARRAY_SIZE(mt8365_afe_o15_mix)),
1383
+
SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0,
1384
+
mt8365_afe_o16_mix, ARRAY_SIZE(mt8365_afe_o16_mix)),
1385
+
SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0,
1386
+
mt8365_afe_o17_mix, ARRAY_SIZE(mt8365_afe_o17_mix)),
1387
+
SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0,
1388
+
mt8365_afe_o18_mix, ARRAY_SIZE(mt8365_afe_o18_mix)),
1389
+
SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0,
1390
+
mt8365_afe_o19_mix, ARRAY_SIZE(mt8365_afe_o19_mix)),
1391
+
SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0,
1392
+
mt8365_afe_o20_mix, ARRAY_SIZE(mt8365_afe_o20_mix)),
1393
+
SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0,
1394
+
mt8365_afe_o21_mix, ARRAY_SIZE(mt8365_afe_o21_mix)),
1395
+
SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0,
1396
+
mt8365_afe_o22_mix, ARRAY_SIZE(mt8365_afe_o22_mix)),
1397
+
SND_SOC_DAPM_MIXER("O23", SND_SOC_NOPM, 0, 0,
1398
+
mt8365_afe_o23_mix, ARRAY_SIZE(mt8365_afe_o23_mix)),
1399
+
SND_SOC_DAPM_MIXER("O24", SND_SOC_NOPM, 0, 0,
1400
+
mt8365_afe_o24_mix, ARRAY_SIZE(mt8365_afe_o24_mix)),
1401
+
SND_SOC_DAPM_MIXER("O25", SND_SOC_NOPM, 0, 0,
1402
+
mt8365_afe_o25_mix, ARRAY_SIZE(mt8365_afe_o25_mix)),
1403
+
SND_SOC_DAPM_MIXER("O26", SND_SOC_NOPM, 0, 0,
1404
+
mt8365_afe_o26_mix, ARRAY_SIZE(mt8365_afe_o26_mix)),
1405
+
SND_SOC_DAPM_MIXER("O27", SND_SOC_NOPM, 0, 0,
1406
+
mt8365_afe_o27_mix, ARRAY_SIZE(mt8365_afe_o27_mix)),
1407
+
SND_SOC_DAPM_MIXER("O28", SND_SOC_NOPM, 0, 0,
1408
+
mt8365_afe_o28_mix, ARRAY_SIZE(mt8365_afe_o28_mix)),
1409
+
SND_SOC_DAPM_MIXER("O29", SND_SOC_NOPM, 0, 0,
1410
+
mt8365_afe_o29_mix, ARRAY_SIZE(mt8365_afe_o29_mix)),
1411
+
SND_SOC_DAPM_MIXER("O30", SND_SOC_NOPM, 0, 0,
1412
+
mt8365_afe_o30_mix, ARRAY_SIZE(mt8365_afe_o30_mix)),
1413
+
SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0,
1414
+
mt8365_afe_o31_mix, ARRAY_SIZE(mt8365_afe_o31_mix)),
1415
+
SND_SOC_DAPM_MIXER("O32", SND_SOC_NOPM, 0, 0,
1416
+
mt8365_afe_o32_mix, ARRAY_SIZE(mt8365_afe_o32_mix)),
1417
+
SND_SOC_DAPM_MIXER("O33", SND_SOC_NOPM, 0, 0,
1418
+
mt8365_afe_o33_mix, ARRAY_SIZE(mt8365_afe_o33_mix)),
1419
+
SND_SOC_DAPM_MIXER("O34", SND_SOC_NOPM, 0, 0,
1420
+
mt8365_afe_o34_mix, ARRAY_SIZE(mt8365_afe_o34_mix)),
1421
+
SND_SOC_DAPM_MIXER("O35", SND_SOC_NOPM, 0, 0,
1422
+
mt8365_afe_o35_mix, ARRAY_SIZE(mt8365_afe_o35_mix)),
1423
+
SND_SOC_DAPM_MIXER("O36", SND_SOC_NOPM, 0, 0,
1424
+
mt8365_afe_o36_mix, ARRAY_SIZE(mt8365_afe_o36_mix)),
1425
+
SND_SOC_DAPM_MIXER("CM2_Mux IO", SND_SOC_NOPM, 0, 0, NULL, 0),
1426
+
SND_SOC_DAPM_MIXER("CM1_IO", SND_SOC_NOPM, 0, 0, NULL, 0),
1427
+
SND_SOC_DAPM_MIXER("O17O18", SND_SOC_NOPM, 0, 0, NULL, 0),
1428
+
/* inter-connections */
1429
+
SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH1", SND_SOC_NOPM, 0, 0,
1430
+
mtk_hw_gain1_in_ch1_mix,
1431
+
ARRAY_SIZE(mtk_hw_gain1_in_ch1_mix)),
1432
+
SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH2", SND_SOC_NOPM, 0, 0,
1433
+
mtk_hw_gain1_in_ch2_mix,
1434
+
ARRAY_SIZE(mtk_hw_gain1_in_ch2_mix)),
1435
+
1436
+
SND_SOC_DAPM_INPUT("DL Source"),
1437
+
1438
+
SND_SOC_DAPM_MUX("CM2_Mux_IO Input Mux", SND_SOC_NOPM, 0, 0,
1439
+
&mt8365_afe_cm2_mux_input_mux),
1440
+
1441
+
SND_SOC_DAPM_MUX("AIN Mux", SND_SOC_NOPM, 0, 0, &ain_mux),
1442
+
SND_SOC_DAPM_MUX("VUL2 Input Mux", SND_SOC_NOPM, 0, 0,
1443
+
&vul2_in_input_mux),
1444
+
1445
+
SND_SOC_DAPM_MUX("FM HW Gain Mux", SND_SOC_NOPM, 0, 0, &fmhwgain_mux),
1446
+
1447
+
SND_SOC_DAPM_INPUT("HW Gain 1 Out Endpoint"),
1448
+
SND_SOC_DAPM_OUTPUT("HW Gain 1 In Endpoint"),
1449
+
};
1450
+
1451
+
static const struct snd_soc_dapm_route mt8365_memif_routes[] = {
1452
+
/* downlink */
1453
+
{"I00", NULL, "2ND I2S Capture"},
1454
+
{"I01", NULL, "2ND I2S Capture"},
1455
+
{"I05", NULL, "DL1"},
1456
+
{"I06", NULL, "DL1"},
1457
+
{"I07", NULL, "DL2"},
1458
+
{"I08", NULL, "DL2"},
1459
+
1460
+
{"O03", "I05 Switch", "I05"},
1461
+
{"O04", "I06 Switch", "I06"},
1462
+
{"O00", "I05 Switch", "I05"},
1463
+
{"O01", "I06 Switch", "I06"},
1464
+
{"O07", "I05 Switch", "I05"},
1465
+
{"O08", "I06 Switch", "I06"},
1466
+
{"O27", "I05 Switch", "I05"},
1467
+
{"O28", "I06 Switch", "I06"},
1468
+
{"O29", "I05 Switch", "I05"},
1469
+
{"O30", "I06 Switch", "I06"},
1470
+
1471
+
{"O03", "I07 Switch", "I07"},
1472
+
{"O04", "I08 Switch", "I08"},
1473
+
{"O00", "I07 Switch", "I07"},
1474
+
{"O01", "I08 Switch", "I08"},
1475
+
{"O07", "I07 Switch", "I07"},
1476
+
{"O08", "I08 Switch", "I08"},
1477
+
1478
+
/* uplink */
1479
+
{"AWB", NULL, "O05"},
1480
+
{"AWB", NULL, "O06"},
1481
+
{"VUL", NULL, "O09"},
1482
+
{"VUL", NULL, "O10"},
1483
+
{"VUL3", NULL, "O11"},
1484
+
{"VUL3", NULL, "O12"},
1485
+
1486
+
{"AIN Mux", "EXT ADC", "I2S Capture"},
1487
+
{"I03", NULL, "AIN Mux"},
1488
+
{"I04", NULL, "AIN Mux"},
1489
+
1490
+
{"HW_GAIN1_IN_CH1", "CONNSYS_I2S_CH1", "Hostless FM DL"},
1491
+
{"HW_GAIN1_IN_CH2", "CONNSYS_I2S_CH2", "Hostless FM DL"},
1492
+
1493
+
{"HW Gain 1 In Endpoint", NULL, "HW Gain 1 In"},
1494
+
{"HW Gain 1 Out", NULL, "HW Gain 1 Out Endpoint"},
1495
+
{"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH1"},
1496
+
{"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH2"},
1497
+
1498
+
{"FM HW Gain Mux", "FM_HW_GAIN_IO", "HW Gain 1 Out"},
1499
+
{"Hostless FM UL", NULL, "FM HW Gain Mux"},
1500
+
{"Hostless FM UL", NULL, "FM 2ND I2S Mux"},
1501
+
1502
+
{"O05", "I05 Switch", "I05L"},
1503
+
{"O06", "I06 Switch", "I06L"},
1504
+
{"O05", "I07 Switch", "I07L"},
1505
+
{"O06", "I08 Switch", "I08L"},
1506
+
1507
+
{"O05", "I03 Switch", "I03"},
1508
+
{"O06", "I04 Switch", "I04"},
1509
+
{"O05", "I00 Switch", "I00"},
1510
+
{"O06", "I01 Switch", "I01"},
1511
+
{"O05", "I09 Switch", "I09"},
1512
+
{"O06", "I22 Switch", "I22"},
1513
+
{"O05", "I14 Switch", "I14"},
1514
+
{"O06", "I15 Switch", "I15"},
1515
+
{"O05", "I16 Switch", "I16"},
1516
+
{"O06", "I17 Switch", "I17"},
1517
+
{"O05", "I18 Switch", "I18"},
1518
+
{"O06", "I19 Switch", "I19"},
1519
+
{"O05", "I20 Switch", "I20"},
1520
+
{"O06", "I21 Switch", "I21"},
1521
+
{"O05", "I23 Switch", "I23"},
1522
+
{"O06", "I24 Switch", "I24"},
1523
+
1524
+
{"O09", "I03 Switch", "I03"},
1525
+
{"O10", "I04 Switch", "I04"},
1526
+
{"O09", "I00 Switch", "I00"},
1527
+
{"O10", "I01 Switch", "I01"},
1528
+
{"O09", "I09 Switch", "I09"},
1529
+
{"O10", "I22 Switch", "I22"},
1530
+
{"O09", "I14 Switch", "I14"},
1531
+
{"O10", "I15 Switch", "I15"},
1532
+
{"O09", "I16 Switch", "I16"},
1533
+
{"O10", "I17 Switch", "I17"},
1534
+
{"O09", "I18 Switch", "I18"},
1535
+
{"O10", "I19 Switch", "I19"},
1536
+
{"O09", "I20 Switch", "I20"},
1537
+
{"O10", "I21 Switch", "I21"},
1538
+
1539
+
{"O11", "I03 Switch", "I03"},
1540
+
{"O12", "I04 Switch", "I04"},
1541
+
{"O11", "I00 Switch", "I00"},
1542
+
{"O12", "I01 Switch", "I01"},
1543
+
{"O11", "I09 Switch", "I09"},
1544
+
{"O12", "I22 Switch", "I22"},
1545
+
{"O11", "I14 Switch", "I14"},
1546
+
{"O12", "I15 Switch", "I15"},
1547
+
{"O11", "I16 Switch", "I16"},
1548
+
{"O12", "I17 Switch", "I17"},
1549
+
{"O11", "I18 Switch", "I18"},
1550
+
{"O12", "I19 Switch", "I19"},
1551
+
{"O11", "I20 Switch", "I20"},
1552
+
{"O12", "I21 Switch", "I21"},
1553
+
1554
+
/* CM2_Mux*/
1555
+
{"CM2_Mux IO", NULL, "CM2_Mux_IO Input Mux"},
1556
+
1557
+
/* VUL2 */
1558
+
{"VUL2", NULL, "VUL2 Input Mux"},
1559
+
{"VUL2 Input Mux", "VUL2_IN_FROM_O17O18", "O17O18"},
1560
+
{"VUL2 Input Mux", "VUL2_IN_FROM_CM1", "CM1_IO"},
1561
+
1562
+
{"O17O18", NULL, "O17"},
1563
+
{"O17O18", NULL, "O18"},
1564
+
{"CM1_IO", NULL, "O17"},
1565
+
{"CM1_IO", NULL, "O18"},
1566
+
{"CM1_IO", NULL, "O19"},
1567
+
{"CM1_IO", NULL, "O20"},
1568
+
{"CM1_IO", NULL, "O21"},
1569
+
{"CM1_IO", NULL, "O22"},
1570
+
{"CM1_IO", NULL, "O23"},
1571
+
{"CM1_IO", NULL, "O24"},
1572
+
{"CM1_IO", NULL, "O25"},
1573
+
{"CM1_IO", NULL, "O26"},
1574
+
{"CM1_IO", NULL, "O31"},
1575
+
{"CM1_IO", NULL, "O32"},
1576
+
{"CM1_IO", NULL, "O33"},
1577
+
{"CM1_IO", NULL, "O34"},
1578
+
{"CM1_IO", NULL, "O35"},
1579
+
{"CM1_IO", NULL, "O36"},
1580
+
1581
+
{"O17", "I14 Switch", "I14"},
1582
+
{"O18", "I15 Switch", "I15"},
1583
+
{"O19", "I16 Switch", "I16"},
1584
+
{"O20", "I17 Switch", "I17"},
1585
+
{"O21", "I18 Switch", "I18"},
1586
+
{"O22", "I19 Switch", "I19"},
1587
+
{"O23", "I20 Switch", "I20"},
1588
+
{"O24", "I21 Switch", "I21"},
1589
+
{"O25", "I23 Switch", "I23"},
1590
+
{"O26", "I24 Switch", "I24"},
1591
+
{"O25", "I25 Switch", "I25"},
1592
+
{"O26", "I26 Switch", "I26"},
1593
+
1594
+
{"O17", "I03 Switch", "I03"},
1595
+
{"O18", "I04 Switch", "I04"},
1596
+
{"O18", "I23 Switch", "I23"},
1597
+
{"O18", "I25 Switch", "I25"},
1598
+
{"O19", "I04 Switch", "I04"},
1599
+
{"O19", "I23 Switch", "I23"},
1600
+
{"O19", "I24 Switch", "I24"},
1601
+
{"O19", "I25 Switch", "I25"},
1602
+
{"O19", "I26 Switch", "I26"},
1603
+
{"O20", "I24 Switch", "I24"},
1604
+
{"O20", "I26 Switch", "I26"},
1605
+
{"O21", "I23 Switch", "I23"},
1606
+
{"O21", "I25 Switch", "I25"},
1607
+
{"O22", "I24 Switch", "I24"},
1608
+
{"O22", "I26 Switch", "I26"},
1609
+
1610
+
{"O23", "I23 Switch", "I23"},
1611
+
{"O23", "I25 Switch", "I25"},
1612
+
{"O24", "I24 Switch", "I24"},
1613
+
{"O24", "I26 Switch", "I26"},
1614
+
{"O24", "I23 Switch", "I23"},
1615
+
{"O24", "I25 Switch", "I25"},
1616
+
{"O13", "I00 Switch", "I00"},
1617
+
{"O14", "I01 Switch", "I01"},
1618
+
{"O03", "I10 Switch", "I10"},
1619
+
{"O04", "I11 Switch", "I11"},
1620
+
};
1621
+
1622
+
static const struct mtk_base_memif_data memif_data[MT8365_AFE_MEMIF_NUM] = {
1623
+
{
1624
+
.name = "DL1",
1625
+
.id = MT8365_AFE_MEMIF_DL1,
1626
+
.reg_ofs_base = AFE_DL1_BASE,
1627
+
.reg_ofs_cur = AFE_DL1_CUR,
1628
+
.fs_reg = AFE_DAC_CON1,
1629
+
.fs_shift = 0,
1630
+
.fs_maskbit = 0xf,
1631
+
.mono_reg = AFE_DAC_CON1,
1632
+
.mono_shift = 21,
1633
+
.hd_reg = AFE_MEMIF_PBUF_SIZE,
1634
+
.hd_shift = 16,
1635
+
.enable_reg = AFE_DAC_CON0,
1636
+
.enable_shift = 1,
1637
+
.msb_reg = -1,
1638
+
.msb_shift = -1,
1639
+
.agent_disable_reg = -1,
1640
+
.agent_disable_shift = -1,
1641
+
}, {
1642
+
.name = "DL2",
1643
+
.id = MT8365_AFE_MEMIF_DL2,
1644
+
.reg_ofs_base = AFE_DL2_BASE,
1645
+
.reg_ofs_cur = AFE_DL2_CUR,
1646
+
.fs_reg = AFE_DAC_CON1,
1647
+
.fs_shift = 4,
1648
+
.fs_maskbit = 0xf,
1649
+
.mono_reg = AFE_DAC_CON1,
1650
+
.mono_shift = 22,
1651
+
.hd_reg = AFE_MEMIF_PBUF_SIZE,
1652
+
.hd_shift = 18,
1653
+
.enable_reg = AFE_DAC_CON0,
1654
+
.enable_shift = 2,
1655
+
.msb_reg = -1,
1656
+
.msb_shift = -1,
1657
+
.agent_disable_reg = -1,
1658
+
.agent_disable_shift = -1,
1659
+
}, {
1660
+
.name = "TDM OUT",
1661
+
.id = MT8365_AFE_MEMIF_TDM_OUT,
1662
+
.reg_ofs_base = AFE_HDMI_OUT_BASE,
1663
+
.reg_ofs_cur = AFE_HDMI_OUT_CUR,
1664
+
.fs_reg = -1,
1665
+
.fs_shift = -1,
1666
+
.fs_maskbit = -1,
1667
+
.mono_reg = -1,
1668
+
.mono_shift = -1,
1669
+
.hd_reg = AFE_MEMIF_PBUF_SIZE,
1670
+
.hd_shift = 28,
1671
+
.enable_reg = AFE_HDMI_OUT_CON0,
1672
+
.enable_shift = 0,
1673
+
.msb_reg = -1,
1674
+
.msb_shift = -1,
1675
+
.agent_disable_reg = -1,
1676
+
.agent_disable_shift = -1,
1677
+
}, {
1678
+
.name = "AWB",
1679
+
.id = MT8365_AFE_MEMIF_AWB,
1680
+
.reg_ofs_base = AFE_AWB_BASE,
1681
+
.reg_ofs_cur = AFE_AWB_CUR,
1682
+
.fs_reg = AFE_DAC_CON1,
1683
+
.fs_shift = 12,
1684
+
.fs_maskbit = 0xf,
1685
+
.mono_reg = AFE_DAC_CON1,
1686
+
.mono_shift = 24,
1687
+
.hd_reg = AFE_MEMIF_PBUF_SIZE,
1688
+
.hd_shift = 20,
1689
+
.enable_reg = AFE_DAC_CON0,
1690
+
.enable_shift = 6,
1691
+
.msb_reg = AFE_MEMIF_MSB,
1692
+
.msb_shift = 17,
1693
+
.agent_disable_reg = -1,
1694
+
.agent_disable_shift = -1,
1695
+
}, {
1696
+
.name = "VUL",
1697
+
.id = MT8365_AFE_MEMIF_VUL,
1698
+
.reg_ofs_base = AFE_VUL_BASE,
1699
+
.reg_ofs_cur = AFE_VUL_CUR,
1700
+
.fs_reg = AFE_DAC_CON1,
1701
+
.fs_shift = 16,
1702
+
.fs_maskbit = 0xf,
1703
+
.mono_reg = AFE_DAC_CON1,
1704
+
.mono_shift = 27,
1705
+
.hd_reg = AFE_MEMIF_PBUF_SIZE,
1706
+
.hd_shift = 22,
1707
+
.enable_reg = AFE_DAC_CON0,
1708
+
.enable_shift = 3,
1709
+
.msb_reg = AFE_MEMIF_MSB,
1710
+
.msb_shift = 20,
1711
+
.agent_disable_reg = -1,
1712
+
.agent_disable_shift = -1,
1713
+
}, {
1714
+
.name = "VUL2",
1715
+
.id = MT8365_AFE_MEMIF_VUL2,
1716
+
.reg_ofs_base = AFE_VUL_D2_BASE,
1717
+
.reg_ofs_cur = AFE_VUL_D2_CUR,
1718
+
.fs_reg = AFE_DAC_CON0,
1719
+
.fs_shift = 20,
1720
+
.fs_maskbit = 0xf,
1721
+
.mono_reg = -1,
1722
+
.mono_shift = -1,
1723
+
.hd_reg = AFE_MEMIF_PBUF_SIZE,
1724
+
.hd_shift = 14,
1725
+
.enable_reg = AFE_DAC_CON0,
1726
+
.enable_shift = 9,
1727
+
.msb_reg = AFE_MEMIF_MSB,
1728
+
.msb_shift = 21,
1729
+
.agent_disable_reg = -1,
1730
+
.agent_disable_shift = -1,
1731
+
}, {
1732
+
.name = "VUL3",
1733
+
.id = MT8365_AFE_MEMIF_VUL3,
1734
+
.reg_ofs_base = AFE_VUL3_BASE,
1735
+
.reg_ofs_cur = AFE_VUL3_CUR,
1736
+
.fs_reg = AFE_DAC_CON1,
1737
+
.fs_shift = 8,
1738
+
.fs_maskbit = 0xf,
1739
+
.mono_reg = AFE_DAC_CON0,
1740
+
.mono_shift = 13,
1741
+
.hd_reg = AFE_MEMIF_PBUF2_SIZE,
1742
+
.hd_shift = 10,
1743
+
.enable_reg = AFE_DAC_CON0,
1744
+
.enable_shift = 12,
1745
+
.msb_reg = AFE_MEMIF_MSB,
1746
+
.msb_shift = 27,
1747
+
.agent_disable_reg = -1,
1748
+
.agent_disable_shift = -1,
1749
+
}, {
1750
+
.name = "TDM IN",
1751
+
.id = MT8365_AFE_MEMIF_TDM_IN,
1752
+
.reg_ofs_base = AFE_HDMI_IN_2CH_BASE,
1753
+
.reg_ofs_cur = AFE_HDMI_IN_2CH_CUR,
1754
+
.fs_reg = -1,
1755
+
.fs_shift = -1,
1756
+
.fs_maskbit = -1,
1757
+
.mono_reg = AFE_HDMI_IN_2CH_CON0,
1758
+
.mono_shift = 1,
1759
+
.hd_reg = AFE_MEMIF_PBUF2_SIZE,
1760
+
.hd_shift = 8,
1761
+
.hd_align_mshift = 5,
1762
+
.enable_reg = AFE_HDMI_IN_2CH_CON0,
1763
+
.enable_shift = 0,
1764
+
.msb_reg = AFE_MEMIF_MSB,
1765
+
.msb_shift = 28,
1766
+
.agent_disable_reg = -1,
1767
+
.agent_disable_shift = -1,
1768
+
},
1769
+
};
1770
+
1771
+
static const struct mtk_base_irq_data irq_data[MT8365_AFE_IRQ_NUM] = {
1772
+
{
1773
+
.id = MT8365_AFE_IRQ1,
1774
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT1,
1775
+
.irq_cnt_shift = 0,
1776
+
.irq_cnt_maskbit = 0x3ffff,
1777
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1778
+
.irq_en_shift = 0,
1779
+
.irq_fs_reg = AFE_IRQ_MCU_CON,
1780
+
.irq_fs_shift = 4,
1781
+
.irq_fs_maskbit = 0xf,
1782
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1783
+
.irq_clr_shift = 0,
1784
+
}, {
1785
+
.id = MT8365_AFE_IRQ2,
1786
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT2,
1787
+
.irq_cnt_shift = 0,
1788
+
.irq_cnt_maskbit = 0x3ffff,
1789
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1790
+
.irq_en_shift = 1,
1791
+
.irq_fs_reg = AFE_IRQ_MCU_CON,
1792
+
.irq_fs_shift = 8,
1793
+
.irq_fs_maskbit = 0xf,
1794
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1795
+
.irq_clr_shift = 1,
1796
+
}, {
1797
+
.id = MT8365_AFE_IRQ3,
1798
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT3,
1799
+
.irq_cnt_shift = 0,
1800
+
.irq_cnt_maskbit = 0x3ffff,
1801
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1802
+
.irq_en_shift = 2,
1803
+
.irq_fs_reg = AFE_IRQ_MCU_CON,
1804
+
.irq_fs_shift = 16,
1805
+
.irq_fs_maskbit = 0xf,
1806
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1807
+
.irq_clr_shift = 2,
1808
+
}, {
1809
+
.id = MT8365_AFE_IRQ4,
1810
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT4,
1811
+
.irq_cnt_shift = 0,
1812
+
.irq_cnt_maskbit = 0x3ffff,
1813
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1814
+
.irq_en_shift = 3,
1815
+
.irq_fs_reg = AFE_IRQ_MCU_CON,
1816
+
.irq_fs_shift = 20,
1817
+
.irq_fs_maskbit = 0xf,
1818
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1819
+
.irq_clr_shift = 3,
1820
+
}, {
1821
+
.id = MT8365_AFE_IRQ5,
1822
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT5,
1823
+
.irq_cnt_shift = 0,
1824
+
.irq_cnt_maskbit = 0x3ffff,
1825
+
.irq_en_reg = AFE_IRQ_MCU_CON2,
1826
+
.irq_en_shift = 3,
1827
+
.irq_fs_reg = -1,
1828
+
.irq_fs_shift = 0,
1829
+
.irq_fs_maskbit = 0x0,
1830
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1831
+
.irq_clr_shift = 4,
1832
+
}, {
1833
+
.id = MT8365_AFE_IRQ6,
1834
+
.irq_cnt_reg = -1,
1835
+
.irq_cnt_shift = 0,
1836
+
.irq_cnt_maskbit = 0x0,
1837
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1838
+
.irq_en_shift = 13,
1839
+
.irq_fs_reg = -1,
1840
+
.irq_fs_shift = 0,
1841
+
.irq_fs_maskbit = 0x0,
1842
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1843
+
.irq_clr_shift = 5,
1844
+
}, {
1845
+
.id = MT8365_AFE_IRQ7,
1846
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT7,
1847
+
.irq_cnt_shift = 0,
1848
+
.irq_cnt_maskbit = 0x3ffff,
1849
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1850
+
.irq_en_shift = 14,
1851
+
.irq_fs_reg = AFE_IRQ_MCU_CON,
1852
+
.irq_fs_shift = 24,
1853
+
.irq_fs_maskbit = 0xf,
1854
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1855
+
.irq_clr_shift = 6,
1856
+
}, {
1857
+
.id = MT8365_AFE_IRQ8,
1858
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT8,
1859
+
.irq_cnt_shift = 0,
1860
+
.irq_cnt_maskbit = 0x3ffff,
1861
+
.irq_en_reg = AFE_IRQ_MCU_CON,
1862
+
.irq_en_shift = 15,
1863
+
.irq_fs_reg = AFE_IRQ_MCU_CON,
1864
+
.irq_fs_shift = 28,
1865
+
.irq_fs_maskbit = 0xf,
1866
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1867
+
.irq_clr_shift = 7,
1868
+
}, {
1869
+
.id = MT8365_AFE_IRQ9,
1870
+
.irq_cnt_reg = -1,
1871
+
.irq_cnt_shift = 0,
1872
+
.irq_cnt_maskbit = 0x0,
1873
+
.irq_en_reg = AFE_IRQ_MCU_CON2,
1874
+
.irq_en_shift = 2,
1875
+
.irq_fs_reg = -1,
1876
+
.irq_fs_shift = 0,
1877
+
.irq_fs_maskbit = 0x0,
1878
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1879
+
.irq_clr_shift = 8,
1880
+
}, {
1881
+
.id = MT8365_AFE_IRQ10,
1882
+
.irq_cnt_reg = AFE_IRQ_MCU_CNT10,
1883
+
.irq_cnt_shift = 0,
1884
+
.irq_cnt_maskbit = 0x3ffff,
1885
+
.irq_en_reg = AFE_IRQ_MCU_CON2,
1886
+
.irq_en_shift = 4,
1887
+
.irq_fs_reg = -1,
1888
+
.irq_fs_shift = 0,
1889
+
.irq_fs_maskbit = 0x0,
1890
+
.irq_clr_reg = AFE_IRQ_MCU_CLR,
1891
+
.irq_clr_shift = 9,
1892
+
},
1893
+
};
1894
+
1895
+
static int memif_specified_irqs[MT8365_AFE_MEMIF_NUM] = {
1896
+
[MT8365_AFE_MEMIF_DL1] = MT8365_AFE_IRQ1,
1897
+
[MT8365_AFE_MEMIF_DL2] = MT8365_AFE_IRQ2,
1898
+
[MT8365_AFE_MEMIF_TDM_OUT] = MT8365_AFE_IRQ5,
1899
+
[MT8365_AFE_MEMIF_AWB] = MT8365_AFE_IRQ3,
1900
+
[MT8365_AFE_MEMIF_VUL] = MT8365_AFE_IRQ4,
1901
+
[MT8365_AFE_MEMIF_VUL2] = MT8365_AFE_IRQ7,
1902
+
[MT8365_AFE_MEMIF_VUL3] = MT8365_AFE_IRQ8,
1903
+
[MT8365_AFE_MEMIF_TDM_IN] = MT8365_AFE_IRQ10,
1904
+
};
1905
+
1906
+
static const struct regmap_config mt8365_afe_regmap_config = {
1907
+
.reg_bits = 32,
1908
+
.reg_stride = 4,
1909
+
.val_bits = 32,
1910
+
.max_register = MAX_REGISTER,
1911
+
.cache_type = REGCACHE_NONE,
1912
+
};
1913
+
1914
+
static irqreturn_t mt8365_afe_irq_handler(int irq, void *dev_id)
1915
+
{
1916
+
struct mtk_base_afe *afe = dev_id;
1917
+
unsigned int reg_value;
1918
+
unsigned int mcu_irq_mask;
1919
+
int i, ret;
1920
+
1921
+
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, ®_value);
1922
+
if (ret) {
1923
+
dev_err_ratelimited(afe->dev, "%s irq status err\n", __func__);
1924
+
reg_value = AFE_IRQ_STATUS_BITS;
1925
+
goto err_irq;
1926
+
}
1927
+
1928
+
ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_irq_mask);
1929
+
if (ret) {
1930
+
dev_err_ratelimited(afe->dev, "%s irq mcu_en err\n", __func__);
1931
+
reg_value = AFE_IRQ_STATUS_BITS;
1932
+
goto err_irq;
1933
+
}
1934
+
1935
+
/* only clr cpu irq */
1936
+
reg_value &= mcu_irq_mask;
1937
+
1938
+
for (i = 0; i < MT8365_AFE_MEMIF_NUM; i++) {
1939
+
struct mtk_base_afe_memif *memif = &afe->memif[i];
1940
+
struct mtk_base_afe_irq *mcu_irq;
1941
+
1942
+
if (memif->irq_usage < 0)
1943
+
continue;
1944
+
1945
+
mcu_irq = &afe->irqs[memif->irq_usage];
1946
+
1947
+
if (!(reg_value & (1 << mcu_irq->irq_data->irq_clr_shift)))
1948
+
continue;
1949
+
1950
+
snd_pcm_period_elapsed(memif->substream);
1951
+
}
1952
+
1953
+
err_irq:
1954
+
/* clear irq */
1955
+
regmap_write(afe->regmap, AFE_IRQ_MCU_CLR,
1956
+
reg_value & AFE_IRQ_STATUS_BITS);
1957
+
1958
+
return IRQ_HANDLED;
1959
+
}
1960
+
1961
+
static int __maybe_unused mt8365_afe_runtime_suspend(struct device *dev)
1962
+
{
1963
+
return 0;
1964
+
}
1965
+
1966
+
static int mt8365_afe_runtime_resume(struct device *dev)
1967
+
{
1968
+
return 0;
1969
+
}
1970
+
1971
+
static int __maybe_unused mt8365_afe_suspend(struct device *dev)
1972
+
{
1973
+
struct mtk_base_afe *afe = dev_get_drvdata(dev);
1974
+
struct regmap *regmap = afe->regmap;
1975
+
int i;
1976
+
1977
+
mt8365_afe_enable_main_clk(afe);
1978
+
1979
+
if (!afe->reg_back_up)
1980
+
afe->reg_back_up =
1981
+
devm_kcalloc(dev, afe->reg_back_up_list_num,
1982
+
sizeof(unsigned int), GFP_KERNEL);
1983
+
1984
+
for (i = 0; i < afe->reg_back_up_list_num; i++)
1985
+
regmap_read(regmap, afe->reg_back_up_list[i],
1986
+
&afe->reg_back_up[i]);
1987
+
1988
+
mt8365_afe_disable_main_clk(afe);
1989
+
1990
+
return 0;
1991
+
}
1992
+
1993
+
static int __maybe_unused mt8365_afe_resume(struct device *dev)
1994
+
{
1995
+
struct mtk_base_afe *afe = dev_get_drvdata(dev);
1996
+
struct regmap *regmap = afe->regmap;
1997
+
int i = 0;
1998
+
1999
+
if (!afe->reg_back_up)
2000
+
return 0;
2001
+
2002
+
mt8365_afe_enable_main_clk(afe);
2003
+
2004
+
for (i = 0; i < afe->reg_back_up_list_num; i++)
2005
+
regmap_write(regmap, afe->reg_back_up_list[i],
2006
+
afe->reg_back_up[i]);
2007
+
2008
+
mt8365_afe_disable_main_clk(afe);
2009
+
2010
+
return 0;
2011
+
}
2012
+
2013
+
static int __maybe_unused mt8365_afe_dev_runtime_suspend(struct device *dev)
2014
+
{
2015
+
struct mtk_base_afe *afe = dev_get_drvdata(dev);
2016
+
2017
+
if (pm_runtime_status_suspended(dev) || afe->suspended)
2018
+
return 0;
2019
+
2020
+
mt8365_afe_suspend(dev);
2021
+
afe->suspended = true;
2022
+
return 0;
2023
+
}
2024
+
2025
+
static int __maybe_unused mt8365_afe_dev_runtime_resume(struct device *dev)
2026
+
{
2027
+
struct mtk_base_afe *afe = dev_get_drvdata(dev);
2028
+
2029
+
if (pm_runtime_status_suspended(dev) || !afe->suspended)
2030
+
return 0;
2031
+
2032
+
mt8365_afe_resume(dev);
2033
+
afe->suspended = false;
2034
+
return 0;
2035
+
}
2036
+
2037
+
static int mt8365_afe_init_registers(struct mtk_base_afe *afe)
2038
+
{
2039
+
size_t i;
2040
+
2041
+
static struct {
2042
+
unsigned int reg;
2043
+
unsigned int mask;
2044
+
unsigned int val;
2045
+
} init_regs[] = {
2046
+
{ AFE_CONN_24BIT, GENMASK(31, 0), GENMASK(31, 0) },
2047
+
{ AFE_CONN_24BIT_1, GENMASK(21, 0), GENMASK(21, 0) },
2048
+
};
2049
+
2050
+
mt8365_afe_enable_main_clk(afe);
2051
+
2052
+
for (i = 0; i < ARRAY_SIZE(init_regs); i++)
2053
+
regmap_update_bits(afe->regmap, init_regs[i].reg,
2054
+
init_regs[i].mask, init_regs[i].val);
2055
+
2056
+
mt8365_afe_disable_main_clk(afe);
2057
+
2058
+
return 0;
2059
+
}
2060
+
2061
+
static int mt8365_dai_memif_register(struct mtk_base_afe *afe)
2062
+
{
2063
+
struct mtk_base_afe_dai *dai;
2064
+
2065
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2066
+
if (!dai)
2067
+
return -ENOMEM;
2068
+
2069
+
list_add(&dai->list, &afe->sub_dais);
2070
+
2071
+
dai->dai_drivers = mt8365_memif_dai_driver;
2072
+
dai->num_dai_drivers = ARRAY_SIZE(mt8365_memif_dai_driver);
2073
+
2074
+
dai->dapm_widgets = mt8365_memif_widgets;
2075
+
dai->num_dapm_widgets = ARRAY_SIZE(mt8365_memif_widgets);
2076
+
dai->dapm_routes = mt8365_memif_routes;
2077
+
dai->num_dapm_routes = ARRAY_SIZE(mt8365_memif_routes);
2078
+
return 0;
2079
+
}
2080
+
2081
+
typedef int (*dai_register_cb)(struct mtk_base_afe *);
2082
+
static const dai_register_cb dai_register_cbs[] = {
2083
+
mt8365_dai_pcm_register,
2084
+
mt8365_dai_i2s_register,
2085
+
mt8365_dai_adda_register,
2086
+
mt8365_dai_dmic_register,
2087
+
mt8365_dai_memif_register,
2088
+
};
2089
+
2090
+
static int mt8365_afe_pcm_dev_probe(struct platform_device *pdev)
2091
+
{
2092
+
struct mtk_base_afe *afe;
2093
+
struct mt8365_afe_private *afe_priv;
2094
+
struct device *dev;
2095
+
int ret, i, sel_irq;
2096
+
unsigned int irq_id;
2097
+
struct resource *res;
2098
+
2099
+
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
2100
+
if (!afe)
2101
+
return -ENOMEM;
2102
+
platform_set_drvdata(pdev, afe);
2103
+
2104
+
afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
2105
+
GFP_KERNEL);
2106
+
if (!afe->platform_priv)
2107
+
return -ENOMEM;
2108
+
2109
+
afe_priv = afe->platform_priv;
2110
+
afe->dev = &pdev->dev;
2111
+
dev = afe->dev;
2112
+
2113
+
spin_lock_init(&afe_priv->afe_ctrl_lock);
2114
+
mutex_init(&afe_priv->afe_clk_mutex);
2115
+
2116
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2117
+
afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
2118
+
if (IS_ERR(afe->base_addr))
2119
+
return PTR_ERR(afe->base_addr);
2120
+
2121
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2122
+
if (res) {
2123
+
afe_priv->afe_sram_vir_addr =
2124
+
devm_ioremap_resource(&pdev->dev, res);
2125
+
if (!IS_ERR(afe_priv->afe_sram_vir_addr)) {
2126
+
afe_priv->afe_sram_phy_addr = res->start;
2127
+
afe_priv->afe_sram_size = resource_size(res);
2128
+
}
2129
+
}
2130
+
2131
+
/* initial audio related clock */
2132
+
ret = mt8365_afe_init_audio_clk(afe);
2133
+
if (ret)
2134
+
return dev_err_probe(afe->dev, ret, "mt8365_afe_init_audio_clk fail\n");
2135
+
2136
+
afe->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "top_audio_sel",
2137
+
afe->base_addr,
2138
+
&mt8365_afe_regmap_config);
2139
+
if (IS_ERR(afe->regmap))
2140
+
return PTR_ERR(afe->regmap);
2141
+
2142
+
/* memif % irq initialize*/
2143
+
afe->memif_size = MT8365_AFE_MEMIF_NUM;
2144
+
afe->memif = devm_kcalloc(afe->dev, afe->memif_size,
2145
+
sizeof(*afe->memif), GFP_KERNEL);
2146
+
if (!afe->memif)
2147
+
return -ENOMEM;
2148
+
2149
+
afe->irqs_size = MT8365_AFE_IRQ_NUM;
2150
+
afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size,
2151
+
sizeof(*afe->irqs), GFP_KERNEL);
2152
+
if (!afe->irqs)
2153
+
return -ENOMEM;
2154
+
2155
+
for (i = 0; i < afe->irqs_size; i++)
2156
+
afe->irqs[i].irq_data = &irq_data[i];
2157
+
2158
+
irq_id = platform_get_irq(pdev, 0);
2159
+
if (!irq_id) {
2160
+
dev_err_probe(afe->dev, irq_id, "np %s no irq\n", afe->dev->of_node->name);
2161
+
return -ENXIO;
2162
+
}
2163
+
ret = devm_request_irq(afe->dev, irq_id, mt8365_afe_irq_handler,
2164
+
0, "Afe_ISR_Handle", (void *)afe);
2165
+
if (ret)
2166
+
return dev_err_probe(afe->dev, ret, "could not request_irq\n");
2167
+
2168
+
/* init sub_dais */
2169
+
INIT_LIST_HEAD(&afe->sub_dais);
2170
+
2171
+
for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
2172
+
ret = dai_register_cbs[i](afe);
2173
+
if (ret) {
2174
+
dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
2175
+
i, ret);
2176
+
return ret;
2177
+
}
2178
+
}
2179
+
2180
+
/* init dai_driver and component_driver */
2181
+
ret = mtk_afe_combine_sub_dai(afe);
2182
+
if (ret) {
2183
+
dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
2184
+
ret);
2185
+
return ret;
2186
+
}
2187
+
2188
+
for (i = 0; i < afe->memif_size; i++) {
2189
+
afe->memif[i].data = &memif_data[i];
2190
+
sel_irq = memif_specified_irqs[i];
2191
+
if (sel_irq >= 0) {
2192
+
afe->memif[i].irq_usage = sel_irq;
2193
+
afe->memif[i].const_irq = 1;
2194
+
afe->irqs[sel_irq].irq_occupyed = true;
2195
+
} else {
2196
+
afe->memif[i].irq_usage = -1;
2197
+
}
2198
+
}
2199
+
2200
+
afe->mtk_afe_hardware = &mt8365_afe_hardware;
2201
+
afe->memif_fs = mt8365_memif_fs;
2202
+
afe->irq_fs = mt8365_irq_fs;
2203
+
2204
+
ret = devm_pm_runtime_enable(&pdev->dev);
2205
+
if (ret)
2206
+
return ret;
2207
+
2208
+
pm_runtime_get_sync(&pdev->dev);
2209
+
afe->reg_back_up_list = mt8365_afe_backup_list;
2210
+
afe->reg_back_up_list_num = ARRAY_SIZE(mt8365_afe_backup_list);
2211
+
afe->runtime_resume = mt8365_afe_runtime_resume;
2212
+
afe->runtime_suspend = mt8365_afe_runtime_suspend;
2213
+
2214
+
/* open afe pdn for dapm read/write audio register */
2215
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE);
2216
+
2217
+
/* Set 26m parent clk */
2218
+
mt8365_afe_set_clk_parent(afe,
2219
+
afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL],
2220
+
afe_priv->clocks[MT8365_CLK_CLK26M]);
2221
+
2222
+
ret = devm_snd_soc_register_component(&pdev->dev,
2223
+
&mtk_afe_pcm_platform,
2224
+
afe->dai_drivers,
2225
+
afe->num_dai_drivers);
2226
+
if (ret) {
2227
+
dev_warn(dev, "err_platform\n");
2228
+
return ret;
2229
+
}
2230
+
2231
+
mt8365_afe_init_registers(afe);
2232
+
2233
+
return 0;
2234
+
}
2235
+
2236
+
static void mt8365_afe_pcm_dev_remove(struct platform_device *pdev)
2237
+
{
2238
+
struct mtk_base_afe *afe = platform_get_drvdata(pdev);
2239
+
2240
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE);
2241
+
2242
+
pm_runtime_disable(&pdev->dev);
2243
+
if (!pm_runtime_status_suspended(&pdev->dev))
2244
+
mt8365_afe_runtime_suspend(&pdev->dev);
2245
+
}
2246
+
2247
+
static const struct of_device_id mt8365_afe_pcm_dt_match[] = {
2248
+
{ .compatible = "mediatek,mt8365-afe-pcm", },
2249
+
{ }
2250
+
};
2251
+
MODULE_DEVICE_TABLE(of, mt8365_afe_pcm_dt_match);
2252
+
2253
+
static const struct dev_pm_ops mt8365_afe_pm_ops = {
2254
+
SET_RUNTIME_PM_OPS(mt8365_afe_dev_runtime_suspend,
2255
+
mt8365_afe_dev_runtime_resume, NULL)
2256
+
SET_SYSTEM_SLEEP_PM_OPS(mt8365_afe_suspend,
2257
+
mt8365_afe_resume)
2258
+
};
2259
+
2260
+
static struct platform_driver mt8365_afe_pcm_driver = {
2261
+
.driver = {
2262
+
.name = "mt8365-afe-pcm",
2263
+
.of_match_table = mt8365_afe_pcm_dt_match,
2264
+
.pm = &mt8365_afe_pm_ops,
2265
+
},
2266
+
.probe = mt8365_afe_pcm_dev_probe,
2267
+
.remove_new = mt8365_afe_pcm_dev_remove,
2268
+
};
2269
+
2270
+
module_platform_driver(mt8365_afe_pcm_driver);
2271
+
2272
+
MODULE_DESCRIPTION("MediaTek ALSA SoC AFE platform driver");
2273
+
MODULE_AUTHOR("Jia Zeng <jia.zeng@mediatek.com>");
2274
+
MODULE_AUTHOR("Alexandre Mergnat <amergnat@baylibre.com>");
2275
+
MODULE_LICENSE("GPL");
+311
sound/soc/mediatek/mt8365/mt8365-dai-adda.c
+311
sound/soc/mediatek/mt8365/mt8365-dai-adda.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek 8365 ALSA SoC Audio DAI ADDA Control
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#include <linux/bitops.h>
11
+
#include <linux/regmap.h>
12
+
#include <sound/pcm_params.h>
13
+
#include "mt8365-afe-clk.h"
14
+
#include "mt8365-afe-common.h"
15
+
#include "../common/mtk-dai-adda-common.h"
16
+
17
+
static int adda_afe_on_ref_cnt;
18
+
19
+
/* DAI Drivers */
20
+
21
+
static int mt8365_dai_set_adda_out(struct mtk_base_afe *afe, unsigned int rate)
22
+
{
23
+
unsigned int val;
24
+
25
+
if (rate == 8000 || rate == 16000)
26
+
val = AFE_ADDA_DL_VOICE_DATA;
27
+
else
28
+
val = 0;
29
+
30
+
val |= FIELD_PREP(AFE_ADDA_DL_SAMPLING_RATE,
31
+
mtk_adda_dl_rate_transform(afe, rate));
32
+
val |= AFE_ADDA_DL_8X_UPSAMPLE |
33
+
AFE_ADDA_DL_MUTE_OFF_CH1 |
34
+
AFE_ADDA_DL_MUTE_OFF_CH2 |
35
+
AFE_ADDA_DL_DEGRADE_GAIN;
36
+
37
+
regmap_update_bits(afe->regmap, AFE_ADDA_PREDIS_CON0, 0xffffffff, 0);
38
+
regmap_update_bits(afe->regmap, AFE_ADDA_PREDIS_CON1, 0xffffffff, 0);
39
+
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, 0xffffffff, val);
40
+
/* SA suggest apply -0.3db to audio/speech path */
41
+
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON1,
42
+
0xffffffff, 0xf74f0000);
43
+
/* SA suggest use default value for sdm */
44
+
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON,
45
+
0xffffffff, 0x0700701e);
46
+
47
+
return 0;
48
+
}
49
+
50
+
static int mt8365_dai_set_adda_in(struct mtk_base_afe *afe, unsigned int rate)
51
+
{
52
+
unsigned int val;
53
+
54
+
val = FIELD_PREP(AFE_ADDA_UL_SAMPLING_RATE,
55
+
mtk_adda_ul_rate_transform(afe, rate));
56
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
57
+
AFE_ADDA_UL_SAMPLING_RATE, val);
58
+
/* Using Internal ADC */
59
+
regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x0);
60
+
61
+
return 0;
62
+
}
63
+
64
+
int mt8365_dai_enable_adda_on(struct mtk_base_afe *afe)
65
+
{
66
+
unsigned long flags;
67
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
68
+
69
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
70
+
71
+
adda_afe_on_ref_cnt++;
72
+
if (adda_afe_on_ref_cnt == 1)
73
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0,
74
+
AFE_ADDA_UL_DL_ADDA_AFE_ON,
75
+
AFE_ADDA_UL_DL_ADDA_AFE_ON);
76
+
77
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
78
+
79
+
return 0;
80
+
}
81
+
82
+
int mt8365_dai_disable_adda_on(struct mtk_base_afe *afe)
83
+
{
84
+
unsigned long flags;
85
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
86
+
87
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
88
+
89
+
adda_afe_on_ref_cnt--;
90
+
if (adda_afe_on_ref_cnt == 0)
91
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0,
92
+
AFE_ADDA_UL_DL_ADDA_AFE_ON,
93
+
~AFE_ADDA_UL_DL_ADDA_AFE_ON);
94
+
else if (adda_afe_on_ref_cnt < 0) {
95
+
adda_afe_on_ref_cnt = 0;
96
+
dev_warn(afe->dev, "Abnormal adda_on ref count. Force it to 0\n");
97
+
}
98
+
99
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
100
+
101
+
return 0;
102
+
}
103
+
104
+
static void mt8365_dai_set_adda_out_enable(struct mtk_base_afe *afe,
105
+
bool enable)
106
+
{
107
+
regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, 0x1, enable);
108
+
109
+
if (enable)
110
+
mt8365_dai_enable_adda_on(afe);
111
+
else
112
+
mt8365_dai_disable_adda_on(afe);
113
+
}
114
+
115
+
static void mt8365_dai_set_adda_in_enable(struct mtk_base_afe *afe, bool enable)
116
+
{
117
+
if (enable) {
118
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 0x1, 0x1);
119
+
mt8365_dai_enable_adda_on(afe);
120
+
/* enable aud_pad_top fifo */
121
+
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP,
122
+
0xffffffff, 0x31);
123
+
} else {
124
+
/* disable aud_pad_top fifo */
125
+
regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP,
126
+
0xffffffff, 0x30);
127
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 0x1, 0x0);
128
+
/* de suggest disable ADDA_UL_SRC at least wait 125us */
129
+
usleep_range(150, 300);
130
+
mt8365_dai_disable_adda_on(afe);
131
+
}
132
+
}
133
+
134
+
static int mt8365_dai_int_adda_startup(struct snd_pcm_substream *substream,
135
+
struct snd_soc_dai *dai)
136
+
{
137
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
138
+
unsigned int stream = substream->stream;
139
+
140
+
mt8365_afe_enable_main_clk(afe);
141
+
142
+
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
143
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DAC);
144
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DAC_PREDIS);
145
+
} else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
146
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_ADC);
147
+
}
148
+
149
+
return 0;
150
+
}
151
+
152
+
static void mt8365_dai_int_adda_shutdown(struct snd_pcm_substream *substream,
153
+
struct snd_soc_dai *dai)
154
+
{
155
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
156
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
157
+
struct mt8365_be_dai_data *be =
158
+
&afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
159
+
unsigned int stream = substream->stream;
160
+
161
+
if (be->prepared[stream]) {
162
+
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
163
+
mt8365_dai_set_adda_out_enable(afe, false);
164
+
mt8365_afe_set_i2s_out_enable(afe, false);
165
+
} else {
166
+
mt8365_dai_set_adda_in_enable(afe, false);
167
+
}
168
+
be->prepared[stream] = false;
169
+
}
170
+
171
+
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
172
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DAC_PREDIS);
173
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DAC);
174
+
} else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
175
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_ADC);
176
+
}
177
+
178
+
mt8365_afe_disable_main_clk(afe);
179
+
}
180
+
181
+
static int mt8365_dai_int_adda_prepare(struct snd_pcm_substream *substream,
182
+
struct snd_soc_dai *dai)
183
+
{
184
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
185
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
186
+
struct mt8365_be_dai_data *be =
187
+
&afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
188
+
unsigned int rate = substream->runtime->rate;
189
+
int bit_width = snd_pcm_format_width(substream->runtime->format);
190
+
int ret;
191
+
192
+
dev_info(afe->dev, "%s '%s' rate = %u\n", __func__,
193
+
snd_pcm_stream_str(substream), rate);
194
+
195
+
if (be->prepared[substream->stream]) {
196
+
dev_info(afe->dev, "%s '%s' prepared already\n",
197
+
__func__, snd_pcm_stream_str(substream));
198
+
return 0;
199
+
}
200
+
201
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
202
+
ret = mt8365_dai_set_adda_out(afe, rate);
203
+
if (ret)
204
+
return ret;
205
+
206
+
ret = mt8365_afe_set_i2s_out(afe, rate, bit_width);
207
+
if (ret)
208
+
return ret;
209
+
210
+
mt8365_dai_set_adda_out_enable(afe, true);
211
+
mt8365_afe_set_i2s_out_enable(afe, true);
212
+
} else {
213
+
ret = mt8365_dai_set_adda_in(afe, rate);
214
+
if (ret)
215
+
return ret;
216
+
217
+
mt8365_dai_set_adda_in_enable(afe, true);
218
+
}
219
+
be->prepared[substream->stream] = true;
220
+
return 0;
221
+
}
222
+
223
+
static const struct snd_soc_dai_ops mt8365_afe_int_adda_ops = {
224
+
.startup = mt8365_dai_int_adda_startup,
225
+
.shutdown = mt8365_dai_int_adda_shutdown,
226
+
.prepare = mt8365_dai_int_adda_prepare,
227
+
};
228
+
229
+
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
230
+
{
231
+
.name = "INT ADDA",
232
+
.id = MT8365_AFE_IO_INT_ADDA,
233
+
.playback = {
234
+
.stream_name = "INT ADDA Playback",
235
+
.channels_min = 1,
236
+
.channels_max = 2,
237
+
.rates = SNDRV_PCM_RATE_8000_48000,
238
+
.formats = SNDRV_PCM_FMTBIT_S16_LE,
239
+
},
240
+
.capture = {
241
+
.stream_name = "INT ADDA Capture",
242
+
.channels_min = 1,
243
+
.channels_max = 2,
244
+
.rates = SNDRV_PCM_RATE_16000 |
245
+
SNDRV_PCM_RATE_32000 |
246
+
SNDRV_PCM_RATE_48000,
247
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
248
+
SNDRV_PCM_FMTBIT_S32_LE,
249
+
},
250
+
.ops = &mt8365_afe_int_adda_ops,
251
+
}
252
+
};
253
+
254
+
/* DAI Controls */
255
+
256
+
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
257
+
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3,
258
+
10, 1, 0),
259
+
};
260
+
261
+
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
262
+
SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4,
263
+
11, 1, 0),
264
+
};
265
+
266
+
static const struct snd_kcontrol_new int_adda_o03_o04_enable_ctl =
267
+
SOC_DAPM_SINGLE_VIRT("Switch", 1);
268
+
269
+
/* DAI widget */
270
+
271
+
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
272
+
SND_SOC_DAPM_SWITCH("INT ADDA O03_O04", SND_SOC_NOPM, 0, 0,
273
+
&int_adda_o03_o04_enable_ctl),
274
+
/* inter-connections */
275
+
SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
276
+
mtk_adda_dl_ch1_mix,
277
+
ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
278
+
SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
279
+
mtk_adda_dl_ch2_mix,
280
+
ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
281
+
};
282
+
283
+
/* DAI route */
284
+
285
+
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
286
+
{"INT ADDA O03_O04", "Switch", "O03"},
287
+
{"INT ADDA O03_O04", "Switch", "O04"},
288
+
{"INT ADDA Playback", NULL, "INT ADDA O03_O04"},
289
+
{"INT ADDA Playback", NULL, "ADDA_DL_CH1"},
290
+
{"INT ADDA Playback", NULL, "ADDA_DL_CH2"},
291
+
{"AIN Mux", "INT ADC", "INT ADDA Capture"},
292
+
{"ADDA_DL_CH1", "GAIN1_OUT_CH1", "Hostless FM DL"},
293
+
{"ADDA_DL_CH2", "GAIN1_OUT_CH2", "Hostless FM DL"},
294
+
};
295
+
296
+
int mt8365_dai_adda_register(struct mtk_base_afe *afe)
297
+
{
298
+
struct mtk_base_afe_dai *dai;
299
+
300
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
301
+
if (!dai)
302
+
return -ENOMEM;
303
+
list_add(&dai->list, &afe->sub_dais);
304
+
dai->dai_drivers = mtk_dai_adda_driver;
305
+
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
306
+
dai->dapm_widgets = mtk_dai_adda_widgets;
307
+
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
308
+
dai->dapm_routes = mtk_dai_adda_routes;
309
+
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
310
+
return 0;
311
+
}
+340
sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
+340
sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek 8365 ALSA SoC Audio DAI DMIC Control
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#include <linux/bitops.h>
11
+
#include <linux/regmap.h>
12
+
#include <sound/pcm_params.h>
13
+
#include "mt8365-afe-clk.h"
14
+
#include "mt8365-afe-common.h"
15
+
16
+
struct mt8365_dmic_data {
17
+
bool two_wire_mode;
18
+
unsigned int clk_phase_sel_ch1;
19
+
unsigned int clk_phase_sel_ch2;
20
+
bool iir_on;
21
+
unsigned int irr_mode;
22
+
unsigned int dmic_mode;
23
+
unsigned int dmic_channel;
24
+
};
25
+
26
+
static int get_chan_reg(unsigned int channel)
27
+
{
28
+
switch (channel) {
29
+
case 8:
30
+
fallthrough;
31
+
case 7:
32
+
return AFE_DMIC3_UL_SRC_CON0;
33
+
case 6:
34
+
fallthrough;
35
+
case 5:
36
+
return AFE_DMIC2_UL_SRC_CON0;
37
+
case 4:
38
+
fallthrough;
39
+
case 3:
40
+
return AFE_DMIC1_UL_SRC_CON0;
41
+
case 2:
42
+
fallthrough;
43
+
case 1:
44
+
return AFE_DMIC0_UL_SRC_CON0;
45
+
default:
46
+
return -EINVAL;
47
+
}
48
+
}
49
+
50
+
/* DAI Drivers */
51
+
52
+
static void audio_dmic_adda_enable(struct mtk_base_afe *afe)
53
+
{
54
+
mt8365_dai_enable_adda_on(afe);
55
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0,
56
+
AFE_ADDA_UL_DL_DMIC_CLKDIV_ON,
57
+
AFE_ADDA_UL_DL_DMIC_CLKDIV_ON);
58
+
}
59
+
60
+
static void audio_dmic_adda_disable(struct mtk_base_afe *afe)
61
+
{
62
+
regmap_update_bits(afe->regmap, AFE_ADDA_UL_DL_CON0,
63
+
AFE_ADDA_UL_DL_DMIC_CLKDIV_ON,
64
+
~AFE_ADDA_UL_DL_DMIC_CLKDIV_ON);
65
+
mt8365_dai_disable_adda_on(afe);
66
+
}
67
+
68
+
static void mt8365_dai_enable_dmic(struct mtk_base_afe *afe,
69
+
struct snd_pcm_substream *substream,
70
+
struct snd_soc_dai *dai)
71
+
{
72
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
73
+
struct mt8365_dmic_data *dmic_data = afe_priv->dai_priv[MT8365_AFE_IO_DMIC];
74
+
unsigned int val_mask;
75
+
int reg = get_chan_reg(dmic_data->dmic_channel);
76
+
77
+
if (reg < 0)
78
+
return;
79
+
80
+
/* val and mask will be always same to enable */
81
+
val_mask = DMIC_TOP_CON_CH1_ON |
82
+
DMIC_TOP_CON_CH2_ON |
83
+
DMIC_TOP_CON_SRC_ON;
84
+
85
+
regmap_update_bits(afe->regmap, reg, val_mask, val_mask);
86
+
}
87
+
88
+
static void mt8365_dai_disable_dmic(struct mtk_base_afe *afe,
89
+
struct snd_pcm_substream *substream,
90
+
struct snd_soc_dai *dai)
91
+
{
92
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
93
+
struct mt8365_dmic_data *dmic_data = afe_priv->dai_priv[MT8365_AFE_IO_DMIC];
94
+
unsigned int mask;
95
+
int reg = get_chan_reg(dmic_data->dmic_channel);
96
+
97
+
if (reg < 0)
98
+
return;
99
+
100
+
dev_dbg(afe->dev, "%s dmic_channel %d\n", __func__, dmic_data->dmic_channel);
101
+
102
+
mask = DMIC_TOP_CON_CH1_ON |
103
+
DMIC_TOP_CON_CH2_ON |
104
+
DMIC_TOP_CON_SRC_ON |
105
+
DMIC_TOP_CON_SDM3_LEVEL_MODE;
106
+
107
+
/* Set all masked values to 0 */
108
+
regmap_update_bits(afe->regmap, reg, mask, 0);
109
+
}
110
+
111
+
static const struct reg_sequence mt8365_dmic_iir_coeff[] = {
112
+
{ AFE_DMIC0_IIR_COEF_02_01, 0x00000000 },
113
+
{ AFE_DMIC0_IIR_COEF_04_03, 0x00003FB8 },
114
+
{ AFE_DMIC0_IIR_COEF_06_05, 0x3FB80000 },
115
+
{ AFE_DMIC0_IIR_COEF_08_07, 0x3FB80000 },
116
+
{ AFE_DMIC0_IIR_COEF_10_09, 0x0000C048 },
117
+
{ AFE_DMIC1_IIR_COEF_02_01, 0x00000000 },
118
+
{ AFE_DMIC1_IIR_COEF_04_03, 0x00003FB8 },
119
+
{ AFE_DMIC1_IIR_COEF_06_05, 0x3FB80000 },
120
+
{ AFE_DMIC1_IIR_COEF_08_07, 0x3FB80000 },
121
+
{ AFE_DMIC1_IIR_COEF_10_09, 0x0000C048 },
122
+
{ AFE_DMIC2_IIR_COEF_02_01, 0x00000000 },
123
+
{ AFE_DMIC2_IIR_COEF_04_03, 0x00003FB8 },
124
+
{ AFE_DMIC2_IIR_COEF_06_05, 0x3FB80000 },
125
+
{ AFE_DMIC2_IIR_COEF_08_07, 0x3FB80000 },
126
+
{ AFE_DMIC2_IIR_COEF_10_09, 0x0000C048 },
127
+
{ AFE_DMIC3_IIR_COEF_02_01, 0x00000000 },
128
+
{ AFE_DMIC3_IIR_COEF_04_03, 0x00003FB8 },
129
+
{ AFE_DMIC3_IIR_COEF_06_05, 0x3FB80000 },
130
+
{ AFE_DMIC3_IIR_COEF_08_07, 0x3FB80000 },
131
+
{ AFE_DMIC3_IIR_COEF_10_09, 0x0000C048 },
132
+
};
133
+
134
+
static int mt8365_dai_load_dmic_iir_coeff_table(struct mtk_base_afe *afe)
135
+
{
136
+
return regmap_multi_reg_write(afe->regmap,
137
+
mt8365_dmic_iir_coeff,
138
+
ARRAY_SIZE(mt8365_dmic_iir_coeff));
139
+
}
140
+
141
+
static int mt8365_dai_configure_dmic(struct mtk_base_afe *afe,
142
+
struct snd_pcm_substream *substream,
143
+
struct snd_soc_dai *dai)
144
+
{
145
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
146
+
struct mt8365_dmic_data *dmic_data = afe_priv->dai_priv[MT8365_AFE_IO_DMIC];
147
+
bool two_wire_mode = dmic_data->two_wire_mode;
148
+
unsigned int clk_phase_sel_ch1 = dmic_data->clk_phase_sel_ch1;
149
+
unsigned int clk_phase_sel_ch2 = dmic_data->clk_phase_sel_ch2;
150
+
unsigned int val = 0;
151
+
unsigned int rate = dai->rate;
152
+
int reg = get_chan_reg(dai->channels);
153
+
154
+
if (reg < 0)
155
+
return -EINVAL;
156
+
157
+
dmic_data->dmic_channel = dai->channels;
158
+
159
+
val |= DMIC_TOP_CON_SDM3_LEVEL_MODE;
160
+
161
+
if (two_wire_mode) {
162
+
val |= DMIC_TOP_CON_TWO_WIRE_MODE;
163
+
} else {
164
+
val |= FIELD_PREP(DMIC_TOP_CON_CK_PHASE_SEL_CH1,
165
+
clk_phase_sel_ch1);
166
+
val |= FIELD_PREP(DMIC_TOP_CON_CK_PHASE_SEL_CH2,
167
+
clk_phase_sel_ch2);
168
+
}
169
+
170
+
switch (rate) {
171
+
case 48000:
172
+
val |= DMIC_TOP_CON_VOICE_MODE_48K;
173
+
break;
174
+
case 32000:
175
+
val |= DMIC_TOP_CON_VOICE_MODE_32K;
176
+
break;
177
+
case 16000:
178
+
val |= DMIC_TOP_CON_VOICE_MODE_16K;
179
+
break;
180
+
case 8000:
181
+
val |= DMIC_TOP_CON_VOICE_MODE_8K;
182
+
break;
183
+
default:
184
+
return -EINVAL;
185
+
}
186
+
187
+
regmap_update_bits(afe->regmap, reg, DMIC_TOP_CON_CONFIG_MASK, val);
188
+
189
+
return 0;
190
+
}
191
+
192
+
static int mt8365_dai_dmic_startup(struct snd_pcm_substream *substream,
193
+
struct snd_soc_dai *dai)
194
+
{
195
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
196
+
197
+
mt8365_afe_enable_main_clk(afe);
198
+
199
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC0_ADC);
200
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC1_ADC);
201
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC2_ADC);
202
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_DMIC3_ADC);
203
+
204
+
audio_dmic_adda_enable(afe);
205
+
206
+
return 0;
207
+
}
208
+
209
+
static void mt8365_dai_dmic_shutdown(struct snd_pcm_substream *substream,
210
+
struct snd_soc_dai *dai)
211
+
{
212
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
213
+
214
+
mt8365_dai_disable_dmic(afe, substream, dai);
215
+
audio_dmic_adda_disable(afe);
216
+
/* HW Request delay 125us before CG off */
217
+
usleep_range(125, 300);
218
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC3_ADC);
219
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC2_ADC);
220
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC1_ADC);
221
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_DMIC0_ADC);
222
+
223
+
mt8365_afe_disable_main_clk(afe);
224
+
}
225
+
226
+
static int mt8365_dai_dmic_prepare(struct snd_pcm_substream *substream,
227
+
struct snd_soc_dai *dai)
228
+
{
229
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
230
+
231
+
mt8365_dai_configure_dmic(afe, substream, dai);
232
+
mt8365_dai_enable_dmic(afe, substream, dai);
233
+
234
+
return 0;
235
+
}
236
+
237
+
static const struct snd_soc_dai_ops mt8365_afe_dmic_ops = {
238
+
.startup = mt8365_dai_dmic_startup,
239
+
.shutdown = mt8365_dai_dmic_shutdown,
240
+
.prepare = mt8365_dai_dmic_prepare,
241
+
};
242
+
243
+
static struct snd_soc_dai_driver mtk_dai_dmic_driver[] = {
244
+
{
245
+
.name = "DMIC",
246
+
.id = MT8365_AFE_IO_DMIC,
247
+
.capture = {
248
+
.stream_name = "DMIC Capture",
249
+
.channels_min = 1,
250
+
.channels_max = 8,
251
+
.rates = SNDRV_PCM_RATE_16000 |
252
+
SNDRV_PCM_RATE_32000 |
253
+
SNDRV_PCM_RATE_48000,
254
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
255
+
SNDRV_PCM_FMTBIT_S32_LE,
256
+
},
257
+
.ops = &mt8365_afe_dmic_ops,
258
+
}
259
+
};
260
+
261
+
/* DAI Controls */
262
+
263
+
/* Values for 48kHz mode */
264
+
static const char * const iir_mode_src[] = {
265
+
"SW custom", "5Hz", "10Hz", "25Hz", "50Hz", "65Hz"
266
+
};
267
+
268
+
static SOC_ENUM_SINGLE_DECL(iir_mode, AFE_DMIC0_UL_SRC_CON0, 7, iir_mode_src);
269
+
270
+
static const struct snd_kcontrol_new mtk_dai_dmic_controls[] = {
271
+
SOC_SINGLE("DMIC IIR Switch", AFE_DMIC0_UL_SRC_CON0, DMIC_TOP_CON_IIR_ON, 1, 0),
272
+
SOC_ENUM("DMIC IIR Mode", iir_mode),
273
+
};
274
+
275
+
/* DAI widget */
276
+
277
+
static const struct snd_soc_dapm_widget mtk_dai_dmic_widgets[] = {
278
+
SND_SOC_DAPM_INPUT("DMIC In"),
279
+
};
280
+
281
+
/* DAI route */
282
+
283
+
static const struct snd_soc_dapm_route mtk_dai_dmic_routes[] = {
284
+
{"I14", NULL, "DMIC Capture"},
285
+
{"I15", NULL, "DMIC Capture"},
286
+
{"I16", NULL, "DMIC Capture"},
287
+
{"I17", NULL, "DMIC Capture"},
288
+
{"I18", NULL, "DMIC Capture"},
289
+
{"I19", NULL, "DMIC Capture"},
290
+
{"I20", NULL, "DMIC Capture"},
291
+
{"I21", NULL, "DMIC Capture"},
292
+
{"DMIC Capture", NULL, "DMIC In"},
293
+
};
294
+
295
+
static int init_dmic_priv_data(struct mtk_base_afe *afe)
296
+
{
297
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
298
+
struct mt8365_dmic_data *dmic_priv;
299
+
struct device_node *np = afe->dev->of_node;
300
+
unsigned int temps[4];
301
+
int ret;
302
+
303
+
dmic_priv = devm_kzalloc(afe->dev, sizeof(*dmic_priv), GFP_KERNEL);
304
+
if (!dmic_priv)
305
+
return -ENOMEM;
306
+
307
+
ret = of_property_read_u32_array(np, "mediatek,dmic-mode",
308
+
&temps[0],
309
+
1);
310
+
if (ret == 0)
311
+
dmic_priv->two_wire_mode = !!temps[0];
312
+
313
+
if (!dmic_priv->two_wire_mode) {
314
+
dmic_priv->clk_phase_sel_ch1 = 0;
315
+
dmic_priv->clk_phase_sel_ch2 = 4;
316
+
}
317
+
318
+
afe_priv->dai_priv[MT8365_AFE_IO_DMIC] = dmic_priv;
319
+
return 0;
320
+
}
321
+
322
+
int mt8365_dai_dmic_register(struct mtk_base_afe *afe)
323
+
{
324
+
struct mtk_base_afe_dai *dai;
325
+
326
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
327
+
if (!dai)
328
+
return -ENOMEM;
329
+
330
+
list_add(&dai->list, &afe->sub_dais);
331
+
dai->dai_drivers = mtk_dai_dmic_driver;
332
+
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_dmic_driver);
333
+
dai->controls = mtk_dai_dmic_controls;
334
+
dai->num_controls = ARRAY_SIZE(mtk_dai_dmic_controls);
335
+
dai->dapm_widgets = mtk_dai_dmic_widgets;
336
+
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_dmic_widgets);
337
+
dai->dapm_routes = mtk_dai_dmic_routes;
338
+
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_dmic_routes);
339
+
return init_dmic_priv_data(afe);
340
+
}
+850
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
+850
sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek 8365 ALSA SoC Audio DAI I2S Control
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#include <linux/bitops.h>
11
+
#include <linux/regmap.h>
12
+
#include <sound/pcm_params.h>
13
+
#include "mt8365-afe-clk.h"
14
+
#include "mt8365-afe-common.h"
15
+
16
+
#define IIR_RATIOVER 9
17
+
#define IIR_INV_COEF 10
18
+
#define IIR_NO_NEED 11
19
+
20
+
struct mtk_afe_i2s_priv {
21
+
bool adda_link;
22
+
int i2s_out_on_ref_cnt;
23
+
int id;
24
+
int low_jitter_en;
25
+
int mclk_id;
26
+
int share_i2s_id;
27
+
unsigned int clk_id_in;
28
+
unsigned int clk_id_in_m_sel;
29
+
unsigned int clk_id_out;
30
+
unsigned int clk_id_out_m_sel;
31
+
unsigned int clk_in_mult;
32
+
unsigned int clk_out_mult;
33
+
unsigned int config_val_in;
34
+
unsigned int config_val_out;
35
+
unsigned int dynamic_bck;
36
+
unsigned int reg_off_in;
37
+
unsigned int reg_off_out;
38
+
};
39
+
40
+
/* This enum is merely for mtk_afe_i2s_priv declare */
41
+
enum {
42
+
DAI_I2S0 = 0,
43
+
DAI_I2S3,
44
+
DAI_I2S_NUM,
45
+
};
46
+
47
+
static const struct mtk_afe_i2s_priv mt8365_i2s_priv[DAI_I2S_NUM] = {
48
+
[DAI_I2S0] = {
49
+
.id = MT8365_AFE_IO_I2S,
50
+
.mclk_id = MT8365_I2S0_MCK,
51
+
.share_i2s_id = -1,
52
+
.clk_id_in = MT8365_CLK_AUD_I2S2_M,
53
+
.clk_id_out = MT8365_CLK_AUD_I2S1_M,
54
+
.clk_id_in_m_sel = MT8365_CLK_I2S2_M_SEL,
55
+
.clk_id_out_m_sel = MT8365_CLK_I2S1_M_SEL,
56
+
.clk_in_mult = 256,
57
+
.clk_out_mult = 256,
58
+
.adda_link = true,
59
+
.config_val_out = AFE_I2S_CON1_I2S2_TO_PAD,
60
+
.reg_off_in = AFE_I2S_CON2,
61
+
.reg_off_out = AFE_I2S_CON1,
62
+
},
63
+
[DAI_I2S3] = {
64
+
.id = MT8365_AFE_IO_2ND_I2S,
65
+
.mclk_id = MT8365_I2S3_MCK,
66
+
.share_i2s_id = -1,
67
+
.clk_id_in = MT8365_CLK_AUD_I2S0_M,
68
+
.clk_id_out = MT8365_CLK_AUD_I2S3_M,
69
+
.clk_id_in_m_sel = MT8365_CLK_I2S0_M_SEL,
70
+
.clk_id_out_m_sel = MT8365_CLK_I2S3_M_SEL,
71
+
.clk_in_mult = 256,
72
+
.clk_out_mult = 256,
73
+
.adda_link = false,
74
+
.config_val_in = AFE_I2S_CON_FROM_IO_MUX,
75
+
.reg_off_in = AFE_I2S_CON,
76
+
.reg_off_out = AFE_I2S_CON3,
77
+
},
78
+
};
79
+
80
+
static const u32 *get_iir_coef(unsigned int input_fs,
81
+
unsigned int output_fs, unsigned int *count)
82
+
{
83
+
static const u32 IIR_COEF_48_TO_44p1[30] = {
84
+
0x061fb0, 0x0bd256, 0x061fb0, 0xe3a3e6, 0xf0a300, 0x000003,
85
+
0x0e416d, 0x1bb577, 0x0e416d, 0xe59178, 0xf23637, 0x000003,
86
+
0x0c7d72, 0x189060, 0x0c7d72, 0xe96f09, 0xf505b2, 0x000003,
87
+
0x126054, 0x249143, 0x126054, 0xe1fc0c, 0xf4b20a, 0x000002,
88
+
0x000000, 0x323c85, 0x323c85, 0xf76d4e, 0x000000, 0x000002,
89
+
};
90
+
91
+
static const u32 IIR_COEF_44p1_TO_32[42] = {
92
+
0x0a6074, 0x0d237a, 0x0a6074, 0xdd8d6c, 0xe0b3f6, 0x000002,
93
+
0x0e41f8, 0x128d48, 0x0e41f8, 0xefc14e, 0xf12d7a, 0x000003,
94
+
0x0cfa60, 0x11e89c, 0x0cfa60, 0xf1b09e, 0xf27205, 0x000003,
95
+
0x15b69c, 0x20e7e4, 0x15b69c, 0xea799a, 0xe9314a, 0x000002,
96
+
0x0f79e2, 0x1a7064, 0x0f79e2, 0xf65e4a, 0xf03d8e, 0x000002,
97
+
0x10c34f, 0x1ffe4b, 0x10c34f, 0x0bbecb, 0xf2bc4b, 0x000001,
98
+
0x000000, 0x23b063, 0x23b063, 0x07335f, 0x000000, 0x000002,
99
+
};
100
+
101
+
static const u32 IIR_COEF_48_TO_32[42] = {
102
+
0x0a2a9b, 0x0a2f05, 0x0a2a9b, 0xe73873, 0xe0c525, 0x000002,
103
+
0x0dd4ad, 0x0e765a, 0x0dd4ad, 0xf49808, 0xf14844, 0x000003,
104
+
0x18a8cd, 0x1c40d0, 0x18a8cd, 0xed2aab, 0xe542ec, 0x000002,
105
+
0x13e044, 0x1a47c4, 0x13e044, 0xf44aed, 0xe9acc7, 0x000002,
106
+
0x1abd9c, 0x2a5429, 0x1abd9c, 0xff3441, 0xe0fc5f, 0x000001,
107
+
0x0d86db, 0x193e2e, 0x0d86db, 0x1a6f15, 0xf14507, 0x000001,
108
+
0x000000, 0x1f820c, 0x1f820c, 0x0a1b1f, 0x000000, 0x000002,
109
+
};
110
+
111
+
static const u32 IIR_COEF_32_TO_16[48] = {
112
+
0x122893, 0xffadd4, 0x122893, 0x0bc205, 0xc0ee1c, 0x000001,
113
+
0x1bab8a, 0x00750d, 0x1bab8a, 0x06a983, 0xe18a5c, 0x000002,
114
+
0x18f68e, 0x02706f, 0x18f68e, 0x0886a9, 0xe31bcb, 0x000002,
115
+
0x149c05, 0x054487, 0x149c05, 0x0bec31, 0xe5973e, 0x000002,
116
+
0x0ea303, 0x07f24a, 0x0ea303, 0x115ff9, 0xe967b6, 0x000002,
117
+
0x0823fd, 0x085531, 0x0823fd, 0x18d5b4, 0xee8d21, 0x000002,
118
+
0x06888e, 0x0acbbb, 0x06888e, 0x40b55c, 0xe76dce, 0x000001,
119
+
0x000000, 0x2d31a9, 0x2d31a9, 0x23ba4f, 0x000000, 0x000001,
120
+
};
121
+
122
+
static const u32 IIR_COEF_96_TO_44p1[48] = {
123
+
0x08b543, 0xfd80f4, 0x08b543, 0x0e2332, 0xe06ed0, 0x000002,
124
+
0x1b6038, 0xf90e7e, 0x1b6038, 0x0ec1ac, 0xe16f66, 0x000002,
125
+
0x188478, 0xfbb921, 0x188478, 0x105859, 0xe2e596, 0x000002,
126
+
0x13eff3, 0xffa707, 0x13eff3, 0x13455c, 0xe533b7, 0x000002,
127
+
0x0dc239, 0x03d458, 0x0dc239, 0x17f120, 0xe8b617, 0x000002,
128
+
0x0745f1, 0x05d790, 0x0745f1, 0x1e3d75, 0xed5f18, 0x000002,
129
+
0x05641f, 0x085e2b, 0x05641f, 0x48efd0, 0xe3e9c8, 0x000001,
130
+
0x000000, 0x28f632, 0x28f632, 0x273905, 0x000000, 0x000001,
131
+
};
132
+
133
+
static const u32 IIR_COEF_44p1_TO_16[48] = {
134
+
0x0998fb, 0xf7f925, 0x0998fb, 0x1e54a0, 0xe06605, 0x000002,
135
+
0x0d828e, 0xf50f97, 0x0d828e, 0x0f41b5, 0xf0a999, 0x000003,
136
+
0x17ebeb, 0xee30d8, 0x17ebeb, 0x1f48ca, 0xe2ae88, 0x000002,
137
+
0x12fab5, 0xf46ddc, 0x12fab5, 0x20cc51, 0xe4d068, 0x000002,
138
+
0x0c7ac6, 0xfbd00e, 0x0c7ac6, 0x2337da, 0xe8028c, 0x000002,
139
+
0x060ddc, 0x015b3e, 0x060ddc, 0x266754, 0xec21b6, 0x000002,
140
+
0x0407b5, 0x04f827, 0x0407b5, 0x52e3d0, 0xe0149f, 0x000001,
141
+
0x000000, 0x1f9521, 0x1f9521, 0x2ac116, 0x000000, 0x000001,
142
+
};
143
+
144
+
static const u32 IIR_COEF_48_TO_16[48] = {
145
+
0x0955ff, 0xf6544a, 0x0955ff, 0x2474e5, 0xe062e6, 0x000002,
146
+
0x0d4180, 0xf297f4, 0x0d4180, 0x12415b, 0xf0a3b0, 0x000003,
147
+
0x0ba079, 0xf4f0b0, 0x0ba079, 0x1285d3, 0xf1488b, 0x000003,
148
+
0x12247c, 0xf1033c, 0x12247c, 0x2625be, 0xe48e0d, 0x000002,
149
+
0x0b98e0, 0xf96d1a, 0x0b98e0, 0x27e79c, 0xe7798a, 0x000002,
150
+
0x055e3b, 0xffed09, 0x055e3b, 0x2a2e2d, 0xeb2854, 0x000002,
151
+
0x01a934, 0x01ca03, 0x01a934, 0x2c4fea, 0xee93ab, 0x000002,
152
+
0x000000, 0x1c46c5, 0x1c46c5, 0x2d37dc, 0x000000, 0x000001,
153
+
};
154
+
155
+
static const u32 IIR_COEF_96_TO_16[48] = {
156
+
0x0805a1, 0xf21ae3, 0x0805a1, 0x3840bb, 0xe02a2e, 0x000002,
157
+
0x0d5dd8, 0xe8f259, 0x0d5dd8, 0x1c0af6, 0xf04700, 0x000003,
158
+
0x0bb422, 0xec08d9, 0x0bb422, 0x1bfccc, 0xf09216, 0x000003,
159
+
0x08fde6, 0xf108be, 0x08fde6, 0x1bf096, 0xf10ae0, 0x000003,
160
+
0x0ae311, 0xeeeda3, 0x0ae311, 0x37c646, 0xe385f5, 0x000002,
161
+
0x044089, 0xfa7242, 0x044089, 0x37a785, 0xe56526, 0x000002,
162
+
0x00c75c, 0xffb947, 0x00c75c, 0x378ba3, 0xe72c5f, 0x000002,
163
+
0x000000, 0x0ef76e, 0x0ef76e, 0x377fda, 0x000000, 0x000001,
164
+
};
165
+
166
+
static const struct {
167
+
const u32 *coef;
168
+
unsigned int cnt;
169
+
} iir_coef_tbl_list[8] = {
170
+
/* 0: 0.9188 */
171
+
{ IIR_COEF_48_TO_44p1, ARRAY_SIZE(IIR_COEF_48_TO_44p1) },
172
+
/* 1: 0.7256 */
173
+
{ IIR_COEF_44p1_TO_32, ARRAY_SIZE(IIR_COEF_44p1_TO_32) },
174
+
/* 2: 0.6667 */
175
+
{ IIR_COEF_48_TO_32, ARRAY_SIZE(IIR_COEF_48_TO_32) },
176
+
/* 3: 0.5 */
177
+
{ IIR_COEF_32_TO_16, ARRAY_SIZE(IIR_COEF_32_TO_16) },
178
+
/* 4: 0.4594 */
179
+
{ IIR_COEF_96_TO_44p1, ARRAY_SIZE(IIR_COEF_96_TO_44p1) },
180
+
/* 5: 0.3628 */
181
+
{ IIR_COEF_44p1_TO_16, ARRAY_SIZE(IIR_COEF_44p1_TO_16) },
182
+
/* 6: 0.3333 */
183
+
{ IIR_COEF_48_TO_16, ARRAY_SIZE(IIR_COEF_48_TO_16) },
184
+
/* 7: 0.1667 */
185
+
{ IIR_COEF_96_TO_16, ARRAY_SIZE(IIR_COEF_96_TO_16) },
186
+
};
187
+
188
+
static const u32 freq_new_index[16] = {
189
+
0, 1, 2, 99, 3, 4, 5, 99, 6, 7, 8, 9, 10, 11, 12, 99
190
+
};
191
+
192
+
static const u32 iir_coef_tbl_matrix[13][13] = {
193
+
{/*0*/
194
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
195
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
196
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
197
+
},
198
+
{/*1*/
199
+
1, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
200
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
201
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
202
+
},
203
+
{/*2*/
204
+
2, 0, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
205
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
206
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
207
+
},
208
+
{/*3*/
209
+
3, IIR_INV_COEF, IIR_INV_COEF, IIR_NO_NEED, IIR_NO_NEED,
210
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
211
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
212
+
},
213
+
{/*4*/
214
+
5, 3, IIR_INV_COEF, 2, IIR_NO_NEED, IIR_NO_NEED,
215
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
216
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
217
+
},
218
+
{/*5*/
219
+
6, 4, 3, 2, 0, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
220
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
221
+
IIR_NO_NEED, IIR_NO_NEED
222
+
},
223
+
{/*6*/
224
+
IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF, 3, IIR_INV_COEF,
225
+
IIR_INV_COEF, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED,
226
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
227
+
},
228
+
{/*7*/
229
+
IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF, 5, 3,
230
+
IIR_INV_COEF, 1, IIR_NO_NEED, IIR_NO_NEED,
231
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
232
+
},
233
+
{/*8*/
234
+
7, IIR_INV_COEF, IIR_INV_COEF, 6, 4, 3, 2, 0, IIR_NO_NEED,
235
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
236
+
},
237
+
{/*9*/
238
+
IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF,
239
+
IIR_INV_COEF, IIR_INV_COEF, 5, 3, IIR_INV_COEF,
240
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
241
+
},
242
+
{/*10*/
243
+
IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF, 7, IIR_INV_COEF,
244
+
IIR_INV_COEF, 6, 4, 3, 0,
245
+
IIR_NO_NEED, IIR_NO_NEED, IIR_NO_NEED
246
+
},
247
+
{ /*11*/
248
+
IIR_RATIOVER, IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF,
249
+
IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF, IIR_INV_COEF,
250
+
IIR_INV_COEF, 3, IIR_INV_COEF, IIR_NO_NEED, IIR_NO_NEED
251
+
},
252
+
{/*12*/
253
+
IIR_RATIOVER, IIR_RATIOVER, IIR_INV_COEF, IIR_INV_COEF,
254
+
IIR_INV_COEF, IIR_INV_COEF, 7, IIR_INV_COEF,
255
+
IIR_INV_COEF, 4, 3, 0, IIR_NO_NEED
256
+
},
257
+
};
258
+
259
+
const u32 *coef = NULL;
260
+
unsigned int cnt = 0;
261
+
u32 i = freq_new_index[input_fs];
262
+
u32 j = freq_new_index[output_fs];
263
+
264
+
if (i < 13 && j < 13) {
265
+
u32 k = iir_coef_tbl_matrix[i][j];
266
+
267
+
if (k >= IIR_NO_NEED) {
268
+
} else if (k == IIR_RATIOVER) {
269
+
} else if (k == IIR_INV_COEF) {
270
+
} else {
271
+
coef = iir_coef_tbl_list[k].coef;
272
+
cnt = iir_coef_tbl_list[k].cnt;
273
+
}
274
+
}
275
+
*count = cnt;
276
+
return coef;
277
+
}
278
+
279
+
static int mt8365_dai_set_config(struct mtk_base_afe *afe,
280
+
struct mtk_afe_i2s_priv *i2s_data,
281
+
bool is_input, unsigned int rate,
282
+
int bit_width)
283
+
{
284
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
285
+
struct mt8365_be_dai_data *be =
286
+
&afe_priv->be_data[i2s_data->id - MT8365_AFE_BACKEND_BASE];
287
+
unsigned int val, reg_off;
288
+
int fs = mt8365_afe_fs_timing(rate);
289
+
290
+
if (fs < 0)
291
+
return -EINVAL;
292
+
293
+
val = AFE_I2S_CON_LOW_JITTER_CLK | AFE_I2S_CON_FORMAT_I2S;
294
+
val |= FIELD_PREP(AFE_I2S_CON_RATE_MASK, fs);
295
+
296
+
if (is_input) {
297
+
reg_off = i2s_data->reg_off_in;
298
+
if (i2s_data->adda_link)
299
+
val |= i2s_data->config_val_in;
300
+
} else {
301
+
reg_off = i2s_data->reg_off_out;
302
+
val |= i2s_data->config_val_in;
303
+
}
304
+
305
+
/* 1:bck=32lrck(16bit) or bck=64lrck(32bit) 0:fix bck=64lrck */
306
+
if (i2s_data->dynamic_bck) {
307
+
if (bit_width > 16)
308
+
val |= AFE_I2S_CON_WLEN_32BIT;
309
+
else
310
+
val &= ~(u32)AFE_I2S_CON_WLEN_32BIT;
311
+
} else {
312
+
val |= AFE_I2S_CON_WLEN_32BIT;
313
+
}
314
+
315
+
if ((be->fmt_mode & SND_SOC_DAIFMT_MASTER_MASK) ==
316
+
SND_SOC_DAIFMT_CBM_CFM) {
317
+
val |= AFE_I2S_CON_SRC_SLAVE;
318
+
val &= ~(u32)AFE_I2S_CON_FROM_IO_MUX;//from consys
319
+
}
320
+
321
+
regmap_update_bits(afe->regmap, reg_off, ~(u32)AFE_I2S_CON_EN, val);
322
+
323
+
if (i2s_data->adda_link && is_input)
324
+
regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1);
325
+
326
+
return 0;
327
+
}
328
+
329
+
int mt8365_afe_set_i2s_out(struct mtk_base_afe *afe,
330
+
unsigned int rate, int bit_width)
331
+
{
332
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
333
+
struct mtk_afe_i2s_priv *i2s_data =
334
+
afe_priv->dai_priv[MT8365_AFE_IO_I2S];
335
+
336
+
return mt8365_dai_set_config(afe, i2s_data, false, rate, bit_width);
337
+
}
338
+
339
+
static int mt8365_afe_set_2nd_i2s_asrc(struct mtk_base_afe *afe,
340
+
unsigned int rate_in,
341
+
unsigned int rate_out,
342
+
unsigned int width,
343
+
unsigned int mono,
344
+
int o16bit, int tracking)
345
+
{
346
+
int ifs, ofs = 0;
347
+
unsigned int val = 0;
348
+
unsigned int mask = 0;
349
+
const u32 *coef;
350
+
u32 iir_stage;
351
+
unsigned int coef_count = 0;
352
+
353
+
ifs = mt8365_afe_fs_timing(rate_in);
354
+
355
+
if (ifs < 0)
356
+
return -EINVAL;
357
+
358
+
ofs = mt8365_afe_fs_timing(rate_out);
359
+
360
+
if (ofs < 0)
361
+
return -EINVAL;
362
+
363
+
val = FIELD_PREP(O16BIT, o16bit) | FIELD_PREP(IS_MONO, mono);
364
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
365
+
O16BIT | IS_MONO, val);
366
+
367
+
coef = get_iir_coef(ifs, ofs, &coef_count);
368
+
iir_stage = ((u32)coef_count / 6) - 1;
369
+
370
+
if (coef) {
371
+
unsigned int i;
372
+
373
+
/* CPU control IIR coeff SRAM */
374
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
375
+
COEFF_SRAM_CTRL, COEFF_SRAM_CTRL);
376
+
377
+
/* set to 0, IIR coeff SRAM addr */
378
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON13,
379
+
0xffffffff, 0x0);
380
+
381
+
for (i = 0; i < coef_count; ++i)
382
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON12,
383
+
0xffffffff, coef[i]);
384
+
385
+
/* disable IIR coeff SRAM access */
386
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
387
+
COEFF_SRAM_CTRL,
388
+
(unsigned long)~COEFF_SRAM_CTRL);
389
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
390
+
CLR_IIR_HISTORY | IIR_EN | IIR_STAGE_MASK,
391
+
CLR_IIR_HISTORY | IIR_EN |
392
+
FIELD_PREP(IIR_STAGE_MASK, iir_stage));
393
+
} else {
394
+
/* disable IIR */
395
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
396
+
IIR_EN, (unsigned long)~IIR_EN);
397
+
}
398
+
399
+
/* CON3 setting (RX OFS) */
400
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON3,
401
+
0x00FFFFFF, rx_frequency_palette(ofs));
402
+
/* CON4 setting (RX IFS) */
403
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON4,
404
+
0x00FFFFFF, rx_frequency_palette(ifs));
405
+
406
+
/* CON5 setting */
407
+
if (tracking) {
408
+
val = CALI_64_CYCLE |
409
+
CALI_AUTORST |
410
+
AUTO_TUNE_FREQ5 |
411
+
COMP_FREQ_RES |
412
+
CALI_BP_DGL |
413
+
CALI_AUTO_RESTART |
414
+
CALI_USE_FREQ_OUT |
415
+
CALI_SEL_01;
416
+
417
+
mask = CALI_CYCLE_MASK |
418
+
CALI_AUTORST |
419
+
AUTO_TUNE_FREQ5 |
420
+
COMP_FREQ_RES |
421
+
CALI_SEL_MASK |
422
+
CALI_BP_DGL |
423
+
AUTO_TUNE_FREQ4 |
424
+
CALI_AUTO_RESTART |
425
+
CALI_USE_FREQ_OUT |
426
+
CALI_ON;
427
+
428
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5,
429
+
mask, val);
430
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5,
431
+
CALI_ON, CALI_ON);
432
+
} else {
433
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON5,
434
+
0xffffffff, 0x0);
435
+
}
436
+
/* CON6 setting fix 8125 */
437
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON6,
438
+
0x0000ffff, 0x1FBD);
439
+
/* CON9 setting (RX IFS) */
440
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON9,
441
+
0x000fffff, AutoRstThHi(ifs));
442
+
/* CON10 setting (RX IFS) */
443
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON10,
444
+
0x000fffff, AutoRstThLo(ifs));
445
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
446
+
CHSET_STR_CLR, CHSET_STR_CLR);
447
+
448
+
return 0;
449
+
}
450
+
451
+
static int mt8365_afe_set_2nd_i2s_asrc_enable(struct mtk_base_afe *afe,
452
+
bool enable)
453
+
{
454
+
if (enable)
455
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
456
+
ASM_ON, ASM_ON);
457
+
else
458
+
regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
459
+
ASM_ON, (unsigned long)~ASM_ON);
460
+
return 0;
461
+
}
462
+
463
+
void mt8365_afe_set_i2s_out_enable(struct mtk_base_afe *afe, bool enable)
464
+
{
465
+
int i;
466
+
unsigned long flags;
467
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
468
+
struct mtk_afe_i2s_priv *i2s_data;
469
+
470
+
for (i = 0; i < DAI_I2S_NUM; i++) {
471
+
if (mt8365_i2s_priv[i].adda_link)
472
+
i2s_data = afe_priv->dai_priv[mt8365_i2s_priv[i].id];
473
+
}
474
+
475
+
spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
476
+
477
+
if (enable) {
478
+
i2s_data->i2s_out_on_ref_cnt++;
479
+
if (i2s_data->i2s_out_on_ref_cnt == 1)
480
+
regmap_update_bits(afe->regmap, AFE_I2S_CON1,
481
+
0x1, enable);
482
+
} else {
483
+
i2s_data->i2s_out_on_ref_cnt--;
484
+
if (i2s_data->i2s_out_on_ref_cnt == 0)
485
+
regmap_update_bits(afe->regmap, AFE_I2S_CON1,
486
+
0x1, enable);
487
+
else if (i2s_data->i2s_out_on_ref_cnt < 0)
488
+
i2s_data->i2s_out_on_ref_cnt = 0;
489
+
}
490
+
491
+
spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
492
+
}
493
+
494
+
static void mt8365_dai_set_enable(struct mtk_base_afe *afe,
495
+
struct mtk_afe_i2s_priv *i2s_data,
496
+
bool is_input, bool enable)
497
+
{
498
+
unsigned int reg_off;
499
+
500
+
if (is_input) {
501
+
reg_off = i2s_data->reg_off_in;
502
+
} else {
503
+
if (i2s_data->adda_link) {
504
+
mt8365_afe_set_i2s_out_enable(afe, enable);
505
+
return;
506
+
}
507
+
reg_off = i2s_data->reg_off_out;
508
+
}
509
+
regmap_update_bits(afe->regmap, reg_off,
510
+
0x1, enable);
511
+
}
512
+
513
+
static int mt8365_dai_i2s_startup(struct snd_pcm_substream *substream,
514
+
struct snd_soc_dai *dai)
515
+
{
516
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
517
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
518
+
struct mtk_afe_i2s_priv *i2s_data = afe_priv->dai_priv[dai->id];
519
+
struct mt8365_be_dai_data *be = &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
520
+
bool i2s_in_slave =
521
+
(substream->stream == SNDRV_PCM_STREAM_CAPTURE) &&
522
+
((be->fmt_mode & SND_SOC_DAIFMT_MASTER_MASK) ==
523
+
SND_SOC_DAIFMT_CBM_CFM);
524
+
525
+
mt8365_afe_enable_main_clk(afe);
526
+
527
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
528
+
clk_prepare_enable(afe_priv->clocks[i2s_data->clk_id_out]);
529
+
530
+
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && !i2s_in_slave)
531
+
clk_prepare_enable(afe_priv->clocks[i2s_data->clk_id_in]);
532
+
533
+
if (i2s_in_slave)
534
+
mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_I2S_IN);
535
+
536
+
return 0;
537
+
}
538
+
539
+
static void mt8365_dai_i2s_shutdown(struct snd_pcm_substream *substream,
540
+
struct snd_soc_dai *dai)
541
+
{
542
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
543
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
544
+
struct mtk_afe_i2s_priv *i2s_data = afe_priv->dai_priv[dai->id];
545
+
struct mt8365_be_dai_data *be = &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
546
+
bool reset_i2s_out_change = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
547
+
bool reset_i2s_in_change = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
548
+
bool i2s_in_slave =
549
+
(substream->stream == SNDRV_PCM_STREAM_CAPTURE) &&
550
+
((be->fmt_mode & SND_SOC_DAIFMT_MASTER_MASK) ==
551
+
SND_SOC_DAIFMT_CBM_CFM);
552
+
553
+
if (be->prepared[substream->stream]) {
554
+
if (reset_i2s_out_change)
555
+
mt8365_dai_set_enable(afe, i2s_data, false, false);
556
+
557
+
if (reset_i2s_in_change)
558
+
mt8365_dai_set_enable(afe, i2s_data, true, false);
559
+
560
+
if (substream->runtime->rate % 8000)
561
+
mt8365_afe_disable_apll_associated_cfg(afe, MT8365_AFE_APLL1);
562
+
else
563
+
mt8365_afe_disable_apll_associated_cfg(afe, MT8365_AFE_APLL2);
564
+
565
+
if (reset_i2s_out_change)
566
+
be->prepared[SNDRV_PCM_STREAM_PLAYBACK] = false;
567
+
568
+
if (reset_i2s_in_change)
569
+
be->prepared[SNDRV_PCM_STREAM_CAPTURE] = false;
570
+
}
571
+
572
+
if (reset_i2s_out_change)
573
+
mt8365_afe_disable_clk(afe,
574
+
afe_priv->clocks[i2s_data->clk_id_out]);
575
+
576
+
if (reset_i2s_in_change && !i2s_in_slave)
577
+
mt8365_afe_disable_clk(afe,
578
+
afe_priv->clocks[i2s_data->clk_id_in]);
579
+
580
+
if (i2s_in_slave)
581
+
mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_I2S_IN);
582
+
583
+
mt8365_afe_disable_main_clk(afe);
584
+
}
585
+
586
+
static int mt8365_dai_i2s_prepare(struct snd_pcm_substream *substream,
587
+
struct snd_soc_dai *dai)
588
+
{
589
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
590
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
591
+
struct mtk_afe_i2s_priv *i2s_data = afe_priv->dai_priv[dai->id];
592
+
struct mt8365_be_dai_data *be = &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
593
+
bool apply_i2s_out_change = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
594
+
bool apply_i2s_in_change = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
595
+
unsigned int rate = substream->runtime->rate;
596
+
int bit_width = snd_pcm_format_width(substream->runtime->format);
597
+
int ret;
598
+
599
+
if (be->prepared[substream->stream]) {
600
+
dev_info(afe->dev, "%s '%s' prepared already\n",
601
+
__func__, snd_pcm_stream_str(substream));
602
+
return 0;
603
+
}
604
+
605
+
if (apply_i2s_out_change) {
606
+
ret = mt8365_dai_set_config(afe, i2s_data, false, rate, bit_width);
607
+
if (ret)
608
+
return ret;
609
+
}
610
+
611
+
if (apply_i2s_in_change) {
612
+
if ((be->fmt_mode & SND_SOC_DAIFMT_MASTER_MASK)
613
+
== SND_SOC_DAIFMT_CBM_CFM) {
614
+
ret = mt8365_afe_set_2nd_i2s_asrc(afe, 32000, rate,
615
+
(unsigned int)bit_width,
616
+
0, 0, 1);
617
+
if (ret < 0)
618
+
return ret;
619
+
}
620
+
ret = mt8365_dai_set_config(afe, i2s_data, true, rate, bit_width);
621
+
if (ret)
622
+
return ret;
623
+
}
624
+
625
+
if (rate % 8000)
626
+
mt8365_afe_enable_apll_associated_cfg(afe, MT8365_AFE_APLL1);
627
+
else
628
+
mt8365_afe_enable_apll_associated_cfg(afe, MT8365_AFE_APLL2);
629
+
630
+
if (apply_i2s_out_change) {
631
+
mt8365_afe_set_clk_parent(afe,
632
+
afe_priv->clocks[i2s_data->clk_id_out_m_sel],
633
+
((rate % 8000) ?
634
+
afe_priv->clocks[MT8365_CLK_AUD1] :
635
+
afe_priv->clocks[MT8365_CLK_AUD2]));
636
+
637
+
mt8365_afe_set_clk_rate(afe,
638
+
afe_priv->clocks[i2s_data->clk_id_out],
639
+
rate * i2s_data->clk_out_mult);
640
+
641
+
mt8365_dai_set_enable(afe, i2s_data, false, true);
642
+
be->prepared[SNDRV_PCM_STREAM_PLAYBACK] = true;
643
+
}
644
+
645
+
if (apply_i2s_in_change) {
646
+
mt8365_afe_set_clk_parent(afe,
647
+
afe_priv->clocks[i2s_data->clk_id_in_m_sel],
648
+
((rate % 8000) ?
649
+
afe_priv->clocks[MT8365_CLK_AUD1] :
650
+
afe_priv->clocks[MT8365_CLK_AUD2]));
651
+
652
+
mt8365_afe_set_clk_rate(afe,
653
+
afe_priv->clocks[i2s_data->clk_id_in],
654
+
rate * i2s_data->clk_in_mult);
655
+
656
+
mt8365_dai_set_enable(afe, i2s_data, true, true);
657
+
658
+
if ((be->fmt_mode & SND_SOC_DAIFMT_MASTER_MASK)
659
+
== SND_SOC_DAIFMT_CBM_CFM)
660
+
mt8365_afe_set_2nd_i2s_asrc_enable(afe, true);
661
+
662
+
be->prepared[SNDRV_PCM_STREAM_CAPTURE] = true;
663
+
}
664
+
return 0;
665
+
}
666
+
667
+
static int mt8365_afe_2nd_i2s_hw_params(struct snd_pcm_substream *substream,
668
+
struct snd_pcm_hw_params *params,
669
+
struct snd_soc_dai *dai)
670
+
{
671
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
672
+
unsigned int width_val = params_width(params) > 16 ?
673
+
(AFE_CONN_24BIT_O00 | AFE_CONN_24BIT_O01) : 0;
674
+
675
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
676
+
regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
677
+
AFE_CONN_24BIT_O00 | AFE_CONN_24BIT_O01, width_val);
678
+
679
+
return 0;
680
+
}
681
+
682
+
static int mt8365_afe_2nd_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
683
+
{
684
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
685
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
686
+
struct mt8365_be_dai_data *be = &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE];
687
+
688
+
be->fmt_mode = 0;
689
+
690
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
691
+
case SND_SOC_DAIFMT_I2S:
692
+
be->fmt_mode |= SND_SOC_DAIFMT_I2S;
693
+
break;
694
+
case SND_SOC_DAIFMT_LEFT_J:
695
+
be->fmt_mode |= SND_SOC_DAIFMT_LEFT_J;
696
+
break;
697
+
default:
698
+
dev_err(afe->dev, "invalid audio format for 2nd i2s!\n");
699
+
return -EINVAL;
700
+
}
701
+
702
+
if (((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) &&
703
+
((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_IF) &&
704
+
((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_IB_NF) &&
705
+
((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_IB_IF)) {
706
+
dev_err(afe->dev, "invalid audio format for 2nd i2s!\n");
707
+
return -EINVAL;
708
+
}
709
+
710
+
be->fmt_mode |= (fmt & SND_SOC_DAIFMT_INV_MASK);
711
+
712
+
if (((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM))
713
+
be->fmt_mode |= (fmt & SND_SOC_DAIFMT_MASTER_MASK);
714
+
715
+
return 0;
716
+
}
717
+
718
+
static const struct snd_soc_dai_ops mt8365_afe_i2s_ops = {
719
+
.startup = mt8365_dai_i2s_startup,
720
+
.shutdown = mt8365_dai_i2s_shutdown,
721
+
.prepare = mt8365_dai_i2s_prepare,
722
+
};
723
+
724
+
static const struct snd_soc_dai_ops mt8365_afe_2nd_i2s_ops = {
725
+
.startup = mt8365_dai_i2s_startup,
726
+
.shutdown = mt8365_dai_i2s_shutdown,
727
+
.hw_params = mt8365_afe_2nd_i2s_hw_params,
728
+
.prepare = mt8365_dai_i2s_prepare,
729
+
.set_fmt = mt8365_afe_2nd_i2s_set_fmt,
730
+
};
731
+
732
+
static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
733
+
{
734
+
.name = "I2S",
735
+
.id = MT8365_AFE_IO_I2S,
736
+
.playback = {
737
+
.stream_name = "I2S Playback",
738
+
.channels_min = 1,
739
+
.channels_max = 2,
740
+
.rates = SNDRV_PCM_RATE_8000_192000,
741
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
742
+
SNDRV_PCM_FMTBIT_S24_LE |
743
+
SNDRV_PCM_FMTBIT_S32_LE,
744
+
},
745
+
.capture = {
746
+
.stream_name = "I2S Capture",
747
+
.channels_min = 1,
748
+
.channels_max = 2,
749
+
.rates = SNDRV_PCM_RATE_8000_192000,
750
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
751
+
SNDRV_PCM_FMTBIT_S24_LE |
752
+
SNDRV_PCM_FMTBIT_S32_LE,
753
+
},
754
+
.ops = &mt8365_afe_i2s_ops,
755
+
}, {
756
+
.name = "2ND I2S",
757
+
.id = MT8365_AFE_IO_2ND_I2S,
758
+
.playback = {
759
+
.stream_name = "2ND I2S Playback",
760
+
.channels_min = 1,
761
+
.channels_max = 2,
762
+
.rates = SNDRV_PCM_RATE_8000_192000,
763
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
764
+
SNDRV_PCM_FMTBIT_S24_LE |
765
+
SNDRV_PCM_FMTBIT_S32_LE,
766
+
},
767
+
.capture = {
768
+
.stream_name = "2ND I2S Capture",
769
+
.channels_min = 1,
770
+
.channels_max = 2,
771
+
.rates = SNDRV_PCM_RATE_8000_192000,
772
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
773
+
SNDRV_PCM_FMTBIT_S24_LE |
774
+
SNDRV_PCM_FMTBIT_S32_LE,
775
+
},
776
+
.ops = &mt8365_afe_2nd_i2s_ops,
777
+
}
778
+
};
779
+
780
+
/* low jitter control */
781
+
static const char * const mt8365_i2s_hd_str[] = {
782
+
"Normal", "Low_Jitter"
783
+
};
784
+
785
+
static SOC_ENUM_SINGLE_EXT_DECL(mt8365_i2s_enum, mt8365_i2s_hd_str);
786
+
787
+
static const char * const fmi2sin_text[] = {
788
+
"OPEN", "FM_2ND_I2S_IN"
789
+
};
790
+
791
+
static SOC_ENUM_SINGLE_VIRT_DECL(fmi2sin_enum, fmi2sin_text);
792
+
793
+
static const struct snd_kcontrol_new fmi2sin_mux =
794
+
SOC_DAPM_ENUM("FM 2ND I2S Source", fmi2sin_enum);
795
+
796
+
static const struct snd_kcontrol_new i2s_o03_o04_enable_ctl =
797
+
SOC_DAPM_SINGLE_VIRT("Switch", 1);
798
+
799
+
static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
800
+
SND_SOC_DAPM_SWITCH("I2S O03_O04", SND_SOC_NOPM, 0, 0,
801
+
&i2s_o03_o04_enable_ctl),
802
+
SND_SOC_DAPM_MUX("FM 2ND I2S Mux", SND_SOC_NOPM, 0, 0, &fmi2sin_mux),
803
+
SND_SOC_DAPM_INPUT("2ND I2S In"),
804
+
};
805
+
806
+
static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
807
+
{"I2S O03_O04", "Switch", "O03"},
808
+
{"I2S O03_O04", "Switch", "O04"},
809
+
{"I2S Playback", NULL, "I2S O03_O04"},
810
+
{"2ND I2S Playback", NULL, "O00"},
811
+
{"2ND I2S Playback", NULL, "O01"},
812
+
{"2ND I2S Capture", NULL, "2ND I2S In"},
813
+
{"FM 2ND I2S Mux", "FM_2ND_I2S_IN", "2ND I2S Capture"},
814
+
};
815
+
816
+
static int mt8365_dai_i2s_set_priv(struct mtk_base_afe *afe)
817
+
{
818
+
int i, ret;
819
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
820
+
821
+
for (i = 0; i < DAI_I2S_NUM; i++) {
822
+
ret = mt8365_dai_set_priv(afe, mt8365_i2s_priv[i].id,
823
+
sizeof(*afe_priv),
824
+
&mt8365_i2s_priv[i]);
825
+
if (ret)
826
+
return ret;
827
+
}
828
+
return 0;
829
+
}
830
+
831
+
int mt8365_dai_i2s_register(struct mtk_base_afe *afe)
832
+
{
833
+
struct mtk_base_afe_dai *dai;
834
+
835
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
836
+
if (!dai)
837
+
return -ENOMEM;
838
+
839
+
list_add(&dai->list, &afe->sub_dais);
840
+
841
+
dai->dai_drivers = mtk_dai_i2s_driver;
842
+
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
843
+
dai->dapm_widgets = mtk_dai_i2s_widgets;
844
+
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
845
+
dai->dapm_routes = mtk_dai_i2s_routes;
846
+
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
847
+
848
+
/* set all dai i2s private data */
849
+
return mt8365_dai_i2s_set_priv(afe);
850
+
}
+293
sound/soc/mediatek/mt8365/mt8365-dai-pcm.c
+293
sound/soc/mediatek/mt8365/mt8365-dai-pcm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek 8365 ALSA SoC Audio DAI PCM Control
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#include <linux/bitops.h>
11
+
#include <linux/regmap.h>
12
+
#include <sound/pcm_params.h>
13
+
#include "mt8365-afe-clk.h"
14
+
#include "mt8365-afe-common.h"
15
+
16
+
struct mt8365_pcm_intf_data {
17
+
bool slave_mode;
18
+
bool lrck_inv;
19
+
bool bck_inv;
20
+
unsigned int format;
21
+
};
22
+
23
+
/* DAI Drivers */
24
+
25
+
static void mt8365_dai_enable_pcm1(struct mtk_base_afe *afe)
26
+
{
27
+
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
28
+
PCM_INTF_CON1_EN, PCM_INTF_CON1_EN);
29
+
}
30
+
31
+
static void mt8365_dai_disable_pcm1(struct mtk_base_afe *afe)
32
+
{
33
+
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
34
+
PCM_INTF_CON1_EN, 0x0);
35
+
}
36
+
37
+
static int mt8365_dai_configure_pcm1(struct snd_pcm_substream *substream,
38
+
struct snd_soc_dai *dai)
39
+
{
40
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
41
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
42
+
struct mt8365_pcm_intf_data *pcm_priv = afe_priv->dai_priv[MT8365_AFE_IO_PCM1];
43
+
bool slave_mode = pcm_priv->slave_mode;
44
+
bool lrck_inv = pcm_priv->lrck_inv;
45
+
bool bck_inv = pcm_priv->bck_inv;
46
+
unsigned int fmt = pcm_priv->format;
47
+
unsigned int bit_width = dai->sample_bits;
48
+
unsigned int val = 0;
49
+
50
+
if (!slave_mode) {
51
+
val |= PCM_INTF_CON1_MASTER_MODE |
52
+
PCM_INTF_CON1_BYPASS_ASRC;
53
+
54
+
if (lrck_inv)
55
+
val |= PCM_INTF_CON1_SYNC_OUT_INV;
56
+
if (bck_inv)
57
+
val |= PCM_INTF_CON1_BCLK_OUT_INV;
58
+
} else {
59
+
val |= PCM_INTF_CON1_SLAVE_MODE;
60
+
61
+
if (lrck_inv)
62
+
val |= PCM_INTF_CON1_SYNC_IN_INV;
63
+
if (bck_inv)
64
+
val |= PCM_INTF_CON1_BCLK_IN_INV;
65
+
66
+
/* TODO: add asrc setting */
67
+
}
68
+
69
+
val |= FIELD_PREP(PCM_INTF_CON1_FORMAT_MASK, fmt);
70
+
71
+
if (fmt == MT8365_PCM_FORMAT_PCMA ||
72
+
fmt == MT8365_PCM_FORMAT_PCMB)
73
+
val |= PCM_INTF_CON1_SYNC_LEN(1);
74
+
else
75
+
val |= PCM_INTF_CON1_SYNC_LEN(bit_width);
76
+
77
+
switch (substream->runtime->rate) {
78
+
case 48000:
79
+
val |= PCM_INTF_CON1_FS_48K;
80
+
break;
81
+
case 32000:
82
+
val |= PCM_INTF_CON1_FS_32K;
83
+
break;
84
+
case 16000:
85
+
val |= PCM_INTF_CON1_FS_16K;
86
+
break;
87
+
case 8000:
88
+
val |= PCM_INTF_CON1_FS_8K;
89
+
break;
90
+
default:
91
+
return -EINVAL;
92
+
}
93
+
94
+
if (bit_width > 16)
95
+
val |= PCM_INTF_CON1_24BIT | PCM_INTF_CON1_64BCK;
96
+
else
97
+
val |= PCM_INTF_CON1_16BIT | PCM_INTF_CON1_32BCK;
98
+
99
+
val |= PCM_INTF_CON1_EXT_MODEM;
100
+
101
+
regmap_update_bits(afe->regmap, PCM_INTF_CON1,
102
+
PCM_INTF_CON1_CONFIG_MASK, val);
103
+
104
+
return 0;
105
+
}
106
+
107
+
static int mt8365_dai_pcm1_startup(struct snd_pcm_substream *substream,
108
+
struct snd_soc_dai *dai)
109
+
{
110
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
111
+
112
+
if (snd_soc_dai_active(dai))
113
+
return 0;
114
+
115
+
mt8365_afe_enable_main_clk(afe);
116
+
117
+
return 0;
118
+
}
119
+
120
+
static void mt8365_dai_pcm1_shutdown(struct snd_pcm_substream *substream,
121
+
struct snd_soc_dai *dai)
122
+
{
123
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
124
+
125
+
if (snd_soc_dai_active(dai))
126
+
return;
127
+
128
+
mt8365_dai_disable_pcm1(afe);
129
+
mt8365_afe_disable_main_clk(afe);
130
+
}
131
+
132
+
static int mt8365_dai_pcm1_prepare(struct snd_pcm_substream *substream,
133
+
struct snd_soc_dai *dai)
134
+
{
135
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
136
+
int ret;
137
+
138
+
if ((snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK) +
139
+
snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE)) > 1) {
140
+
dev_info(afe->dev, "%s '%s' active(%u-%u) already\n",
141
+
__func__, snd_pcm_stream_str(substream),
142
+
snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK),
143
+
snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE));
144
+
return 0;
145
+
}
146
+
147
+
ret = mt8365_dai_configure_pcm1(substream, dai);
148
+
if (ret)
149
+
return ret;
150
+
151
+
mt8365_dai_enable_pcm1(afe);
152
+
153
+
return 0;
154
+
}
155
+
156
+
static int mt8365_dai_pcm1_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
157
+
{
158
+
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
159
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
160
+
struct mt8365_pcm_intf_data *pcm_priv = afe_priv->dai_priv[MT8365_AFE_IO_PCM1];
161
+
162
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
163
+
case SND_SOC_DAIFMT_I2S:
164
+
pcm_priv->format = MT8365_PCM_FORMAT_I2S;
165
+
break;
166
+
default:
167
+
return -EINVAL;
168
+
}
169
+
170
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
171
+
case SND_SOC_DAIFMT_NB_NF:
172
+
pcm_priv->bck_inv = false;
173
+
pcm_priv->lrck_inv = false;
174
+
break;
175
+
case SND_SOC_DAIFMT_NB_IF:
176
+
pcm_priv->bck_inv = false;
177
+
pcm_priv->lrck_inv = true;
178
+
break;
179
+
case SND_SOC_DAIFMT_IB_NF:
180
+
pcm_priv->bck_inv = true;
181
+
pcm_priv->lrck_inv = false;
182
+
break;
183
+
case SND_SOC_DAIFMT_IB_IF:
184
+
pcm_priv->bck_inv = true;
185
+
pcm_priv->lrck_inv = true;
186
+
break;
187
+
default:
188
+
return -EINVAL;
189
+
}
190
+
191
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
192
+
case SND_SOC_DAIFMT_CBM_CFM:
193
+
pcm_priv->slave_mode = true;
194
+
break;
195
+
case SND_SOC_DAIFMT_CBS_CFS:
196
+
pcm_priv->slave_mode = false;
197
+
break;
198
+
default:
199
+
return -EINVAL;
200
+
}
201
+
202
+
return 0;
203
+
}
204
+
205
+
static const struct snd_soc_dai_ops mt8365_dai_pcm1_ops = {
206
+
.startup = mt8365_dai_pcm1_startup,
207
+
.shutdown = mt8365_dai_pcm1_shutdown,
208
+
.prepare = mt8365_dai_pcm1_prepare,
209
+
.set_fmt = mt8365_dai_pcm1_set_fmt,
210
+
};
211
+
212
+
static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
213
+
{
214
+
.name = "PCM1",
215
+
.id = MT8365_AFE_IO_PCM1,
216
+
.playback = {
217
+
.stream_name = "PCM1 Playback",
218
+
.channels_min = 1,
219
+
.channels_max = 2,
220
+
.rates = SNDRV_PCM_RATE_8000 |
221
+
SNDRV_PCM_RATE_16000 |
222
+
SNDRV_PCM_RATE_32000 |
223
+
SNDRV_PCM_RATE_48000,
224
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
225
+
SNDRV_PCM_FMTBIT_S32_LE,
226
+
},
227
+
.capture = {
228
+
.stream_name = "PCM1 Capture",
229
+
.channels_min = 1,
230
+
.channels_max = 2,
231
+
.rates = SNDRV_PCM_RATE_8000 |
232
+
SNDRV_PCM_RATE_16000 |
233
+
SNDRV_PCM_RATE_32000 |
234
+
SNDRV_PCM_RATE_48000,
235
+
.formats = SNDRV_PCM_FMTBIT_S16_LE |
236
+
SNDRV_PCM_FMTBIT_S32_LE,
237
+
},
238
+
.ops = &mt8365_dai_pcm1_ops,
239
+
.symmetric_rate = 1,
240
+
.symmetric_sample_bits = 1,
241
+
}
242
+
};
243
+
244
+
/* DAI widget */
245
+
246
+
static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
247
+
SND_SOC_DAPM_OUTPUT("PCM1 Out"),
248
+
SND_SOC_DAPM_INPUT("PCM1 In"),
249
+
};
250
+
251
+
/* DAI route */
252
+
253
+
static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
254
+
{"PCM1 Playback", NULL, "O07"},
255
+
{"PCM1 Playback", NULL, "O08"},
256
+
{"PCM1 Out", NULL, "PCM1 Playback"},
257
+
258
+
{"I09", NULL, "PCM1 Capture"},
259
+
{"I22", NULL, "PCM1 Capture"},
260
+
{"PCM1 Capture", NULL, "PCM1 In"},
261
+
};
262
+
263
+
static int init_pcmif_priv_data(struct mtk_base_afe *afe)
264
+
{
265
+
struct mt8365_afe_private *afe_priv = afe->platform_priv;
266
+
struct mt8365_pcm_intf_data *pcmif_priv;
267
+
268
+
pcmif_priv = devm_kzalloc(afe->dev, sizeof(struct mt8365_pcm_intf_data),
269
+
GFP_KERNEL);
270
+
if (!pcmif_priv)
271
+
return -ENOMEM;
272
+
273
+
afe_priv->dai_priv[MT8365_AFE_IO_PCM1] = pcmif_priv;
274
+
return 0;
275
+
}
276
+
277
+
int mt8365_dai_pcm_register(struct mtk_base_afe *afe)
278
+
{
279
+
struct mtk_base_afe_dai *dai;
280
+
281
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
282
+
if (!dai)
283
+
return -ENOMEM;
284
+
285
+
list_add(&dai->list, &afe->sub_dais);
286
+
dai->dai_drivers = mtk_dai_pcm_driver;
287
+
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
288
+
dai->dapm_widgets = mtk_dai_pcm_widgets;
289
+
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
290
+
dai->dapm_routes = mtk_dai_pcm_routes;
291
+
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
292
+
return init_pcmif_priv_data(afe);
293
+
}
+345
sound/soc/mediatek/mt8365/mt8365-mt6357.c
+345
sound/soc/mediatek/mt8365/mt8365-mt6357.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek MT8365 Sound Card driver
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Nicolas Belin <nbelin@baylibre.com>
7
+
*/
8
+
9
+
#include <linux/module.h>
10
+
#include <linux/of_gpio.h>
11
+
#include <sound/soc.h>
12
+
#include <sound/pcm_params.h>
13
+
#include "mt8365-afe-common.h"
14
+
#include <linux/pinctrl/consumer.h>
15
+
#include "../common/mtk-soc-card.h"
16
+
#include "../common/mtk-soundcard-driver.h"
17
+
18
+
enum pinctrl_pin_state {
19
+
PIN_STATE_DEFAULT,
20
+
PIN_STATE_DMIC,
21
+
PIN_STATE_MISO_OFF,
22
+
PIN_STATE_MISO_ON,
23
+
PIN_STATE_MOSI_OFF,
24
+
PIN_STATE_MOSI_ON,
25
+
PIN_STATE_MAX
26
+
};
27
+
28
+
static const char * const mt8365_mt6357_pin_str[PIN_STATE_MAX] = {
29
+
"default",
30
+
"dmic",
31
+
"miso_off",
32
+
"miso_on",
33
+
"mosi_off",
34
+
"mosi_on",
35
+
};
36
+
37
+
struct mt8365_mt6357_priv {
38
+
struct pinctrl *pinctrl;
39
+
struct pinctrl_state *pin_states[PIN_STATE_MAX];
40
+
};
41
+
42
+
enum {
43
+
/* FE */
44
+
DAI_LINK_DL1_PLAYBACK = 0,
45
+
DAI_LINK_DL2_PLAYBACK,
46
+
DAI_LINK_AWB_CAPTURE,
47
+
DAI_LINK_VUL_CAPTURE,
48
+
/* BE */
49
+
DAI_LINK_2ND_I2S_INTF,
50
+
DAI_LINK_DMIC,
51
+
DAI_LINK_INT_ADDA,
52
+
DAI_LINK_NUM
53
+
};
54
+
55
+
static const struct snd_soc_dapm_widget mt8365_mt6357_widgets[] = {
56
+
SND_SOC_DAPM_OUTPUT("HDMI Out"),
57
+
};
58
+
59
+
static const struct snd_soc_dapm_route mt8365_mt6357_routes[] = {
60
+
{"HDMI Out", NULL, "2ND I2S Playback"},
61
+
{"DMIC In", NULL, "MICBIAS0"},
62
+
};
63
+
64
+
static int mt8365_mt6357_int_adda_startup(struct snd_pcm_substream *substream)
65
+
{
66
+
struct snd_soc_pcm_runtime *rtd = substream->private_data;
67
+
struct mt8365_mt6357_priv *priv = snd_soc_card_get_drvdata(rtd->card);
68
+
int ret = 0;
69
+
70
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
71
+
if (IS_ERR(priv->pin_states[PIN_STATE_MOSI_ON]))
72
+
return ret;
73
+
74
+
ret = pinctrl_select_state(priv->pinctrl,
75
+
priv->pin_states[PIN_STATE_MOSI_ON]);
76
+
if (ret)
77
+
dev_err(rtd->card->dev, "%s failed to select state %d\n",
78
+
__func__, ret);
79
+
}
80
+
81
+
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
82
+
if (IS_ERR(priv->pin_states[PIN_STATE_MISO_ON]))
83
+
return ret;
84
+
85
+
ret = pinctrl_select_state(priv->pinctrl,
86
+
priv->pin_states[PIN_STATE_MISO_ON]);
87
+
if (ret)
88
+
dev_err(rtd->card->dev, "%s failed to select state %d\n",
89
+
__func__, ret);
90
+
}
91
+
92
+
return 0;
93
+
}
94
+
95
+
static void mt8365_mt6357_int_adda_shutdown(struct snd_pcm_substream *substream)
96
+
{
97
+
struct snd_soc_pcm_runtime *rtd = substream->private_data;
98
+
struct mt8365_mt6357_priv *priv = snd_soc_card_get_drvdata(rtd->card);
99
+
int ret = 0;
100
+
101
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
102
+
if (IS_ERR(priv->pin_states[PIN_STATE_MOSI_OFF]))
103
+
return;
104
+
105
+
ret = pinctrl_select_state(priv->pinctrl,
106
+
priv->pin_states[PIN_STATE_MOSI_OFF]);
107
+
if (ret)
108
+
dev_err(rtd->card->dev, "%s failed to select state %d\n",
109
+
__func__, ret);
110
+
}
111
+
112
+
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
113
+
if (IS_ERR(priv->pin_states[PIN_STATE_MISO_OFF]))
114
+
return;
115
+
116
+
ret = pinctrl_select_state(priv->pinctrl,
117
+
priv->pin_states[PIN_STATE_MISO_OFF]);
118
+
if (ret)
119
+
dev_err(rtd->card->dev, "%s failed to select state %d\n",
120
+
__func__, ret);
121
+
}
122
+
}
123
+
124
+
static const struct snd_soc_ops mt8365_mt6357_int_adda_ops = {
125
+
.startup = mt8365_mt6357_int_adda_startup,
126
+
.shutdown = mt8365_mt6357_int_adda_shutdown,
127
+
};
128
+
129
+
SND_SOC_DAILINK_DEFS(playback1,
130
+
DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
131
+
DAILINK_COMP_ARRAY(COMP_DUMMY()),
132
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
133
+
SND_SOC_DAILINK_DEFS(playback2,
134
+
DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
135
+
DAILINK_COMP_ARRAY(COMP_DUMMY()),
136
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
137
+
SND_SOC_DAILINK_DEFS(awb_capture,
138
+
DAILINK_COMP_ARRAY(COMP_CPU("AWB")),
139
+
DAILINK_COMP_ARRAY(COMP_DUMMY()),
140
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
141
+
SND_SOC_DAILINK_DEFS(vul,
142
+
DAILINK_COMP_ARRAY(COMP_CPU("VUL")),
143
+
DAILINK_COMP_ARRAY(COMP_DUMMY()),
144
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
145
+
146
+
SND_SOC_DAILINK_DEFS(i2s3,
147
+
DAILINK_COMP_ARRAY(COMP_CPU("2ND I2S")),
148
+
DAILINK_COMP_ARRAY(COMP_DUMMY()),
149
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
150
+
SND_SOC_DAILINK_DEFS(dmic,
151
+
DAILINK_COMP_ARRAY(COMP_CPU("DMIC")),
152
+
DAILINK_COMP_ARRAY(COMP_DUMMY()),
153
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
154
+
SND_SOC_DAILINK_DEFS(primary_codec,
155
+
DAILINK_COMP_ARRAY(COMP_CPU("INT ADDA")),
156
+
DAILINK_COMP_ARRAY(COMP_CODEC("mt6357-sound", "mt6357-snd-codec-aif1")),
157
+
DAILINK_COMP_ARRAY(COMP_EMPTY()));
158
+
159
+
/* Digital audio interface glue - connects codec <---> CPU */
160
+
static struct snd_soc_dai_link mt8365_mt6357_dais[] = {
161
+
/* Front End DAI links */
162
+
[DAI_LINK_DL1_PLAYBACK] = {
163
+
.name = "DL1_FE",
164
+
.stream_name = "MultiMedia1_PLayback",
165
+
.id = DAI_LINK_DL1_PLAYBACK,
166
+
.trigger = {
167
+
SND_SOC_DPCM_TRIGGER_POST,
168
+
SND_SOC_DPCM_TRIGGER_POST
169
+
},
170
+
.dynamic = 1,
171
+
.dpcm_playback = 1,
172
+
.dpcm_merged_rate = 1,
173
+
SND_SOC_DAILINK_REG(playback1),
174
+
},
175
+
[DAI_LINK_DL2_PLAYBACK] = {
176
+
.name = "DL2_FE",
177
+
.stream_name = "MultiMedia2_PLayback",
178
+
.id = DAI_LINK_DL2_PLAYBACK,
179
+
.trigger = {
180
+
SND_SOC_DPCM_TRIGGER_POST,
181
+
SND_SOC_DPCM_TRIGGER_POST
182
+
},
183
+
.dynamic = 1,
184
+
.dpcm_playback = 1,
185
+
.dpcm_merged_rate = 1,
186
+
SND_SOC_DAILINK_REG(playback2),
187
+
},
188
+
[DAI_LINK_AWB_CAPTURE] = {
189
+
.name = "AWB_FE",
190
+
.stream_name = "DL1_AWB_Record",
191
+
.id = DAI_LINK_AWB_CAPTURE,
192
+
.trigger = {
193
+
SND_SOC_DPCM_TRIGGER_POST,
194
+
SND_SOC_DPCM_TRIGGER_POST
195
+
},
196
+
.dynamic = 1,
197
+
.dpcm_capture = 1,
198
+
.dpcm_merged_rate = 1,
199
+
SND_SOC_DAILINK_REG(awb_capture),
200
+
},
201
+
[DAI_LINK_VUL_CAPTURE] = {
202
+
.name = "VUL_FE",
203
+
.stream_name = "MultiMedia1_Capture",
204
+
.id = DAI_LINK_VUL_CAPTURE,
205
+
.trigger = {
206
+
SND_SOC_DPCM_TRIGGER_POST,
207
+
SND_SOC_DPCM_TRIGGER_POST
208
+
},
209
+
.dynamic = 1,
210
+
.dpcm_capture = 1,
211
+
.dpcm_merged_rate = 1,
212
+
SND_SOC_DAILINK_REG(vul),
213
+
},
214
+
/* Back End DAI links */
215
+
[DAI_LINK_2ND_I2S_INTF] = {
216
+
.name = "I2S_OUT_BE",
217
+
.no_pcm = 1,
218
+
.id = DAI_LINK_2ND_I2S_INTF,
219
+
.dai_fmt = SND_SOC_DAIFMT_I2S |
220
+
SND_SOC_DAIFMT_NB_NF |
221
+
SND_SOC_DAIFMT_CBS_CFS,
222
+
.dpcm_playback = 1,
223
+
.dpcm_capture = 1,
224
+
SND_SOC_DAILINK_REG(i2s3),
225
+
},
226
+
[DAI_LINK_DMIC] = {
227
+
.name = "DMIC_BE",
228
+
.no_pcm = 1,
229
+
.id = DAI_LINK_DMIC,
230
+
.dpcm_capture = 1,
231
+
SND_SOC_DAILINK_REG(dmic),
232
+
},
233
+
[DAI_LINK_INT_ADDA] = {
234
+
.name = "MTK_Codec",
235
+
.no_pcm = 1,
236
+
.id = DAI_LINK_INT_ADDA,
237
+
.dpcm_playback = 1,
238
+
.dpcm_capture = 1,
239
+
.ops = &mt8365_mt6357_int_adda_ops,
240
+
SND_SOC_DAILINK_REG(primary_codec),
241
+
},
242
+
};
243
+
244
+
static int mt8365_mt6357_gpio_probe(struct snd_soc_card *card)
245
+
{
246
+
struct mt8365_mt6357_priv *priv = snd_soc_card_get_drvdata(card);
247
+
int ret, i;
248
+
249
+
priv->pinctrl = devm_pinctrl_get(card->dev);
250
+
if (IS_ERR(priv->pinctrl)) {
251
+
ret = PTR_ERR(priv->pinctrl);
252
+
return dev_err_probe(card->dev, ret,
253
+
"Failed to get pinctrl\n");
254
+
}
255
+
256
+
for (i = PIN_STATE_DEFAULT ; i < PIN_STATE_MAX ; i++) {
257
+
priv->pin_states[i] = pinctrl_lookup_state(priv->pinctrl,
258
+
mt8365_mt6357_pin_str[i]);
259
+
if (IS_ERR(priv->pin_states[i])) {
260
+
ret = PTR_ERR(priv->pin_states[i]);
261
+
dev_warn(card->dev, "No pin state for %s\n",
262
+
mt8365_mt6357_pin_str[i]);
263
+
} else {
264
+
ret = pinctrl_select_state(priv->pinctrl,
265
+
priv->pin_states[i]);
266
+
if (ret) {
267
+
dev_err_probe(card->dev, ret,
268
+
"Failed to select pin state %s\n",
269
+
mt8365_mt6357_pin_str[i]);
270
+
return ret;
271
+
}
272
+
}
273
+
}
274
+
return 0;
275
+
}
276
+
277
+
static struct snd_soc_card mt8365_mt6357_soc_card = {
278
+
.name = "mt8365-evk",
279
+
.owner = THIS_MODULE,
280
+
.dai_link = mt8365_mt6357_dais,
281
+
.num_links = ARRAY_SIZE(mt8365_mt6357_dais),
282
+
.dapm_widgets = mt8365_mt6357_widgets,
283
+
.num_dapm_widgets = ARRAY_SIZE(mt8365_mt6357_widgets),
284
+
.dapm_routes = mt8365_mt6357_routes,
285
+
.num_dapm_routes = ARRAY_SIZE(mt8365_mt6357_routes),
286
+
};
287
+
288
+
static int mt8365_mt6357_dev_probe(struct mtk_soc_card_data *soc_card_data, bool legacy)
289
+
{
290
+
struct mtk_platform_card_data *card_data = soc_card_data->card_data;
291
+
struct snd_soc_card *card = card_data->card;
292
+
struct device *dev = card->dev;
293
+
struct device_node *platform_node;
294
+
struct mt8365_mt6357_priv *mach_priv;
295
+
int i, ret;
296
+
297
+
card->dev = dev;
298
+
ret = parse_dai_link_info(card);
299
+
if (ret)
300
+
goto err;
301
+
302
+
mach_priv = devm_kzalloc(dev, sizeof(*mach_priv),
303
+
GFP_KERNEL);
304
+
if (!mach_priv)
305
+
return -ENOMEM;
306
+
soc_card_data->mach_priv = mach_priv;
307
+
snd_soc_card_set_drvdata(card, soc_card_data);
308
+
mt8365_mt6357_gpio_probe(card);
309
+
return 0;
310
+
311
+
err:
312
+
clean_card_reference(card);
313
+
return ret;
314
+
}
315
+
316
+
static const struct mtk_soundcard_pdata mt8365_mt6357_card = {
317
+
.card_name = "mt8365-mt6357",
318
+
.card_data = &(struct mtk_platform_card_data) {
319
+
.card = &mt8365_mt6357_soc_card,
320
+
},
321
+
.soc_probe = mt8365_mt6357_dev_probe
322
+
};
323
+
324
+
static const struct of_device_id mt8365_mt6357_dt_match[] = {
325
+
{ .compatible = "mediatek,mt8365-mt6357", .data = &mt8365_mt6357_card },
326
+
{ /* sentinel */ }
327
+
};
328
+
MODULE_DEVICE_TABLE(of, mt8365_mt6357_dt_match);
329
+
330
+
static struct platform_driver mt8365_mt6357_driver = {
331
+
.driver = {
332
+
.name = "mt8365_mt6357",
333
+
.of_match_table = mt8365_mt6357_dt_match,
334
+
.pm = &snd_soc_pm_ops,
335
+
},
336
+
.probe = mtk_soundcard_common_probe,
337
+
};
338
+
339
+
module_platform_driver(mt8365_mt6357_driver);
340
+
341
+
/* Module information */
342
+
MODULE_DESCRIPTION("MT8365 EVK SoC machine driver");
343
+
MODULE_AUTHOR("Nicolas Belin <nbelin@baylibre.com>");
344
+
MODULE_LICENSE("GPL");
345
+
MODULE_ALIAS("platform: mt8365_mt6357");
+991
sound/soc/mediatek/mt8365/mt8365-reg.h
+991
sound/soc/mediatek/mt8365/mt8365-reg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0
2
+
*
3
+
* MediaTek 8365 audio driver reg definition
4
+
*
5
+
* Copyright (c) 2024 MediaTek Inc.
6
+
* Authors: Jia Zeng <jia.zeng@mediatek.com>
7
+
* Alexandre Mergnat <amergnat@baylibre.com>
8
+
*/
9
+
10
+
#ifndef _MT8365_REG_H_
11
+
#define _MT8365_REG_H_
12
+
13
+
#define AUDIO_TOP_CON0 (0x0000)
14
+
#define AUDIO_TOP_CON1 (0x0004)
15
+
#define AUDIO_TOP_CON2 (0x0008)
16
+
#define AUDIO_TOP_CON3 (0x000c)
17
+
18
+
#define AFE_DAC_CON0 (0x0010)
19
+
#define AFE_DAC_CON1 (0x0014)
20
+
#define AFE_I2S_CON (0x0018)
21
+
#define AFE_CONN0 (0x0020)
22
+
#define AFE_CONN1 (0x0024)
23
+
#define AFE_CONN2 (0x0028)
24
+
#define AFE_CONN3 (0x002c)
25
+
#define AFE_CONN4 (0x0030)
26
+
#define AFE_I2S_CON1 (0x0034)
27
+
#define AFE_I2S_CON2 (0x0038)
28
+
#define AFE_MRGIF_CON (0x003c)
29
+
#define AFE_DL1_BASE (0x0040)
30
+
#define AFE_DL1_CUR (0x0044)
31
+
#define AFE_DL1_END (0x0048)
32
+
#define AFE_I2S_CON3 (0x004c)
33
+
#define AFE_DL2_BASE (0x0050)
34
+
#define AFE_DL2_CUR (0x0054)
35
+
#define AFE_DL2_END (0x0058)
36
+
#define AFE_CONN5 (0x005c)
37
+
#define AFE_AWB_BASE (0x0070)
38
+
#define AFE_AWB_END (0x0078)
39
+
#define AFE_AWB_CUR (0x007c)
40
+
#define AFE_VUL_BASE (0x0080)
41
+
#define AFE_VUL_END (0x0088)
42
+
#define AFE_VUL_CUR (0x008c)
43
+
#define AFE_CONN6 (0x00bc)
44
+
#define AFE_MEMIF_MSB (0x00cc)
45
+
#define AFE_MEMIF_MON0 (0x00d0)
46
+
#define AFE_MEMIF_MON1 (0x00d4)
47
+
#define AFE_MEMIF_MON2 (0x00d8)
48
+
#define AFE_MEMIF_MON3 (0x00dc)
49
+
#define AFE_MEMIF_MON4 (0x00e0)
50
+
#define AFE_MEMIF_MON5 (0x00e4)
51
+
#define AFE_MEMIF_MON6 (0x00e8)
52
+
#define AFE_MEMIF_MON7 (0x00ec)
53
+
#define AFE_MEMIF_MON8 (0x00f0)
54
+
#define AFE_MEMIF_MON9 (0x00f4)
55
+
#define AFE_MEMIF_MON10 (0x00f8)
56
+
#define AFE_MEMIF_MON11 (0x00fc)
57
+
#define AFE_ADDA_DL_SRC2_CON0 (0x0108)
58
+
#define AFE_ADDA_DL_SRC2_CON1 (0x010c)
59
+
#define AFE_ADDA_UL_SRC_CON0 (0x0114)
60
+
#define AFE_ADDA_UL_SRC_CON1 (0x0118)
61
+
#define AFE_ADDA_TOP_CON0 (0x0120)
62
+
#define AFE_ADDA_UL_DL_CON0 (0x0124)
63
+
#define AFE_ADDA_SRC_DEBUG (0x012c)
64
+
#define AFE_ADDA_SRC_DEBUG_MON0 (0x0130)
65
+
#define AFE_ADDA_SRC_DEBUG_MON1 (0x0134)
66
+
#define AFE_ADDA_UL_SRC_MON0 (0x0148)
67
+
#define AFE_ADDA_UL_SRC_MON1 (0x014c)
68
+
#define AFE_SRAM_BOUND (0x0170)
69
+
#define AFE_SECURE_CON (0x0174)
70
+
#define AFE_SECURE_CONN0 (0x0178)
71
+
#define AFE_SIDETONE_DEBUG (0x01d0)
72
+
#define AFE_SIDETONE_MON (0x01d4)
73
+
#define AFE_SIDETONE_CON0 (0x01e0)
74
+
#define AFE_SIDETONE_COEFF (0x01e4)
75
+
#define AFE_SIDETONE_CON1 (0x01e8)
76
+
#define AFE_SIDETONE_GAIN (0x01ec)
77
+
#define AFE_SGEN_CON0 (0x01f0)
78
+
#define AFE_SINEGEN_CON_TDM (0x01f8)
79
+
#define AFE_SINEGEN_CON_TDM_IN (0x01fc)
80
+
#define AFE_TOP_CON0 (0x0200)
81
+
#define AFE_BUS_CFG (0x0240)
82
+
#define AFE_BUS_MON0 (0x0244)
83
+
#define AFE_ADDA_PREDIS_CON0 (0x0260)
84
+
#define AFE_ADDA_PREDIS_CON1 (0x0264)
85
+
#define AFE_CONN_MON0 (0x0280)
86
+
#define AFE_CONN_MON1 (0x0284)
87
+
#define AFE_CONN_MON2 (0x0288)
88
+
#define AFE_CONN_MON3 (0x028c)
89
+
#define AFE_ADDA_IIR_COEF_02_01 (0x0290)
90
+
#define AFE_ADDA_IIR_COEF_04_03 (0x0294)
91
+
#define AFE_ADDA_IIR_COEF_06_05 (0x0298)
92
+
#define AFE_ADDA_IIR_COEF_08_07 (0x029c)
93
+
#define AFE_ADDA_IIR_COEF_10_09 (0x02a0)
94
+
#define AFE_VUL_D2_BASE (0x0350)
95
+
#define AFE_VUL_D2_END (0x0358)
96
+
#define AFE_VUL_D2_CUR (0x035c)
97
+
#define AFE_HDMI_OUT_CON0 (0x0370)
98
+
#define AFE_HDMI_OUT_BASE (0x0374)
99
+
#define AFE_HDMI_OUT_CUR (0x0378)
100
+
#define AFE_HDMI_OUT_END (0x037c)
101
+
#define AFE_SPDIF_OUT_CON0 (0x0380)
102
+
#define AFE_SPDIF_OUT_BASE (0x0384)
103
+
#define AFE_SPDIF_OUT_CUR (0x0388)
104
+
#define AFE_SPDIF_OUT_END (0x038c)
105
+
#define AFE_HDMI_CONN0 (0x0390)
106
+
#define AFE_HDMI_CONN1 (0x0398)
107
+
#define AFE_CONN_TDMIN_CON (0x039c)
108
+
#define AFE_IRQ_MCU_CON (0x03a0)
109
+
#define AFE_IRQ_MCU_STATUS (0x03a4)
110
+
#define AFE_IRQ_MCU_CLR (0x03a8)
111
+
#define AFE_IRQ_MCU_CNT1 (0x03ac)
112
+
#define AFE_IRQ_MCU_CNT2 (0x03b0)
113
+
#define AFE_IRQ_MCU_EN (0x03b4)
114
+
#define AFE_IRQ_MCU_MON2 (0x03b8)
115
+
#define AFE_IRQ_MCU_CNT5 (0x03bc)
116
+
#define AFE_IRQ1_MCU_CNT_MON (0x03c0)
117
+
#define AFE_IRQ2_MCU_CNT_MON (0x03c4)
118
+
#define AFE_IRQ1_MCU_EN_CNT_MON (0x03c8)
119
+
#define AFE_IRQ5_MCU_CNT_MON (0x03cc)
120
+
#define AFE_MEMIF_MINLEN (0x03d0)
121
+
#define AFE_MEMIF_MAXLEN (0x03d4)
122
+
#define AFE_MEMIF_PBUF_SIZE (0x03d8)
123
+
#define AFE_IRQ_MCU_CNT7 (0x03dc)
124
+
#define AFE_IRQ7_MCU_CNT_MON (0x03e0)
125
+
#define AFE_MEMIF_PBUF2_SIZE (0x03ec)
126
+
#define AFE_APLL_TUNER_CFG (0x03f0)
127
+
#define AFE_APLL_TUNER_CFG1 (0x03f4)
128
+
#define AFE_IRQ_MCU_CON2 (0x03f8)
129
+
#define IRQ13_MCU_CNT (0x0408)
130
+
#define IRQ13_MCU_CNT_MON (0x040c)
131
+
#define AFE_GAIN1_CON0 (0x0410)
132
+
#define AFE_GAIN1_CON1 (0x0414)
133
+
#define AFE_GAIN1_CON2 (0x0418)
134
+
#define AFE_GAIN1_CON3 (0x041c)
135
+
#define AFE_GAIN2_CON0 (0x0428)
136
+
#define AFE_GAIN2_CON1 (0x042c)
137
+
#define AFE_GAIN2_CON2 (0x0430)
138
+
#define AFE_GAIN2_CON3 (0x0434)
139
+
#define AFE_GAIN2_CUR (0x043c)
140
+
#define AFE_CONN11 (0x0448)
141
+
#define AFE_CONN12 (0x044c)
142
+
#define AFE_CONN13 (0x0450)
143
+
#define AFE_CONN14 (0x0454)
144
+
#define AFE_CONN15 (0x0458)
145
+
#define AFE_CONN16 (0x045c)
146
+
#define AFE_CONN7 (0x0460)
147
+
#define AFE_CONN8 (0x0464)
148
+
#define AFE_CONN9 (0x0468)
149
+
#define AFE_CONN10 (0x046c)
150
+
#define AFE_CONN21 (0x0470)
151
+
#define AFE_CONN22 (0x0474)
152
+
#define AFE_CONN23 (0x0478)
153
+
#define AFE_CONN24 (0x047c)
154
+
#define AFE_IEC_CFG (0x0480)
155
+
#define AFE_IEC_NSNUM (0x0484)
156
+
#define AFE_IEC_BURST_INFO (0x0488)
157
+
#define AFE_IEC_BURST_LEN (0x048c)
158
+
#define AFE_IEC_NSADR (0x0490)
159
+
#define AFE_CONN_RS (0x0494)
160
+
#define AFE_CONN_DI (0x0498)
161
+
#define AFE_IEC_CHL_STAT0 (0x04a0)
162
+
#define AFE_IEC_CHL_STAT1 (0x04a4)
163
+
#define AFE_IEC_CHR_STAT0 (0x04a8)
164
+
#define AFE_IEC_CHR_STAT1 (0x04ac)
165
+
#define AFE_CONN25 (0x04b0)
166
+
#define AFE_CONN26 (0x04b4)
167
+
#define FPGA_CFG2 (0x04b8)
168
+
#define FPGA_CFG3 (0x04bc)
169
+
#define FPGA_CFG0 (0x04c0)
170
+
#define FPGA_CFG1 (0x04c4)
171
+
#define AFE_SRAM_DELSEL_CON0 (0x04f0)
172
+
#define AFE_SRAM_DELSEL_CON1 (0x04f4)
173
+
#define AFE_SRAM_DELSEL_CON2 (0x04f8)
174
+
#define FPGA_CFG4 (0x04fc)
175
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON0 (0x0500)
176
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON1 (0x0504)
177
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON2 (0x0508)
178
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON3 (0x050c)
179
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON4 (0x0510)
180
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON5 (0x0514)
181
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON6 (0x0518)
182
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON7 (0x051c)
183
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON8 (0x0520)
184
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON9 (0x0524)
185
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON10 (0x0528)
186
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON12 (0x0530)
187
+
#define AFE_TDM_GASRC4_ASRC_2CH_CON13 (0x0534)
188
+
#define PCM_INTF_CON2 (0x0538)
189
+
#define PCM2_INTF_CON (0x053c)
190
+
#define AFE_APB_MON (0x0540)
191
+
#define AFE_CONN34 (0x0544)
192
+
#define AFE_TDM_CON1 (0x0548)
193
+
#define AFE_TDM_CON2 (0x054c)
194
+
#define PCM_INTF_CON1 (0x0550)
195
+
#define AFE_SECURE_MASK_CONN47_1 (0x0554)
196
+
#define AFE_SECURE_MASK_CONN48_1 (0x0558)
197
+
#define AFE_SECURE_MASK_CONN49_1 (0x055c)
198
+
#define AFE_SECURE_MASK_CONN50_1 (0x0560)
199
+
#define AFE_SECURE_MASK_CONN51_1 (0x0564)
200
+
#define AFE_SECURE_MASK_CONN52_1 (0x0568)
201
+
#define AFE_SECURE_MASK_CONN53_1 (0x056c)
202
+
#define AFE_SE_SECURE_CON (0x0570)
203
+
#define AFE_TDM_IN_CON1 (0x0588)
204
+
#define AFE_TDM_IN_CON2 (0x058c)
205
+
#define AFE_TDM_IN_MON1 (0x0590)
206
+
#define AFE_TDM_IN_MON2 (0x0594)
207
+
#define AFE_TDM_IN_MON3 (0x0598)
208
+
#define AFE_DMIC0_UL_SRC_CON0 (0x05b4)
209
+
#define AFE_DMIC0_UL_SRC_CON1 (0x05b8)
210
+
#define AFE_DMIC0_SRC_DEBUG (0x05bc)
211
+
#define AFE_DMIC0_SRC_DEBUG_MON0 (0x05c0)
212
+
#define AFE_DMIC0_UL_SRC_MON0 (0x05c8)
213
+
#define AFE_DMIC0_UL_SRC_MON1 (0x05cc)
214
+
#define AFE_DMIC0_IIR_COEF_02_01 (0x05d0)
215
+
#define AFE_DMIC0_IIR_COEF_04_03 (0x05d4)
216
+
#define AFE_DMIC0_IIR_COEF_06_05 (0x05d8)
217
+
#define AFE_DMIC0_IIR_COEF_08_07 (0x05dc)
218
+
#define AFE_DMIC0_IIR_COEF_10_09 (0x05e0)
219
+
#define AFE_DMIC1_UL_SRC_CON0 (0x0620)
220
+
#define AFE_DMIC1_UL_SRC_CON1 (0x0624)
221
+
#define AFE_DMIC1_SRC_DEBUG (0x0628)
222
+
#define AFE_DMIC1_SRC_DEBUG_MON0 (0x062c)
223
+
#define AFE_DMIC1_UL_SRC_MON0 (0x0634)
224
+
#define AFE_DMIC1_UL_SRC_MON1 (0x0638)
225
+
#define AFE_DMIC1_IIR_COEF_02_01 (0x063c)
226
+
#define AFE_DMIC1_IIR_COEF_04_03 (0x0640)
227
+
#define AFE_DMIC1_IIR_COEF_06_05 (0x0644)
228
+
#define AFE_DMIC1_IIR_COEF_08_07 (0x0648)
229
+
#define AFE_DMIC1_IIR_COEF_10_09 (0x064c)
230
+
#define AFE_SECURE_MASK_CONN39_1 (0x068c)
231
+
#define AFE_SECURE_MASK_CONN40_1 (0x0690)
232
+
#define AFE_SECURE_MASK_CONN41_1 (0x0694)
233
+
#define AFE_SECURE_MASK_CONN42_1 (0x0698)
234
+
#define AFE_SECURE_MASK_CONN43_1 (0x069c)
235
+
#define AFE_SECURE_MASK_CONN44_1 (0x06a0)
236
+
#define AFE_SECURE_MASK_CONN45_1 (0x06a4)
237
+
#define AFE_SECURE_MASK_CONN46_1 (0x06a8)
238
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON0 (0x06c0)
239
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON1 (0x06c4)
240
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON2 (0x06c8)
241
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON3 (0x06cc)
242
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON4 (0x06d0)
243
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON5 (0x06d4)
244
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON6 (0x06d8)
245
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON7 (0x06dc)
246
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON8 (0x06e0)
247
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON9 (0x06e4)
248
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON10 (0x06e8)
249
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON12 (0x06f0)
250
+
#define AFE_TDM_GASRC1_ASRC_2CH_CON13 (0x06f4)
251
+
#define AFE_TDM_ASRC_CON0 (0x06f8)
252
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON0 (0x0700)
253
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON1 (0x0704)
254
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON2 (0x0708)
255
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON3 (0x070c)
256
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON4 (0x0710)
257
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON5 (0x0714)
258
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON6 (0x0718)
259
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON7 (0x071c)
260
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON8 (0x0720)
261
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON9 (0x0724)
262
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON10 (0x0728)
263
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON12 (0x0730)
264
+
#define AFE_TDM_GASRC2_ASRC_2CH_CON13 (0x0734)
265
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON0 (0x0740)
266
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON1 (0x0744)
267
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON2 (0x0748)
268
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON3 (0x074c)
269
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON4 (0x0750)
270
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON5 (0x0754)
271
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON6 (0x0758)
272
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON7 (0x075c)
273
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON8 (0x0760)
274
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON9 (0x0764)
275
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON10 (0x0768)
276
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON12 (0x0770)
277
+
#define AFE_TDM_GASRC3_ASRC_2CH_CON13 (0x0774)
278
+
#define AFE_DMIC2_UL_SRC_CON0 (0x0780)
279
+
#define AFE_DMIC2_UL_SRC_CON1 (0x0784)
280
+
#define AFE_DMIC2_SRC_DEBUG (0x0788)
281
+
#define AFE_DMIC2_SRC_DEBUG_MON0 (0x078c)
282
+
#define AFE_DMIC2_UL_SRC_MON0 (0x0794)
283
+
#define AFE_DMIC2_UL_SRC_MON1 (0x0798)
284
+
#define AFE_DMIC2_IIR_COEF_02_01 (0x079c)
285
+
#define AFE_DMIC2_IIR_COEF_04_03 (0x07a0)
286
+
#define AFE_DMIC2_IIR_COEF_06_05 (0x07a4)
287
+
#define AFE_DMIC2_IIR_COEF_08_07 (0x07a8)
288
+
#define AFE_DMIC2_IIR_COEF_10_09 (0x07ac)
289
+
#define AFE_DMIC3_UL_SRC_CON0 (0x07ec)
290
+
#define AFE_DMIC3_UL_SRC_CON1 (0x07f0)
291
+
#define AFE_DMIC3_SRC_DEBUG (0x07f4)
292
+
#define AFE_DMIC3_SRC_DEBUG_MON0 (0x07f8)
293
+
#define AFE_DMIC3_UL_SRC_MON0 (0x0800)
294
+
#define AFE_DMIC3_UL_SRC_MON1 (0x0804)
295
+
#define AFE_DMIC3_IIR_COEF_02_01 (0x0808)
296
+
#define AFE_DMIC3_IIR_COEF_04_03 (0x080c)
297
+
#define AFE_DMIC3_IIR_COEF_06_05 (0x0810)
298
+
#define AFE_DMIC3_IIR_COEF_08_07 (0x0814)
299
+
#define AFE_DMIC3_IIR_COEF_10_09 (0x0818)
300
+
#define AFE_SECURE_MASK_CONN25_1 (0x0858)
301
+
#define AFE_SECURE_MASK_CONN26_1 (0x085c)
302
+
#define AFE_SECURE_MASK_CONN27_1 (0x0860)
303
+
#define AFE_SECURE_MASK_CONN28_1 (0x0864)
304
+
#define AFE_SECURE_MASK_CONN29_1 (0x0868)
305
+
#define AFE_SECURE_MASK_CONN30_1 (0x086c)
306
+
#define AFE_SECURE_MASK_CONN31_1 (0x0870)
307
+
#define AFE_SECURE_MASK_CONN32_1 (0x0874)
308
+
#define AFE_SECURE_MASK_CONN33_1 (0x0878)
309
+
#define AFE_SECURE_MASK_CONN34_1 (0x087c)
310
+
#define AFE_SECURE_MASK_CONN35_1 (0x0880)
311
+
#define AFE_SECURE_MASK_CONN36_1 (0x0884)
312
+
#define AFE_SECURE_MASK_CONN37_1 (0x0888)
313
+
#define AFE_SECURE_MASK_CONN38_1 (0x088c)
314
+
#define AFE_IRQ_MCU_SCP_EN (0x0890)
315
+
#define AFE_IRQ_MCU_DSP_EN (0x0894)
316
+
#define AFE_IRQ3_MCU_CNT_MON (0x0898)
317
+
#define AFE_IRQ4_MCU_CNT_MON (0x089c)
318
+
#define AFE_IRQ8_MCU_CNT_MON (0x08a0)
319
+
#define AFE_IRQ_MCU_CNT3 (0x08a4)
320
+
#define AFE_IRQ_MCU_CNT4 (0x08a8)
321
+
#define AFE_IRQ_MCU_CNT8 (0x08ac)
322
+
#define AFE_IRQ_MCU_CNT11 (0x08b0)
323
+
#define AFE_IRQ_MCU_CNT12 (0x08b4)
324
+
#define AFE_IRQ11_MCU_CNT_MON (0x08b8)
325
+
#define AFE_IRQ12_MCU_CNT_MON (0x08bc)
326
+
#define AFE_VUL3_BASE (0x08c0)
327
+
#define AFE_VUL3_CUR (0x08c4)
328
+
#define AFE_VUL3_END (0x08c8)
329
+
#define AFE_VUL3_BASE_MSB (0x08d0)
330
+
#define AFE_VUL3_END_MSB (0x08d4)
331
+
#define AFE_IRQ10_MCU_CNT_MON (0x08d8)
332
+
#define AFE_IRQ_MCU_CNT10 (0x08dc)
333
+
#define AFE_IRQ_ACC1_CNT (0x08e0)
334
+
#define AFE_IRQ_ACC2_CNT (0x08e4)
335
+
#define AFE_IRQ_ACC1_CNT_MON1 (0x08e8)
336
+
#define AFE_IRQ_ACC2_CNT_MON (0x08ec)
337
+
#define AFE_TSF_CON (0x08f0)
338
+
#define AFE_TSF_MON (0x08f4)
339
+
#define AFE_IRQ_ACC1_CNT_MON2 (0x08f8)
340
+
#define AFE_SPDIFIN_CFG0 (0x0900)
341
+
#define AFE_SPDIFIN_CFG1 (0x0904)
342
+
#define AFE_SPDIFIN_CHSTS1 (0x0908)
343
+
#define AFE_SPDIFIN_CHSTS2 (0x090c)
344
+
#define AFE_SPDIFIN_CHSTS3 (0x0910)
345
+
#define AFE_SPDIFIN_CHSTS4 (0x0914)
346
+
#define AFE_SPDIFIN_CHSTS5 (0x0918)
347
+
#define AFE_SPDIFIN_CHSTS6 (0x091c)
348
+
#define AFE_SPDIFIN_DEBUG1 (0x0920)
349
+
#define AFE_SPDIFIN_DEBUG2 (0x0924)
350
+
#define AFE_SPDIFIN_DEBUG3 (0x0928)
351
+
#define AFE_SPDIFIN_DEBUG4 (0x092c)
352
+
#define AFE_SPDIFIN_EC (0x0930)
353
+
#define AFE_SPDIFIN_CKLOCK_CFG (0x0934)
354
+
#define AFE_SPDIFIN_BR (0x093c)
355
+
#define AFE_SPDIFIN_BR_DBG1 (0x0940)
356
+
#define AFE_SPDIFIN_INT_EXT (0x0948)
357
+
#define AFE_SPDIFIN_INT_EXT2 (0x094c)
358
+
#define SPDIFIN_FREQ_INFO (0x0950)
359
+
#define SPDIFIN_FREQ_INFO_2 (0x0954)
360
+
#define SPDIFIN_FREQ_INFO_3 (0x0958)
361
+
#define SPDIFIN_FREQ_STATUS (0x095c)
362
+
#define SPDIFIN_USERCODE1 (0x0960)
363
+
#define SPDIFIN_USERCODE2 (0x0964)
364
+
#define SPDIFIN_USERCODE3 (0x0968)
365
+
#define SPDIFIN_USERCODE4 (0x096c)
366
+
#define SPDIFIN_USERCODE5 (0x0970)
367
+
#define SPDIFIN_USERCODE6 (0x0974)
368
+
#define SPDIFIN_USERCODE7 (0x0978)
369
+
#define SPDIFIN_USERCODE8 (0x097c)
370
+
#define SPDIFIN_USERCODE9 (0x0980)
371
+
#define SPDIFIN_USERCODE10 (0x0984)
372
+
#define SPDIFIN_USERCODE11 (0x0988)
373
+
#define SPDIFIN_USERCODE12 (0x098c)
374
+
#define SPDIFIN_MEMIF_CON0 (0x0990)
375
+
#define SPDIFIN_BASE_ADR (0x0994)
376
+
#define SPDIFIN_END_ADR (0x0998)
377
+
#define SPDIFIN_APLL_TUNER_CFG (0x09a0)
378
+
#define SPDIFIN_APLL_TUNER_CFG1 (0x09a4)
379
+
#define SPDIFIN_APLL2_TUNER_CFG (0x09a8)
380
+
#define SPDIFIN_APLL2_TUNER_CFG1 (0x09ac)
381
+
#define SPDIFIN_TYPE_DET (0x09b0)
382
+
#define MPHONE_MULTI_CON0 (0x09b4)
383
+
#define SPDIFIN_CUR_ADR (0x09b8)
384
+
#define AFE_SINEGEN_CON_SPDIFIN (0x09bc)
385
+
#define AFE_HDMI_IN_2CH_CON0 (0x09c0)
386
+
#define AFE_HDMI_IN_2CH_BASE (0x09c4)
387
+
#define AFE_HDMI_IN_2CH_END (0x09c8)
388
+
#define AFE_HDMI_IN_2CH_CUR (0x09cc)
389
+
#define AFE_MEMIF_BUF_MON0 (0x09d0)
390
+
#define AFE_MEMIF_BUF_MON1 (0x09d4)
391
+
#define AFE_MEMIF_BUF_MON2 (0x09d8)
392
+
#define AFE_MEMIF_BUF_MON3 (0x09dc)
393
+
#define AFE_MEMIF_BUF_MON6 (0x09e8)
394
+
#define AFE_MEMIF_BUF_MON7 (0x09ec)
395
+
#define AFE_MEMIF_BUF_MON8 (0x09f0)
396
+
#define AFE_MEMIF_BUF_MON10 (0x09f8)
397
+
#define AFE_MEMIF_BUF_MON11 (0x09fc)
398
+
#define SYSTOP_STC_CONFIG (0x0a00)
399
+
#define AUDIO_STC_STATUS (0x0a04)
400
+
#define SYSTOP_W_STC_H (0x0a08)
401
+
#define SYSTOP_W_STC_L (0x0a0c)
402
+
#define SYSTOP_R_STC_H (0x0a10)
403
+
#define SYSTOP_R_STC_L (0x0a14)
404
+
#define AUDIO_W_STC_H (0x0a18)
405
+
#define AUDIO_W_STC_L (0x0a1c)
406
+
#define AUDIO_R_STC_H (0x0a20)
407
+
#define AUDIO_R_STC_L (0x0a24)
408
+
#define SYSTOP_W_STC2_H (0x0a28)
409
+
#define SYSTOP_W_STC2_L (0x0a2c)
410
+
#define SYSTOP_R_STC2_H (0x0a30)
411
+
#define SYSTOP_R_STC2_L (0x0a34)
412
+
#define AUDIO_W_STC2_H (0x0a38)
413
+
#define AUDIO_W_STC2_L (0x0a3c)
414
+
#define AUDIO_R_STC2_H (0x0a40)
415
+
#define AUDIO_R_STC2_L (0x0a44)
416
+
417
+
#define AFE_CONN17 (0x0a48)
418
+
#define AFE_CONN18 (0x0a4c)
419
+
#define AFE_CONN19 (0x0a50)
420
+
#define AFE_CONN20 (0x0a54)
421
+
#define AFE_CONN27 (0x0a58)
422
+
#define AFE_CONN28 (0x0a5c)
423
+
#define AFE_CONN29 (0x0a60)
424
+
#define AFE_CONN30 (0x0a64)
425
+
#define AFE_CONN31 (0x0a68)
426
+
#define AFE_CONN32 (0x0a6c)
427
+
#define AFE_CONN33 (0x0a70)
428
+
#define AFE_CONN35 (0x0a74)
429
+
#define AFE_CONN36 (0x0a78)
430
+
#define AFE_CONN37 (0x0a7c)
431
+
#define AFE_CONN38 (0x0a80)
432
+
#define AFE_CONN39 (0x0a84)
433
+
#define AFE_CONN40 (0x0a88)
434
+
#define AFE_CONN41 (0x0a8c)
435
+
#define AFE_CONN42 (0x0a90)
436
+
#define AFE_CONN44 (0x0a94)
437
+
#define AFE_CONN45 (0x0a98)
438
+
#define AFE_CONN46 (0x0a9c)
439
+
#define AFE_CONN47 (0x0aa0)
440
+
#define AFE_CONN_24BIT (0x0aa4)
441
+
#define AFE_CONN0_1 (0x0aa8)
442
+
#define AFE_CONN1_1 (0x0aac)
443
+
#define AFE_CONN2_1 (0x0ab0)
444
+
#define AFE_CONN3_1 (0x0ab4)
445
+
#define AFE_CONN4_1 (0x0ab8)
446
+
#define AFE_CONN5_1 (0x0abc)
447
+
#define AFE_CONN6_1 (0x0ac0)
448
+
#define AFE_CONN7_1 (0x0ac4)
449
+
#define AFE_CONN8_1 (0x0ac8)
450
+
#define AFE_CONN9_1 (0x0acc)
451
+
#define AFE_CONN10_1 (0x0ad0)
452
+
#define AFE_CONN11_1 (0x0ad4)
453
+
#define AFE_CONN12_1 (0x0ad8)
454
+
#define AFE_CONN13_1 (0x0adc)
455
+
#define AFE_CONN14_1 (0x0ae0)
456
+
#define AFE_CONN15_1 (0x0ae4)
457
+
#define AFE_CONN16_1 (0x0ae8)
458
+
#define AFE_CONN17_1 (0x0aec)
459
+
#define AFE_CONN18_1 (0x0af0)
460
+
#define AFE_CONN19_1 (0x0af4)
461
+
#define AFE_CONN43 (0x0af8)
462
+
#define AFE_CONN43_1 (0x0afc)
463
+
#define AFE_CONN21_1 (0x0b00)
464
+
#define AFE_CONN22_1 (0x0b04)
465
+
#define AFE_CONN23_1 (0x0b08)
466
+
#define AFE_CONN24_1 (0x0b0c)
467
+
#define AFE_CONN25_1 (0x0b10)
468
+
#define AFE_CONN26_1 (0x0b14)
469
+
#define AFE_CONN27_1 (0x0b18)
470
+
#define AFE_CONN28_1 (0x0b1c)
471
+
#define AFE_CONN29_1 (0x0b20)
472
+
#define AFE_CONN30_1 (0x0b24)
473
+
#define AFE_CONN31_1 (0x0b28)
474
+
#define AFE_CONN32_1 (0x0b2c)
475
+
#define AFE_CONN33_1 (0x0b30)
476
+
#define AFE_CONN34_1 (0x0b34)
477
+
#define AFE_CONN35_1 (0x0b38)
478
+
#define AFE_CONN36_1 (0x0b3c)
479
+
#define AFE_CONN37_1 (0x0b40)
480
+
#define AFE_CONN38_1 (0x0b44)
481
+
#define AFE_CONN39_1 (0x0b48)
482
+
#define AFE_CONN40_1 (0x0b4c)
483
+
#define AFE_CONN41_1 (0x0b50)
484
+
#define AFE_CONN42_1 (0x0b54)
485
+
#define AFE_CONN44_1 (0x0b58)
486
+
#define AFE_CONN45_1 (0x0b5c)
487
+
#define AFE_CONN46_1 (0x0b60)
488
+
#define AFE_CONN47_1 (0x0b64)
489
+
#define AFE_CONN_RS_1 (0x0b68)
490
+
#define AFE_CONN_DI_1 (0x0b6c)
491
+
#define AFE_CONN_24BIT_1 (0x0b70)
492
+
#define AFE_GAIN1_CUR (0x0b78)
493
+
#define AFE_CONN20_1 (0x0b7c)
494
+
#define AFE_DL1_BASE_MSB (0x0b80)
495
+
#define AFE_DL1_END_MSB (0x0b84)
496
+
#define AFE_DL2_BASE_MSB (0x0b88)
497
+
#define AFE_DL2_END_MSB (0x0b8c)
498
+
#define AFE_AWB_BASE_MSB (0x0b90)
499
+
#define AFE_AWB_END_MSB (0x0b94)
500
+
#define AFE_VUL_BASE_MSB (0x0ba0)
501
+
#define AFE_VUL_END_MSB (0x0ba4)
502
+
#define AFE_VUL_D2_BASE_MSB (0x0ba8)
503
+
#define AFE_VUL_D2_END_MSB (0x0bac)
504
+
#define AFE_HDMI_OUT_BASE_MSB (0x0bb8)
505
+
#define AFE_HDMI_OUT_END_MSB (0x0bbc)
506
+
#define AFE_HDMI_IN_2CH_BASE_MSB (0x0bc0)
507
+
#define AFE_HDMI_IN_2CH_END_MSB (0x0bc4)
508
+
#define AFE_SPDIF_OUT_BASE_MSB (0x0bc8)
509
+
#define AFE_SPDIF_OUT_END_MSB (0x0bcc)
510
+
#define SPDIFIN_BASE_MSB (0x0bd0)
511
+
#define SPDIFIN_END_MSB (0x0bd4)
512
+
#define AFE_DL1_CUR_MSB (0x0bd8)
513
+
#define AFE_DL2_CUR_MSB (0x0bdc)
514
+
#define AFE_AWB_CUR_MSB (0x0be8)
515
+
#define AFE_VUL_CUR_MSB (0x0bf8)
516
+
#define AFE_VUL_D2_CUR_MSB (0x0c04)
517
+
#define AFE_HDMI_OUT_CUR_MSB (0x0c0c)
518
+
#define AFE_HDMI_IN_2CH_CUR_MSB (0x0c10)
519
+
#define AFE_SPDIF_OUT_CUR_MSB (0x0c14)
520
+
#define SPDIFIN_CUR_MSB (0x0c18)
521
+
#define AFE_CONN_REG (0x0c20)
522
+
#define AFE_SECURE_MASK_CONN14_1 (0x0c24)
523
+
#define AFE_SECURE_MASK_CONN15_1 (0x0c28)
524
+
#define AFE_SECURE_MASK_CONN16_1 (0x0c2c)
525
+
#define AFE_SECURE_MASK_CONN17_1 (0x0c30)
526
+
#define AFE_SECURE_MASK_CONN18_1 (0x0c34)
527
+
#define AFE_SECURE_MASK_CONN19_1 (0x0c38)
528
+
#define AFE_SECURE_MASK_CONN20_1 (0x0c3c)
529
+
#define AFE_SECURE_MASK_CONN21_1 (0x0c40)
530
+
#define AFE_SECURE_MASK_CONN22_1 (0x0c44)
531
+
#define AFE_SECURE_MASK_CONN23_1 (0x0c48)
532
+
#define AFE_SECURE_MASK_CONN24_1 (0x0c4c)
533
+
#define AFE_ADDA_DL_SDM_DCCOMP_CON (0x0c50)
534
+
#define AFE_ADDA_DL_SDM_TEST (0x0c54)
535
+
#define AFE_ADDA_DL_DC_COMP_CFG0 (0x0c58)
536
+
#define AFE_ADDA_DL_DC_COMP_CFG1 (0x0c5c)
537
+
#define AFE_ADDA_DL_SDM_FIFO_MON (0x0c60)
538
+
#define AFE_ADDA_DL_SRC_LCH_MON (0x0c64)
539
+
#define AFE_ADDA_DL_SRC_RCH_MON (0x0c68)
540
+
#define AFE_ADDA_DL_SDM_OUT_MON (0x0c6c)
541
+
#define AFE_ADDA_DL_SDM_DITHER_CON (0x0c70)
542
+
543
+
#define AFE_VUL3_CUR_MSB (0x0c78)
544
+
#define AFE_ASRC_2CH_CON0 (0x0c80)
545
+
#define AFE_ASRC_2CH_CON1 (0x0c84)
546
+
#define AFE_ASRC_2CH_CON2 (0x0c88)
547
+
#define AFE_ASRC_2CH_CON3 (0x0c8c)
548
+
#define AFE_ASRC_2CH_CON4 (0x0c90)
549
+
#define AFE_ASRC_2CH_CON5 (0x0c94)
550
+
#define AFE_ASRC_2CH_CON6 (0x0c98)
551
+
#define AFE_ASRC_2CH_CON7 (0x0c9c)
552
+
#define AFE_ASRC_2CH_CON8 (0x0ca0)
553
+
#define AFE_ASRC_2CH_CON9 (0x0ca4)
554
+
#define AFE_ASRC_2CH_CON10 (0x0ca8)
555
+
#define AFE_ASRC_2CH_CON12 (0x0cb0)
556
+
#define AFE_ASRC_2CH_CON13 (0x0cb4)
557
+
558
+
#define AFE_PCM_TX_ASRC_2CH_CON0 (0x0cc0)
559
+
#define AFE_PCM_TX_ASRC_2CH_CON1 (0x0cc4)
560
+
#define AFE_PCM_TX_ASRC_2CH_CON2 (0x0cc8)
561
+
#define AFE_PCM_TX_ASRC_2CH_CON3 (0x0ccc)
562
+
#define AFE_PCM_TX_ASRC_2CH_CON4 (0x0cd0)
563
+
#define AFE_PCM_TX_ASRC_2CH_CON5 (0x0cd4)
564
+
#define AFE_PCM_TX_ASRC_2CH_CON6 (0x0cd8)
565
+
#define AFE_PCM_TX_ASRC_2CH_CON7 (0x0cdc)
566
+
#define AFE_PCM_TX_ASRC_2CH_CON8 (0x0ce0)
567
+
#define AFE_PCM_TX_ASRC_2CH_CON9 (0x0ce4)
568
+
#define AFE_PCM_TX_ASRC_2CH_CON10 (0x0ce8)
569
+
#define AFE_PCM_TX_ASRC_2CH_CON12 (0x0cf0)
570
+
#define AFE_PCM_TX_ASRC_2CH_CON13 (0x0cf4)
571
+
#define AFE_PCM_RX_ASRC_2CH_CON0 (0x0d00)
572
+
#define AFE_PCM_RX_ASRC_2CH_CON1 (0x0d04)
573
+
#define AFE_PCM_RX_ASRC_2CH_CON2 (0x0d08)
574
+
#define AFE_PCM_RX_ASRC_2CH_CON3 (0x0d0c)
575
+
#define AFE_PCM_RX_ASRC_2CH_CON4 (0x0d10)
576
+
#define AFE_PCM_RX_ASRC_2CH_CON5 (0x0d14)
577
+
#define AFE_PCM_RX_ASRC_2CH_CON6 (0x0d18)
578
+
#define AFE_PCM_RX_ASRC_2CH_CON7 (0x0d1c)
579
+
#define AFE_PCM_RX_ASRC_2CH_CON8 (0x0d20)
580
+
#define AFE_PCM_RX_ASRC_2CH_CON9 (0x0d24)
581
+
#define AFE_PCM_RX_ASRC_2CH_CON10 (0x0d28)
582
+
#define AFE_PCM_RX_ASRC_2CH_CON12 (0x0d30)
583
+
#define AFE_PCM_RX_ASRC_2CH_CON13 (0x0d34)
584
+
585
+
#define AFE_ADDA_PREDIS_CON2 (0x0d40)
586
+
#define AFE_ADDA_PREDIS_CON3 (0x0d44)
587
+
#define AFE_SECURE_MASK_CONN4_1 (0x0d48)
588
+
#define AFE_SECURE_MASK_CONN5_1 (0x0d4c)
589
+
#define AFE_SECURE_MASK_CONN6_1 (0x0d50)
590
+
#define AFE_SECURE_MASK_CONN7_1 (0x0d54)
591
+
#define AFE_SECURE_MASK_CONN8_1 (0x0d58)
592
+
#define AFE_SECURE_MASK_CONN9_1 (0x0d5c)
593
+
#define AFE_SECURE_MASK_CONN10_1 (0x0d60)
594
+
#define AFE_SECURE_MASK_CONN11_1 (0x0d64)
595
+
#define AFE_SECURE_MASK_CONN12_1 (0x0d68)
596
+
#define AFE_SECURE_MASK_CONN13_1 (0x0d6c)
597
+
#define AFE_MEMIF_MON12 (0x0d70)
598
+
#define AFE_MEMIF_MON13 (0x0d74)
599
+
#define AFE_MEMIF_MON14 (0x0d78)
600
+
#define AFE_MEMIF_MON15 (0x0d7c)
601
+
#define AFE_SECURE_MASK_CONN42 (0x0dbc)
602
+
#define AFE_SECURE_MASK_CONN43 (0x0dc0)
603
+
#define AFE_SECURE_MASK_CONN44 (0x0dc4)
604
+
#define AFE_SECURE_MASK_CONN45 (0x0dc8)
605
+
#define AFE_SECURE_MASK_CONN46 (0x0dcc)
606
+
#define AFE_HD_ENGEN_ENABLE (0x0dd0)
607
+
#define AFE_SECURE_MASK_CONN47 (0x0dd4)
608
+
#define AFE_SECURE_MASK_CONN48 (0x0dd8)
609
+
#define AFE_SECURE_MASK_CONN49 (0x0ddc)
610
+
#define AFE_SECURE_MASK_CONN50 (0x0de0)
611
+
#define AFE_SECURE_MASK_CONN51 (0x0de4)
612
+
#define AFE_SECURE_MASK_CONN52 (0x0de8)
613
+
#define AFE_SECURE_MASK_CONN53 (0x0dec)
614
+
#define AFE_SECURE_MASK_CONN0_1 (0x0df0)
615
+
#define AFE_SECURE_MASK_CONN1_1 (0x0df4)
616
+
#define AFE_SECURE_MASK_CONN2_1 (0x0df8)
617
+
#define AFE_SECURE_MASK_CONN3_1 (0x0dfc)
618
+
619
+
#define AFE_ADDA_MTKAIF_CFG0 (0x0e00)
620
+
#define AFE_ADDA_MTKAIF_SYNCWORD_CFG (0x0e14)
621
+
#define AFE_ADDA_MTKAIF_RX_CFG0 (0x0e20)
622
+
#define AFE_ADDA_MTKAIF_RX_CFG1 (0x0e24)
623
+
#define AFE_ADDA_MTKAIF_RX_CFG2 (0x0e28)
624
+
#define AFE_ADDA_MTKAIF_MON0 (0x0e34)
625
+
#define AFE_ADDA_MTKAIF_MON1 (0x0e38)
626
+
#define AFE_AUD_PAD_TOP (0x0e40)
627
+
628
+
#define AFE_CM1_CON4 (0x0e48)
629
+
#define AFE_CM2_CON4 (0x0e4c)
630
+
#define AFE_CM1_CON0 (0x0e50)
631
+
#define AFE_CM1_CON1 (0x0e54)
632
+
#define AFE_CM1_CON2 (0x0e58)
633
+
#define AFE_CM1_CON3 (0x0e5c)
634
+
#define AFE_CM2_CON0 (0x0e60)
635
+
#define AFE_CM2_CON1 (0x0e64)
636
+
#define AFE_CM2_CON2 (0x0e68)
637
+
#define AFE_CM2_CON3 (0x0e6c)
638
+
#define AFE_CM2_CONN0 (0x0e70)
639
+
#define AFE_CM2_CONN1 (0x0e74)
640
+
#define AFE_CM2_CONN2 (0x0e78)
641
+
642
+
#define AFE_GENERAL1_ASRC_2CH_CON0 (0x0e80)
643
+
#define AFE_GENERAL1_ASRC_2CH_CON1 (0x0e84)
644
+
#define AFE_GENERAL1_ASRC_2CH_CON2 (0x0e88)
645
+
#define AFE_GENERAL1_ASRC_2CH_CON3 (0x0e8c)
646
+
#define AFE_GENERAL1_ASRC_2CH_CON4 (0x0e90)
647
+
#define AFE_GENERAL1_ASRC_2CH_CON5 (0x0e94)
648
+
#define AFE_GENERAL1_ASRC_2CH_CON6 (0x0e98)
649
+
#define AFE_GENERAL1_ASRC_2CH_CON7 (0x0e9c)
650
+
#define AFE_GENERAL1_ASRC_2CH_CON8 (0x0ea0)
651
+
#define AFE_GENERAL1_ASRC_2CH_CON9 (0x0ea4)
652
+
#define AFE_GENERAL1_ASRC_2CH_CON10 (0x0ea8)
653
+
#define AFE_GENERAL1_ASRC_2CH_CON12 (0x0eb0)
654
+
#define AFE_GENERAL1_ASRC_2CH_CON13 (0x0eb4)
655
+
#define GENERAL_ASRC_MODE (0x0eb8)
656
+
#define GENERAL_ASRC_EN_ON (0x0ebc)
657
+
658
+
#define AFE_CONN48 (0x0ec0)
659
+
#define AFE_CONN49 (0x0ec4)
660
+
#define AFE_CONN50 (0x0ec8)
661
+
#define AFE_CONN51 (0x0ecc)
662
+
#define AFE_CONN52 (0x0ed0)
663
+
#define AFE_CONN53 (0x0ed4)
664
+
#define AFE_CONN48_1 (0x0ee0)
665
+
#define AFE_CONN49_1 (0x0ee4)
666
+
#define AFE_CONN50_1 (0x0ee8)
667
+
#define AFE_CONN51_1 (0x0eec)
668
+
#define AFE_CONN52_1 (0x0ef0)
669
+
#define AFE_CONN53_1 (0x0ef4)
670
+
671
+
#define AFE_GENERAL2_ASRC_2CH_CON0 (0x0f00)
672
+
#define AFE_GENERAL2_ASRC_2CH_CON1 (0x0f04)
673
+
#define AFE_GENERAL2_ASRC_2CH_CON2 (0x0f08)
674
+
#define AFE_GENERAL2_ASRC_2CH_CON3 (0x0f0c)
675
+
#define AFE_GENERAL2_ASRC_2CH_CON4 (0x0f10)
676
+
#define AFE_GENERAL2_ASRC_2CH_CON5 (0x0f14)
677
+
#define AFE_GENERAL2_ASRC_2CH_CON6 (0x0f18)
678
+
#define AFE_GENERAL2_ASRC_2CH_CON7 (0x0f1c)
679
+
#define AFE_GENERAL2_ASRC_2CH_CON8 (0x0f20)
680
+
#define AFE_GENERAL2_ASRC_2CH_CON9 (0x0f24)
681
+
#define AFE_GENERAL2_ASRC_2CH_CON10 (0x0f28)
682
+
#define AFE_GENERAL2_ASRC_2CH_CON12 (0x0f30)
683
+
#define AFE_GENERAL2_ASRC_2CH_CON13 (0x0f34)
684
+
685
+
#define AFE_SECURE_MASK_CONN28 (0x0f48)
686
+
#define AFE_SECURE_MASK_CONN29 (0x0f4c)
687
+
#define AFE_SECURE_MASK_CONN30 (0x0f50)
688
+
#define AFE_SECURE_MASK_CONN31 (0x0f54)
689
+
#define AFE_SECURE_MASK_CONN32 (0x0f58)
690
+
#define AFE_SECURE_MASK_CONN33 (0x0f5c)
691
+
#define AFE_SECURE_MASK_CONN34 (0x0f60)
692
+
#define AFE_SECURE_MASK_CONN35 (0x0f64)
693
+
#define AFE_SECURE_MASK_CONN36 (0x0f68)
694
+
#define AFE_SECURE_MASK_CONN37 (0x0f6c)
695
+
#define AFE_SECURE_MASK_CONN38 (0x0f70)
696
+
#define AFE_SECURE_MASK_CONN39 (0x0f74)
697
+
#define AFE_SECURE_MASK_CONN40 (0x0f78)
698
+
#define AFE_SECURE_MASK_CONN41 (0x0f7c)
699
+
#define AFE_SIDEBAND0 (0x0f80)
700
+
#define AFE_SIDEBAND1 (0x0f84)
701
+
#define AFE_SECURE_SIDEBAND0 (0x0f88)
702
+
#define AFE_SECURE_SIDEBAND1 (0x0f8c)
703
+
#define AFE_SECURE_MASK_CONN0 (0x0f90)
704
+
#define AFE_SECURE_MASK_CONN1 (0x0f94)
705
+
#define AFE_SECURE_MASK_CONN2 (0x0f98)
706
+
#define AFE_SECURE_MASK_CONN3 (0x0f9c)
707
+
#define AFE_SECURE_MASK_CONN4 (0x0fa0)
708
+
#define AFE_SECURE_MASK_CONN5 (0x0fa4)
709
+
#define AFE_SECURE_MASK_CONN6 (0x0fa8)
710
+
#define AFE_SECURE_MASK_CONN7 (0x0fac)
711
+
#define AFE_SECURE_MASK_CONN8 (0x0fb0)
712
+
#define AFE_SECURE_MASK_CONN9 (0x0fb4)
713
+
#define AFE_SECURE_MASK_CONN10 (0x0fb8)
714
+
#define AFE_SECURE_MASK_CONN11 (0x0fbc)
715
+
#define AFE_SECURE_MASK_CONN12 (0x0fc0)
716
+
#define AFE_SECURE_MASK_CONN13 (0x0fc4)
717
+
#define AFE_SECURE_MASK_CONN14 (0x0fc8)
718
+
#define AFE_SECURE_MASK_CONN15 (0x0fcc)
719
+
#define AFE_SECURE_MASK_CONN16 (0x0fd0)
720
+
#define AFE_SECURE_MASK_CONN17 (0x0fd4)
721
+
#define AFE_SECURE_MASK_CONN18 (0x0fd8)
722
+
#define AFE_SECURE_MASK_CONN19 (0x0fdc)
723
+
#define AFE_SECURE_MASK_CONN20 (0x0fe0)
724
+
#define AFE_SECURE_MASK_CONN21 (0x0fe4)
725
+
#define AFE_SECURE_MASK_CONN22 (0x0fe8)
726
+
#define AFE_SECURE_MASK_CONN23 (0x0fec)
727
+
#define AFE_SECURE_MASK_CONN24 (0x0ff0)
728
+
#define AFE_SECURE_MASK_CONN25 (0x0ff4)
729
+
#define AFE_SECURE_MASK_CONN26 (0x0ff8)
730
+
#define AFE_SECURE_MASK_CONN27 (0x0ffc)
731
+
732
+
#define MAX_REGISTER AFE_SECURE_MASK_CONN27
733
+
734
+
#define AFE_IRQ_STATUS_BITS 0x3ff
735
+
736
+
/* AUDIO_TOP_CON0 (0x0000) */
737
+
#define AUD_TCON0_PDN_TML BIT(27)
738
+
#define AUD_TCON0_PDN_DAC_PREDIS BIT(26)
739
+
#define AUD_TCON0_PDN_DAC BIT(25)
740
+
#define AUD_TCON0_PDN_ADC BIT(24)
741
+
#define AUD_TCON0_PDN_TDM_IN BIT(23)
742
+
#define AUD_TCON0_PDN_TDM_OUT BIT(22)
743
+
#define AUD_TCON0_PDN_SPDIF BIT(21)
744
+
#define AUD_TCON0_PDN_APLL_TUNER BIT(19)
745
+
#define AUD_TCON0_PDN_APLL2_TUNER BIT(18)
746
+
#define AUD_TCON0_PDN_INTDIR BIT(15)
747
+
#define AUD_TCON0_PDN_24M BIT(9)
748
+
#define AUD_TCON0_PDN_22M BIT(8)
749
+
#define AUD_TCON0_PDN_I2S_IN BIT(6)
750
+
#define AUD_TCON0_PDN_AFE BIT(2)
751
+
752
+
/* AUDIO_TOP_CON1 (0x0004) */
753
+
#define AUD_TCON1_PDN_TDM_ASRC BIT(15)
754
+
#define AUD_TCON1_PDN_GENERAL2_ASRC BIT(14)
755
+
#define AUD_TCON1_PDN_GENERAL1_ASRC BIT(13)
756
+
#define AUD_TCON1_PDN_CONNSYS_I2S_ASRC BIT(12)
757
+
#define AUD_TCON1_PDN_DMIC3_ADC BIT(11)
758
+
#define AUD_TCON1_PDN_DMIC2_ADC BIT(10)
759
+
#define AUD_TCON1_PDN_DMIC1_ADC BIT(9)
760
+
#define AUD_TCON1_PDN_DMIC0_ADC BIT(8)
761
+
#define AUD_TCON1_PDN_I2S4_BCLK BIT(7)
762
+
#define AUD_TCON1_PDN_I2S3_BCLK BIT(6)
763
+
#define AUD_TCON1_PDN_I2S2_BCLK BIT(5)
764
+
#define AUD_TCON1_PDN_I2S1_BCLK BIT(4)
765
+
766
+
/* AUDIO_TOP_CON3 (0x000C) */
767
+
#define AUD_TCON3_HDMI_BCK_INV BIT(3)
768
+
769
+
/* AFE_I2S_CON (0x0018) */
770
+
#define AFE_I2S_CON_PHASE_SHIFT_FIX BIT(31)
771
+
#define AFE_I2S_CON_FROM_IO_MUX BIT(28)
772
+
#define AFE_I2S_CON_LOW_JITTER_CLK BIT(12)
773
+
#define AFE_I2S_CON_RATE_MASK GENMASK(11, 8)
774
+
#define AFE_I2S_CON_FORMAT_I2S BIT(3)
775
+
#define AFE_I2S_CON_SRC_SLAVE BIT(2)
776
+
777
+
/* AFE_ASRC_2CH_CON0 */
778
+
#define ONE_HEART BIT(31)
779
+
#define CHSET_STR_CLR BIT(4)
780
+
#define COEFF_SRAM_CTRL BIT(1)
781
+
#define ASM_ON BIT(0)
782
+
783
+
/* CON2 */
784
+
#define O16BIT BIT(19)
785
+
#define CLR_IIR_HISTORY BIT(17)
786
+
#define IS_MONO BIT(16)
787
+
#define IIR_EN BIT(11)
788
+
#define IIR_STAGE_MASK GENMASK(10, 8)
789
+
790
+
/* CON5 */
791
+
#define CALI_CYCLE_MASK GENMASK(31, 16)
792
+
#define CALI_64_CYCLE FIELD_PREP(CALI_CYCLE_MASK, 0x3F)
793
+
#define CALI_96_CYCLE FIELD_PREP(CALI_CYCLE_MASK, 0x5F)
794
+
#define CALI_441_CYCLE FIELD_PREP(CALI_CYCLE_MASK, 0x1B8)
795
+
796
+
#define CALI_AUTORST BIT(15)
797
+
#define AUTO_TUNE_FREQ5 BIT(12)
798
+
#define COMP_FREQ_RES BIT(11)
799
+
800
+
#define CALI_SEL_MASK GENMASK(9, 8)
801
+
#define CALI_SEL_00 FIELD_PREP(CALI_SEL_MASK, 0)
802
+
#define CALI_SEL_01 FIELD_PREP(CALI_SEL_MASK, 1)
803
+
804
+
#define CALI_BP_DGL BIT(7) /* Bypass the deglitch circuit */
805
+
#define AUTO_TUNE_FREQ4 BIT(3)
806
+
#define CALI_AUTO_RESTART BIT(2)
807
+
#define CALI_USE_FREQ_OUT BIT(1)
808
+
#define CALI_ON BIT(0)
809
+
810
+
#define AFE_I2S_CON_WLEN_32BIT BIT(1)
811
+
#define AFE_I2S_CON_EN BIT(0)
812
+
813
+
#define AFE_CONN3_I03_O03_S BIT(3)
814
+
#define AFE_CONN4_I04_O04_S BIT(4)
815
+
#define AFE_CONN4_I03_O04_S BIT(3)
816
+
817
+
/* AFE_I2S_CON1 (0x0034) */
818
+
#define AFE_I2S_CON1_I2S2_TO_PAD BIT(18)
819
+
#define AFE_I2S_CON1_TDMOUT_TO_PAD (0 << 18)
820
+
#define AFE_I2S_CON1_RATE GENMASK(11, 8)
821
+
#define AFE_I2S_CON1_FORMAT_I2S BIT(3)
822
+
#define AFE_I2S_CON1_WLEN_32BIT BIT(1)
823
+
#define AFE_I2S_CON1_EN BIT(0)
824
+
825
+
/* AFE_I2S_CON2 (0x0038) */
826
+
#define AFE_I2S_CON2_LOW_JITTER_CLK BIT(12)
827
+
#define AFE_I2S_CON2_RATE GENMASK(11, 8)
828
+
#define AFE_I2S_CON2_FORMAT_I2S BIT(3)
829
+
#define AFE_I2S_CON2_WLEN_32BIT BIT(1)
830
+
#define AFE_I2S_CON2_EN BIT(0)
831
+
832
+
/* AFE_I2S_CON3 (0x004C) */
833
+
#define AFE_I2S_CON3_LOW_JITTER_CLK BIT(12)
834
+
#define AFE_I2S_CON3_RATE GENMASK(11, 8)
835
+
#define AFE_I2S_CON3_FORMAT_I2S BIT(3)
836
+
#define AFE_I2S_CON3_WLEN_32BIT BIT(1)
837
+
#define AFE_I2S_CON3_EN BIT(0)
838
+
839
+
/* AFE_ADDA_DL_SRC2_CON0 (0x0108) */
840
+
#define AFE_ADDA_DL_SAMPLING_RATE GENMASK(31, 28)
841
+
#define AFE_ADDA_DL_8X_UPSAMPLE GENMASK(25, 24)
842
+
#define AFE_ADDA_DL_MUTE_OFF_CH1 BIT(12)
843
+
#define AFE_ADDA_DL_MUTE_OFF_CH2 BIT(11)
844
+
#define AFE_ADDA_DL_VOICE_DATA BIT(5)
845
+
#define AFE_ADDA_DL_DEGRADE_GAIN BIT(1)
846
+
847
+
/* AFE_ADDA_UL_SRC_CON0 (0x0114) */
848
+
#define AFE_ADDA_UL_SAMPLING_RATE GENMASK(19, 17)
849
+
850
+
/* AFE_ADDA_UL_DL_CON0 */
851
+
#define AFE_ADDA_UL_DL_ADDA_AFE_ON BIT(0)
852
+
#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON BIT(1)
853
+
854
+
/* AFE_APLL_TUNER_CFG (0x03f0) */
855
+
#define AFE_APLL_TUNER_CFG_MASK GENMASK(15, 1)
856
+
#define AFE_APLL_TUNER_CFG_EN_MASK BIT(0)
857
+
858
+
/* AFE_APLL_TUNER_CFG1 (0x03f4) */
859
+
#define AFE_APLL_TUNER_CFG1_MASK GENMASK(15, 1)
860
+
#define AFE_APLL_TUNER_CFG1_EN_MASK BIT(0)
861
+
862
+
/* PCM_INTF_CON1 (0x0550) */
863
+
#define PCM_INTF_CON1_EXT_MODEM BIT(17)
864
+
#define PCM_INTF_CON1_16BIT (0 << 16)
865
+
#define PCM_INTF_CON1_24BIT BIT(16)
866
+
#define PCM_INTF_CON1_32BCK (0 << 14)
867
+
#define PCM_INTF_CON1_64BCK BIT(14)
868
+
#define PCM_INTF_CON1_MASTER_MODE (0 << 5)
869
+
#define PCM_INTF_CON1_SLAVE_MODE BIT(5)
870
+
#define PCM_INTF_CON1_FS_MASK GENMASK(4, 3)
871
+
#define PCM_INTF_CON1_FS_8K FIELD_PREP(PCM_INTF_CON1_FS_MASK, 0)
872
+
#define PCM_INTF_CON1_FS_16K FIELD_PREP(PCM_INTF_CON1_FS_MASK, 1)
873
+
#define PCM_INTF_CON1_FS_32K FIELD_PREP(PCM_INTF_CON1_FS_MASK, 2)
874
+
#define PCM_INTF_CON1_FS_48K FIELD_PREP(PCM_INTF_CON1_FS_MASK, 3)
875
+
#define PCM_INTF_CON1_SYNC_LEN_MASK GENMASK(13, 9)
876
+
#define PCM_INTF_CON1_SYNC_LEN(x) FIELD_PREP(PCM_INTF_CON1_SYNC_LEN_MASK, ((x) - 1))
877
+
#define PCM_INTF_CON1_FORMAT_MASK GENMASK(2, 1)
878
+
#define PCM_INTF_CON1_SYNC_OUT_INV BIT(23)
879
+
#define PCM_INTF_CON1_BCLK_OUT_INV BIT(22)
880
+
#define PCM_INTF_CON1_SYNC_IN_INV BIT(21)
881
+
#define PCM_INTF_CON1_BCLK_IN_INV BIT(20)
882
+
#define PCM_INTF_CON1_BYPASS_ASRC BIT(6)
883
+
#define PCM_INTF_CON1_EN BIT(0)
884
+
#define PCM_INTF_CON1_CONFIG_MASK (0xf3fffe)
885
+
886
+
/* AFE_DMIC0_UL_SRC_CON0 (0x05b4)
887
+
* AFE_DMIC1_UL_SRC_CON0 (0x0620)
888
+
* AFE_DMIC2_UL_SRC_CON0 (0x0780)
889
+
* AFE_DMIC3_UL_SRC_CON0 (0x07ec)
890
+
*/
891
+
#define DMIC_TOP_CON_CK_PHASE_SEL_CH1 GENMASK(29, 27)
892
+
#define DMIC_TOP_CON_CK_PHASE_SEL_CH2 GENMASK(26, 24)
893
+
#define DMIC_TOP_CON_TWO_WIRE_MODE BIT(23)
894
+
#define DMIC_TOP_CON_CH2_ON BIT(22)
895
+
#define DMIC_TOP_CON_CH1_ON BIT(21)
896
+
#define DMIC_TOP_CON_VOICE_MODE_MASK GENMASK(19, 17)
897
+
#define DMIC_TOP_CON_VOICE_MODE_8K FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 0)
898
+
#define DMIC_TOP_CON_VOICE_MODE_16K FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 1)
899
+
#define DMIC_TOP_CON_VOICE_MODE_32K FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 2)
900
+
#define DMIC_TOP_CON_VOICE_MODE_48K FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 3)
901
+
#define DMIC_TOP_CON_LOW_POWER_MODE_MASK GENMASK(15, 14)
902
+
#define DMIC_TOP_CON_LOW_POWER_MODE(x) FIELD_PREP(DMIC_TOP_CON_LOW_POWER_MODE_MASK, (x))
903
+
#define DMIC_TOP_CON_IIR_ON BIT(10)
904
+
#define DMIC_TOP_CON_IIR_MODE GENMASK(9, 7)
905
+
#define DMIC_TOP_CON_INPUT_MODE BIT(5)
906
+
#define DMIC_TOP_CON_SDM3_LEVEL_MODE BIT(1)
907
+
#define DMIC_TOP_CON_SRC_ON BIT(0)
908
+
#define DMIC_TOP_CON_SDM3_DE_SELECT (0 << 1)
909
+
#define DMIC_TOP_CON_CONFIG_MASK (0x3f8ed7a6)
910
+
911
+
/* AFE_CONN_24BIT (0x0AA4) */
912
+
#define AFE_CONN_24BIT_O10 BIT(10)
913
+
#define AFE_CONN_24BIT_O09 BIT(9)
914
+
#define AFE_CONN_24BIT_O06 BIT(6)
915
+
#define AFE_CONN_24BIT_O05 BIT(5)
916
+
#define AFE_CONN_24BIT_O04 BIT(4)
917
+
#define AFE_CONN_24BIT_O03 BIT(3)
918
+
#define AFE_CONN_24BIT_O02 BIT(2)
919
+
#define AFE_CONN_24BIT_O01 BIT(1)
920
+
#define AFE_CONN_24BIT_O00 BIT(0)
921
+
922
+
/* AFE_HD_ENGEN_ENABLE */
923
+
#define AFE_22M_PLL_EN BIT(0)
924
+
#define AFE_24M_PLL_EN BIT(1)
925
+
926
+
/* AFE_GAIN1_CON0 (0x0410) */
927
+
#define AFE_GAIN1_CON0_EN_MASK GENMASK(0, 0)
928
+
#define AFE_GAIN1_CON0_MODE_MASK GENMASK(7, 4)
929
+
#define AFE_GAIN1_CON0_SAMPLE_PER_STEP_MASK GENMASK(15, 8)
930
+
931
+
/* AFE_GAIN1_CON1 (0x0414) */
932
+
#define AFE_GAIN1_CON1_MASK GENMASK(19, 0)
933
+
934
+
/* AFE_GAIN1_CUR (0x0B78) */
935
+
#define AFE_GAIN1_CUR_MASK GENMASK(19, 0)
936
+
937
+
/* AFE_CM1_CON0 (0x0e50) */
938
+
/* AFE_CM2_CON0 (0x0e60) */
939
+
#define CM_AFE_CM_CH_NUM_MASK GENMASK(3, 0)
940
+
#define CM_AFE_CM_CH_NUM(x) FIELD_PREP(CM_AFE_CM_CH_NUM_MASK, ((x) - 1))
941
+
#define CM_AFE_CM_ON BIT(4)
942
+
#define CM_AFE_CM_START_DATA_MASK GENMASK(11, 8)
943
+
944
+
#define CM_AFE_CM1_VUL_SEL BIT(12)
945
+
#define CM_AFE_CM1_IN_MODE_MASK GENMASK(19, 16)
946
+
#define CM_AFE_CM2_TDM_SEL BIT(12)
947
+
#define CM_AFE_CM2_CLK_SEL BIT(13)
948
+
#define CM_AFE_CM2_GASRC1_OUT_SEL BIT(17)
949
+
#define CM_AFE_CM2_GASRC2_OUT_SEL BIT(16)
950
+
951
+
/* AFE_CM2_CONN* */
952
+
#define CM2_AFE_CM2_CONN_CFG1(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG1_MASK, (x))
953
+
#define CM2_AFE_CM2_CONN_CFG1_MASK GENMASK(4, 0)
954
+
#define CM2_AFE_CM2_CONN_CFG2(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG2_MASK, (x))
955
+
#define CM2_AFE_CM2_CONN_CFG2_MASK GENMASK(9, 5)
956
+
#define CM2_AFE_CM2_CONN_CFG3(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG3_MASK, (x))
957
+
#define CM2_AFE_CM2_CONN_CFG3_MASK GENMASK(14, 10)
958
+
#define CM2_AFE_CM2_CONN_CFG4(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG4_MASK, (x))
959
+
#define CM2_AFE_CM2_CONN_CFG4_MASK GENMASK(19, 15)
960
+
#define CM2_AFE_CM2_CONN_CFG5(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG5_MASK, (x))
961
+
#define CM2_AFE_CM2_CONN_CFG5_MASK GENMASK(24, 20)
962
+
#define CM2_AFE_CM2_CONN_CFG6(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG6_MASK, (x))
963
+
#define CM2_AFE_CM2_CONN_CFG6_MASK GENMASK(29, 25)
964
+
#define CM2_AFE_CM2_CONN_CFG7(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG7_MASK, (x))
965
+
#define CM2_AFE_CM2_CONN_CFG7_MASK GENMASK(4, 0)
966
+
#define CM2_AFE_CM2_CONN_CFG8(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG8_MASK, (x))
967
+
#define CM2_AFE_CM2_CONN_CFG8_MASK GENMASK(9, 5)
968
+
#define CM2_AFE_CM2_CONN_CFG9(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG9_MASK, (x))
969
+
#define CM2_AFE_CM2_CONN_CFG9_MASK GENMASK(14, 10)
970
+
#define CM2_AFE_CM2_CONN_CFG10(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG10_MASK, (x))
971
+
#define CM2_AFE_CM2_CONN_CFG10_MASK GENMASK(19, 15)
972
+
#define CM2_AFE_CM2_CONN_CFG11(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG11_MASK, (x))
973
+
#define CM2_AFE_CM2_CONN_CFG11_MASK GENMASK(24, 20)
974
+
#define CM2_AFE_CM2_CONN_CFG12(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG12_MASK, (x))
975
+
#define CM2_AFE_CM2_CONN_CFG12_MASK GENMASK(29, 25)
976
+
#define CM2_AFE_CM2_CONN_CFG13(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG13_MASK, (x))
977
+
#define CM2_AFE_CM2_CONN_CFG13_MASK GENMASK(4, 0)
978
+
#define CM2_AFE_CM2_CONN_CFG14(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG14_MASK, (x))
979
+
#define CM2_AFE_CM2_CONN_CFG14_MASK GENMASK(9, 5)
980
+
#define CM2_AFE_CM2_CONN_CFG15(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG15_MASK, (x))
981
+
#define CM2_AFE_CM2_CONN_CFG15_MASK GENMASK(14, 10)
982
+
#define CM2_AFE_CM2_CONN_CFG16(x) FIELD_PREP(CM2_AFE_CM2_CONN_CFG16_MASK, (x))
983
+
#define CM2_AFE_CM2_CONN_CFG16_MASK GENMASK(19, 15)
984
+
985
+
/* AFE_CM1_CON* */
986
+
#define CM_AFE_CM_UPDATE_CNT1_MASK GENMASK(15, 0)
987
+
#define CM_AFE_CM_UPDATE_CNT1(x) FIELD_PREP(CM_AFE_CM_UPDATE_CNT1_MASK, (x))
988
+
#define CM_AFE_CM_UPDATE_CNT2_MASK GENMASK(31, 16)
989
+
#define CM_AFE_CM_UPDATE_CNT2(x) FIELD_PREP(CM_AFE_CM_UPDATE_CNT2_MASK, (x))
990
+
991
+
#endif