Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull radeon drm fixes from Dave Airlie:
"Just piping a bunch of fixes from pre-xmas from Alex for radeon, all
either fix bad hw setup issues or regressions"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon: Bump version for CIK DCE tiling fix
drm/radeon: set correct number of banks for CIK chips in DCE
drm/radeon: set correct pipe config for Hawaii in DCE
drm/radeon: expose render backend mask to the userspace
drm/radeon: fix render backend setup for SI and CIK
drm/radeon: 0x9649 is SUMO2 not SUMO
drm/radeon: fix UVD 256MB check
+80
-49
+49
-34
drivers/gpu/drm/radeon/atombios_crtc.c
+49
-34
drivers/gpu/drm/radeon/atombios_crtc.c
···
1143
1143
}
1144
1144
1145
1145
if (tiling_flags & RADEON_TILING_MACRO) {
1146
-
if (rdev->family >= CHIP_BONAIRE)
1147
-
tmp = rdev->config.cik.tile_config;
1148
-
else if (rdev->family >= CHIP_TAHITI)
1149
-
tmp = rdev->config.si.tile_config;
1150
-
else if (rdev->family >= CHIP_CAYMAN)
1151
-
tmp = rdev->config.cayman.tile_config;
1152
-
else
1153
-
tmp = rdev->config.evergreen.tile_config;
1146
+
evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1154
1147
1155
-
switch ((tmp & 0xf0) >> 4) {
1156
-
case 0: /* 4 banks */
1157
-
fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1158
-
break;
1159
-
case 1: /* 8 banks */
1160
-
default:
1161
-
fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1162
-
break;
1163
-
case 2: /* 16 banks */
1164
-
fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1165
-
break;
1148
+
/* Set NUM_BANKS. */
1149
+
if (rdev->family >= CHIP_BONAIRE) {
1150
+
unsigned tileb, index, num_banks, tile_split_bytes;
1151
+
1152
+
/* Calculate the macrotile mode index. */
1153
+
tile_split_bytes = 64 << tile_split;
1154
+
tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1155
+
tileb = min(tile_split_bytes, tileb);
1156
+
1157
+
for (index = 0; tileb > 64; index++) {
1158
+
tileb >>= 1;
1159
+
}
1160
+
1161
+
if (index >= 16) {
1162
+
DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1163
+
target_fb->bits_per_pixel, tile_split);
1164
+
return -EINVAL;
1165
+
}
1166
+
1167
+
num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1168
+
fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1169
+
} else {
1170
+
/* SI and older. */
1171
+
if (rdev->family >= CHIP_TAHITI)
1172
+
tmp = rdev->config.si.tile_config;
1173
+
else if (rdev->family >= CHIP_CAYMAN)
1174
+
tmp = rdev->config.cayman.tile_config;
1175
+
else
1176
+
tmp = rdev->config.evergreen.tile_config;
1177
+
1178
+
switch ((tmp & 0xf0) >> 4) {
1179
+
case 0: /* 4 banks */
1180
+
fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1181
+
break;
1182
+
case 1: /* 8 banks */
1183
+
default:
1184
+
fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1185
+
break;
1186
+
case 2: /* 16 banks */
1187
+
fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1188
+
break;
1189
+
}
1166
1190
}
1167
1191
1168
1192
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1169
-
1170
-
evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1171
1193
fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1172
1194
fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1173
1195
fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
···
1202
1180
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1203
1181
1204
1182
if (rdev->family >= CHIP_BONAIRE) {
1205
-
u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;
1206
-
u32 num_rb = rdev->config.cik.max_backends_per_se;
1207
-
if (num_pipe_configs > 8)
1208
-
num_pipe_configs = 8;
1209
-
if (num_pipe_configs == 8)
1210
-
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);
1211
-
else if (num_pipe_configs == 4) {
1212
-
if (num_rb == 4)
1213
-
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);
1214
-
else if (num_rb < 4)
1215
-
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);
1216
-
} else if (num_pipe_configs == 2)
1217
-
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);
1183
+
/* Read the pipe config from the 2D TILED SCANOUT mode.
1184
+
* It should be the same for the other modes too, but not all
1185
+
* modes set the pipe config field. */
1186
+
u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1187
+
1188
+
fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1218
1189
} else if ((rdev->family == CHIP_TAHITI) ||
1219
1190
(rdev->family == CHIP_PITCAIRN))
1220
1191
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
+7
-5
drivers/gpu/drm/radeon/cik.c
+7
-5
drivers/gpu/drm/radeon/cik.c
···
3057
3057
* Returns the disabled RB bitmask.
3058
3058
*/
3059
3059
static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3060
-
u32 max_rb_num, u32 se_num,
3060
+
u32 max_rb_num_per_se,
3061
3061
u32 sh_per_se)
3062
3062
{
3063
3063
u32 data, mask;
···
3071
3071
3072
3072
data >>= BACKEND_DISABLE_SHIFT;
3073
3073
3074
-
mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);
3074
+
mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3075
3075
3076
3076
return data & mask;
3077
3077
}
···
3088
3088
*/
3089
3089
static void cik_setup_rb(struct radeon_device *rdev,
3090
3090
u32 se_num, u32 sh_per_se,
3091
-
u32 max_rb_num)
3091
+
u32 max_rb_num_per_se)
3092
3092
{
3093
3093
int i, j;
3094
3094
u32 data, mask;
···
3098
3098
for (i = 0; i < se_num; i++) {
3099
3099
for (j = 0; j < sh_per_se; j++) {
3100
3100
cik_select_se_sh(rdev, i, j);
3101
-
data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
3101
+
data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3102
3102
if (rdev->family == CHIP_HAWAII)
3103
3103
disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3104
3104
else
···
3108
3108
cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3109
3109
3110
3110
mask = 1;
3111
-
for (i = 0; i < max_rb_num; i++) {
3111
+
for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3112
3112
if (!(disabled_rbs & mask))
3113
3113
enabled_rbs |= mask;
3114
3114
mask <<= 1;
3115
3115
}
3116
+
3117
+
rdev->config.cik.backend_enable_mask = enabled_rbs;
3116
3118
3117
3119
for (i = 0; i < se_num; i++) {
3118
3120
cik_select_se_sh(rdev, i, 0xffffffff);
+2
-2
drivers/gpu/drm/radeon/radeon.h
+2
-2
drivers/gpu/drm/radeon/radeon.h
···
1940
1940
unsigned sc_earlyz_tile_fifo_size;
1941
1941
1942
1942
unsigned num_tile_pipes;
1943
-
unsigned num_backends_per_se;
1943
+
unsigned backend_enable_mask;
1944
1944
unsigned backend_disable_mask_per_asic;
1945
1945
unsigned backend_map;
1946
1946
unsigned num_texture_channel_caches;
···
1970
1970
unsigned sc_earlyz_tile_fifo_size;
1971
1971
1972
1972
unsigned num_tile_pipes;
1973
-
unsigned num_backends_per_se;
1973
+
unsigned backend_enable_mask;
1974
1974
unsigned backend_disable_mask_per_asic;
1975
1975
unsigned backend_map;
1976
1976
unsigned num_texture_channel_caches;
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
+2
-1
drivers/gpu/drm/radeon/radeon_drv.c
···
77
77
* 2.33.0 - Add SI tiling mode array query
78
78
* 2.34.0 - Add CIK tiling mode array query
79
79
* 2.35.0 - Add CIK macrotile mode array query
80
+
* 2.36.0 - Fix CIK DCE tiling setup
80
81
*/
81
82
#define KMS_DRIVER_MAJOR 2
82
-
#define KMS_DRIVER_MINOR 35
83
+
#define KMS_DRIVER_MINOR 36
83
84
#define KMS_DRIVER_PATCHLEVEL 0
84
85
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
85
86
int radeon_driver_unload_kms(struct drm_device *dev);
+9
drivers/gpu/drm/radeon/radeon_kms.c
+9
drivers/gpu/drm/radeon/radeon_kms.c
···
461
461
case RADEON_INFO_SI_CP_DMA_COMPUTE:
462
462
*value = 1;
463
463
break;
464
+
case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
465
+
if (rdev->family >= CHIP_BONAIRE) {
466
+
*value = rdev->config.cik.backend_enable_mask;
467
+
} else if (rdev->family >= CHIP_TAHITI) {
468
+
*value = rdev->config.si.backend_enable_mask;
469
+
} else {
470
+
DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
471
+
}
472
+
break;
464
473
default:
465
474
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
466
475
return -EINVAL;
+1
-1
drivers/gpu/drm/radeon/radeon_uvd.c
+1
-1
drivers/gpu/drm/radeon/radeon_uvd.c
+7
-5
drivers/gpu/drm/radeon/si.c
+7
-5
drivers/gpu/drm/radeon/si.c
···
2811
2811
}
2812
2812
2813
2813
static u32 si_get_rb_disabled(struct radeon_device *rdev,
2814
-
u32 max_rb_num, u32 se_num,
2814
+
u32 max_rb_num_per_se,
2815
2815
u32 sh_per_se)
2816
2816
{
2817
2817
u32 data, mask;
···
2825
2825
2826
2826
data >>= BACKEND_DISABLE_SHIFT;
2827
2827
2828
-
mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
2828
+
mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
2829
2829
2830
2830
return data & mask;
2831
2831
}
2832
2832
2833
2833
static void si_setup_rb(struct radeon_device *rdev,
2834
2834
u32 se_num, u32 sh_per_se,
2835
-
u32 max_rb_num)
2835
+
u32 max_rb_num_per_se)
2836
2836
{
2837
2837
int i, j;
2838
2838
u32 data, mask;
···
2842
2842
for (i = 0; i < se_num; i++) {
2843
2843
for (j = 0; j < sh_per_se; j++) {
2844
2844
si_select_se_sh(rdev, i, j);
2845
-
data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
2845
+
data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
2846
2846
disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
2847
2847
}
2848
2848
}
2849
2849
si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2850
2850
2851
2851
mask = 1;
2852
-
for (i = 0; i < max_rb_num; i++) {
2852
+
for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2853
2853
if (!(disabled_rbs & mask))
2854
2854
enabled_rbs |= mask;
2855
2855
mask <<= 1;
2856
2856
}
2857
+
2858
+
rdev->config.si.backend_enable_mask = enabled_rbs;
2857
2859
2858
2860
for (i = 0; i < se_num; i++) {
2859
2861
si_select_se_sh(rdev, i, 0xffffffff);
+1
-1
include/drm/drm_pciids.h
+1
-1
include/drm/drm_pciids.h
···
600
600
{0x1002, 0x9645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
601
601
{0x1002, 0x9647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
602
602
{0x1002, 0x9648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
603
-
{0x1002, 0x9649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
603
+
{0x1002, 0x9649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
604
604
{0x1002, 0x964a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
605
605
{0x1002, 0x964b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
606
606
{0x1002, 0x964c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+2
include/uapi/drm/radeon_drm.h
+2
include/uapi/drm/radeon_drm.h
···
983
983
#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
984
984
/* CIK macrotile mode array */
985
985
#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
986
+
/* query the number of render backends */
987
+
#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
986
988
987
989
988
990
struct drm_radeon_info {