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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Merge patch series "scsi: ufs: ufs-qcom: Debug clean ups"
Andrew Halaney <ahalaney@redhat.com> says:
This patch series attempts to clean up some debug code paths in the
ufs-qcom driver.
Link: https://lore.kernel.org/r/20221201230810.1019834-1-ahalaney@redhat.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+48
-98
+48
-87
drivers/ufs/host/ufs-qcom.c
+48
-87
drivers/ufs/host/ufs-qcom.c
···
22
22
#include <ufs/ufshci.h>
23
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#include <ufs/ufs_quirks.h>
24
24
25
-
#define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
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(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
27
-
28
25
enum {
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26
TSTBUS_UAWM,
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27
TSTBUS_UARM,
···
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static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
48
51
{
49
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return container_of(rcd, struct ufs_qcom_host, rcdev);
50
-
}
51
-
52
-
static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
53
-
const char *prefix, void *priv)
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-
{
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ufshcd_dump_regs(hba, offset, len * 4, prefix);
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53
}
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static int ufs_qcom_host_clk_get(struct device *dev,
···
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struct ufs_dev_params ufs_qcom_cap;
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int ret = 0;
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691
683
-
if (!dev_req_params) {
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pr_err("%s: incoming dev_req_params is NULL\n", __func__);
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ret = -EINVAL;
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goto out;
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-
}
688
-
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switch (status) {
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case PRE_CHANGE:
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ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
···
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dev_max_params,
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dev_req_params);
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if (ret) {
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pr_err("%s: failed to determine capabilities\n",
721
+
dev_err(hba->dev, "%s: failed to determine capabilities\n",
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__func__);
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goto out;
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}
···
1031
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if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
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ufs_qcom_hosts[hba->dev->id] = host;
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-
host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
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ufs_qcom_get_default_testbus_cfg(host);
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err = ufs_qcom_testbus_config(host);
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if (err) {
···
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return err;
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}
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-
static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
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void *priv, void (*print_fn)(struct ufs_hba *hba,
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int offset, int num_regs, const char *str, void *priv))
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-
{
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u32 reg;
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struct ufs_qcom_host *host;
1188
-
1189
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if (unlikely(!hba)) {
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pr_err("%s: hba is NULL\n", __func__);
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return;
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-
}
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if (unlikely(!print_fn)) {
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dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
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return;
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-
}
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host = ufshcd_get_variant(hba);
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if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
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return;
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
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print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
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reg = ufshcd_readl(hba, REG_UFS_CFG1);
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reg |= UTP_DBG_RAMS_EN;
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ufshcd_writel(hba, reg, REG_UFS_CFG1);
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
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print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
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print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
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print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1217
-
1218
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/* clear bit 17 - UTP_DBG_RAMS_EN */
1219
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ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1220
-
1221
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1222
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print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1223
-
1224
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
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print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1226
-
1227
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1228
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print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1229
-
1230
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1231
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print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1232
-
1233
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1234
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print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1235
-
1236
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1237
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print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1238
-
1239
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reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1240
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print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1241
-
}
1242
-
1243
1198
static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1244
1199
{
1245
-
if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1246
-
ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1247
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UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1248
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ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1249
-
} else {
1250
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ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1251
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ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1252
-
}
1200
+
ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1201
+
UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1202
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ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1253
1203
}
1254
1204
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1205
static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
···
1292
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1293
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static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1294
1376
{
1377
+
u32 reg;
1378
+
struct ufs_qcom_host *host;
1379
+
1380
+
host = ufshcd_get_variant(hba);
1381
+
1295
1382
ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1296
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"HCI Vendor Specific Registers ");
1297
1384
1298
-
ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1385
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1386
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ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1387
+
1388
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reg = ufshcd_readl(hba, REG_UFS_CFG1);
1389
+
reg |= UTP_DBG_RAMS_EN;
1390
+
ufshcd_writel(hba, reg, REG_UFS_CFG1);
1391
+
1392
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1393
+
ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1394
+
1395
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1396
+
ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1397
+
1398
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1399
+
ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1400
+
1401
+
/* clear bit 17 - UTP_DBG_RAMS_EN */
1402
+
ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1403
+
1404
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1405
+
ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1406
+
1407
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1408
+
ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1409
+
1410
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1411
+
ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1412
+
1413
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1414
+
ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1415
+
1416
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1417
+
ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1418
+
1419
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1420
+
ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1421
+
1422
+
reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1423
+
ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1299
1424
}
1300
1425
1301
1426
/**
-11
drivers/ufs/host/ufs-qcom.h
-11
drivers/ufs/host/ufs-qcom.h
···
113
113
MASK_CLK_NS_REG = 0xFFFC00,
114
114
};
115
115
116
-
/* QCOM UFS debug print bit mask */
117
-
#define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0)
118
-
#define UFS_QCOM_DBG_PRINT_ICE_REGS_EN BIT(1)
119
-
#define UFS_QCOM_DBG_PRINT_TEST_BUS_EN BIT(2)
120
-
121
-
#define UFS_QCOM_DBG_PRINT_ALL \
122
-
(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
123
-
UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
124
-
125
116
/* QUniPro Vendor specific attributes */
126
117
#define PA_VS_CONFIG_REG1 0x9000
127
118
#define DME_VS_CORE_CLK_CTRL 0xD002
···
203
212
204
213
u32 dev_ref_clk_en_mask;
205
214
206
-
/* Bitmask for enabling debug prints */
207
-
u32 dbg_print_en;
208
215
struct ufs_qcom_testbus testbus;
209
216
210
217
/* Reset control of HCI */