+14

arch/i386/boot/video.S

reviewed

··· 571 571 jmp _m_s 572 572 573 573 check_vesa: 574 574 + #ifdef CONFIG_FIRMWARE_EDID 575 575 + leaw modelist+1024, %di 576 576 + movw $0x4f00, %ax 577 577 + int $0x10 578 578 + cmpw $0x004f, %ax 579 579 + jnz setbad 580 580 + 581 581 + movw 4(%di), %ax 582 582 + movw %ax, vbe_version 583 583 + #endif 574 584 leaw modelist+1024, %di 575 585 subb $VIDEO_FIRST_VESA>>8, %bh 576 586 movw %bx, %cx # Get mode information structure ··· 1955 1945 rep 1956 1946 stosl 1957 1947 1948 1948 + cmpw $0x0200, vbe_version # only do EDID on >= VBE2.0 1949 1949 + jl no_edid 1950 1950 + 1958 1951 pushw %es # save ES 1959 1952 xorw %di, %di # Report Capability 1960 1953 pushw %di ··· 2000 1987 svga_prefix: .byte VIDEO_FIRST_BIOS>>8 # Default prefix for BIOS modes 2001 1988 graphic_mode: .byte 0 # Graphic mode with a linear frame buffer 2002 1989 dac_size: .byte 6 # DAC bit depth 1990 1990 + vbe_version: .word 0 # VBE bios version 2003 1991 2004 1992 # Status messages 2005 1993 keymsg: .ascii "Press <RETURN> to see video modes available, "

+3 -29

arch/i386/kernel/apic.c

reviewed

··· 272 272 } 273 273 274 274 /* 275 275 - * Detect systems with known broken BIOS implementations 276 276 - */ 277 277 - static int __init lapic_check_broken_bios(struct dmi_system_id *d) 278 278 - { 279 279 - printk(KERN_NOTICE "%s detected: disabling lapic timer.\n", 280 280 - d->ident); 281 281 - local_apic_timer_disabled = 1; 282 282 - return 0; 283 283 - } 284 284 - 285 285 - static struct dmi_system_id __initdata broken_bios_dmi_table[] = { 286 286 - { 287 287 - /* 288 288 - * BIOS exports only C1 state, but uses deeper power 289 289 - * modes behind the kernels back. 290 290 - */ 291 291 - .callback = lapic_check_broken_bios, 292 292 - .ident = "HP nx6325", 293 293 - .matches = { 294 294 - DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"), 295 295 - }, 296 296 - }, 297 297 - {} 298 298 - }; 299 299 - 300 300 - /* 301 275 * In this functions we calibrate APIC bus clocks to the external timer. 302 276 * 303 277 * We want to do the calibration only once since we want to have local timer ··· 346 372 long delta, deltapm; 347 373 int pm_referenced = 0; 348 374 349 349 - /* Detect know broken systems */ 350 350 - dmi_check_system(broken_bios_dmi_table); 375 375 + if (boot_cpu_has(X86_FEATURE_LAPIC_TIMER_BROKEN)) 376 376 + local_apic_timer_disabled = 1; 351 377 352 378 /* 353 379 * The local apic timer can be disabled via the kernel 354 354 - * commandline or from the dmi quirk above. Register the lapic 380 380 + * commandline or from the test above. Register the lapic 355 381 * timer as a dummy clock event source on SMP systems, so the 356 382 * broadcast mechanism is used. On UP systems simply ignore it. 357 383 */

+34

arch/i386/kernel/cpu/amd.c

reviewed

··· 22 22 extern void vide(void); 23 23 __asm__(".align 4\nvide: ret"); 24 24 25 25 + #define ENABLE_C1E_MASK 0x18000000 26 26 + #define CPUID_PROCESSOR_SIGNATURE 1 27 27 + #define CPUID_XFAM 0x0ff00000 28 28 + #define CPUID_XFAM_K8 0x00000000 29 29 + #define CPUID_XFAM_10H 0x00100000 30 30 + #define CPUID_XFAM_11H 0x00200000 31 31 + #define CPUID_XMOD 0x000f0000 32 32 + #define CPUID_XMOD_REV_F 0x00040000 33 33 + 34 34 + /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ 35 35 + static __cpuinit int amd_apic_timer_broken(void) 36 36 + { 37 37 + u32 lo, hi; 38 38 + u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 39 39 + switch (eax & CPUID_XFAM) { 40 40 + case CPUID_XFAM_K8: 41 41 + if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) 42 42 + break; 43 43 + case CPUID_XFAM_10H: 44 44 + case CPUID_XFAM_11H: 45 45 + rdmsr(MSR_K8_ENABLE_C1E, lo, hi); 46 46 + if (lo & ENABLE_C1E_MASK) 47 47 + return 1; 48 48 + break; 49 49 + default: 50 50 + /* err on the side of caution */ 51 51 + return 1; 52 52 + } 53 53 + return 0; 54 54 + } 55 55 + 25 56 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 26 57 { 27 58 u32 l, h; ··· 272 241 273 242 if (cpuid_eax(0x80000000) >= 0x80000006) 274 243 num_cache_leaves = 3; 244 244 + 245 245 + if (amd_apic_timer_broken()) 246 246 + set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability); 275 247 } 276 248 277 249 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)

+107 -42

arch/i386/kernel/nmi.c

reviewed

··· 122 122 /* checks for a bit availability (hack for oprofile) */ 123 123 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter) 124 124 { 125 125 + int cpu; 125 126 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 126 126 - 127 127 - return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner))); 127 127 + for_each_possible_cpu (cpu) { 128 128 + if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu))) 129 129 + return 0; 130 130 + } 131 131 + return 1; 128 132 } 129 133 130 134 /* checks the an msr for availability */ 131 135 int avail_to_resrv_perfctr_nmi(unsigned int msr) 132 136 { 133 137 unsigned int counter; 138 138 + int cpu; 134 139 135 140 counter = nmi_perfctr_msr_to_bit(msr); 136 141 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 137 142 138 138 - return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner))); 143 143 + for_each_possible_cpu (cpu) { 144 144 + if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu))) 145 145 + return 0; 146 146 + } 147 147 + return 1; 148 148 + } 149 149 + 150 150 + static int __reserve_perfctr_nmi(int cpu, unsigned int msr) 151 151 + { 152 152 + unsigned int counter; 153 153 + if (cpu < 0) 154 154 + cpu = smp_processor_id(); 155 155 + 156 156 + counter = nmi_perfctr_msr_to_bit(msr); 157 157 + BUG_ON(counter > NMI_MAX_COUNTER_BITS); 158 158 + 159 159 + if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu))) 160 160 + return 1; 161 161 + return 0; 162 162 + } 163 163 + 164 164 + static void __release_perfctr_nmi(int cpu, unsigned int msr) 165 165 + { 166 166 + unsigned int counter; 167 167 + if (cpu < 0) 168 168 + cpu = smp_processor_id(); 169 169 + 170 170 + counter = nmi_perfctr_msr_to_bit(msr); 171 171 + BUG_ON(counter > NMI_MAX_COUNTER_BITS); 172 172 + 173 173 + clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)); 139 174 } 140 175 141 176 int reserve_perfctr_nmi(unsigned int msr) 142 177 { 143 143 - unsigned int counter; 144 144 - 145 145 - counter = nmi_perfctr_msr_to_bit(msr); 146 146 - BUG_ON(counter > NMI_MAX_COUNTER_BITS); 147 147 - 148 148 - if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner))) 149 149 - return 1; 150 150 - return 0; 178 178 + int cpu, i; 179 179 + for_each_possible_cpu (cpu) { 180 180 + if (!__reserve_perfctr_nmi(cpu, msr)) { 181 181 + for_each_possible_cpu (i) { 182 182 + if (i >= cpu) 183 183 + break; 184 184 + __release_perfctr_nmi(i, msr); 185 185 + } 186 186 + return 0; 187 187 + } 188 188 + } 189 189 + return 1; 151 190 } 152 191 153 192 void release_perfctr_nmi(unsigned int msr) 154 193 { 155 155 - unsigned int counter; 156 156 - 157 157 - counter = nmi_perfctr_msr_to_bit(msr); 158 158 - BUG_ON(counter > NMI_MAX_COUNTER_BITS); 159 159 - 160 160 - clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner)); 194 194 + int cpu; 195 195 + for_each_possible_cpu (cpu) { 196 196 + __release_perfctr_nmi(cpu, msr); 197 197 + } 161 198 } 162 199 163 163 - int reserve_evntsel_nmi(unsigned int msr) 200 200 + int __reserve_evntsel_nmi(int cpu, unsigned int msr) 164 201 { 165 202 unsigned int counter; 203 203 + if (cpu < 0) 204 204 + cpu = smp_processor_id(); 166 205 167 206 counter = nmi_evntsel_msr_to_bit(msr); 168 207 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 169 208 170 170 - if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0])) 209 209 + if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0])) 171 210 return 1; 172 211 return 0; 173 212 } 174 213 175 175 - void release_evntsel_nmi(unsigned int msr) 214 214 + static void __release_evntsel_nmi(int cpu, unsigned int msr) 176 215 { 177 216 unsigned int counter; 217 217 + if (cpu < 0) 218 218 + cpu = smp_processor_id(); 178 219 179 220 counter = nmi_evntsel_msr_to_bit(msr); 180 221 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 181 222 182 182 - clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]); 223 223 + clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]); 224 224 + } 225 225 + 226 226 + int reserve_evntsel_nmi(unsigned int msr) 227 227 + { 228 228 + int cpu, i; 229 229 + for_each_possible_cpu (cpu) { 230 230 + if (!__reserve_evntsel_nmi(cpu, msr)) { 231 231 + for_each_possible_cpu (i) { 232 232 + if (i >= cpu) 233 233 + break; 234 234 + __release_evntsel_nmi(i, msr); 235 235 + } 236 236 + return 0; 237 237 + } 238 238 + } 239 239 + return 1; 240 240 + } 241 241 + 242 242 + void release_evntsel_nmi(unsigned int msr) 243 243 + { 244 244 + int cpu; 245 245 + for_each_possible_cpu (cpu) { 246 246 + __release_evntsel_nmi(cpu, msr); 247 247 + } 183 248 } 184 249 185 250 static __cpuinit inline int nmi_known_cpu(void) ··· 328 263 for_each_possible_cpu(cpu) 329 264 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count; 330 265 local_irq_enable(); 331 331 - mdelay((10*1000)/nmi_hz); // wait 10 ticks 266 266 + mdelay((20*1000)/nmi_hz); // wait 20 ticks 332 267 333 268 for_each_possible_cpu(cpu) { 334 269 #ifdef CONFIG_SMP ··· 572 507 573 508 perfctr_msr = MSR_K7_PERFCTR0; 574 509 evntsel_msr = MSR_K7_EVNTSEL0; 575 575 - if (!reserve_perfctr_nmi(perfctr_msr)) 510 510 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 576 511 goto fail; 577 512 578 578 - if (!reserve_evntsel_nmi(evntsel_msr)) 513 513 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 579 514 goto fail1; 580 515 581 516 wrmsrl(perfctr_msr, 0UL); ··· 598 533 wd->check_bit = 1ULL<<63; 599 534 return 1; 600 535 fail1: 601 601 - release_perfctr_nmi(perfctr_msr); 536 536 + __release_perfctr_nmi(-1, perfctr_msr); 602 537 fail: 603 538 return 0; 604 539 } ··· 609 544 610 545 wrmsr(wd->evntsel_msr, 0, 0); 611 546 612 612 - release_evntsel_nmi(wd->evntsel_msr); 613 613 - release_perfctr_nmi(wd->perfctr_msr); 547 547 + __release_evntsel_nmi(-1, wd->evntsel_msr); 548 548 + __release_perfctr_nmi(-1, wd->perfctr_msr); 614 549 } 615 550 616 551 #define P6_EVNTSEL0_ENABLE (1 << 22) ··· 628 563 629 564 perfctr_msr = MSR_P6_PERFCTR0; 630 565 evntsel_msr = MSR_P6_EVNTSEL0; 631 631 - if (!reserve_perfctr_nmi(perfctr_msr)) 566 566 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 632 567 goto fail; 633 568 634 634 - if (!reserve_evntsel_nmi(evntsel_msr)) 569 569 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 635 570 goto fail1; 636 571 637 572 wrmsrl(perfctr_msr, 0UL); ··· 655 590 wd->check_bit = 1ULL<<39; 656 591 return 1; 657 592 fail1: 658 658 - release_perfctr_nmi(perfctr_msr); 593 593 + __release_perfctr_nmi(-1, perfctr_msr); 659 594 fail: 660 595 return 0; 661 596 } ··· 666 601 667 602 wrmsr(wd->evntsel_msr, 0, 0); 668 603 669 669 - release_evntsel_nmi(wd->evntsel_msr); 670 670 - release_perfctr_nmi(wd->perfctr_msr); 604 604 + __release_evntsel_nmi(-1, wd->evntsel_msr); 605 605 + __release_perfctr_nmi(-1, wd->perfctr_msr); 671 606 } 672 607 673 608 /* Note that these events don't tick when the CPU idles. This means ··· 733 668 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4); 734 669 } 735 670 736 736 - if (!reserve_perfctr_nmi(perfctr_msr)) 671 671 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 737 672 goto fail; 738 673 739 739 - if (!reserve_evntsel_nmi(evntsel_msr)) 674 674 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 740 675 goto fail1; 741 676 742 677 evntsel = P4_ESCR_EVENT_SELECT(0x3F) ··· 760 695 wd->check_bit = 1ULL<<39; 761 696 return 1; 762 697 fail1: 763 763 - release_perfctr_nmi(perfctr_msr); 698 698 + __release_perfctr_nmi(-1, perfctr_msr); 764 699 fail: 765 700 return 0; 766 701 } ··· 772 707 wrmsr(wd->cccr_msr, 0, 0); 773 708 wrmsr(wd->evntsel_msr, 0, 0); 774 709 775 775 - release_evntsel_nmi(wd->evntsel_msr); 776 776 - release_perfctr_nmi(wd->perfctr_msr); 710 710 + __release_evntsel_nmi(-1, wd->evntsel_msr); 711 711 + __release_perfctr_nmi(-1, wd->perfctr_msr); 777 712 } 778 713 779 714 #define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL ··· 801 736 perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0; 802 737 evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0; 803 738 804 804 - if (!reserve_perfctr_nmi(perfctr_msr)) 739 739 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 805 740 goto fail; 806 741 807 807 - if (!reserve_evntsel_nmi(evntsel_msr)) 742 742 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 808 743 goto fail1; 809 744 810 745 wrmsrl(perfctr_msr, 0UL); ··· 829 764 wd->check_bit = 1ULL << (eax.split.bit_width - 1); 830 765 return 1; 831 766 fail1: 832 832 - release_perfctr_nmi(perfctr_msr); 767 767 + __release_perfctr_nmi(-1, perfctr_msr); 833 768 fail: 834 769 return 0; 835 770 } ··· 852 787 return; 853 788 854 789 wrmsr(wd->evntsel_msr, 0, 0); 855 855 - release_evntsel_nmi(wd->evntsel_msr); 856 856 - release_perfctr_nmi(wd->perfctr_msr); 790 790 + __release_evntsel_nmi(-1, wd->evntsel_msr); 791 791 + __release_perfctr_nmi(-1, wd->perfctr_msr); 857 792 } 858 793 859 794 void setup_apic_nmi_watchdog (void *unused)

+14

arch/x86_64/boot/video.S

reviewed

··· 571 571 jmp _m_s 572 572 573 573 check_vesa: 574 574 + #ifdef CONFIG_FIRMWARE_EDID 575 575 + leaw modelist+1024, %di 576 576 + movw $0x4f00, %ax 577 577 + int $0x10 578 578 + cmpw $0x004f, %ax 579 579 + jnz setbad 580 580 + 581 581 + movw 4(%di), %ax 582 582 + movw %ax, vbe_version 583 583 + #endif 574 584 leaw modelist+1024, %di 575 585 subb $VIDEO_FIRST_VESA>>8, %bh 576 586 movw %bx, %cx # Get mode information structure ··· 1955 1945 rep 1956 1946 stosl 1957 1947 1948 1948 + cmpw $0x0200, vbe_version # only do EDID on >= VBE2.0 1949 1949 + jl no_edid 1950 1950 + 1958 1951 pushw %es # save ES 1959 1952 xorw %di, %di # Report Capability 1960 1953 pushw %di ··· 2000 1987 svga_prefix: .byte VIDEO_FIRST_BIOS>>8 # Default prefix for BIOS modes 2001 1988 graphic_mode: .byte 0 # Graphic mode with a linear frame buffer 2002 1989 dac_size: .byte 6 # DAC bit depth 1990 1990 + vbe_version: .word 0 # VBE bios version 2003 1991 2004 1992 # Status messages 2005 1993 keymsg: .ascii "Press <RETURN> to see video modes available, "

+102 -38

arch/x86_64/kernel/nmi.c

reviewed

··· 108 108 /* checks for a bit availability (hack for oprofile) */ 109 109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter) 110 110 { 111 111 + int cpu; 111 112 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 112 112 - 113 113 - return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner))); 113 113 + for_each_possible_cpu (cpu) { 114 114 + if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu))) 115 115 + return 0; 116 116 + } 117 117 + return 1; 114 118 } 115 119 116 120 /* checks the an msr for availability */ 117 121 int avail_to_resrv_perfctr_nmi(unsigned int msr) 118 122 { 119 123 unsigned int counter; 124 124 + int cpu; 120 125 121 126 counter = nmi_perfctr_msr_to_bit(msr); 122 127 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 123 128 124 124 - return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner))); 129 129 + for_each_possible_cpu (cpu) { 130 130 + if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu))) 131 131 + return 0; 132 132 + } 133 133 + return 1; 134 134 + } 135 135 + 136 136 + static int __reserve_perfctr_nmi(int cpu, unsigned int msr) 137 137 + { 138 138 + unsigned int counter; 139 139 + if (cpu < 0) 140 140 + cpu = smp_processor_id(); 141 141 + 142 142 + counter = nmi_perfctr_msr_to_bit(msr); 143 143 + BUG_ON(counter > NMI_MAX_COUNTER_BITS); 144 144 + 145 145 + if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu))) 146 146 + return 1; 147 147 + return 0; 148 148 + } 149 149 + 150 150 + static void __release_perfctr_nmi(int cpu, unsigned int msr) 151 151 + { 152 152 + unsigned int counter; 153 153 + if (cpu < 0) 154 154 + cpu = smp_processor_id(); 155 155 + 156 156 + counter = nmi_perfctr_msr_to_bit(msr); 157 157 + BUG_ON(counter > NMI_MAX_COUNTER_BITS); 158 158 + 159 159 + clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)); 125 160 } 126 161 127 162 int reserve_perfctr_nmi(unsigned int msr) 128 163 { 129 129 - unsigned int counter; 130 130 - 131 131 - counter = nmi_perfctr_msr_to_bit(msr); 132 132 - BUG_ON(counter > NMI_MAX_COUNTER_BITS); 133 133 - 134 134 - if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner))) 135 135 - return 1; 136 136 - return 0; 164 164 + int cpu, i; 165 165 + for_each_possible_cpu (cpu) { 166 166 + if (!__reserve_perfctr_nmi(cpu, msr)) { 167 167 + for_each_possible_cpu (i) { 168 168 + if (i >= cpu) 169 169 + break; 170 170 + __release_perfctr_nmi(i, msr); 171 171 + } 172 172 + return 0; 173 173 + } 174 174 + } 175 175 + return 1; 137 176 } 138 177 139 178 void release_perfctr_nmi(unsigned int msr) 140 179 { 141 141 - unsigned int counter; 142 142 - 143 143 - counter = nmi_perfctr_msr_to_bit(msr); 144 144 - BUG_ON(counter > NMI_MAX_COUNTER_BITS); 145 145 - 146 146 - clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner)); 180 180 + int cpu; 181 181 + for_each_possible_cpu (cpu) 182 182 + __release_perfctr_nmi(cpu, msr); 147 183 } 148 184 149 149 - int reserve_evntsel_nmi(unsigned int msr) 185 185 + int __reserve_evntsel_nmi(int cpu, unsigned int msr) 150 186 { 151 187 unsigned int counter; 188 188 + if (cpu < 0) 189 189 + cpu = smp_processor_id(); 152 190 153 191 counter = nmi_evntsel_msr_to_bit(msr); 154 192 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 155 193 156 156 - if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner))) 194 194 + if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0])) 157 195 return 1; 158 196 return 0; 159 197 } 160 198 161 161 - void release_evntsel_nmi(unsigned int msr) 199 199 + static void __release_evntsel_nmi(int cpu, unsigned int msr) 162 200 { 163 201 unsigned int counter; 202 202 + if (cpu < 0) 203 203 + cpu = smp_processor_id(); 164 204 165 205 counter = nmi_evntsel_msr_to_bit(msr); 166 206 BUG_ON(counter > NMI_MAX_COUNTER_BITS); 167 207 168 168 - clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner)); 208 208 + clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]); 209 209 + } 210 210 + 211 211 + int reserve_evntsel_nmi(unsigned int msr) 212 212 + { 213 213 + int cpu, i; 214 214 + for_each_possible_cpu (cpu) { 215 215 + if (!__reserve_evntsel_nmi(cpu, msr)) { 216 216 + for_each_possible_cpu (i) { 217 217 + if (i >= cpu) 218 218 + break; 219 219 + __release_evntsel_nmi(i, msr); 220 220 + } 221 221 + return 0; 222 222 + } 223 223 + } 224 224 + return 1; 225 225 + } 226 226 + 227 227 + void release_evntsel_nmi(unsigned int msr) 228 228 + { 229 229 + int cpu; 230 230 + for_each_possible_cpu (cpu) { 231 231 + __release_evntsel_nmi(cpu, msr); 232 232 + } 169 233 } 170 234 171 235 static __cpuinit inline int nmi_known_cpu(void) ··· 317 253 for (cpu = 0; cpu < NR_CPUS; cpu++) 318 254 counts[cpu] = cpu_pda(cpu)->__nmi_count; 319 255 local_irq_enable(); 320 320 - mdelay((10*1000)/nmi_hz); // wait 10 ticks 256 256 + mdelay((20*1000)/nmi_hz); // wait 20 ticks 321 257 322 258 for_each_online_cpu(cpu) { 323 259 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled) ··· 536 472 537 473 perfctr_msr = MSR_K7_PERFCTR0; 538 474 evntsel_msr = MSR_K7_EVNTSEL0; 539 539 - if (!reserve_perfctr_nmi(perfctr_msr)) 475 475 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 540 476 goto fail; 541 477 542 542 - if (!reserve_evntsel_nmi(evntsel_msr)) 478 478 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 543 479 goto fail1; 544 480 545 481 /* Simulator may not support it */ ··· 565 501 wd->check_bit = 1ULL<<63; 566 502 return 1; 567 503 fail2: 568 568 - release_evntsel_nmi(evntsel_msr); 504 504 + __release_evntsel_nmi(-1, evntsel_msr); 569 505 fail1: 570 570 - release_perfctr_nmi(perfctr_msr); 506 506 + __release_perfctr_nmi(-1, perfctr_msr); 571 507 fail: 572 508 return 0; 573 509 } ··· 578 514 579 515 wrmsr(wd->evntsel_msr, 0, 0); 580 516 581 581 - release_evntsel_nmi(wd->evntsel_msr); 582 582 - release_perfctr_nmi(wd->perfctr_msr); 517 517 + __release_evntsel_nmi(-1, wd->evntsel_msr); 518 518 + __release_perfctr_nmi(-1, wd->perfctr_msr); 583 519 } 584 520 585 521 /* Note that these events don't tick when the CPU idles. This means ··· 645 581 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4); 646 582 } 647 583 648 648 - if (!reserve_perfctr_nmi(perfctr_msr)) 584 584 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 649 585 goto fail; 650 586 651 651 - if (!reserve_evntsel_nmi(evntsel_msr)) 587 587 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 652 588 goto fail1; 653 589 654 590 evntsel = P4_ESCR_EVENT_SELECT(0x3F) ··· 673 609 wd->check_bit = 1ULL<<39; 674 610 return 1; 675 611 fail1: 676 676 - release_perfctr_nmi(perfctr_msr); 612 612 + __release_perfctr_nmi(-1, perfctr_msr); 677 613 fail: 678 614 return 0; 679 615 } ··· 685 621 wrmsr(wd->cccr_msr, 0, 0); 686 622 wrmsr(wd->evntsel_msr, 0, 0); 687 623 688 688 - release_evntsel_nmi(wd->evntsel_msr); 689 689 - release_perfctr_nmi(wd->perfctr_msr); 624 624 + __release_evntsel_nmi(-1, wd->evntsel_msr); 625 625 + __release_perfctr_nmi(-1, wd->perfctr_msr); 690 626 } 691 627 692 628 #define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL ··· 714 650 perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0; 715 651 evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0; 716 652 717 717 - if (!reserve_perfctr_nmi(perfctr_msr)) 653 653 + if (!__reserve_perfctr_nmi(-1, perfctr_msr)) 718 654 goto fail; 719 655 720 720 - if (!reserve_evntsel_nmi(evntsel_msr)) 656 656 + if (!__reserve_evntsel_nmi(-1, evntsel_msr)) 721 657 goto fail1; 722 658 723 659 wrmsrl(perfctr_msr, 0UL); ··· 744 680 wd->check_bit = 1ULL << (eax.split.bit_width - 1); 745 681 return 1; 746 682 fail1: 747 747 - release_perfctr_nmi(perfctr_msr); 683 683 + __release_perfctr_nmi(-1, perfctr_msr); 748 684 fail: 749 685 return 0; 750 686 } ··· 768 704 769 705 wrmsr(wd->evntsel_msr, 0, 0); 770 706 771 771 - release_evntsel_nmi(wd->evntsel_msr); 772 772 - release_perfctr_nmi(wd->perfctr_msr); 707 707 + __release_evntsel_nmi(-1, wd->evntsel_msr); 708 708 + __release_perfctr_nmi(-1, wd->perfctr_msr); 773 709 } 774 710 775 711 void setup_apic_nmi_watchdog(void *unused)

+1

include/asm-i386/cpufeature.h

reviewed

··· 75 75 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 76 76 #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 77 77 #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 78 78 + #define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */ 78 79 79 80 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 80 81 #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */

+2

include/asm-i386/msr.h

reviewed

··· 275 275 #define MSR_K7_FID_VID_CTL 0xC0010041 276 276 #define MSR_K7_FID_VID_STATUS 0xC0010042 277 277 278 278 + #define MSR_K8_ENABLE_C1E 0xC0010055 279 279 + 278 280 /* extended feature register */ 279 281 #define MSR_EFER 0xc0000080 280 282