Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
powerpc/perf: Fix to update cache events with l2l3 events in power10
Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
(PM_L3_PF_MISS_L3) via sysfs, and also add these to list of
cache_events.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-7-git-send-email-atrajeev@linux.vnet.ibm.com
authored by
Athira Rajeev
and committed by
Michael Ellerman
9a8ee526
1f123163
+15
-3
+6
arch/powerpc/perf/power10-events-list.h
+6
arch/powerpc/perf/power10-events-list.h
···
39
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EVENT(PM_DATA_FROM_L3, 0x01340000001c040);
40
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe);
42
+
/* All successful D-side store dispatches for this thread */
43
+
EVENT(PM_L2_ST, 0x010000046080);
44
+
/* All successful D-side store dispatches for this thread that were L2 Miss */
45
+
EVENT(PM_L2_ST_MISS, 0x26880);
46
+
/* Total HW L3 prefetches(Load+store) */
47
+
EVENT(PM_L3_PF_MISS_L3, 0x100000016080);
42
48
/* Data PTEG reload */
43
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EVENT(PM_DTLB_MISS, 0x300fc);
44
50
/* ITLB Reloaded */
+9
-3
arch/powerpc/perf/power10-pmu.c
+9
-3
arch/powerpc/perf/power10-pmu.c
···
127
127
CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
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CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
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CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
130
+
CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3);
131
+
CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
132
+
CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
130
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
131
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CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
132
135
CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
···
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CACHE_EVENT_PTR(PM_IC_PREF_REQ),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3),
178
+
CACHE_EVENT_PTR(PM_L3_PF_MISS_L3),
179
+
CACHE_EVENT_PTR(PM_L2_ST_MISS),
180
+
CACHE_EVENT_PTR(PM_L2_ST),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_BR_CMPL),
183
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CACHE_EVENT_PTR(PM_DTLB_MISS),
···
466
460
[C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
467
461
},
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462
[C(OP_WRITE)] = {
469
-
[C(RESULT_ACCESS)] = -1,
470
-
[C(RESULT_MISS)] = -1,
463
+
[C(RESULT_ACCESS)] = PM_L2_ST,
464
+
[C(RESULT_MISS)] = PM_L2_ST_MISS,
471
465
},
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[C(OP_PREFETCH)] = {
473
-
[C(RESULT_ACCESS)] = -1,
467
+
[C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
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[C(RESULT_MISS)] = 0,
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469
},
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},